DUAL 1-OF-4 DECODER/ DEMULTIPLEXER

SN74LS155
DUAL 1-OF-4 DECODER/
DEMULTIPLEXER
The SN54 / 74LS156 is a high speed Dual 1-of-4
Decoder/Demultiplexer. This device has two decoders with common
2-bit Address inputs and separate gated Enable inputs. Decoder “a”
has an Enable gate with one active HIGH and one active LOW input.
Decoder “b” has two active LOW Enable inputs. If the Enable
functions are satisfied, one output of each decoder will be LOW as
selected by the address inputs. The LS156 has open collector outputs
for wired-OR (DOT-AND) decoding and function generator
applications.
The LS156 is fabricated with the Schottky barrier diode process for
high speed and are completely compatible with all Motorola TTL
families.
• Schottky Process for High Speed
• Multifunction Capability
• Common Address Inputs
• True or Complement Data Demultiplexing
• Input Clamp Diodes Limit High Speed Termination Effects
• ESD > 3500 Volts
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DUAL 1-OF-4 DECODER/
DEMULTIPLEXER
LS156-OPEN-COLLECTOR
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC
Eb
Eb
A0
O3b
O2b
O1b
O0b
16
15
14
13
12
11
10
9
D SUFFIX
SOIC
CASE 751B-03
16
NOTE:
The Flatpak version
has the same pinouts (Connection
Diagram) as the Dual In-Line Package.
1
ORDERING INFORMATION
1
Ea
2
Ea
3
A1
4
O3a
5
O2a
6
O1a
7
O0a
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
8
GND
Ceramic
Plastic
SOIC
LOGIC SYMBOL
1 2
A0, A1
Ea, Eb
Ea
O0 −O3
13 3
14 15
LOADING (Note a)
PIN NAMES
Address Inputs
Enable (Active LOW) Inputs
Enable (Active HIGH) Input
Active LOW Outputs (Note b)
HIGH
LOW
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 μA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges. The HIGH level drive for the LS156 must be established by an
external resistor.
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 7
1
E
DECODER a
A0
A0
A1
A1
0
0
1
2
3
7
6
5
4
9
E
DECODER b
1
2
3
10 11 12
VCC = PIN 16
GND = PIN 8
Publication Order Number:
SN74LS155/D
SN74LS155
SN54/74LS156
LOGIC DIAGRAM
Ea Ea
1
A0
2
A1
13
Eb Eb
3
14
15
VCC = PIN 16
GND = PIN 8
7
= PIN NUMBERS
5
6
O0a
O1a
4
O2a
9
O3a
10
O0b
11
O1b
12
O2b
O3b
FUNCTIONAL DESCRIPTION
AND the minterm functions by tying outputs together. Any
number of terms can be wired-AND as shown below.
The LS156 is a Dual 1-of-4 Decoder/Demultiplexer with
common Address inputs and separate gated Enable inputs.
When enabled, each decoder section accepts the binary
weighted Address inputs (A0, A1) and provides four mutually
exclusive active LOW outputs (O0 −O3). If the Enable
requirements of each decoder are not met, all outputs of that
decoder are HIGH.
Each decoder section has a 2-input enable gate. The
enable gate for Decoder “a” requires one active HIGH input
and one active LOW input (Ea•Ea). In demultiplexing
applications, Decoder “a” can accept either true or
complemented data by using the Ea or Ea inputs respectively.
The enable gate for Decoder “b” requires two active LOW
inputs (Eb•Eb). The LS155 or LS156 can be used as a 1-of-8
Decoder/Demultiplexer by tying Ea to Eb and relabeling the
common connection as (A2). The other Eb and Ea are
connected together to form the common enable.
The LS156 can be used to generate all four minterms of
two variables. These four minterms are useful in some
applications replacing multiple gate functions as shown in
Fig. a. The LS156 has the further advantage of being able to
f = (E + A0 + A1) ⋅ (E + A0 + A1) ⋅ (E + A0 + A1) ⋅
(E + A0 + A1)
where E = Ea + Ea; E = Eb + Eb
E
A0
A1
E
O0 A0
A1
O0
E
A0
A1
E
O1 A0
A1
O1
E
A0
A1
E
O2 A0
A1
O2
E
A0
A1
E
O3 A0
A1
O3
Figure a
TRUTH TABLE
ADDRESS
ENABLE “a”
OUTPUT “a”
ENABLE “b”
OUTPUT “b”
A0
A1
Ea
Ea
O0
O1
O2
O3
Eb
Eb
O0
O1
O2
O3
X
X
L
H
L
H
X
X
L
L
H
H
L
X
H
H
H
H
X
H
L
L
L
L
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
X
L
L
L
L
X
H
L
L
L
L
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
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2
SN74LS155
SN54/74LS156
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
TA
Operating Ambient Temperature Range
54
74
−55
0
25
25
125
70
°C
VOH
Output Voltage — High
54, 74
5.5
V
IOL
Output Current — Low
54
74
4.0
8.0
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Min
Parameter
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VIK
Input Clamp Diode Voltage
IOH
Output HIGH Current
VOL
Output LOW Voltage
IIH
Input HIGH Current
IIL
Input LOW Current
ICC
Power Supply Current
Typ
Max
V
V
Guaranteed Input LOW Voltage for
All Inputs
−1.5
V
VCC = MIN, IIN = − 18 mA
100
μA
VCC = MIN, VOH = MAX
54
0.7
74
0.8
54, 74
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
2.0
−0.65
Unit
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
54, 74
0.25
0.4
V
IOL = 4.0 mA
74
0.35
0.5
V
IOL = 8.0 mA
20
μA
VCC = MAX, VIN = 2.7 V
0.1
mA
VCC = MAX, VIN = 7.0 V
−0.4
mA
VCC = MAX, VIN = 0.4 V
10
mA
VCC = MAX
Typ
Max
Unit
AC CHARACTERISTICS (TA = 25°C)
Limits
Symbol
Min
Parameter
Test Conditions
tPLH
tPHL
Propagation Delay
Address, Ea or Eb to Output
25
34
40
51
ns
Figure 1
tPLH
tPHL
Propagation Delay
Address to Output
31
34
46
51
ns
Figure 2
tPLH
tPHL
Propagation Delay
Ea to Output
32
32
48
48
ns
Figure 1
VCC = 5.0 V
CL = 15 pF
RL = 2.0 kΩ
AC WAVEFORMS
VIN
VOUT
1.3 V
1.3 V
VIN
tPHL
tPLH
1.3 V
1.3 V
VOUT
Figure 1
1.3 V
1.3 V
tPHL
tPLH
1.3 V
1.3 V
Figure 2
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3
SN74LS155
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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SN74LS155/D
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