DG406, DG407 Datasheet

DG406, DG407
www.vishay.com
Vishay Siliconix
16-Ch/Dual 8-Ch High-Performance CMOS Analog Multiplexers
DESCRIPTION
FEATURES
The DG406 is a 16 channel single-ended analog multiplexer
designed to connect one of sixteen inputs to a common
output as determined by a 4-bit binary address. The DG407
selects one of eight differential inputs to a common
differential output. Break-before-make switching action
protects against momentary shorting of inputs.
•
•
•
•
•
•
•
An on channel conducts current equally well in both
directions. In the off state each channel blocks voltages up
to the power supply rails. An enable (EN) function allows the
user to reset the multiplexer/demultiplexer to all switches off
for stacking several devices. All control inputs, address (Ax)
and enable (EN) are TTL compatible over the full specified
operating temperature range.
Applications for the DG406, DG407 include high speed data
acquisition, audio signal switching and routing, ATE
systems, and avionics. High performance and low power
dissipation make them ideal for battery operated and
remote instrumentation applications.
Designed in the 44 V silicon-gate CMOS process, the
absolute maximum voltage rating is extended to 44 V,
allowing operation with ± 20 V supplies. Additionally
single (12 V) supply operation is allowed. An epitaxial layer
prevents latchup.
For applications information please request documents
70601 and 70604.
Low on-resistance - RDS(on): 50 
Low charge injection - Q: 15 pC
Fast transition time - tTRANS: 200 ns
Low power: 0.2 mW
Single supply capability
44 V supply max. rating
Material categorization:
For definitions of compliance please see
www.vishay.com/doc?99912
Available
Available
Note
* This datasheet provides information about parts that are
RoHS-compliant and/or parts that are non-RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information/tables in this datasheet for details.
BENEFITS
•
•
•
•
•
•
Higher accuracy
Reduced glitching
Improved data throughput
Reduced power consumption
Increased ruggedness
Wide supply ranges: ± 5 V to ± 20 V
APPLICATIONS
•
•
•
•
•
•
•
Data acquisition systems
Audio signal routing
Medical instrumentation
ATE systems
Battery powered systems
High-rel systems
Single supply systems
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG406
DG407
Dual-In-Line and SOIC Wide-Body
V+
NC
NC
Dual-In-Line and SOIC Wide-Body
28
D
V+
1
28
Da
2
27
V-
Db
2
27
V-
3
26
S8
NC
3
26
S8a
S8b
4
25
S7a
1
S16
4
25
S7
S15
5
24
S6
S7b
5
24
S6a
S6b
6
23
S5a
S14
6
23
S5
S13
7
22
S4
S5b
7
22
S4a
S4b
8
21
S3a
20
S2a
S12
8
21
S3
S11
9
20
S2
S3b
9
19
S1
S2b
10
19
S1a
18
EN
S1b
11
18
EN
17
A0
GND
12
17
A0
16
A1
NC
13
16
A1
15
A2
NC
14
15
A2
S10
10
S9
11
GND
12
NC
13
A3
Decoders/Drivers
14
Top View
S13-2518-Rev. K, 09-Dec-13
2
Decoders/Drivers
Top View
Document Number: 70061
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DG406, DG407
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Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
Da
V-
V+
D
28 27 26
Db
V+
1
NC
NC
2
S 8b
NC
3
S8
S 16
4
S 8a
PLCC and LCC
DG407
4
3
2
1
28 27 26
V-
PLCC and LCC
DG406
S15
5
25
S7
S7b
5
25
S7a
S14
6
24
S6
S6b
6
24
S6a
S13
7
23
S5
S5b
7
23
S5a
S12
8
22
S4
S4b
8
22
S4a
S3b
9
21
S3a
20
S2a
19
S1a
S11
9
21
S3
S10
10
20
S2
S2b
10
19
S1
S1b
11
11
EN
A0
A1
A2
NC
NC
GND
EN
NC
A0
12 13 14 15 16 17 18
A1
12 13 14 15 16 17 18
A2
Decoders/Drivers
A3
Decoders/Drivers
GND
S9
Top View
Top View
TRUTH TABLE (DG406)
TRUTH TABLE (DG407)
A3
A2
A1
A0
EN
ON SWITCH
A2
A1
A0
EN
ON SWITCH PAIR
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
None
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
None
1
2
3
4
5
6
7
8
ORDERING INFORMATION (DG406)
TEMP. RANGE
-40 °C to 85 °C
PACKAGE
PART NUMBER
28-Pin Plastic DIP
DG406DJ,
DG406DJ-E3
28-Pin PLCC
DG406DN,
DG406DN-T1-E3
28-Pin Widebody SOIC
DG406DW,
DG406DW-E3,
DG406DW-T1-E3
Notes
• Logic “0” = VAL  0.8 V
• Logic “1” = VAH 2.4 V
• X = Do not Care
ORDERING INFORMATION (DG407)
TEMP. RANGE
-40 °C to 85 °C
PACKAGE
PART NUMBER
28-Pin Plastic DIP
DG407DJ,
DG407DJ-E3
28-Pin PLCC
DG407DN,
DG407DN-T1-E3
28-Pin Widebody SOIC
DG407DW,
DG407DW-E3,
DG407DW-T1-E3
Note
• -T1 indicates Tape and Reel, -E3 indicates Lead-Free and RoHS Compliant, NO -E3 indicates standard Tin/Lead finish.
S13-2518-Rev. K, 09-Dec-13
Document Number: 70061
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DG406, DG407
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ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltages Referenced to V-
LIMIT
V+ to V -f
44
GND to V-
-25
(V-) - 2 to (V+) + 2 V
or 20 mA, whichever occurs first
30
Digital Inputsa, VS, VD
Current (Any terminal)
Peak Current, S or D (Pulsed at 1 ms, 10 % duty cycle max.)
Storage Temperature
Power Dissipation (Package)b
100
(AK, AZ Suffix)
-65 to 150
(DJ, DN Suffix)
-65 to 125
28-Pin Plastic DIPb
625
28-Pin Plastic PLCCc
450
28-Pin Widebody SOIC
450
UNIT
V
mA
°C
mW
Notes
a. Signals on SX, DX or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
b. All leads soldered or welded to PC board.
c. Derate 6 mW/°C above 75 °C.
d. Derate 12 mW/°C above 75 °C.
e. Derate 13.5 mW/°C above 75 °C.
f. Also applies when V- = GND
S13-2518-Rev. K, 09-Dec-13
Document Number: 70061
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DG406, DG407
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SPECIFICATIONSa
PARAMETER
SYMBOL
TEST CONDITIONS
UNLESS OTHERWISE
SPECIFIED
V+ = 15 V, V- = -15 V
VAL = 0.8 V, VAH = 2.4 Vf
D SUFFIX
-40 °C TO 85 °C
TEMP.b
TYP.c
UNIT
MIN.d
MAX.d
Analog Switch
Analog Signal Rangee
Drain-Source 
On-Resistance
RDS(on) Matching Between
Channelsg
Source Off Leakage Current
Drain Off Leakage Current
VANALOG
Full
-
-15
15
V
RDS(on)
VD = ± 10 V, IS = -10 mA
sequence each switch on
Room
50
-
100
Full
50
-
125

RDS(on)
VD = ± 10 V
Room
5
-
-
Room
0.01
-0.5
0.5
Full
0.01
-5
5
Room
0.04
-1
1
40
IS(off)
ID(off)
VEN = 0 V
VD = ± 10 V
VS = ± 10 V
DG406
DG407
Drain On Leakage Current
ID(on)
VS = VD = ± 10
sequence each
switch on
DG406
DG407
Full
0.04
-40
Room
0.04
-1
1
Full
0.04
-20
20
Room
0.04
-1
1
Full
0.04
-40
40
Room
0.04
-1
1
Full
0.04
-20
20
%
nA
Digital Control
Logic High Input Voltage
VINH
Full
-
2.4
-
Logic Low Input Voltage
VINL
Full
-
-
0.8
Logic High Input Current
IAH
VA = 2.4 V, 15 V
Full
-
-1
1
Logic Low Input Current
IAL
VEN = 0 V, 2.4 V, VA = 0 V
Full
-
-1
1
Logic Input Capacitance
Cin
f = 1 MHz
Room
7
-
-
tTRANS
see figure 2
Room
200
-
350
Full
-
-
450
Room
50
25
-
Full
-
10
-
Room
150
-
200
V
μA
pF
Dynamic Characteristics
Transition Time
Break-Before-Make Interval
Enable Turn-On Time
tOPEN
see figure 4
tON(EN)
see figure 3
Enable Turn-Off Time
tOFF(EN)
Charge Injection
Q
Isolationh
OIRR
Off
Source Off Capacitance
Drain Off Capacitance
Drain On Capacitance
CS(off)
CD(off)
CD(on)
VS = 0 V, CL = 1 nF, RS = 0 
VEN = 0 V, RL = 1 k
f = 100 kHz
VEN = 0 V, VS = 0 V, f = 1 MHz
VEN = 0 V
VD = 0 V
f = 1 MHz
Full
-
-
400
Room
70
-
150
ns
Full
-
-
300
Room
15
-
-
pC
Room
-69
-
-
dB
Room
8
-
-
Room
130
-
-
DG407
Room
65
-
-
DG406
Room
140
-
-
DG407
Room
70
-
-
Room
13
-
30
Full
-
-
75
Room
-0.01
-1
-
Full
-
-10
-
Room
50
-
500
-
700
Room
-0.01
-20
-
Full
-0.01
-20
-
pF
Power Supplies
Positive Supply Current
I+
VEN = VA = 0 or 5 V
Negative Supply Current
Positive Supply Current
II+
VEN = 2.4 V, VA = 0 V
Negative Supply Current
S13-2518-Rev. K, 09-Dec-13
I-
Full
μA
Document Number: 70061
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DG406, DG407
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SPECIFICATIONSa (for Single Supply)
PARAMETER
SYMBOL
TEST CONDITIONS
UNLESS OTHERWISE
SPECIFIED
V+ = 12 V, V- = 0 V
VAL = 0.8 V, VAH = 2.4 Vf
D SUFFIX
-40 °C TO 85 °C
TEMP.b
TYP.c
UNIT
MIN.d
MAX.d
Analog Switch
Analog Signal Rangee
Drain-Source 
On-Resistance
RDS(on) Matching Between
Channelsg
Source Off Leakage Current
Drain Off Leakage Current
Drain On Leakage Current
VANALOG
RDS(on)
RDS(on)
IS(off)
ID(off)
ID(on)
VD = 3 V, 10 V, IS = -1 mA
sequence each switch on
VEN = 0 V
VD = 10 V or 0.5 V
VS = 0.5 V or 10 V
VS = VD = ± 10 V
sequence each
switch on
Full
-
0
12
V
Room
90
-
120

Room
5
-
-
%
Room
0.01
-
-
DG406
Room
0.04
-
-
DG407
Room
0.04
-
-
DG406
Room
0.04
-
-
DG407
Room
0.04
-
-
nA
Dynamic Characteristics
Switching Time of Multiplexer
tOPEN
VS1 = 8 V, VS8 = 0 V, VIN = 2.4 V
Room
300
-
450
Enable Turn-On Time
tON(EN)
Room
250
-
600
Enable Turn-Off Time
tOFF(EN)
VINH = 2.4 V, VINL = 0 V
VS1 = 5 V
Room
150
-
300
Q
CL = 1 nF, VS = 6 V, RS = 0
Room
20
-
-
Room
13
-
30
Full
-
-
75
Room
-0.01
-20
-
Full
-0.01
-20
-
Charge Injection
ns
pC
Power Supplies
Positive Supply Current
I+
Negative Supply Current
I-
VEN = 0 V or 5 V, VA = 0 V or 5 V
μA
Notes
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25 °C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
g. RDS(on) = RDS(on) max. - RDS(on) min.
h. Worst case isolation occurs on Channel 4 due to proximity to the drain pin.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
S13-2518-Rev. K, 09-Dec-13
Document Number: 70061
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
DG406, DG407
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TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
160
80
RDS(on) - On-Resistance (Ω)
RDS(on) - On-Resistance (Ω)
70
120
± 5V
80
±8V
± 10 V
± 12 V
± 15 V
40
125 °C
60
85 °C
50
25 °C
40
0 °C
30
- 40 °C
20
- 55 °C
± 20 V
10
0
- 20
- 12
-4
4
VD - Drain Voltage (V)
12
V+ = 15 V
V- = - 15 V
0
- 15
20
- 10
-5
0
5
10
15
10
15
VD - Drain Voltage (V)
RDS(on) vs. VD and Supply
RDS(on) vs. VD and Temperature
120
V- = 0 V
240
V+ = 15 V
V- = - 15 V
VS = - VD for ID(off)
VD = V S(open) for ID(on)
80
200
I D , I S - Current (pA)
RDS(on) - On-Resistance (Ω)
V+ = 7.5 V
160
10 V
120
12 V
15 V
80
20 V
40
IS(off)
0
DG406 ID(on), ID(off)
- 40
22 V
DG407 ID(on), ID(off)
- 80
40
0
0
4
8
12
16
- 120
- 15
20
VD - Drain Voltage (V)
0
5
ID , IS Leakage Currents vs. Analog Voltage
350
100 nA
V+ = 15 V
V- = - 15 V
VD = "14 V
300
tTRANS
250
1 nA
ID(on), ID(off)
Time (ns)
I D , I S - Current
-5
VS , V D - Source Drain Voltage (V)
RDS(on) vs. VD and Supply
10 nA
- 10
100 pA
200
tON(EN)
150
IS(off)
10 pA
100
tOFF(EN)
1 pA
50
0.1 pA
- 55 - 35 - 15
0
5
25
45
65
85
Temperature (°C)
ID, IS Leakages vs. Temperature
S13-2518-Rev. K, 09-Dec-13
105
125
±5
± 10
± 15
± 20
VSUPPLY - Supply Voltage (V)
Switching Times vs. Bipolar Supplies
Document Number: 70061
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TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
70
700
600
60
500
50
tTRANS
400
Q (pC)
Time (ns)
V- = 0 V
300
40
V+ = 12 V,
V- = 0 V
30
tON(EN)
200
V+ = 15 V,
V- = - 15 V
20
100
10
tOFF(EN)
0
5
10
15
0
- 15
20
- 10
-5
0
5
15
VS - Source Voltage (V)
V+ - Supply Voltage (V)
Charge Injection vs. Analog Voltage
Switching Times vs. Single Supply
- 140
10
EN = 5 V
AX = 0 or 5 V
8
- 120
I+
6
- 100
4
I - Current (mA)
ISOL (dB)
10
- 80
- 60
2
0
-2
IGND
-4
- 40
I-6
- 20
-8
0
- 10
100
1K
10K
100K
1M
10
10M
100
1K
1M
10M
Supply Currents vs. Switching Frequency
Off-Isolation vs. Frequency
300
3
V+ = 15 V
V- = - 15 V
2
220
tTRANS
V TH (V)
Time (ns)
100K
f - Frequency (Hz)
f - Frequency (Hz)
260
10K
tON(EN)
180
1
140
100
tOFF(EN)
0
60
- 55 - 35 - 15
5
25
45
65
Temperature (°C)
tON/tOFF vs. Temperature
S13-2518-Rev. K, 09-Dec-13
85
105
125
0
5
10
15
20
VSUPPLY - Supply Voltage (V)
Switching Threshold vs. Supply Voltage
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SCHEMATIC DIAGRAM (Typical Channel)
V+
VREF
GND
D
A0
V+
Level
Shift
AX
V-
Decode/
Drive
S1
V+
EN
Sn
V-
Fig. 1
TEST CIRCUITS
+ 15 V
+ 2.4 V
V+
EN
A2
A1
± 10 V
S1
A3
S2 - S 15
DG406
S16
A0
± 10 V
VO
D
GND
Logic
Input
V-
tr < 20 ns
tf < 20 ns
3V
50 %
0V
50 Ω
35 pF
300 Ω
- 15 V
VS1
90 %
Switch
Output
+ 15 V
+ 2.4 V
V+
EN
A2
VO
S1b
0V
90 %
± 10 V
VS8
*
DG407
S8b
A1
A0
tTRANS
± 10 V
S1 ON
Db
GND
tTRANS
S8 ON
VO
V-
50 Ω
300 Ω
35 pF
- 15 V
* = S1a - S 8a, S2b S ± 7b, Da
Fig. 2 - Transition Time
S13-2518-Rev. K, 09-Dec-13
Document Number: 70061
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TEST CIRCUITS
+ 15 V
V+
A3
A1
A0
-5V
S1
A2
S2 - S 16
DG406
VO
D
EN
GND
V35 pF
300 Ω
50 Ω
Logic
Input
- 15 V
tr < 20 ns
tf < 20 ns
3V
50 %
0V
tON(EN)
0V
+ 15 V
V+
A2
S1b
S1a - S 8a
S2b - S 8b
A1
A0
tOFF(EN)
Switch
Output
-5V
VO
90 %
90 %
VO
DG407
Da and Db
EN
GND
VO
V-
35 pF
50 Ω
300 Ω
- 15 V
Fig. 3 - Enable Switching Time
+ 15 V
Logic
Input
V+
EN
+ 2.4 V
All S and Da
A3
A2
A1
+5V
tr < 20 ns
tf < 20 ns
3V
50 %
0V
DG406
DG407
A0
GND
50 Ω
VS
VO
D,D b
80 %
Switch
Output
V300 Ω
35 pF
VO
- 15 V
0V
tOPEN
Fig. 4 - Break-Before-Make Interval
S13-2518-Rev. K, 09-Dec-13
Document Number: 70061
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DG406, DG407
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APPLICATIONS HINTS
Sampling speed is limited by two consecutive events: the
transition time of the multiplexer, and the settling time of the
sampled signal at the output.
tTRANS is given on the data sheet. Settling time at the load
depends on several parameters: RDS(on) of the multiplexer,
source impedance, multiplexer and load capacitances,
charge injection of the multiplexer and accuracy desired.
The settling time for the multiplexer alone can be derived
from the model shown in figure 5. Assuming a low
impedance signal source like that presented by an op amp
or a buffer amplifier, the settling time of the RC network for
a given accuracy is equal to n:
For the DG406 then, at room temp and for 12-bit accuracy,
using the maximum limits:
1
(2)
f s = -------------------------------------------------------------------------------------------------------- 12
- 12
16  9  100   10
F  + 300  10 s
or
f s = 694 kHz
(3)
From the sampling theorem, to properly recover the original
signal, the sampling frequency should be more than twice
the maximum component frequency of the original signal.
This assumes perfect bandlimiting. In a real application
sampling at three to four times the filter cutoff frequency is
a good practice.
Therefore from equation 2 above:
% ACCURACY
# BITS
N
0.25
8
6
0.012
12
9
0.0017
15
11
R DS(on)
VOUT
RS = 0
CD(on)
Fig. 5 - Simplified Model of One Multiplexer Channel
The maximum sampling frequency of the multiplexer is:
1
f s = ------------------------------------------------------------- (1)
N  t SETTLING + t TRANS 

where N = number of channels to scan
tSETTLING = n = n x RDS(on) x CD(on)
To
Sensor 1
To
Sensor 8
Analog
Multiplexer
1
f c = ---  f s = 173 kHz
(4)
4

From this we can see that the DG406 can be used to sample
16 different signals whose maximum component frequency
can be as high as 173 kHz. If for example, two channels are
used to double sample the same incoming signal then its
cutoff frequency can be doubled.
The block diagram shown in figure 6 illustrates a typical data
acquisition front end suitable for low-level analog signals.
Differential multiplexing of small signals is preferred since
this method helps to reject any common mode noise. This
is especially important when the sensors are located at a
distance and it may eliminate the need for individual
amplifiers. A low RDS(on), low leakage multiplexer like the
DG407 helps to reduce measurement errors. The low power
dissipation of the DG407 minimizes on-chip thermal
gradients which can cause errors due to temperature
mismatch along the parasitic thermocouple paths. Please
refer to Application Note AN203 for additional information.
Inst
Amp
DG407
S/H
12-Bit
A/D
Converter
Controller
Fig. 6 - Measuring Low-Level Analog Signals is more accurate when using a Differential Multiplexing Technique

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Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?70061.
S13-2518-Rev. K, 09-Dec-13
Document Number: 70061
10
For technical questions, contact: analogswitchsupport@vishay.com
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
PDIP: 28ĆLEAD
28
27
26
25
24
23
22
21
20
19
18
17
16
15
E1
1
2
3
4
5
6
7
8
9
10
11
12
13
E
14
D
Q1
S
A(1)
A
L
A1
L
15°
MAX.
C
e1
B1
Dim
A
A1
B
B1
C
D
E
E1
e1
eA
L
Q1
S
eA
B
MILLIMETERS
Min
Max
INCHES
Min
Max
2.29
5.08
0.090
0.200
0.39
1.77
0.015
0.070
0.38
0.56
0.015
0.022
0.89
1.65
0.035
0.065
0.204
0.30
0.008
0.012
35.10
39.70
1.380
1.565
15.24
15.88
0.600
0.625
13.21
14.73
0.520
0.580
2.29
2.79
0.090
0.110
14.99
15.49
0.590
0.610
2.60
5.08
0.100
0.200
0.95
2.345
0.0375
0.0925
0.995
2.665
0.0375
0.105
ECN: S-03946—Rev. F, 09-Jul-01
DWG: 5488
Document Number: 71243
06-Jul-01
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Package Information
Vishay Siliconix
PLCC: 28-LEAD
D-SQUARE
MILLIMETERS
MIN.
MAX.
A
4.20
4.57
2.29
3.04
A1
0.51
A2
B
0.331
0.553
0.661
0.812
B1
D
12.32
12.57
11.430
11.582
D1
9.91
10.92
D2
1.27 BSC
e1
ECN: T09-0766-Rev. D, 28-Sep-09
DWG: 5491
DIM.
A2
INCHES
MIN.
MAX.
0.165
0.180
0.090
0.120
0.020
0.013
0.021
0.026
0.032
0.485
0.495
0.450
0.456
0.390
0.430
0.050 BSC
e1
B1
D2
B
D1-SQUARE
A1
D
A
Document Number: 71264
28-Sep-09
0.101 mm
0.004"
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Package Information
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SOIC (WIDE-BODY): 28-LEADS
0.06 0.002D
CAVITY NO.
0.3525 0.001
0.334 0.005
28 27
26 25 24 23 22 21
20 19
18
R0.004
17 16 15
0.010
0.1475 0.001
R0.008
0.295 0.001
R0.009
1
2 3
4
5
6
7
8
9
10
11
12 13 14
4°
R0.004
2°
0.032 0.005
0.070 0.005
0.055 0.005
DETAIL A
PIN 1 INDICATOR
0.047 0.007 0.001 dp
SURFACE POLISHED
0.334 0.005
0.291 0.001
0.091 0.001
0.020 45°
0.705 0.001
0.098 0.002
R0.004
0.00825 ± 0.00325
0.041 0.001
0.050 TYP.
0.017 0.0003
7°(4 )
0.295 0.001
0.406 0.004
DETAIL A
All Dimensions In Inches
ECN: E11-2209-Rev. D, 01-Aug-11
DWG: 5850
Revision: 01-Aug-11
1
Document Number: 71268
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Package Information
Vishay Siliconix
28ĆLEAD LCC
A1
D
L1
A
28
e
1
2
L
Document Number: 71278
02-Jul-01
E
Dim
A
A1
B
D
E
e
L
L1
MILLIMETERS
Min
Max
INCHES
Min
Max
1.37
2.24
0.054
0.088
1.63
2.54
0.064
0.100
0.56
0.71
0.022
0.028
11.23
11.63
0.442
0.458
11.23
11.63
0.442
0.458
1.27 BSC
0.050 BSC
1.14
1.40
0.045
0.055
1.96
2.36
0.077
0.093
ECN: S-03946—Rev. B, 09-Jul-01
DWG: 5319
B
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Package Information
Vishay Siliconix
CERDIP: 28ĆLEAD
28
E1
E
1
2
3
D
Q1
S
A
L1
A1
B1
L
e1
C
B
eA
MILLIMETERS
Dim
A
A1
B
B1
C
D
E
E1
e1
eA
L
L1
Q1
S
∝
INCHES
Min
Max
Min
Max
4.06
5.92
0.160
0.232
0.38
1.52
0.015
0.060
0.38
0.51
0.015
0.020
1.14
1.65
0.045
0.065
0.20
0.30
0.008
0.012
36.58
37.08
1.440
1.460
15.24
15.88
0.600
0.625
12.95
13.46
0.510
0.530
2.54 BSC
∝
0.100 BSC
15.24 BSC
0.600 BSC
3.18
3.81
0.125
0.150
3.81
5.08
0.150
0.200
1.27
2.16
0.050
0.085
1.52
2.29
0.060
0.090
0°
15°
0°
15°
ECN: S-03946—Rev. E, 09-Jul-01
DWG: 5434
Document Number: 71283
03-Jul-01
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Revision: 02-Oct-12
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Document Number: 91000