318G-02

MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−6
CASE 318G−02
ISSUE V
1
SCALE 2:1
D
H
ÉÉ
ÉÉ
6
E1
1
NOTE 5
5
2
L2
4
GAUGE
PLANE
E
3
L
b
DETAIL Z
e
C
SEATING
PLANE
DIM
A
A1
b
c
D
E
E1
e
L
L2
M
c
A
0.05
M
DATE 12 JUN 2012
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
A1
DETAIL Z
MIN
0.90
0.01
0.25
0.10
2.90
2.50
1.30
0.85
0.20
0°
MILLIMETERS
NOM
MAX
1.00
1.10
0.06
0.10
0.38
0.50
0.18
0.26
3.00
3.10
2.75
3.00
1.50
1.70
0.95
1.05
0.40
0.60
0.25 BSC
10°
−
STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
STYLE 2:
PIN 1. EMITTER 2
2. BASE 1
3. COLLECTOR 1
4. EMITTER 1
5. BASE 2
6. COLLECTOR 2
STYLE 3:
PIN 1. ENABLE
2. N/C
3. R BOOST
4. Vz
5. V in
6. V out
STYLE 4:
PIN 1. N/C
2. V in
3. NOT USED
4. GROUND
5. ENABLE
6. LOAD
STYLE 5:
PIN 1. EMITTER 2
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
6. COLLECTOR 2
STYLE 6:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTOR
STYLE 7:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. N/C
5. COLLECTOR
6. EMITTER
STYLE 8:
PIN 1. Vbus
2. D(in)
3. D(in)+
4. D(out)+
5. D(out)
6. GND
STYLE 9:
PIN 1. LOW VOLTAGE GATE
2. DRAIN
3. SOURCE
4. DRAIN
5. DRAIN
6. HIGH VOLTAGE GATE
STYLE 10:
PIN 1. D(OUT)+
2. GND
3. D(OUT)−
4. D(IN)−
5. VBUS
6. D(IN)+
STYLE 11:
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
6. DRAIN 1/GATE 2
STYLE 12:
PIN 1. I/O
2. GROUND
3. I/O
4. I/O
5. VCC
6. I/O
STYLE 13:
PIN 1. GATE 1
2. SOURCE 2
3. GATE 2
4. DRAIN 2
5. SOURCE 1
6. DRAIN 1
STYLE 14:
PIN 1. ANODE
2. SOURCE
3. GATE
4. CATHODE/DRAIN
5. CATHODE/DRAIN
6. CATHODE/DRAIN
STYLE 15:
PIN 1. ANODE
2. SOURCE
3. GATE
4. DRAIN
5. N/C
6. CATHODE
STYLE 16:
PIN 1. ANODE/CATHODE
2. BASE
3. EMITTER
4. COLLECTOR
5. ANODE
6. CATHODE
STYLE 17:
PIN 1. EMITTER
2. BASE
3. ANODE/CATHODE
4. ANODE
5. CATHODE
6. COLLECTOR
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.60
XXXAYWG
G
1
6X
3.20
XXX
A
Y
W
G
0.95
PITCH
DIMENSIONS: MILLIMETERS
STATUS:
ON SEMICONDUCTOR STANDARD
1
NEW STANDARD:
TSOP−6
XXX = Specific Device Code
M
= Date Code
G
= Pb−Free Package
*This information is generic. Please refer to device data sheet
for actual part marking. Pb−Free indicator, “G” or microdot “
G”, may or may not be present.
98ASB14888C
© Semiconductor Components Industries, LLC, 2002
October, DESCRIPTION:
2002 Rev. 0
= Specific Device Code
=Assembly Location
= Year
= Work Week
= Pb−Free Package
STANDARD
(Note: Microdot may be in either location)
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
1
IC
0.95
XXX MG
G
http://onsemi.com
1
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
Case Outline Number:
PAGE 1 OFXXX
2
DOCUMENT NUMBER:
98ASB14888C
PAGE 2 OF 2
ISSUE
REVISION
DATE
B
ADDED STYLE 2. REQ.BY A. PATEL.
05 MAY 1997
C
ADDED STYLE 3. REQ.BY D. BOLDT, ADDED STYLE 4. REQ.BY UKO.
14 APR 1998
D
ADDED STYLE 5. REQ.BY D. BOLDT.
13 MAY 1998
E
ADDED STYLE 6. REQ.BY M. ATANOVICH.
17 NOV 1999
F
MOTOROLA WAS NOT REMOVED FROM (STATUS) PAGES. PAGES NOT NUMBERED CORRECTLY. REV PAGE WAS MISSING. REQ.BY F. BLAKLEY.
22 NOV 1999
G
ADDED STYLE 7. REQ.BY M. ATANOVICH.
15 DEC 1999
H
ADDED STYLE 8. REQ.BY D. TRUHITTE.
11 MAY 2001
J
ADDED NOTE 4. REQ. BY S. RIGGS.
26 JUN 2003
K
ADDED STYLE 9. REQ.BY S. BACHMAN.
09 SEP 2003
L
ADDED STYLE 10. REQ. BY A. TAM.
25 FEB 2004
M
ADDED STYLE 11 AND 12. REQ. BY L. ROBINSON.
07 JUN 2004
N
CORRECTED STYLE 11, PIN 4 SOURCE 2. REQ. BY C. CHENG .
03 FEB 2005
P
ADDED NOMINAL VALUES AND UPDATED GENERIC MARKING DIAGRAM. REQ.
BY HONG XIAO.
27 MAY 2005
R
ADDED STYLE 13. REQ. BY J. CARTER.
09 MAR 2006
S
ADDED STYLE 14. REQ. BY A. SAM.
22 MAR 2006
T
ADDED STYLE 15. REQ. BY S. WINSTON.
06 FEB 2008
U
ADDED DETAIL Z, REMOVED INCH VALUES, ADDED L2, ADDED NOTE 5. REQ.
BY J. LETTERMAN.
14 JAN 2010
V
ADDED STYLES 16 & 17. REQ. BY Y. KALDERON.
12 JUN 2012
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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© Semiconductor Components Industries, LLC, 2012
June, 2012 − Rev. V
Case Outline Number:
318G
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