X80140, X80141, X80142, X80143, X80144 ® Data Sheet PRELIMINARY January 20, 2005 Voltage Supervisor/Sequencer Quad Programmable Time Delay with Local/Remote Voltage Monitors Features The X80140 is a voltage supervisor/sequencer with four built in voltage monitors. This allows the designer to monitor up to four voltages and sequence up to five events. Low voltage detection circuitry protects the system from power supply failure or “brown out” conditions, resetting the system and resequencing the voltages when any of the monitored inputs fall below the minimum threshold level. The RESET pin is active until all monitored voltages reach proper operating levels and stabilize for a selectable period of time. Five common low voltage combinations are available, however, Intersil’s unique circuits allow the any voltage monitor threshold to be reprogrammed for special needs or for applications requiring higher precision. A manual reset input provides debounce circuitry for minimum reset component count. Activating the manual reset both controls the RESET output and resequences the supplies through control of the ViGDO pins. The X80140 has 2kb of EEPROM for system configuration, manufacturing or maintenance information. This memory is protected to prevent inadvertent changes to the contents. Pinout VSS MR NC VCC A0 5X5 QFN TOP VIEW 20 19 18 17 16 V4GDO 1 15 V4MON 2 14 RESET V3GDO 3 13 V3MON 4 12 V1GDO V1MON V2GDO 5 11 SCL (5mm x 5mm) 1 • Quad Voltage Monitor and Sequencing - Four independent voltage monitors - Four time delay circuits (in circuit programmable) - Remote delay via SMBus - Factory programmable voltage thresholds - Sequence up to 5 power supplies. • Fault Detection Register - Remote diagnostics of voltage fail event. • Debounced Manual Reset Input • Manufacturing/Configuration Memory - 2Kbits of EEPROM - 400kHz SMBus interface • Available Packages - 20-lead Quad No-Lead Frame (QFN - 5x5mm) Applications • • • • • • • • • • • • • • • • • General Purpose Timers Long Time Delay Generation Cycle Timers / Waveform Generation ON/OFF Delay Timers Supply Sequencing for Distributed Power Programmable Delay Event Sequencing Multiple DC-DC ON/OFF Sequencing Voltage Window Monitoring with Reset ON/OFF Switches with Programmable Delay Voltage Supervisor with Programmable Output Delays Databus Power Sequencing 100 ms to 5 secs Selectable Delay Switches ATE or Data Acquisition Timing Applications Datapath/Memory Timing Applications Data Pipeline Timing Applications Batch Timer/Sequencers Adjustable Duty Cycle Applications SDA 9 10 A1 8 DNC VP 7 V2MON 6 WP FN8153.0 Ordering Information PART NUMBER VREF1 VREF2 VREF3 VREF4 PACKAGE X80140Q20I 4.5 3.0 2.25 0.9 QFN X80141Q20I 4.5 2.25 0.9 0.9 QFN X80142Q20I 3.0 2.25 1.7 0.9 QFN X80143Q20I 3.0 2.25 0.9 0.9 QFN X80144Q20I 2.25 2.25 0.9 0.9 QFN CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X80140, X80141, X80142, X80143, X80144 Block Diagram RESET VCC POR CONTROL AND FAULT REGISTERS RESET LOGIC AND DELAY MR BUS INTERFACE SDA VSS SCL WP A0 A1 EEPROM 2kbits VP OSC VMON LOGIC DIVIDER VSS 4 Reset V1MON V1GDO 4 VREF1 V2MON Select 0.1s 0.5s 1s 5s V2GDO VREF2 delay1 V3MON V3GDO delay2 VREF3 delay3 V4MON VREF4 Delay circuit repeated 4 times VSS 2 V4GDO delay4 VSS FN8153.0 January 20, 2005 X80140, X80141, X80142, X80143, X80144 Absolute Maximum Ratings Recommended Operating Conditions Temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C ViMON pins (i = 1 to 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V ViGDO pins (i = 1 to 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V SDA, SCL, WP, A0, A1 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V MR pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V VP pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14V D.C. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . 300°C Temperature Range (Industrial) . . . . . . . . . . . . . . . . . . -40°C to 85°C VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 to 5.5V CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Electrical Specifications SYMBOL (Standard Setting) Over the recommended operating conditions unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 5.5 V 2.5 mA 12 V 10 mA 10 µA 15 µA DC CHARACTERISTICS VCC Supply Operating Range ICC Supply Current VP (Note 3) 4.5 fSCL = 0kHz EEPROM programming voltage 1.0 9 IP Programming Current ILI Input Leakage Current (MR) ILO Output Leakage Current (V1GDO, V2GDO, V3GDO, V4GDO, RESET) VIL Input LOW Voltage (MR) -0.5 VCC x 0.3 V VIH Input HIGH Voltage (MR) VCC x 0.7 5.5 V VOL Output LOW Voltage (RESET, V1GDO, V2GDO, V3GDO, V4GDO) IOL = 4.0mA 0.4 V COUT (Note 1) Output Capacitance (RESET, V1GDO, V2GDO, V3GDO, V4GDO) VOUT = 0V 8 pF 4.70 V VREF1 VREF2 VIL = GND to VCC V1MON Trip Point Voltage (Range) 2.20 X80140 4.45 4.50 4.55 V X80141 4.45 4.50 4.55 V X80142 2.95 3.00 3.05 V X80143 2.95 3.00 3.05 V X80144 2.20 2.25 2.30 V 4.70 V V2MON Trip Point Voltage 3 2.20 X80140 2.95 3.00 3.05 V X80141 2.20 2.25 2.30 V X80142 2.20 2.25 2.30 V X80143 2.20 2.25 2.30 V X80144 2.20 2.25 2.30 V FN8153.0 January 20, 2005 X80140, X80141, X80142, X80143, X80144 Electrical Specifications SYMBOL (Standard Setting) Over the recommended operating conditions unless otherwise specified. (Continued) PARAMETER VREF3 TEST CONDITIONS MIN V3MON Trip Point Voltage VREF4 0.85 MAX UNIT 3.50 V X80140 2.20 2.25 2.30 V X80141 0.85 0.90 0.95 V X80142 1.65 1.70 1.75 V X80143 0.85 0.90 0.95 V X80144 0.85 0.90 0.95 V 3.50 V 0.95 V -100 mV V4MON Trip Point Voltage 0.85 All Devices VREF TYP Voltage Reference Long Term Drift 0.85 10 years 0.90 0 AC CHARACTERISTICS tMR (Note 3) Minimum time high for reset valid on the MR pin tMRE (Note 3) Delay from MR enable to V1GDO HIGH tDPOR (Note 3) Internal Device Delay on power up tTO (Note 3) ViGDO turn off time tSPOR tDELAYi 45 50 1.6 µs 55 ms 50 Electrical Specifications SYMBOL µs 5 ns (Programmable Parameters) Over the recommended operating conditions unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Delay before RESET assertion TPOR1 = 0 TPOR0 = 0 Factory Default 90 100 110 ms TPOR1 = 0 TPOR0 = 1 (Note 3) 450 500 550 ms TPOR1 = 1 TPOR0 = 0 (Note 3) 0.9 1 1.1 s TPOR1 = 1 TPOR0 = 1 (Note 3) 4.5 5 5.5 s Time Delay used in Power Sequencing (i = 1 to 4) TiD1 = 0 TiD0 = 0 Factory Default 90 100 110 ms TiD1 = 0 TiD0 = 1 (Note 3) 450 500 550 ms TiD1 = 1 TiD0 = 0 (Note 3) 0.9 1 1.1 s TiD1 = 1 TiD0 = 1 (Note 3) 4.5 5 5.5 s Equivalent A.C. Output Load Circuit Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns V1GDO, Input and output timing levels VCC x 0.5 V2GDO, Output load Standard output load 4.6kΩ 4.6kΩ 4.6kΩ A.C. Test Conditions 5V 5V 5V RESET SDA V3GDO, 30pF 30pF 4 V4GDO 30pF FN8153.0 January 20, 2005 X80140, X80141, X80142, X80143, X80144 Initial Power-up VCC VREFi tDPOR ViMON tDELAYi tTO tDELAYi ViGDO i = 1, 2, 3, 4 FIGURE 1. INITIAL POWER UP AND DELAY TIMING Symbol Table WAVEFORM INPUTS tMR MR ViGDO tDELAYi RESET tDELAYi tMRE OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known + tSPOR FIGURE 2. MANUAL RESET (MR) MR ViMON (i= 1 to 4) tDELAY1 tDELAY1 V1GDO tDELAY2 tDELAY2 V2GDO tDELAY3 tDELAY3 V3GDO tDELAY4 tDELAY4 V4GDO tSPOR tSPOR RESET Any ViGDO (1st occurance) FIGURE 3. ViGDO, RESET TIMINGS 5 FN8153.0 January 20, 2005 X80140, X80141, X80142, X80143, X80144 Serial Interface Over the recommended operating conditions unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC CHARACTERISTICS ICC1 Active Supply Current (VCC) Read or Write to Memory or registers VIL = VCC x 0.1 VIH = VCC x 0.9, fSCL = 400kHz 2.5 mA ILI Input Leakage Current (SCL, WP, A0, A1) VIL = GND to VCC 15 µA ILO Output Leakage Current (SDA) VSDA = GND to VCC Device is in Standby 15 µA VIL Input LOW Voltage (SDA, SCL, WP, A0, A1) -0.5 VCC x 0.3 V VIH Input HIGH Voltage (SDA, SCL, WP, A0, A1) VCC x 0.7 5.5 V VHYS VOL Schmidt Trigger Input Hysteresis Fixed input level 0.2 V VCC related level 0.05 x 5 V Output LOW Voltage (SDA) IOL = 4.0mA 0.4 V 400 kHz AC CHARACTERISTICS fSCL tIN tAA (Note 1) SCL Clock Frequency Pulse width Suppression Time at inputs 50 SCL LOW to SDA Data Out Valid 0.1 tBUF (Note 1) Time the bus is free before start of new transmission ns 1.5 µs 1.3 µs tLOW Clock LOW Time 1.3 µs tHIGH Clock HIGH Time 0.6 µs tSU:STA Start Condition Setup Time 0.6 µs tHD:STA Start Condition Hold Time 0.6 µs tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0 µs tSU:STO Stop Condition Setup Time 0.6 µs tHD:STO Stop Condition Hold Time 0.6 µs 50 ns tDH (Note 1) Data Output Hold Time tR (Note 1) SDA and SCL Rise Time 20 +.1Cb 300 ns tF (Note 1) SDA and SCL Fall Time 20 +.1Cb 300 ns tSU:WP WP Setup Time 0.6 µs tHD:WP WP Hold Time 0 µs tSU:ADR A0, A1 Setup Time 0.6 µs tHD:ADR A0, A1 Hold Time 0 µs 0.6 µs tSU:VP Cb (Note 3) VP Setup Time Capacitive load for each bus line tWC (Note 2) EEPROM Write Cycle Time 5 400 pF 10 ms NOTES: 1. This parameter is based on characterization data. 2. tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. 3. This parameter is not 100% tested. 6 FN8153.0 January 20, 2005 X80140, X80141, X80142, X80143, X80144 Timing Diagrams tBUF tF tHIGH tR tLOW tBUF SCL tSU:DAT tSU:STA tHD:DAT tSU:STO tHD:STO tHD:STA SDA IN tAA tDH tHD:DAT SDA OUT FIGURE 4. BUS TIMING STOP START SCL Clk 1 Clk 9 Slave Address Byte SDA IN tSU:WP tHD:WP tSU:ADR tHD:ADR WP A1, A0 tWC tSU:VP VP FIGURE 5. WP, A0, A1, VP PIN TIMING SCL SDA 8th Bit of Last Byte ACK tWC Stop Condition Start Condition FIGURE 6. WRITE CYCLE TIMING 7 FN8153.0 January 20, 2005 X80140, X80141, X80142, X80143, X80144 Pin Configuration VSS MR NC VCC A0 X80140/1/2/3/4 20 19 18 17 16 V4GDO 1 15 WP V4MON 2 14 RESET V3GDO 3 13 V3MON 4 12 V1GDO V1MON V2GDO 5 11 SCL 7 8 9 10 V2MON DNC A1 SDA 6 VP (5mm x 5mm) Pin Descriptions PIN NAME DESCRIPTION 1 V4GDO V4 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V4MON is less than VREF4 and goes LOW when V4MON is greater than VREF4. There is user selectable delay circuitry on this pin. 2 V4MON V4 Voltage Monitor Input. Fourth voltage monitor pin. If unused connect to VCC. 3 V3GDO V3 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V3MON is less than VREF3 and goes LOW when V3MON is greater than VREF3. There is user selectable delay circuitry on this pin. 4 V3MON V3 Voltage Monitor Input. Third voltage monitor pin. If unused connect to VCC. 5 V2GDO V2 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V2MON is less than VREF2 and goes LOW when V2MON is greater than VREF2. There is user selectable delay circuitry on this pin. 6 VP 7 V2MON 8 DNC 9 A1 10 SDA Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated). 11 SCL Serial Clock. The Serial Clock controls the serial bus timing for data input and output. 12 V1MON V1 Voltage Monitor Input. First voltage monitor pin. If unused connect to VCC. 13 V1GDO V1 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V1MON is less than VREF1 and goes LOW when V1MON is greater than VREF1. There is user selectable delay circuitry on this pin. 14 RESET RESET Output. This open drain pin is an active LOW output. This pin will be active until all ViGDO pins go inactive and the power sequencing is complete. This pin will be released after a programmable delay. 15 WP Write Protect. Input Pin. WP HIGH (in conjunction with WPEN bit=1) prevents writes to any memory location in the device. It has an internal pull-down resistor. (>10MΩ typical) 16 MR Manual Reset. Pulling the MR pin HIGH initiates a RESET. The MR signal must be held HIGH for 5µsecs. It has an internal pull-down resistor. (>10MΩ typical) 17 VSS Ground Input. 18 NC No Connect. No internal connections. 19 A0 Address Select Input. It has an internal pull-down resistor. (>10MΩ typical) The A0 and A1 bits allow for up to 4 X80140 devices to be used on the same SMBus serial interface. 20 VCC EEPROM programming Voltage. V2 Voltage Monitor Input. Second voltage monitor pin. If unused connect to VCC. Do Not Connect. Address Select Input. It has an internal pull-down resistor. (>10MΩ typical) The A0 and A1 bits allow for up to 4 X80140 devices to be used on the same SMBus serial interface. Supply Voltage. 8 FN8153.0 January 20, 2005 X80140, X80141, X80142, X80143, X80144 Functional Description Power On Reset and System Reset With Delay Application of power to the X80140 activates a Power On Reset circuit that pulls the RESET pin active. This signal, if used, prevents the system microprocessor from starting to operate while there is insufficient voltage on any of the supplies. This circuit also does the following: • It prevents the processor from operating prior to stabilization of the oscillator. • It allows time for an FPGA to download its configuration prior to initialization of the circuit. • It prevents communication to the EEPROM during unstable power conditions, greatly reducing the likelihood of data corruption on power up. • It allows time for all supplies to turn on and stabilize prior to system initialization. The POR/RESET circuit is activated when all voltages are within specified ranges and the V1GDO, V2GDO, V3GDO, and V4GDO time-out conditions are met. The POR/RESET circuit will then wait tSPOR and de-assert the RESET pin. The POR delay may be changed by setting the TPOR bits in register CR2. The delay can be set to 100ms, 500ms, 1 second, or 5 seconds. TABLE 1. POR RESET DELAY OPTIONS TPOR1 TPOR0 tSPOR DELAY BEFORE RESET ASSERTION 0 0 100 milliseconds (default) 0 1 500 milliseconds 1 0 1 second 1 1 5 seconds Each ViGDO signal remains active until its associated ViMON input rises above the threshold. TABLE 2. VIGDO OUTPUT TIME DELAY OPTIONS TiD1 TiD0 tDELAYi 0 0 100ms (default) 0 1 500ms 1 0 1 secs 1 1 5 secs where i is the specific voltage monitor (i = 1 to 4). Fault Detection The X80140 contains a Fault Detection Register (FDR) that provides the user the status of the causes for a RESET pin active (See Table 20). At power-up, the FDR is defaulted to all “0”. The system needs to initialize the register to 0Fh before the actual monitoring can take place. In the event that any one of the monitored sources fail, the corresponding bit in the register changes from a “1” to a “0” to indicate the failure. When a RESET is detected by the main controller, the controller should read the FDR and note the cause of the fault. After reading the register, the controller can reset the register bit back to all “1” in preparation for future failure conditions. Flexible Power Sequencing of Multiple Power Supplies The X80140 provides several circuits such as multiple voltage monitors, programmable delays, and output drive signals that can be used to set up flexible power monitoring or sequencing schemes system power supplies. Below are two examples: Manual Reset 1. Power Up of Supplies In Parallel Using Programmable Delays. (See Figure 7 and Figure 8). The manual reset option allows a hardware reset of the power sequencing pins. These can be used to recover the system in the event of an abnormal operating condition. Activating the MR pin for more than 5us sets all of the ViGDO outputs and the RESET output active (LOW). When MR is released (and if all supplies are still at their proper operating voltage) then the ViGDO and RESET pins will be released after their programmed delay periods. (See Figure 3.) 2. The X80140 monitors several power supplies, powered by the same source voltage, that all begin power up at the same time. Each voltage source is fed into the ViMON inputs to the X80140. The ViMON inputs monitor the voltage to make sure it has reached the minimum desired level. When each voltage monitor determines that its input is good, a counter starts. After the programmed delay time, the X80140 sets the ViGDO signals LOW. Any individual voltage failure can be viewed in the Fault Detection Register. Quad Voltage Monitoring X80140 monitors 4 voltage inputs. When the ViMON (i=1-4) input is detected to be above the input threshold, the output ViGDO (i = 1 to 4) goes inactive (LOW). The ViGDO signal is de-asserted after a delay of 100ms. This delay can be changed on each ViGDO output individually with bits in register CR3. The delay can be 100ms, 500ms, 1s and 5s. 9 3. In the factory default condition, each ViGDO output is instructed to go LOW 100ms after the input voltage reaches its threshold. However, each ViGDO delay is individually selectable as 100ms, 500ms, 1s and 5s. The delay times are changed via the SMBus during calibration of the system. FN8153.0 January 20, 2005 X80140, X80141, X80142, X80143, X80144 Power Supplies 5V 3.3V 2.5V 1.2V Can Choose Different Delays for each Voltage Monitor V1MON On/Off tDELAY1 On/Off V1GDO Programmable Delay 100ms 500ms 1 sec 5 secs On/Off V4MON X80140/41/42/43/44 tDELAY4 µC V4GDO V4MON VCC1 Programmable Delay V4GDO IRQ RESET V3GDO V3MON VCC2 Programmable Delay tSPOR FPGA V2GDO V2MON VCC1 VCC2 V1GDO V1MON ASIC RESET RESET Timing not to scale FIGURE 8. PARALLEL POWER CONTROL - TIMING VCC1 VCC2 MR FIGURE 7. EXAMPLE APPLICATION OF PARALLEL POWER CONTROL 4. Power Up of Supplies Via Relay Sequencing Using Voltage Monitors (see Figure 10 and Figure 9). 5. Several power supplies and their respective power up start times can be controlled using the X80140 such that each of the power supplies will start in a relay sequencing fashion. In the following example, the 1st supply is allowed to power up when the input regulated supply reaches an acceptable threshold. Subsequent supplies power up after the prior supply has reached its operating voltage. This configuration ensures that each subsequent power supply turns on after the preceding supplies voltage output is valid. Again, the X80140 offers programmable delays for each voltage monitor and this delay is selectable via the SMBus during calibration of the system. 10 FN8153.0 January 20, 2005 X80140, X80141, X80142, X80143, X80144 Power 5V Supply On/Off 12V µC VCC1 1.2V Power Supply On/Off VCC2 RESET Power 3.3V Supply On/Off VCC1 FPGA VCC2 Power 2.5V Supply On/Off ASIC X80140/41/42/43 VCC1 VCC2 V4GDO V4MON VCC V3GDO V3MON V2GDO V2MON V1MON V1GDO RESET 5V MR FIGURE 9. EXAMPLE OF RELAY POWER SUPPLY SEQUENCING V1MON threshold V1MON (12V) Programmable Delay tDELAY1 Timing Not To Scale 100ms 500ms 1sec 5sec Example: Five Independent Power Supplies in relay timing Power Supply #2 ON V1GDO Power Supply #2 OUTPUT (5V) V2MON threshold tDELAY2 Programmable Delay 100ms 500ms 1sec 5sec Power Supply #3 ON V2GDO Power Supply #3 OUTPUT (1.2V) V3MON threshold tDELAY3 Programmable Delay 100ms 500ms 1sec 5sec Power Supply #4 ON V3GDO Power Supply #4 OUTPUT (3.3V) V4MON threshold tDELAY4 Programmable Delay 100ms 500ms 1sec 5sec V4GDO Power Supply #5 OUTPUT (2.5V) tSPOR RESET FIGURE 10. RELAY SEQUENCING OF DC-DC SUPPLIES (TIMING) 11 FN8153.0 January 20, 2005 X80140, X80141, X80142, X80143, X80144 Control Registers and Memory WEL: Write Enable Latch The user addressable internal control, status and memory components of the X80140 can be split up into three parts: A write enable latch (WEL) bit controls write accesses to the nonvolatile registers and the EEPROM memory array in the X80140. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to any address (registers or memory) will be ignored. The WEL bit is set by writing a “1” to the WEL bit and zeroes to the other bits of the control register 0 (CR0). It is important to write only 00h or 80h to the CR0 register. • Control Register (CR) • Fault Detection Register (FDR) • EEPROM array Registers The Control Registers and Fault Detection Register are summarized in Table 4. Changing bits in these registers change the operation of the device or clear fault conditions. Reading bits from these registers provides information about device configuration or fault conditions. Reads and writes are done through the SMBus serial port. Once set, WEL remains set until either it is reset to 0 (by writing a “0” to the WEL bit and zeroes to the other bits of the control register) or until the part powers up again. All of the Control Register bits are nonvolatile (except for the WEL bit), so they do not change when power is removed. The Block Protect Bits, BP1 and BP0, determines which blocks of the memory array are write protected. A write to a protected block of memory is ignored. The block protect bits will prevent write operations to one of four segments of the array. EEPROM Array The X80140 contains a 2kbit EEPROM memory array. This array can contain information about manufacturing location and dates, board configuration, fault conditions, service history, etc. Access to this memory is through the SMBus serial port. Read and write operations are similar to those of the control registers, but a single command can write up to 16 bytes at one time. A single read command can return the entire contents of the EEPROM memory. Register and Memory Protection In order to reduce the possibility of inadvertent changes to either a control register of the contents of memory, several protection mechanisms are built into the X80140. These are a Write Enable Latch, Block Protect bits, a Write Protect Enable bit and a Write Protect pin. BP0 Bits in the registers can be modified by performing a single byte write operation directly to the address of the register and only one data byte can change for each register write operation. BP1 and BP0: Block Protect Bits BP1 The values of the Register Block can be read at any time by performing a random read (see Serial Interface) at the specific byte address location. Only one byte is read by each register read operation. Note, a write to FDR does not require that WEL=1. PROTECTED ADDRESSES (SIZE) 0 0 None (Default) None (Default) 0 1 C0h - FFh (64 bytes) Upper 1/4 1 0 80h - FFh (128 bytes) Upper 1/2 1 1 00h - FFh (256 bytes) All ARRAY LOCK WPEN: Write Protect Enable The Write Protect pin and Write Protect Enable bit in the CR1 register control the Programmable Hardware Write Protect feature. Hardware Protection is enabled when the WP pin is HIGH and WPEN bit is HIGH and disabled when WP pin is LOW or the WPEN bit is LOW. When the chip is Hardware Write Protected, non-volatile writes to all control registers (CR1, CR2, and CR) are disabled including BP bits, the WPEN bit itself, and the blocked sections in the memory Array. Only the section of the memory array that is not block protected can be written. Non Volatile Programming Voltage (VP) Nonvolatile writes require that a programming voltage be applied to the VP for the duration of a nonvolatile write operation. TABLE 3. WRITE PROTECT CONDITIONS WEL WP WPEN MEMORY ARRAY NOT BLOCK PROTECTED LOW X X Writes Blocked Writes Blocked Writes Blocked Hardware HIGH LOW X Writes Enabled Writes Blocked Writes Enabled Software HIGH X LOW Writes Enabled Writes Blocked Writes Enabled Software HIGH HIGH HIGH Writes Enabled Writes Blocked Writes Blocked Hardware 12 MEMORY ARRAY BLOCK PROTECTED WRITES TO CR1, CR2, CR3 PROTECTION FN8153.0 January 20, 2005 X80140, X80141, X80142, X80143, X80144 TABLE 4. REGISTER ADDRESS MAP BIT BYTE ADDR. NAME CONTROL/STATUS 7 6 5 4 3 2 1 0 MEMORY TYPE 00H CR0 Write Enable WEL 0 0 0 0 0 0 0 Volatile 01H CR1 EEPROM Block Control WPEN 0 0 BP1 BP0 0 0 0 EEPROM 02H CR2 POR Timing 0 0 0 0 TPOR1 TPOR0 0 0 EEPROM 03H CR3 ViGDO Time Delay T4D1 T4D0 T3D1 T3D0 T2D1 T2D0 T1D1 T1D0 EEPROM FF FDR Fault Detection Register 0 0 0 0 V40S V30S V20S V10S Volatile TABLE 5. HARDWARE/SOFTWARE CONTROL AND FAULT DETECTION BITS SUMMARY OPERATION CONTROL /STATUS LOCATION(S) REGISTER BITS DESCRIPTION (SEE FUNCTIONAL FOR DETAILS) SOFTWARE CONTROL BITS EEPROM Write Enable WEL CR0 7 WEL = 1 enables write operations to the control registers and EEPROM. WEL = 0 prevents write operations. EEPROM Write Protect WPEN CR1 7 WPEN = 1 (and WP pin HIGH) prevents writes to the control registers and the EEPROM. EEPROM Block Protect BP1 BP0 CR1 4:3 BP1=0, BP0=0 : No EEPROM memory protected. BP1=0, BP0=1 : Upper 1/4 of EEPROM memory protected BP1=1, BP0=0 : Upper 1/2 of EEPROM memory protected. BP1=1, BP0=1 : All of EEPROM memory protected. RESET Time Delay TPOR1 TPOR0 CR2 3:2 TPOR1=0, TPOR0=0 : RESET delay = 100ms TPOR1=0, TPOR0=1 : RESET delay = 500ms TPOR1=1, TPOR0=0 : RESET delay = 1s TPOR1=1, TPOR0=1 : RESET delay = 5s V1GDO Time Delay T1D1 T1D0 CR3 1:0 V2GDO Time Delay T2D1 T2D0 CR3 3:2 TiD1=0, TiD0=0 : ViGDO delay = 100ms TiD1=0, TiD0=1 : ViGDO delay = 500ms TiD1=1, TiD0=0 : ViGDO delay = 1s TiD1=1, TiD0=1 : ViGDO delay = 5s V3GDO Time Delay T3D1 T3D0 CR3 5:4 V4GDO Time Delay T4D1 T4D0 CR3 7:6 1st Voltage Monitor V1OS FDR 0 V1OS = 0 : V1GDO pin has been asserted (must be preset to 1). 2nd Voltage Monitor V2OS FDR 1 V2OS = 0 : V2GDO pin has been asserted (must be preset to 1). 3rd Voltage Monitor V3OS FDR 2 V3OS = 0 : V3GDO pin has been asserted (must be preset to 1). 4th Voltage Monitor V4OS FDR 3 V4OS = 0 : V4GDO pin has been asserted (must be preset to 1). STATUS BITS 13 FN8153.0 January 20, 2005 X80140, X80141, X80142, X80143, X80144 Bus Interface Information Interface Conventions The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive operations. Therefore, the devices in this family operate as slaves in all applications. It should be noted that the ninth clock cycle of the read operation is not a “don’t care.” To terminate a read operation, the master must either issue a STOP condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a STOP condition. Serial Clock and Data The device does not acknowledge any instructions following a non-volatile write operation, unless the VP pin has the recommended programming voltage applied for the duration of the write cycle. In the read mode, the device transmits eight bits of data, releases the SDA line, then monitors the line for an acknowledge. If an acknowledge is detected and no STOP condition is generated by the master, the device continues transmitting data. The device terminates further data transmissions if an acknowledge is not detected. The master must then issue a STOP condition to return the device to Standby mode and place the device into a known state. SCL SDA Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions. See Figure 11. Serial START Condition All commands are preceded by the START condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition has been met. On power up, the SCL pin must be brought LOW prior to the START condition. Start Stop FIGURE 11. VALID START AND STOP CONDITIONS SCL from Master 1 8 9 Data Output from Transmitter Data Output from Receiver Serial STOP Condition All communications must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA when SCL is HIGH followed by a HIGH to LOW on SCL. After going LOW, SCL can stay LOW or return to HIGH. The STOP condition also places the device into the Standby power mode after a read sequence. Device Addressing Serial Acknowledge Addressing Protocol Overview Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, releases the bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge that it received the eight bits of data. See Figure 12. Depending upon the operation to be performed on each of these individual parts, a 1, 2 or 3 Byte protocol is used. All operations however must begin with the Slave Address Byte being clocked into the SMBus port on the SCL and SDA pins. The Slave address selects the part of the device to be addressed, and specifies if a Read or Write operation is to be performed. The device responds with an acknowledge after recognition of a START condition and if the correct Device Identifier and Select bits are contained in the Slave Address Byte. If a write operation is selected, the device responds with an acknowledge after the receipt of each subsequent eight bit word. The device acknowledges all incoming data and address bytes, except for the Slave Address Byte when the Device Identifier and/or Select bits are incorrect. 14 Start Acknowledge FIGURE 12. ACKNOWLEDGE RESPONSE FROM RECEIVER Slave Address Byte Following a START condition, the master must output a Slave Address Byte. This byte consists of three parts: • The Device Type Identifier which consists of the most significant four bits of the Slave Address (SA7 - SA4). FN8153.0 January 20, 2005 X80140, X80141, X80142, X80143, X80144 The Device Type Identifier MUST be set to 1010 in order to select the device. • The next two bits (SA3 - SA2) are slave address bits. The bits received via the SMBus are compared to A0 and A1 pins and must match or the communication is aborted. • The next bit, SA1, selects the device memory sector. There are two addressable sectors: the memory array and the control, fault detection and remote shutdown registers. • The Least Significant Bit of the Slave Address (SA0) Byte is the R/W bit. This bit defines the operation to be performed. When the R/W bit is “1”, then a READ operation is selected. A “0” selects a WRITE operation (Refer to Figure 13). BYTE WRITE For a write operation, the device requires the Slave Address Byte and a Word Address Byte. This gives the master access to any one of the words in the array. After receipt of the Word Address Byte, the device responds with an acknowledge, and awaits the next eight bits of data. After receiving the 8 bits of the Data Byte, the device again responds with an acknowledge. The master then terminates the transfer by generating a STOP condition, at which time the device begins the internal write cycle to the nonvolatile memory. During this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. The SDA output is at high impedance. A write to a protected block of memory will suppress the acknowledge bit. EXTERNAL DEVICE ADDRESS DEVICE TYPE IDENTIFIER SA7 1 Memory READ / Select WRITE SA6 SA5 SA4 SA3 SA2 SA1 0 1 0 A1 A0 MS SA0 R/W INTERNAL ADDRESS (SA1) INTERNALLY ADDRESSED DEVICE 0 EEPROM Array 1 Control Register, Fault Detection Register BIT SA0 OPERATION 0 WRITE 1 READ FIGURE 13. SLAVE ADDRESS FORMAT Serial Write Operations Before any write operations can be performed, a programming supply voltage (VP) must be supplied. This voltage is only needed for programming, but the nonvolatile registers and EEPROM locations cannot be programmed without it. In order to successfully complete a write operation to either a Control Register or the EEPROM array, the Write Enable Latch (WEL) bit must first be set and either the WP pin or the WPEN bit must be LOW. Writes to the WEL bit do not cause a high voltage write cycle, so the device is ready for the next operation immediately after the STOP condition. PAGE WRITE The device is capable of a page write operation. See Figure 14. It is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit an unlimited number of 8-bit bytes. After the receipt of each byte, the device will respond with an acknowledge, and the address is internally incremented by one. The page address remains constant. When the counter reaches the end of the page, it “rolls over” and goes back to ‘0’ on the same page. See Figure 15. This means that the master can write 16 bytes to the page starting at any location on that page. If the master begins writing at location 10, and loads 12 bytes, then the first 6 bytes are written to locations 10 through 15, and the last 6 bytes are written to locations 0 through 5. Afterwards, the address counter would point to location 6 of the page that was just written. If the master supplies more than 16 bytes of data, then new data overwrites the previous data, one byte at a time. The master terminates the Data Byte loading by issuing a STOP condition, which causes the device to begin the nonvolatile write cycle. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. STOP AND WRITE MODES STOP conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ACK signal. If a STOP is issued in the middle of a data byte, or before 1 full data byte plus its associated ACK is sent, then the device will reset itself without performing the write. The contents of the array will not be effected. ACKNOWLEDGE POLLING The disabling of the inputs during high voltage cycles can be used to take advantage of the typical 5ms write cycle time. Once the STOP condition is issued to indicate the end of the 15 FN8153.0 January 20, 2005 X80140, X80141, X80142, X80143, X80144 cycle then no ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the read or write operation. See Figure 18. master’s byte load operation, the device initiates the internal high voltage cycle. Acknowledge polling can be initiated immediately. To do this, the master issues a START condition followed by the Slave Address Byte for a write or read operation. If the device is still busy with the high voltage (1 to n to 16) S t a r t Signals from the Master Byte Address Slave Address SDA Bus Data (1) S t o p Data (n) 0 1 0 1 0 A C K Signals from the Slave A C K A C K A C K FIGURE 14. PAGE WRITE OPERATION 7 Bytes 5 Bytes address pointer ends here Addr = 7 address =6 address 10 address n-1 FIGURE 15. WRITING 12 BYTES TO A 16-BYTE PAGE STARTING AT LOCATION 10 S t a r t Signals from the Master SDA Bus 1 0 1 0 S t a r t Byte Address Slave Address 1 0 1 0 0 A C K Signals from the Slave S t o p Slave Address 1 A C K A C K Data FIGURE 16. RANDOM ADDRESS READ SEQUENCE S t a r t Signals from the Master SDA Bus Signals from the Slave S t o p Slave Address 1 0 1 0 1 A C K Data FIGURE 17. CURRENT ADDRESS READ SEQUENCE 16 FN8153.0 January 20, 2005 X80140, X80141, X80142, X80143, X80144 CURRENT ADDRESS READ Internally the device contains an address counter that maintains the address of the last word read incremented by one. Therefore, if the last read was to address n, the next read operation would access data from address n+1. On power up, the address of the address counter is undefined, requiring a read or write operation for initialization. Byte Load Completed by Issuing STOP. Enter ACK Polling Issue START Issue Slave Address Byte (Read or Write) Issue STOP NO ACK Returned? Upon receipt of the Slave Address Byte with the R/W bit set to one, the device issues an acknowledge and then transmits the eight bits of the Data Byte. The master terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a STOP condition. See Figure 17 or the address, acknowledge, and data transfer sequence. Operational Notes YES The device powers-up in the following state: High Voltage Cycle Complete. Continue Command Sequence? Issue STOP NO YES Continue Normal Read or Write Command Sequence • The device is in the low power standby state. • The WEL bit is set to ‘0’. In this state it is not possible to write to the device. • SDA pin is the input mode. Data Protection The following circuitry has been included to prevent inadvertent writes: • The WEL bit must be set to allow write operations. PROCEED FIGURE 18. ACKNOWLEDGE POLLING SEQUENCE • The proper clock count and bit sequence is required prior to the STOP bit in order to start a nonvolatile write cycle. • The WP pin, when held HIGH, prevents all writes to the array and all the Register. Serial Read Operations Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the Slave Address Byte is set to one. There are three basic read operations: Current Address Reads, Random Reads, and Sequential Reads. • A programming voltage must be applied to the VP pin prior to any programming sequence. RANDOM READ Random read operation allows the master to access any memory location in the array. Prior to issuing the Slave Address Byte with the R/W bit set to one, the master must first perform a “dummy” write operation. The master issues the START condition and the Slave Address Byte, receives an acknowledge, then issues the Word Address Bytes. After acknowledging receipts of the Word Address Bytes, the master immediately issues another START condition and the Slave Address Byte with the R/W bit set to one. This is followed by an acknowledge from the device and then by the eight bit word. The master terminates the read operation by not responding with an acknowledge and then issuing a STOP condition. See Figure 16 for the address, acknowledge, and data transfer sequence. 17 FN8153.0 January 20, 2005 X80140, X80141, X80142, X80143, X80144 Packaging Information C 20-Lead Quad Flat No Lead Package (Package Code: Q20) 5mm x 5mm Body with 0.65mm Lead Pitch A3 A1 Pin 1 Indent b E E2 e D2 NOTES: 1. The package outline drawing is compatible with JEDEC MO-220; variations: WHHC-2, except dimensions D2 and E2. 2. The terminal #1 identifier is a laser marked feature L A DIMENSIONS IN MILLIMETERS y C D SYMBOLS MIN NOM MAX A 0.70 0.75 0.80 A1 0.00 0.02 0.05 b 0.25 0.30 0.35 A3 0.19 0.20 0.25 D 4.90 5.00 5.10 D2 3.70 3.80 3.90 E 4.90 5.00 5.10 E2 3.70 3.80 3.90 e — 0.65 — L 0.35 0.40 0.45 — 0.08 y All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 18 FN8153.0 January 20, 2005