INTERSIL ISL28005FH

ISL28005
Features
The ISL28005 is a micropower, uni-directional
high-side and low-side current sense amplifier
featuring a proprietary rail-to-rail input current sensing
amplifier. The ISL28005 is ideal for high-side current
sense applications where the sense voltage is usually
much higher than the amplifier supply voltage. The
device can be used to sense voltages as high as 28V
when operating from a supply voltage as low as 2.7V.
The micropower ISL28005 consumes only 50µA of supply
current when operating from a 2.7V to 28V supply.
• Low Power Consumption . . . . . . . . . . . 50µA,Typ
The ISL28005 features a common-mode input voltage
range from 0V to 28V. The proprietary architecture
extends the input voltage sensing range down to 0V,
making it an excellent choice for low-side ground sensing
applications. The benefit of this architecture is that a high
degree of total output accuracy is maintained over the
entire 0V to 28V common mode input voltage range.
The ISL28005 is available in fixed (100V/V, 50V/V and
20V/V) gains in the space saving 5 Ld SOT-23 package.
The parts operate over the extended temperature range
from -40°C to +125°C.
Typical Application
+5VDC
+
• Package . . . . . . . . . . . . . . . . . . . . .5 Ld SOT-23
Applications*(see page 13)
• Power Management/Monitors
• Power Distribution and Safety
• DC/DC, AC/DC Converters
• Battery Management /Charging
• Automotive Power Distribution
Related Literature*(see page 13)
• See AN1531 for “ISL28005 Evaluation Board User’s
Guide”
RSENSE
-
+5VDC
ISENSE
+5VDC
+
SENSE
RSENSE
-
+5VDC
ISL28005
+
1.8
+1.0VDC
OUTPUT
ISENSE
+1.0VDC
VRS+
1.6
ISENSE
+12VDC
+5VDC
OUTPUT
ISL28005
MULTIPLE
OUTPUT
POWER SUPPLY
• Operating Temperature Range . . -40°C to +125°C
1.4
VTH(L-H) = 1.52V
1.2
VOLTS (V)
-
SENSE
+1.0VDC
• Fixed Gain Versions
- ISL28005-100 . . . . . . . . . . . . . . . . . . . 100V/V
- ISL28005-50. . . . . . . . . . . . . . . . . . . . . 50V/V
- ISL28005-20. . . . . . . . . . . . . . . . . . . . . 20V/V
+12VDC
OUTPUT
RSENSE
ISL28005
+5VDC
• Wide Common Mode Input . . . . . . . . . 0V to 28V
High-Side And Low-Side
Threshold Voltage
SENSE
+12VDC
• Supply Range. . . . . . . . . . . . . . . . . . 2.7V to 28V
VTH(H-L) = 1.23V
1.0
0.8
VOUT (G=100)
0.6
G100, VOUT = 1V
G50, VOUT = 500mV
G20, VOUT = 200mV
0.4
0.2
0
0
0.2
0.4
0.6
0.8 1.0 1.2
TIME (ms)
1.4
1.6
1.8
2.0
GND
May 27, 2010
FN6973.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL28005
Micropower, Rail-to-Rail Input Current Sense
Amplifier with Voltage Output
ISL28005
Block Diagram
VCC
I = 2.86µA
VSENSE
RS+
R1
gmHI
HIGH-SIDE
AND
LOW-SIDE
SENSING
RSR2
+
-
1.35V
R3
gmLO
IMIRROR
Rg
R5
VSENSE
R4
ISL28005
(5 LD SOT-23)
TOP VIEW
OUT 2
GND
Pin Descriptions
Pin Configuration
GND 1
ISL28005
PIN
(5 LD SOT-23) NAME
5 RSFIXED
GAIN
4 RS+
VCC 3
OUT
Rf
DESCRIPTION
1
GND
Power Ground
2
OUT
Amplifier Output
3
VCC
Positive Power Supply
4
RS+
Sense Voltage Non-inverting Input
5
RS-
Sense Voltage Inverting Input
VCC
RS-
CAPACITIVELY
COUPLED
ESD CLAMP
OUT
RS+
GND
2
FN6973.2
May 27, 2010
ISL28005
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
(Note 4)
GAIN
ISL28005FH100Z-T7
PACKAGE
Tape & Reel
(Pb-Free)
PKG.
DWG. #
100V/V
BDEA
5 Ld SOT-23
P5.064A
ISL28005FH50Z-T7
50V/V
BDDA
5 Ld SOT-23
P5.064A
ISL28005FH20Z-T7
20V/V
BDCA
5 Ld SOT-23
P5.064A
ISL28005FH-100EVAL1Z
100V/V Evaluation Board
ISL28005FH-50EVAL1Z
50V/V Evaluation Board
ISL28005FH-20EVAL1Z
20V/V Evaluation Board
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28005. For more information on MSL please
see techbrief TB363.
4. The part marking is located on the bottom of the part.
3
FN6973.2
May 27, 2010
ISL28005
Absolute Maximum Ratings
Max Supply Voltage . . . . . . . . . . . . . . . .
Max Differential Input Current . . . . . . . .
Max Differential Input Voltage . . . . . . . . .
Max Input Voltage (RS+, RS-) . . . . . . . . .
Max Input Current for Input Voltage <GND
Output Short-Circuit Duration . . . . . . . . .
ESD Rating
Human Body Model . . . . . . . . . . . . . . .
Machine Model . . . . . . . . . . . . . . . . . .
Charged Device Model . . . . . . . . . . . . .
Thermal Information
. . . . . . . . . ..28V
. . . . . . . . .20mA
. . . . . . . . .±0.5V
GND-0.5V to 30V
-0.5V . . . ±20mA
. . . . . . Indefinite
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
. . . . . . . . . . 4kV
. . . . . . . . . .200V
. . . . . . . . . 1.5kV
Recommended Operating Conditions
5 Ld SOT-23 (Notes 5, 6) . . . . . . .
190
90
Maximum Storage Temperature Range . . . -65°C to +150°C
Maximum Junction Temperature (TJMAX) . . . . . . . . . +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Ambient Temperature Range (TA) . . . . . . . -40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
6. For θJC, the “case temp” location is taken at the package top center.
Electrical Specifications VCC = 12V, VRS+ = 0V to 28V, VSENSE = 0V, RLOAD = 1MΩ, TA = +25°C unless otherwise specified.
Boldface limits apply over the operating temperature range, -40°C to +125°C.
Temperature data established by characterization.
PARAMETER
VOS
DESCRIPTION
Input Offset Voltage
(Notes 8, 9)
CONDITIONS
UNIT
60
500
500
µV
VCC = 12V, VRS+ = 0.2V, VS = 20mV,
VS = 100mV
-3
-3.3
-1.2
3
3.3
mV
0.041
1.2
1.5
µA
4.7
6
7
µA
VCC = 0V, VRS+ = 28V
IRS+
Gain = 100 + Input Bias Current
VRS+ = 2V, VSENSE = 5mV
VRS+ = 0V, VSENSE = 5mV
-500
-600
VRS+ = 2V, VSENSE = 5mV
VRS+ = 0V, VSENSE = 5mV
Input Bias Current
MAX
(Note 7)
-500
-500
Leakage Current
IRS -
TYP
VCC = VRS+ = 12V,
VS = 20mV to = 100mV
IRS+, IRS -
Gain = 50, Gain = 20 +Input Bias
Current
MIN
(Note 7)
-425
4.7
-700
-840
VRS+ = 2V, VSENSE = 5mV
nA
6
8
-432
5
µA
nA
50
75
nA
VRS+ = 0V, VSENSE = 5mV
-125
-130
-45
nA
CMRR
Common Mode Rejection Ratio
VRS+ = 2V to 28V
105
115
dB
PSRR
Power Supply Rejection Ratio
VCC = 2.7V to 28V, VRS+ = 2V
90
105
dB
VFS
Full-scale Sense Voltage
VCC = 28V, VRS+ = 0.2V, 12V
200
G
Gain
(Note 8)
ISL28005-100
100
V/V
ISL28005-50
50
V/V
ISL28005-20
20
V/V
4
mV
FN6973.2
May 27, 2010
ISL28005
Electrical Specifications VCC = 12V, VRS+ = 0V to 28V, VSENSE = 0V, RLOAD = 1MΩ, TA = +25°C unless otherwise specified.
Boldface limits apply over the operating temperature range, -40°C to +125°C.
Temperature data established by characterization. (Continued)
PARAMETER
GA
DESCRIPTION
Gain = 100 Gain Accuracy
(Note 10)
CONDITIONS
MIN
(Note 7)
VCC = VRS+ = 12V, VSENSE = 20mV
to 100mV
-2
-3
VCC = 12V, VRS+ = 0.1V,
VSENSE = 20mV to 100mV
Gain = 50, Gain = 20 Gain Accuracy
(Note 10)
VOA
Gain = 100 Total Output Accuracy
(Note 11)
-2
-3
VCC = 12V, VRS+ = 0.1V,
VSENSE = 20mV to 100mV
-3
-4
VCC = VRS+ = 12V,
VSENSE = 100mV
VCC = 12V, VRS+ = 0.1V,
VSENSE = 100mV
2
3
-0.31
-2.5
-2.7
VCC = 12V, VRS+ = 0.1V,
VSENSE = 100mV
Gain = 50, Gain = 20 Total Output
Accuracy (Note 11)
MAX
(Note 7)
%
2
3
%
3
4
%
2.5
2.7
%
-1.25
-2.5
-2.7
-6
-7
UNIT
%
-0.25
VCC = VRS+ = 12V, VSENSE = 20mV
to 100mV
VCC = VRS+ = 12V,
VSENSE = 100mV
TYP
%
2.5
2.7
%
-1.41
6
7
%
VOH
Output Voltage Swing, High
VCC - VOUT
IO = -500µA, VCC = 2.7V
VSENSE = 100mV
VRS+ = 2V
39
50
mV
VOL
Output Voltage Swing, Low
VOUT
IO = 500µA, VCC = 2.7V
VSENSE = 0V, VRS+ = 2V
30
50
mV
ROUT
Output Resistance
VCC = VRS+ = 12V,
VSENSE = 100mV
IOUT = 10µA to 1mA
6.5
Ω
ISC+
Short Circuit Sourcing Current
VCC = VRS+ = 5V, RL = 10Ω
4.8
mA
ISC-
Short Circuit Sinking Current
VCC = VRS+ = 5V, RL = 10Ω
8.7
mA
IS
Gain = 100
Supply Current
VRS+ > 2V, VSENSE = 5mV
50
59
62
µA
Gain = 50, 20
Supply Current
VRS+ > 2V, VSENSE = 5mV
50
62
63
µA
VCC
Supply Voltage
Guaranteed by PSRR
2.7
28
V
SR
Gain = 100 Slew Rate
Pulse on RS+ pin,
VOUT = 8VP-P
(see Figure 15)
0.58
0.76
V/µs
Gain = 50 Slew Rate
Pulse on RS+ pin,
VOUT = 8VP-P
(see Figure 15)
0.58
0.67
V/µs
Gain = 20 Slew Rate
Pulse on RS+ pin,
VOUT = 3.5VP-P
(see Figure 15)
0.50
0.67
V/µs
Gain = 100
-3dB Bandwidth
VRS+ = 12V, 0.1V,
VSENSE = 100mV
110
kHz
Gain = 50
-3dB Bandwidth
VRS+ = 12V, 0.1V,
VSENSE = 100mV
160
kHz
Gain = 20
-3dB Bandwidth
VRS+ = 12V, 0.1V,
VSENSE = 100mV
180
kHz
BW-3dB
5
FN6973.2
May 27, 2010
ISL28005
Electrical Specifications VCC = 12V, VRS+ = 0V to 28V, VSENSE = 0V, RLOAD = 1MΩ, TA = +25°C unless otherwise specified.
Boldface limits apply over the operating temperature range, -40°C to +125°C.
Temperature data established by characterization. (Continued)
PARAMETER
ts
Output Settling Time to 1% of Final
Value
VCC = VRS+ = 12V, VOUT = 10V
step, VSENSE >7mV
15
µs
VCC = VRS+ = 0.2V, VOUT = 10V
step, VSENSE >7mV
20
µs
No sustained oscillations
300
pF
15
µs
VCC = 12V, VRS+ = 0.2V
VSENSE = 100mV
50
µs
VCC = VRS+ = 12V,
VSENSE = 100mV, overdrive
10
µs
Power-Up Time to 1% of Final Value VCC = VRS+ = 12V,
VSENSE = 100mV
Saturation Recovery Time
TYP
MAX
(Note 7)
CONDITIONS
Capacitive-Load Stability
ts Power-up
MIN
(Note 7)
DESCRIPTION
UNIT
NOTES:
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
8. DEFINITION OF TERMS:
• VSENSEA = VSENSE @100mV
• VSENSEB = VSENSE @20mV
• VOUTA = VOUT@VSENSEA=100mV
• VOUTB = VOUT@VSENSEB=20mV
⎛ V OUT A – V OUT B ⎞
• G = GAIN = ⎜ --------------------------------------------------------------⎟
⎝ V SENSE A – V SENSE B⎠
V OUT A
9. VOS is extrapolated from the gain measurement. V OS = V SENSE A – -------------------G
⎛ G MEASURED – G EXPECTED⎞
10. % Gain Accuracy = GA = ⎜ -------------------------------------------------------------------------------⎟ × 100
G EXPECTED
⎝
⎠
⎛ VOUT MEASURED – VOUT EXPECTED⎞
11. Output Accuracy % VOA = ⎜ ----------------------------------------------------------------------------------------------------------⎟ × 100 where VOUT = VSENSE X GAIN and VSENSE = 100mV
VOUT EXPECTED
⎝
⎠
6
FN6973.2
May 27, 2010
ISL28005
Typical Performance Curves
Vcc = 12V, RL = 1M, unless otherwise specified.
12
12
GAIN 100
GAIN 100
8
8
VOUT (V)
10
6
6
4
4
2
2
0
0
10
20
30
40
50
60
70
80
90
0
100
0
10
20
30
40
50
60
TIME (µs)
TIME (µs)
FIGURE 1. LARGE SIGNAL TRANSIENT RESPONSE
VRS+ = 0.2V, VSENSE = 100mV
1.8
1.0
0.8
VOUT (G = 100)
0.6
0.2
1.2
0
0.4
0.6
0.8 1.0 1.2
TIME (ms)
1.4
1.6
1.8
2.0
FIGURE 3. HIGH-SIDE and LOW-SIDE THRESHOLD
VOLTAGE VRS+(L-H) and VRS+(H-L),
VSENSE = 10mV
0.2
6
4
G100, VOUT = 2V
G50, VOUT = 1V
G20, VOUT = 400mV
0.4
0
8
RL = 1M
VCC = 12V
0.8
G100, VOUT = 1V
G50, VOUT = 500mV
G20, VOUT = 200mV
0.4
10
VOUT (G = 100)
1.6
VTH(H-L) = 1.23V
VRS+ (V)
VOLTS (V)
12
2.0
1.2
0
0.2
0.4
0.6
0.8
1.0 1.2
TIME (ms)
2
1.4
1.6
1.8
0
2.0
FIGURE 4. VOUT vs VRS+, VSENSE = 20mV
TRANSIENT RESPONSE
45
GAIN 100
35
0.0
GAIN 100
25
-0.2
GAIN (dB)
VOA PERCENT ACCURACY (%)
100
VRS+
VTH(L-H) = 1.52V
0.2
90
2.4
1.4
0
80
FIGURE 2. LARGE SIGNAL TRANSIENT RESPONSE
VRS+ =12V, VSENSE = 100mV
VRS+
1.6
70
VOUT (V)
VOUT (V)
10
+25°C
-0.4
-40°C
-0.6
-0.8
+125°C
-1.0
1µ
10µ
100µ
IOUT(A)
1m
FIGURE 5. NORMALIZED VOA vs IOUT
7
10m
15
5
VRS+= 100mV
-5
VCC = 12V
-15 V
SENSE = 100mV
-25 AV = 100
RL = 1M
-35
10
100
VRS+ = 12V
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 6. GAIN vs FREQUENCY VRS+= 100mV/12V,
VSENSE = 100mV, VOUT = 250mVP-P
FN6973.2
May 27, 2010
ISL28005
Typical Performance Curves
GAIN 50
35
0.0
25
-0.2
-0.4
+25°C
-0.6
-40°C
+125°C
10µ
100µ
IOUT(A)
1m
15
VRS+= 100mV
5
-5
VCC = 12V
-15 V
SENSE = 100mV
A = 100
-25 V
RL = 1M
-35
10
100
-0.8
-1.0
1µ
10m
VRS+ = 12V
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 8. GAIN vs FREQUENCY VRS+=100mV/12V,
VSENSE = 100mV, VOUT = 250mVP-P
FIGURE 7. NORMALIZED VOA vs IOUT
0.2
45
GAIN 20
GAIN 20
35
0.0
25
-0.2
-40°C
-0.4
GAIN (dB)
VOA PERCENT ACCURACY (%)
45
GAIN 50
GAIN (dB)
VOA PERCENT ACCURACY (%)
0.2
Vcc = 12V, RL = 1M, unless otherwise specified. (Continued)
+25°C
-0.6
-0.8
-1.0
1µ
+125°C
10µ
100µ
1m
10m
15
VRS+= 100mV
5
-5
VCC = 12V
-15 V
SENSE = 100mV
A = 100
-25 V
RL = 1M
-35
10
100
IOUT(A)
FIGURE 9. NORMALIZED VOA vs IOUT
VRS+ = 12V
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 10. GAIN vs FREQUENCY VRS+=100mV/12V,
VSENSE = 100mV, VOUT = 250mVP-P
Test Circuits and Waveforms
VCC
VR1
VCC
R1
+
+
VRS+
VSENSE
RS+
OUT
+
VRS+
GND
-
1MΩ
RS+
+
RSRL VOUT
VSENSE
OUT
RS-
R2
GND
-
1MΩ
RL VOUT
VR2
FIGURE 11. IS, VOS, VOA, CMRR, PSRR, GAIN
ACCURACY
8
FIGURE 12. INPUT BIAS CURRENT, LEAKAGE
CURRENT
FN6973.2
May 27, 2010
ISL28005
Test Circuits and Waveforms (Continued)
SIGNAL
GENERATOR
VCC
RS+
OUT
RS+
RS-
VRS+
GND
1MΩ
VRS-
VCC
VRS+
RL VOUT
VSENSE
OUT
RSGND
1MΩ
RL VOUT
PULSE
GENERATOR
FIGURE 13. SLEW RATE, ts, SATURATION RECOVERY
TIME
FIGURE 14. GAIN vs FREQUENCY
VCC
RS+
OUT
RS-
VRS+
GND
1MΩ
RL VOUT
PULSE
GENERATOR
FIGURE 15. SLEW RATE
Applications Information
Functional Description
The ISL28005-20, ISL28005-50 and ISL28005-100 are
single supply, uni-directional current sense amplifiers
with fixed gains of 20V/V, 50V/V and 100V/V
respectively.
The ISL28005 is a 2-stage amplifier. Figure 16 shows the
active circuitry for high-side current sense applications
where the sense voltage is between 1.35V to 28V.
Figure 17 shows the active circuitry for ground sense
applications where the sense voltage is between 0V to
1.35V.
The first stage is a bi-level trans-conductance amp and
level translator. The gm stage converts the low voltage
drop (VSENSE) sensed across an external milli-ohm
sense resistor, to a current (@ gm = 21.3µA/V). The
trans-conductance amplifier forces a current through R1
resulting to a voltage drop across R1 that is equal to the
sense voltage (VSENSE). The current through R1 is
mirrored across R5 creating a ground-referenced voltage
at the input of the second amplifier equal to VSENSE.
9
The second stage is responsible for the overall gain and
frequency response performance of the device. The fixed
gains (20, 50, 100) are set with internal resistors Rf and
Rg. The only external component needed is a current
sense resistor (typically 0.001Ω to 0.01Ω, 1W to 2W).
The transfer function is given in Equation 1.
V OUT = GAIN × ( I S R S + V OS )
(EQ. 1)
The input gm stage derives its ~2.86µA supply current
from the input source through the RS+ terminal as long
as the sensed voltage at the RS+ pin is >1.35V and the
gmHI amplifier is selected. When the sense voltage at
RS+ drops below the 1.35V threshold, the gmLO
amplifier kicks in and the gmLO output current reverses,
flowing out of the RS- pin.
FN6973.2
May 27, 2010
ISL28005
VCC
OPTIONAL
FILTER
CAPACITOR
I = 2.86µA
VSENSE
RS+
IS
+
RS
R1
VSENSE
gmHI
HIGH-SIDE
SENSING
VRS+= 2V TO 28V
-
VCC = 2V TO 28V
RSR2
+
OPTIONAL
TRANSIENT
PROTECTION
R3
OUT
-
1.35V
gmLO ‘VSENSE
Rf
Rg
R5
IMIRROR
LOAD
R4
GND
FIGURE 16. HIGH-SIDE CURRENT DETECTION
VCC
OPTIONAL
FILTER
CAPACITOR
I = 2.86µA
VSENSE
RS+
IS
+
R1
VSENSE
RS
gmHI
LOW-SIDE
SENSING
VRS+= 0V TO 2V
-
VCC = 2V TO 28V
RSR2
+
OPTIONAL
TRANSIENT
PROTECTION
1.35V
R3
VCC
gmLO
IMIRROR
LOAD
R4
OUT
-
Rf
Rg
R5
‘VSENSE
GND
FIGURE 17. LOW-SIDE CURRENT DETECTION
10
FN6973.2
May 27, 2010
ISL28005
Hysteretic Comparator
The input trans-conductance amps are under control of a
hysteretic comparator operating from the incoming
source voltage on the RS+ pin (see Figure 18). The
comparator monitors the voltage on RS+ and switches
the sense amplifier from the low-side gm amp to the
high-side gm amplifier whenever the input voltage at
RS+ increases above the 1.35V threshold. Conversely, a
decreasing voltage on the RS+ pin, causes the hysteric
comparator to switch from the high-side gm amp to the
low-side gm amp as the voltage decreases below 1.35V.
It is that low-side sense gm amplifier that gives the
ISL28005 the proprietary ability to sense current all the
way to 0V. Negative voltages on the RS+ or RS- are
beyond the sensing voltage range of this amplifier.
0.5
0.4
ACCURACY (%)
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
((RP x IRS-) = (100Ω x 130nA) = 13µV)
Switching applications can generate voltage spikes that
can overdrive the amplifier input and drive the output of
the amplifier into the rails, resulting in a long overload
recovery time. Capacitors CM and CD filter the common
mode and differential voltage spikes.
Error Sources
There are 3 dominant error sources: gain error, input
offset voltage error and Kelvin voltage error (see
Figure 19). The gain error is dominated by the internal
resistance matching tolerances. The remaining errors
appear as sense voltage errors at the input to the
amplifier. They are VOS of the amplifier and Kelvin
voltage errors. If the transient protection resistor is
added, an additional VOS error can result from the IxR
voltage due to input bias current. The limiting resistor
should only be added to the RS- input, due to the
high-side gm amplifier (gmHI) sinking several micro
amps of current through the RS+ pin.
Layout Guidelines
-0.4
-0.5
0
flowing through the input while adding only an additional
13µV (worse case over-temperature) of VOS. Refer to the
following formula:
0.2
0.4
0.6
0.8
1.0
1.2
VRS+ (V)
1.4
1.6
1.8
2.0
FIGURE 18. GAIN ACCURACY vs VRS+ = 0V TO 2V
Typical Application Circuit
Figure 20 shows the basic application circuit and optional
protection components for switched-load applications.
For applications where the load and the power source is
permanently connected, only an external sense resistor
is needed. For applications where fast transients are
caused by hot plugging the source or load, external
protection components may be needed. The external
current limiting resistor (RP) in Figure 20 may be
required to limit the peak current through the internal
ESD diodes to < 20mA. This condition can occur in
applications that experience high levels of in-rush current
causing high peak voltages that can damage the internal
ESD diodes. An RP resistor value of 100Ω will provide
protection for a 2V transient with the maximum of 20mA
Kelvin Connected Sense Resistor
The source of Kelvin voltage errors is illustrated in
Figure 19. The resistance of 1/2 oz. copper is ~1mΩ per
square with a TC of ~3900ppm/°C (0.39%/°C). When
you compare this unwanted parasitic resistance with the
total of 1mΩ to 10mΩ resistance of the sense resistor, it
is easy to see why the sense connection must be chosen
very carefully. For example, consider a maximum current
of 20A through a 0.005Ω sense resistor, generating a
VSENSE = 0.1 and a full scale output voltage of 10V
(G = 100). Two side contacts of only 0.25 square per
contact puts the VSENSE input about 0.5 x 1mΩ away
from the resistor end capacitor. If only 10A the 20A total
current flows through the kelvin path to the resistor, you
get an error voltage of 10mV (10A x 0.5sq x 0.001Ω/sq.
= 10mV) added to the 100mV sense voltage for a sense
voltage error of 10% (0.110V - 0.1)/0.1V)x 100.
CURRENT
RESISTOR
CurrentSENSE
Sense Resistor
Non-uniform
NON-UNIFORM
CURRENT
FLOW
Current Flow
CURRENT
Current InIN
1mΩ
10mΩ
1 toTO
10mO
Copper
Trace TRACE
1/2
Oz COPPER
1mΩ /SQ
30mO/Sq.
CURRENT OUT
Current Out
PCBOARD
Board
PC
KELVIN
CONTACTS
Kelvin VVSSContacts
FIGURE 19. PC BOARD CURRENT SENSE KELVIN CONNECTION
11
FN6973.2
May 27, 2010
ISL28005
2.7VDC
TO
28VDC
VCC
I = 2.86µA
RS+
(1mΩ
RS TO
0.1Ω)
CD
gmHI
RSCM
+
RP
+
-
0.1VDC
TO
28VDC
OUT
-
1.35V
gmLO
LOAD
GND
FIGURE 20. TYPICAL APPLICATION CIRCUIT
Overall Accuracy (VOA %)
where:
VOA is defined as the total output accuracy
Referred-to-Output (RTO). The output accuracy contains
all offset and gain errors, at a single output voltage.
Equation 2 is used to calculate the % total output
accuracy.
• PDMAXTOTAL is the sum of the maximum power
dissipation of each amplifier in the package (PDMAX)
⎛ V OUT actual – V OUT exp ected⎞
V OA = 100 × ⎜ ------------------------------------------------------------------------------------⎟
V OUT exp ected
⎝
⎠
(EQ. 2)
where
VOUT Actual = VSENSE x GAIN
Example: Gain = 100, For 100mV VSENSE input we
measure 10.1V. The overall accuracy (VOA) is 1% as
shown in Equation 3.
10.1 – 10
V OA = 100 × ⎛ ------------------------⎞ = 1percent
⎝
10 ⎠
(EQ. 3)
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power supply
conditions. It is therefore important to calculate the
maximum junction temperature (TJMAX) for all
applications to determine if power supply voltages, load
conditions, or package type need to be modified to
remain in the safe operating area. These parameters are
related using Equation 4:
12
V OUTMAX
PD MAX = V S × I qMAX + ( V S - V OUTMAX ) × ---------------------------R
L
(EQ. 5)
where:
• TMAX = Maximum ambient temperature
• θJA = Thermal resistance of the package
• PDMAX = Maximum power dissipation of 1 amplifier
• VCC = Total supply voltage
• IqMAX = Maximum quiescent supply current of 1
amplifier
Power Dissipation
T JMAX = T MAX + θ JA xPD MAXTOTAL
• PDMAX for each amplifier can be calculated using
Equation 5:
• VOUTMAX = Maximum output voltage swing of the
application
RL = Load resistance
(EQ. 4)
FN6973.2
May 27, 2010
ISL28005
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
5/12/10
FN6973.2
4/12/10
CHANGE
Added Note 4 to Part Marking Column in “Ordering Information” on page 3.
Corrected hyperlinks in Notes 1 and 3 in “Ordering Information” on page 3.
Corrected ISL28005 hyperlink in “Products” on page 13.
Added Eval boards to ordering info.
4/7/10
Added “Related Literature*(see page 13)” on page 1
Updated Package Drawing Number in the “Ordering Information” on page 3 from MDP0038 to
P50.64A.
Revised package outline drawing from MDP0038 to P5.064A on page 14. MDP0038 package
contained 2 packages for both the 5 and 6 Ld SOT-23. MDP0038 was obsoleted and the
packages were separated and made into 2 separate package outline drawings; P5.064A and
P6.064A. Changes to the 5 Ld SOT-23 were to move dimensions from table onto drawing, add
land pattern and add JEDEC reference number.
2/3/10
FN6973.1
-Page1:
Edited last sentence of paragraph 2.
Moved order of GAIN listings from 20, 50, 100 to 100, 50, 20 in the 3rd paragraph.
Under Features ....removed "Low Input Offset Voltage 250µV,max"
Under Features .... moved order of parts listing from 20, 50, 100 (from top to bottom) to 100,
50, 20.
-Page 3:
Removed coming soon on ISL28005FH50Z and ISL28005FH20Z and changes the order or
listing them to 100, 50, 20.
-Page 5:
VOA test. Under conditions column ...deleted “20mV to”. It now reads ... Vsense = 100mV
SR test. Under conditions column ..deleted what was there. It now reads ... Pulse on RS+pin,
See Figure 15
-Page 6:
ts test. Removed Gain = 100 and Gain = 100V/V in both description and conditions columns
respectively.
-Page 9
Added Figure 15 and adjusted figure numbers to account for the added figure.
12/14/09
FN6973.0
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL28005
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
13
FN6973.2
May 27, 2010
ISL28005
Package Outline Drawing
P5.064A
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 0, 2/10
1.90
0-3°
D
A
0.08-0.20
5
4
PIN 1
INDEX AREA
2.80
3
1.60
3
0.15 C D
2x
2
5
(0.60)
0.20 C
2x
0.95
SEE DETAIL X
B
0.40 ±0.05
3
END VIEW
0.20 M C A-B D
TOP VIEW
10° TYP
(2 PLCS)
2.90
5
H
0.15 C A-B
2x
C
1.45 MAX
1.14 ±0.15
0.10 C
SIDE VIEW
SEATING PLANE
(0.25) GAUGE
PLANE
0.45±0.1
0.05-0.15
4
DETAIL "X"
(0.60)
(1.20)
NOTES:
(2.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5M-1994.
3.
Dimension is exclusive of mold flash, protrusions or gate burrs.
4.
Foot length is measured at reference to guage plane.
5.
This dimension is measured at Datum “H”.
6.
Package conforms to JEDEC MO-178AA.
(0.95)
(1.90)
TYPICAL RECOMMENDED LAND PATTERN
14
FN6973.2
May 27, 2010