ISL55012 ® Data Sheet August 25, 2010 MMIC Silicon Bipolar Broadband Amplifier Features The ISL55012 is a high performance gain block featuring a Darlington configuration using high fT transistors and excellent thermal performance. They are an ideal choice for DVB-S LNB cable receiver applications. • Input Impedance of 75Ω Other members of the family include: • Noise Figure of 4.7dB @ 2GHz ISL55012 and ISL55015 match a 75Ω source to a 50Ω load. ISL55013 and ISL55014 match a 50Ω source to a 50Ω load. • OIP3 of 30dBm @ 1GHz Ordering Information PART NUMBER (Note) ISL55012IEZ-T7 PART MARKING CCG • Output Impedance of 50Ω • Gain of 18dB @ 1GHz • Low Input and Output Return Losses • Pb-Free Available (RoHS compliant) PACKAGE (Pb-Free) 6 Ld SC-70 PKG. DWG. NUMBER P6.049A * Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Typical Application Circuit Applications • LNB and LNB-T (HDTV) Amplifiers • IF Gain Blocks for Satellite and Terrestrial STBs • PA Driver Amplifier • Wireless Data, Satellite • Bluetooth/WiFi • Satellite Locator and Signal Strength Meters Pinout ISL55012 (6 LD SC-70) TOP VIEW +5V 0.1µF 24Ω 100pF 3 68pF 4 6 1, 2, 5 1 FN6258.2 100pF 100nH 0.1µF GND 1 6 OUT GND 2 5 GND IN 3 4 VSP 68pF CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2006, 2007, 2009. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL55012 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage from VSP to GND . . . . . . . . . . . . . . . . . . . . . . . . 6V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . VS+ +0.3V to GND -0.3V Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +125°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) . . .6000V Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . .300V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +125°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C Thermal Resistance (Typical, Note 1) θJA (°C/W) 6 Ld SC-70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.. 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Electrical Specifications PARAMETER VSP = +5V, ZRSC = ZLOAD = 50Ω, TA = +25°C, 24Ω VSP to OUT, unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT 5.5 V Vsp Supply Voltage To operate below 5V, the 24Ω resistor to supply should be reduced 3.0 Gt Small Signal Gain 1.0GHz 17 18.3 19.5 dB 1.5GHz 16.1 17.4 18.6 dB 2.0GHz 15.1 16.6 17.6 dB 1.0GHz 16 17.7 19 dBm 2.0GHz 15.9 17.2 18.9 dBm P1dB OIP3 Output Power at 1dB Compression Output Third Order Intercept Point 1.0GHz 30 dBm 2.0GHz 27 dBm OIP2 Output Second Order Intercept Point Input tones at 1.0GHz and 1.1GHz, at Input Power = -15dBm, Output tone 2.1GHz 44.2 dBm BW 3dB Bandwidth 3dB below Gain @ 500MHz 2.4 GHz IRL Input Return Loss 1.0GHz ZRSC = 75Ω, ZLOAD = 50Ω 23.5 dB ORL Output Return Loss 1.0GHz ZRSC = 75Ω, ZLOAD = 50Ω 21.8 dB RISOL Reverse Isolation 2.0GHz 22.4 dB NF Noise Figure 2.0GHz 4.7 dB ID Device Operating Current 2 56 63.5 71 mA FN6258.2 August 25, 2010 ISL55012 Device Test Setup AGILENT _8753ES VNA 50Ω 50Ω CONNECTORLESS PLATFORM 50Ω DC BLOCK PIN 3 PIN 6 DUT PICOSECOND LABS MODEL 5542 50Ω BIAS TEE 5V PICOSECOND LABS MODEL 5508-110 24Ω I1 I2 IDEVICE OUTPUT REFERENCE PLANE INPUT REFERENCE PLANE 5V POWER SUPPLY Typical Performance Curves ZSRC = 75Ω, ZLOAD = 50Ω 24 32 28 20 16 20 ORL (dB) IRL (dB) 24 16 12 12 8 8 4 4 0 0.5G 1.0G 1.5G 2.0G 2.5G 0 0.5G 3.0G 1.0G FREQUENCY (Hz) 1.5G 2.0G 2.5G 3.0G FREQUENCY (Hz) FIGURE 1. INPUT RETURN LOSS vs FREQUENCY FIGURE 2. OUTPUT RETURN LOSS vs FREQUENCY Typical Performance Curves 50Ω Environment 20 0 -2 -4 16 S11 (dB) S21 (dB) 18 14 -6 -8 -10 -12 12 -14 10 0.5G 1.0G 1.5G 2.0G 2.5G FREQUENCY (Hz) FIGURE 3. |S21| vs FREQUENCY 3 3.0G -16 0.5G 1.0G 1.5G 2.0G 2.5G 3.0G FREQUENCY (Hz) FIGURE 4. |S11| vs FREQUENCY FN6258.2 August 25, 2010 ISL55012 Typical Performance Curves 50Ω Environment (Continued) -8 -18 -10 -12 S12 (dB) S22 (dB) -20 -22 -14 -16 -18 -20 -22 -24 0.5G 1.0G 1.5G 2.0G FREQUENCY (Hz) 2.5G -24 0.5G 3.0G 1.0G 1.5G 2.0G 2.5G 3.0G FREQUENCY (Hz) FIGURE 6. |S22| vs FREQUENCY FIGURE 5. |S12| vs FREQUENCY 20 34 10 32 FUNDAMENTAL (1GHz) 0 HD (dBm) OIP3 (dBm) 30 28 26 FUNDAMENTAL (1.1GHz) -10 -20 -30 -40 24 -50 22 IM2 (2.1GHz) -60 20 0.5G 1.0G 1.5G 2.0G 2.5G -70 -25 3.0G -20 FREQUENCY (GHz) 7 -5 0 2.5G 3.0G 1dB OUTPUT COMPRESSION POINT (dBm) 20 6 NOISE FIGURE (dB) -10 FIGURE 8. IM2 vs INPUT POWER FIGURE 7. OIP3 vs FREQUENCY 5 4 3 2 1 0 0.5G -15 INPUT POWER (dBm) 1.0G 1.5G 2.0G FREQUENCY (Hz) 2.5G FIGURE 9. NOISE FIGURE vs FREQUENCY 4 3.0G 19 18 17 16 15 14 13 12 11 10 0.5G 1.0G 1.5G 2.0G FREQUENCY (Hz) FIGURE 10. P1dB vs FREQUENCY FN6258.2 August 25, 2010 ISL55012 1.8 0.6 1.6 0.7 1.4 1.2 0.8 0.9 1.0 Typical Performance Curves 50Ω Environment (Continued) 0.5 2.0 0.2 0.4 3.0 0.4 0.6 0.3 0.8 4.0 1.0 1.0 5.0 6.0 0.2 0.8 7.0 8.0 9.0 10 0.6 0.1 50 20 10 5.0 4.0 3.0 2.0 1.8 1.6 1.4 1.2 0.9 0.8 0.7 0.6 0.5 0.4 2.2 20 S11 1.0 0.4 0.6 2.2 7.0 0.3 1.0 1.0 0.2 0.8 1.0 6.0 0.2 50 8.0 9.0 10 0.2 0.5 GHz 3 GHz 0.1 0.5 GHz 50 0 20 0.2 0.1 0.4 S22 5.0 1.0 3 GHz 4.0 0.8 0.3 3.0 0.6 0.4 1.8 2.0 0.5 0.4 1.2 1.0 0.8 0.9 1.4 0.7 1.6 0.6 0.2 RF Café 2002 FIGURE 11. S11 AND S22 vs FREQUENCY 5 FN6258.2 August 25, 2010 Small Outline Transistor Plastic Packages (SC70-6) 0.20 (0.008) M VIEW C C P6.049A CL 6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE e b 6 INCHES 5 4 CL CL E1 E 1 2 3 e1 SYMBOL MIN MAX MIN MAX NOTES A 0.031 0.039 0.80 1.00 - A1 0.001 0.004 0.025 0.10 - A2 0.034 0.036 0.85 0.90 - b 0.006 0.012 0.15 0.30 - b1 0.006 0.010 0.15 0.25 - c 0.004 0.008 0.10 0.20 6 D c1 0.004 0.006 0.10 0.15 6 CL D 0.073 0.085 1.85 2.15 3 C E A MILLIMETERS A2 SEATING PLANE A1 -C- E1 e e1 L 0.10 (0.004) C WITH b PLATING b1 0.084 BSC 0.045 c1 1.15 0.0256 Ref 0.018 - 1.35 3 0.65 Ref 0.0512 Ref 0.010 - 1.30 Ref 0.26 - 0.46 4 L1 0.016 Ref. 0.400 Ref. - L2 0.006 BSC 0.15 BSC - N c 0.053 2.1 BSC 6 6 5 R 0.004 - 0.10 - α 0° 8° 0° 8° Rev. 0 7/05 NOTES: BASE METAL 1. Dimensioning and tolerance per ASME Y14.5M-1994. 2. Package conforms to EIAJ SC70 and JEDEC MO203AB. 4X θ1 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. R1 4. Footlength L measured at reference to gauge plane. 5. “N” is the number of terminal positions. R GAUGE PLANE SEATING PLANE L C L1 α L2 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only 4X θ1 VIEW C All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 6 FN6258.2 August 25, 2010