c165 Data Sheet v2.0

Da t a Sh e e t , V2 . 0 , De c . 2 0 0 0
C165
16-Bit Single-Chip Microcontroller
Microcontrollers
N e v e r
s t o p
t h i n k i n g .
Edition 2000-12
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 2000.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
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approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
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and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Da t a Sh e e t , V2 . 0 , De c . 2 0 0 0
C165
16-Bit Single-Chip Microcontroller
Microcontrollers
N e v e r
s t o p
t h i n k i n g .
C165
Revision History:
2000-12
Previous Version:
1998-12
01.96
07.95
09.94
V2.0
Update 0.5µ technology
3 Volt Addendum
25 MHz Addendum
Data Sheet
Page
Subjects (major changes since last revision)
All
Converted to Infineon layout
2
ROM derivatives removed, 25-MHz derivatives and 3 V derivatives
included
6ff
Pin numbers for TQFP added
14
Address window arbitration and master/slave mode introduced
32
New standard layout for section “Absolute Maximum Ratings”
33
Section “Operating Conditions” added
34f
Parameter “RSTIN pullup” replaced by “RSTIN current”
36f
DC Characteristics for reduced supply voltage added
38f
Separate specification for power consumption with greatly improved values
40ff
Description of clock generation improved
45, 55, 65
Timing adapted to 25 MHz
48, 58, 66
Timing for reduced supply voltage added
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16-Bit Single-Chip Microcontroller
C166 Family
C165
C165
• High Performance 16-bit CPU with 4-Stage Pipeline
– 80 ns Instruction Cycle Time at 25 MHz CPU Clock
– 400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit)
– Enhanced Boolean Bit Manipulation Facilities
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Single-Cycle Context Switching Support
– 16 MBytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area
• 16-Priority-Level Interrupt System with 28 Sources, Sample-Rate down to 40 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC)
• Clock Generation via prescaler or via direct clock input
• On-Chip Memory Modules
– 2 KBytes On-Chip Internal RAM (IRAM)
• On-Chip Peripheral Modules
– Two Multi-Functional General Purpose Timer Units with 5 Timers
– Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)
• Up to 16 MBytes External Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit
Data Bus Width
– Five Programmable Chip-Select Signals
– Hold- and Hold-Acknowledge Bus Arbitration Support
• Idle and Power Down Modes
• Programmable Watchdog Timer
• Up to 77 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis
• Power Supply: the C165 can operate from a 5 V or a 3 V power supply
• Supported by a Large Range of Development Tools like C-Compilers,
Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers, Programming Boards
• On-Chip Bootstrap Loader
• 100-Pin MQFP Package (0.65 mm pitch)
• 100-Pin TQFP Package (0.5 mm pitch)
Data Sheet
1
V2.0, 2000-12
C165
This document describes several derivatives of the C165 group. Table 1 enumerates
these derivatives and summarizes the differences. As this document refers to all of these
derivatives, some descriptions may not apply to a specific product.
Table 1
C165 Derivative Synopsis
Derivative1)
Max. Operating
Frequency
Operating
Voltage
Package
SAF-C165-LM
20 MHz
4.5 to 5.5 V
MQFP-100
SAB-C165-LM
20 MHz
4.5 to 5.5 V
MQFP-100
SAF-C165-L25M
25 MHz
4.5 to 5.5 V
MQFP-100
SAB-C165-L25M
25 MHz
4.5 to 5.5 V
MQFP-100
SAF-C165-LF
20 MHz
4.5 to 5.5 V
TQFP-100
SAB-C165-LF
20 MHz
4.5 to 5.5 V
TQFP-100
SAF-C165-L25F
25 MHz
4.5 to 5.5 V
TQFP-100
SAB-C165-L25F
25 MHz
4.5 to 5.5 V
TQFP-100
SAF-C165-LM3V
20 MHz
3.0 to 3.6 V
MQFP-100
SAB-C165-LM3V
20 MHz
3.0 to 3.6 V
MQFP-100
SAF-C165-LF3V
20 MHz
3.0 to 3.6 V
TQFP-100
SAB-C165-LF3V
20 MHz
3.0 to 3.6 V
TQFP-100
1)
This Data Sheet is valid for devices starting with and including design step HA.
For simplicity all versions are referred to by the term C165 throughout this document.
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:
• the derivative itself, i.e. its function set, the temperature range, and the supply voltage
• the package and the type of delivery.
For the available ordering codes for the C165 please refer to the “Product Catalog
Microcontrollers”, which summarizes all available microcontroller variants.
Note: The ordering codes for Mask-ROM versions are defined for each product after
verification of the respective ROM code.
Data Sheet
2
V2.0, 2000-12
C165
Introduction
The C165 is a derivative of the Infineon C166 Family of full featured single-chip CMOS
microcontrollers. It combines high CPU performance (up to 12.5 million instructions per
second) with peripheral functionality and enhanced IO-capabilities. The C165 is
especially suited for cost sensitive applications.
VDD
VSS
XTAL1
XTAL2
Port 0
16 Bit
RSTIN
RSTOUT
Port 1
16 Bit
NMI
Port 2
8 Bit
EA
READY
Port 3
15 Bit
C165
Port 4
8 Bit
ALE
RD
WR/WRL
Port 6
8 Bit
Port 5
6 Bit
MCL04824
Figure 1
Data Sheet
Logic Symbol
3
V2.0, 2000-12
C165
P5.12/T6IN
P5.11/T5EUD
P5.10/T6EUD
P2.15/EX7IN
P2.14/EX6IN
P2.13/EX5IN
P2.12/EX4IN
P2.11/EX3IN
P2.10/EX2IN
P2.9/EX1IN
P2.8/EX0IN
P6.7/BREQ
P6.6/HLDA
P6.5/HOLD
P6.4/CS4
P6.3/CS3
P6.2/CS2
P6.1/CS1
P6.0/CS0
NMI
RSTOUT
RSTIN
VDD
VSS
P1H.7/A15
Pin Configuration TQFP Package
(top view)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
1
74
2
3
73
72
4
5
71
6
70
7
69
8
68
9
67
10
66
65
11
64
12
13
63
62
14
15
61
16
60
59
17
18
58
19
57
20
56
55
21
54
22
23
53
52
24
25
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
C165
P4.3/A19
VSS
VDD
P4.4/A20
P4.5/A21
P4.6/A22
P4.7/A23
RD
WR/WRL
READY
ALE
EA
V DD
V SS
N.C.
P0L.0/AD0
P0L.1/AD1
P0L.2/AD2
P0L.3/AD3
P0L.4/AD4
P0L.5/AD5
P0L.6/AD6
P0L.7/AD7
VDD
VSS
P5.13/T5IN
P5.14/T4EUD
P5.15/T2EUD
VSS
XTAL1
XTAL2
VDD
P3.0
P3.1/T6OUT
P3.2/CAPIN
P3.3/T3OUT
P3.4/T3EUD
P3.5/T4IN
P3.6/T3IN
P3.7/T2IN
P3.8/MRST
P3.9/MTSR
P3.10/TxD0
P3.11/RxD0
P3.12/BHE/WRH
P3.13/SCLK
P3.15/CLKOUT
P4.0/A16
P4.1/A17
P4.2/A18
P1H.6/A14
P1H.5/A13
P1H.4/A12
P1H.3/A11
P1H.2/A10
VSS
VDD
P1H.1/A9
P1H.0/A8
P1L.7/A7
P1L.6/A6
P1L.5/A5
P1L.4/A4
P1L.3/A3
P1L.2/A2
P1L.1/A1
P1L.0/A0
P0H.7/AD15
P0H.6/AD14
P0H.5/AD13
P0H.4/AD12
P0H.3/AD11
P0H.2/AD10
P0H.1/AD9
P0H.0/AD8
MCP02216
Figure 2
Data Sheet
4
V2.0, 2000-12
C165
P5.10/T6EUD
P2.15/EX7IN
P2.14/EX6IN
P2.13/EX5IN
P2.12/EX4IN
P2.11/EX3IN
P2.10/EX2IN
P2.9/EX1IN
P2.8/EX0IN
P6.7/BREQ
P6.6/HLDA
P6.5/HOLD
P6.4/CS4
P6.3/CS3
P6.2/CS2
P6.1/CS1
P6.0/CS0
NMI
RSTOUT
RSTIN
Pin Configuration MQFP Package
(top view)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
P5.11/T5EUD
P5.12/T6IN
P5.13/T5IN
P5.14/T4EUD
P5.15/T2EUD
V SS
XTAL1
XTAL2
VDD
P3.0
P3.1/T6OUT
P3.2/CAPIN
P3.3/T3OUT
P3.4/T3EUD
P3.5/T4IN
P3.6/T3IN
P3.7/T2IN
P3.8/MRST
P3.9/MTSR
P3.10/TxD0
P3.11/RxD0
P3.12/BHE/WRH
P3.13/SCLK
P3.15/CLKOUT
P4.0/A16
P4.1/A17
P4.2/A18
P4.3/A19
V SS
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
C165
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDD
VSS
P1H.7/A15
P1H.6/A14
P1H.5/A13
P1H.4/A12
P1H.3/A11
P1H.2/A10
VSS
VDD
P1H.1/A9
P1H.0/A8
P1L.7/A7
P1L.6/A6
P1L.5/A5
P1L.4/A4
P1L.3/A3
P1L.2/A2
P1L.1/A1
P1L.0/A0
P0H.7/AD15
P0H.6/AD14
P0H.5/AD13
P0H.4/AD12
P0H.3/AD11
P0H.2/AD10
P0H.1/AD9
P0H.0/AD8
VSS
VDD
P4.4/A20
P4.5/A21
P4.6/A22
P4.7/A23
RD
WR/WRL
READY
ALE
EA
V DD
V SS
N.C.
P0L.0/AD0
P0L.1/AD1
P0L.2/AD2
P0L.3/AD3
P0L.4/AD4
P0L.5/AD5
P0L.6/AD6
P0L.7/AD7
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MCP02144
Figure 3
Data Sheet
5
V2.0, 2000-12
C165
Table 2
Pin Definitions and Functions
Symbol Pin Nr Pin Nr Input
TQFP MQFP Outp.
Function
XTAL1
5
7
I
XTAL1:
XTAL2
6
8
O
P3
Input to the oscillator amplifier and input
to the internal clock generator
XTAL2:
Output of the oscillator amplifier circuit.
To clock the device from an external source, drive
XTAL1, while leaving XTAL2 unconnected.
Minimum and maximum high/low and rise/fall times
specified in the AC Characteristics must be
observed.
IO
Port 3 is a 15-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits.
For a pin configured as input, the output driver is put
into high-impedance state. Port 3 outputs can be
configured as push/pull or open drain drivers. The
Port 3 pins serve for following alternate functions:
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
8
9
10
11
12
13
10
11
12
13
14
15
O
I
O
I
I
T6OUT
CAPIN
T3OUT
T3EUD
T4IN
P3.6
P3.7
14
15
16
17
I
I
T3IN
T2IN
P3.8
16
18
I/O
MRST
P3.9
17
19
I/O
MTSR
P3.10
P3.11
P3.12
18
19
20
20
21
22
P3.13
P3.15
21
22
23
24
O
I/O
O
O
I/O
O
TxD0
RxD0
BHE
WRH
SCLK
CLKOUT
Data Sheet
6
GPT2 Timer T6 Toggle Latch Output
GPT2 Register CAPREL Capture Input
GPT1 Timer T3 Toggle Latch Output
GPT1 Timer T3 Ext. Up/Down Ctrl Input
GPT1 Timer T4
Count/Gate/Reload/Capture Input
GPT1 Timer T3 Count/Gate Input
GPT1 Timer T2
Count/Gate/Reload/Capture Input
SSC Master-Receive/Slave-Transmit
Input/Output
SSC Master-Transmit/Slave-Receive
Output/Input
ASC0 Clock/Data Output (Asyn./Sync.)
ASC0 Data Inp. (Asyn.) or In/Out (Sync)
Ext. Memory High Byte Enable Signal,
Ext. Memory High Byte Write Strobe
SSC Master Cl. Output / Slave Cl. Input
System Clock Output (= CPU Clock)
V2.0, 2000-12
C165
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin Nr Pin Nr Input
TQFP MQFP Outp.
IO
P4
Function
Port 4 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits.
For a pin configured as input, the output driver is put
into high-impedance state. Port 4 can be used to
output the segment address lines:
A16 Least Significant Segment Address Line
A17 Segment Address Line
A18 Segment Address Line
A19 Segment Address Line
A20 Segment Address Line
A21 Segment Address Line
A22 Segment Address Line
A23 Most Significant Segment Address Line
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
23
24
25
26
29
30
31
32
25
26
27
28
31
32
33
34
O
O
O
O
O
O
O
O
RD
33
35
O
External Memory Read Strobe. RD is activated for
every external instruction or data read access.
WR/
WRL
34
36
O
External Memory Write Strobe. In WR-mode this pin
is activated for every external data write access. In
WRL-mode this pin is activated for low byte data
write accesses on a 16-bit bus, and for every data
write access on an 8-bit bus. See WRCFG in register
SYSCON for mode selection.
READY 35
37
I
Ready Input. When the Ready function is enabled, a
high level at this pin during an external memory
access will force the insertion of memory cycle
waitstates until the pin returns to a low level.
An internal pullup device holds this pin high when
nothing is driving it.
ALE
36
38
O
Address Latch Enable Output. Can be used for
latching the address into external memory or an
address latch in the multiplexed bus modes.
EA
37
39
I
External Access Enable pin. A low level at this pin
during and after Reset forces the C165 to begin
instruction execution out of external memory. A high
level forces execution out of the internal program
memory.
“ROMless” versions must have this pin tied to ‘0’.
Data Sheet
7
V2.0, 2000-12
C165
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin Nr Pin Nr Input
TQFP MQFP Outp.
Function
NC
–
This pin is not connected in the C165.
No connection to the PCB is required.
IO
PORT0 consists of the two 8-bit bidirectional I/O
ports P0L and P0H. It is bit-wise programmable for
input or output via direction bits. For a pin configured
as input, the output driver is put into high-impedance
state. In case of an external bus configuration,
PORT0 serves as the address (A) and address/data
(AD) bus in multiplexed bus modes and as the data
(D) bus in demultiplexed bus modes.
Demultiplexed bus modes:
Data Path Width:
8-bit
16-bit
P0L.0 – P0L.7:
D0 – D7
D0 – D7
P0H.0 – P0H.7:
I/O
D8 – D15
Multiplexed bus modes:
Data Path Width:
8-bit
16-bit
P0L.0 – P0L.7:
AD0 – AD7 AD0 – AD7
P0H.0 – P0H.7:
A8 – A15
AD8 – AD15
IO
PORT1 consists of the two 8-bit bidirectional I/O
ports P1L and P1H. It is bit-wise programmable for
input or output via direction bits. For a pin configured
as input, the output driver is put into high-impedance
state. PORT1 is used as the 16-bit address bus (A)
in demultiplexed bus modes and also after switching
from a demultiplexed bus mode to a multiplexed bus
mode.
40
42
PORT0
P0L.0-7 41-48
43-50
P0H.0-7 51-58
53-60
PORT1
P1L.0-7 59-66
61-68
P1H.0-7 67,68, 69-70,
71-76 73-78
Data Sheet
8
V2.0, 2000-12
C165
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin Nr Pin Nr Input
TQFP MQFP Outp.
Function
RSTIN
Reset Input with Schmitt-Trigger characteristics. A
low level at this pin while the oscillator is running
resets the C165. An internal pullup resistor permits
power-on reset using only a capacitor connected to
VSS. A spike filter suppresses input pulses < 10 ns.
Input pulses >100 ns safely pass the filter. The
minimum duration for a safe recognition should be
100 ns + 2 CPU clock cycles.
In bidirectional reset mode (enabled by setting bit
BDRSTEN in register SYSCON) the RSTIN line is
internally pulled low for the duration of the internal
reset sequence upon any reset (HW, SW, WDT).
See note below this table.
79
81
I/O
Note: To let the reset configuration of PORT0 settle
a reset duration of ca. 1 ms is recommended.
RST
OUT
80
82
O
Internal Reset Indication Output. This pin is set to a
low level when the part is executing either a
hardware-, a software- or a watchdog timer reset.
RSTOUT remains low until the EINIT (end of
initialization) instruction is executed.
NMI
81
83
I
Non-Maskable Interrupt Input. A high to low
transition at this pin causes the CPU to vector to the
NMI trap routine. When the PWRDN (power down)
instruction is executed, the NMI pin must be low in
order to force the C165 to go into power down mode.
If NMI is high, when PWRDN is executed, the part
will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
Data Sheet
9
V2.0, 2000-12
C165
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin Nr Pin Nr Input
TQFP MQFP Outp.
IO
P6
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
82
83
84
85
86
87
88
84
85
86
87
88
89
90
O
O
O
O
O
I
I/O
P6.7
89
91
O
IO
P2
P2.8
P2.9
P2.10
P2.11
P2.12
P2.13
P2.14
P2.15
90
91
92
93
94
95
96
97
92
93
94
95
96
97
98
99
P5
P5.10
P5.11
P5.12
P5.13
P5.14
P5.15
I
I
I
I
I
I
I
I
I
98
99
100
1
2
3
Data Sheet
100
1
2
3
4
5
I
I
I
I
I
I
Function
Port 6 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits.
For a pin configured as input, the output driver is put
into high-impedance state. Port 6 outputs can be
configured as push/pull or open drain drivers.
The Port 6 pins also serve for alternate functions:
Chip Select 0 Output
CS0
Chip Select 1 Output
CS1
Chip Select 2 Output
CS2
Chip Select 3 Output
CS3
Chip Select 4 Output
CS4
External Master Hold Request Input
HOLD
Hold Acknowledge Outp.(master mode)
HLDA
or Input (slave mode)
Bus Request Output
BREQ
Port 2 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits.
For a pin configured as input, the output driver is put
into high-impedance state. Port 2 outputs can be
configured as push/pull or open drain drivers. The
following Port 2 pins serve for alternate functions:
EX0IN
Fast External Interrupt 0 Input
EX1IN
Fast External Interrupt 1 Input
EX2IN
Fast External Interrupt 2 Input
EX3IN
Fast External Interrupt 3 Input
EX4IN
Fast External Interrupt 4 Input
EX5IN
Fast External Interrupt 5 Input
EX6IN
Fast External Interrupt 6 Input
EX7IN
Fast External Interrupt 7 Input
Port 5 is a 6-bit input-only port with Schmitt-Trigger
char. The pins of Port 5 also serve as timer inputs:
T6EUD
GPT2 Timer T6 Ext. Up/Down Ctrl Input
T5EUD
GPT2 Timer T5 Ext. Up/Down Ctrl Input
T6IN
GPT2 Timer T6 Count Input
T5IN
GPT2 Timer T5 Count Input
T4EUD
GPT1 Timer T4 Ext. Up/Down Ctrl Input
T2EUD
GPT1 Timer T2 Ext. Up/Down Ctrl Input
10
V2.0, 2000-12
C165
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin Nr Pin Nr Input
TQFP MQFP Outp.
Function
VDD
7, 28, 9, 30, –
38,
40, 51,
49,
71, 80
69, 78
Digital Supply Voltage:
+ 5 V or + 3 V during normal operation and idle
mode.
≥ 2.5 V during power down mode.
VSS
4, 27, 6, 29, –
41, 52,
39,
50,
72, 79
70, 77
Digital Ground.
Note: The following behavioural differences must be observed when the bidirectional
reset is active:
• Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared
automatically after a reset.
• The reset indication flags always indicate a long hardware reset.
• The PORT0 configuration is treated like on a hardware reset. Especially the bootstrap
loader may be activated when P0L.4 is low.
• Pin RSTIN may only be connected to external reset devices with an open drain output
driver.
• A short hardware reset is extended to the duration of the internal reset sequence.
Data Sheet
11
V2.0, 2000-12
C165
Functional Description
The architecture of the C165 combines advantages of both RISC and CISC processors
and of advanced peripheral subsystems in a very well-balanced way. In addition the
on-chip memory blocks allow the design of compact systems with maximum
performance.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the C165.
Note: All time specifications refer to a CPU clock of 25 MHz
(see definition in the AC Characteristics section).
16
Data
32
Internal
ROM
Area
16
CPU
Instr. / Data
Data
16
Dual Port
C166-Core
ProgMem
IRAM
Internal
RAM
2 KByte
Osc
XTAL
PEC
External Instr. / Data
Interrupt Controller 16-Level
Priority
WDT
Peripheral Data Bus
16
ASC0
SSC
(USART)
(SPI)
GPT
T2
EBC
T3
XBUS Control
External Bus
Control
T4
Port 0
16
Figure 4
Interrupt Bus
Port 2
8
Port 6
8
Port 4
On-Chip XBUS (16-Bit Demux)
16
T5
BRGen
Port 1
16
BRGen
Port 3
15
T6
8
Port 5
6
Block Diagram
The program memory, the internal RAM (IRAM) and the set of generic peripherals are
connected to the CPU via separate buses. A fourth bus, the XBUS, connects external
resources as well as additional on-chip resoures, the X-Peripherals (see Figure 4).
Data Sheet
12
V2.0, 2000-12
C165
Memory Organization
The memory space of the C165 is configured in a Von Neumann architecture which
means that code memory, data memory, registers and I/O ports are organized within the
same linear address space which includes 16 MBytes. The entire memory space can be
accessed bytewise or wordwise. Particular portions of the on-chip memory have
additionally been made directly bitaddressable.
The C165 is prepared to incorporate on-chip program memory (not in the ROM-less
derivatives, of course) for code or constant data. The internal ROM area can be mapped
either to segment 0 or segment 1.
2 KBytes of on-chip Internal RAM (IRAM) are provided as a storage for user defined
variables, for the system stack, general purpose register banks and even for code. A
register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0,
…, RL7, RH7) so-called General Purpose Registers (GPRs).
1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the C166 Family.
In order to meet the needs of designs where more memory is required than is provided
on chip, up to 16 MBytes of external RAM and/or ROM can be connected to the
microcontroller.
Data Sheet
13
V2.0, 2000-12
C165
External Bus Controller
All of the external memory accesses are performed by a particular on-chip External Bus
Controller (EBC). It can be programmed either to Single Chip Mode when no external
memory is required, or to one of four different external memory access modes, which are
as follows:
–
–
–
–
16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed
16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed
16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed
16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed
In the demultiplexed bus modes, addresses are output on PORT1 and data is input/
output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses
and data use PORT0 for input/output.
Important timing characteristics of the external bus interface (Memory Cycle Time,
Memory Tri-State Time, Length of ALE and Read Write Delay) have been made
programmable to allow the user the adaption of a wide range of different types of
memories and external peripherals.
In addition, up to 4 independent address windows may be defined (via register pairs
ADDRSELx / BUSCONx) which control the access to different resources with different
bus characteristics. These address windows are arranged hierarchically where
BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to
locations not covered by these 4 address windows are controlled by BUSCON0.
Up to 5 external CS signals (4 windows plus default) can be generated in order to save
external glue logic. The C165 offers the possibility to switch the CS outputs to an
unlatched mode. In this mode the internal filter logic is switched off and the CS signals
are directly generated from the address. The unlatched CS mode is enabled by setting
CSCFG (SYSCON.6).
Access to very slow memories or memories with varying access times is supported via
a particular ‘Ready’ function.
A HOLD/HLDA protocol is available for bus arbitration and allows to share external
resources with other bus masters. The bus arbitration is enabled by setting bit HLDEN
in register PSW. After setting HLDEN once, pins P6.7 … P6.5 (BREQ, HLDA, HOLD)
are automatically controlled by the EBC. In Master Mode (default after reset) the HLDA
pin is an output. By setting bit DP6.7 to ‘1’ the Slave Mode is selected where pin HLDA
is switched to input. This allows to directly connect the slave controller to another master
controller without glue logic.
For applications which require less than 16 MBytes of external memory space, this
address space can be restricted to 1 MByte, 256 KByte, or to 64 KByte. In this case
Port 4 outputs four, two, or no address lines at all. It outputs all 8 address lines, if an
address space of 16 MBytes is used.
Data Sheet
14
V2.0, 2000-12
C165
Central Processing Unit (CPU)
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic
and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a
separate multiply and divide unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the C165’s instructions can be executed
in just one machine cycle which requires 80 ns at 25 MHz CPU clock. For example, shift
and rotate instructions are always processed during one machine cycle independent of
the number of bits to be shifted. All multiple-cycle instructions have been optimized so
that they can be executed very fast as well: branches in 2 cycles, a 16 × 16 bit
multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline
optimization, the so-called ‘Jump Cache’, allows reducing the execution time of
repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
CPU
Internal
RAM
SP
STKOV
STKUN
MDH
MDL
R15
Exec. Unit
Instr. Ptr.
Instr. Reg.
Mul/Div-HW
Bit-Mask Gen
General
4-Stage
Pipeline
R15
Purpose
ALU
32
ROM
16
(16-bit)
Barrel - Shifter
Registers
R0
PSW
SYSCON
Context Ptr.
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3
ADDRSEL 4
Data Page Ptr.
Code Seg. Ptr.
R0
16
MCB02147
Figure 5
Data Sheet
CPU Block Diagram
15
V2.0, 2000-12
C165
The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal.
These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer
(CP) register determines the base address of the active register bank to be accessed by
the CPU at any time. The number of register banks is only restricted by the available
internal RAM space. For easy parameter passing, a register bank may overlap others.
A system stack of up to 1024 words is provided as a storage for temporary data. The
system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the
stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly
compared against the stack pointer value upon each stack access for the detection of a
stack overflow or underflow.
The high performance offered by the hardware implementation of the CPU can efficiently
be utilized by a programmer via the highly efficient C165 instruction set which includes
the following instruction classes:
–
–
–
–
–
–
–
–
–
–
–
–
Arithmetic Instructions
Logical Instructions
Boolean Bit Manipulation Instructions
Compare and Loop Control Instructions
Shift and Rotate Instructions
Prioritize Instruction
Data Movement Instructions
System Stack Instructions
Jump and Call Instructions
Return Instructions
System Control Instructions
Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes
and words. A variety of direct, indirect or immediate addressing modes are provided to
specify the required operands.
Data Sheet
16
V2.0, 2000-12
C165
Interrupt System
With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of
internal program execution), the C165 is capable of reacting very fast to the occurrence
of non-deterministic events.
The architecture of the C165 supports several mechanisms for fast and flexible response
to service requests that can be generated from various sources internal or external to the
microcontroller. Any of these interrupt requests can be programmed to being serviced by
the Interrupt Controller or by the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is
suspended and a branch to the interrupt vector table is performed, just one cycle is
‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a
single byte or word data transfer between any two memory locations with an additional
increment of either the PEC source or the destination pointer. An individual PEC transfer
counter is implicity decremented for each PEC service except when performing in the
continuous transfer mode. When this counter reaches zero, a standard interrupt is
performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data.
The C165 has 8 PEC channels each of which offers such fast interrupt-driven data
transfer capabilities.
A separate control register which contains an interrupt request flag, an interrupt enable
flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via
its related register, each source can be programmed to one of sixteen interrupt priority
levels. Once having been accepted by the CPU, an interrupt service can only be
interrupted by a higher prioritized service request. For the standard interrupt processing,
each of the possible interrupt sources has a dedicated vector location.
Fast external interrupt inputs are provided to service external interrupts with high
precision requirements. These fast interrupt inputs feature programmable edge
detection (rising edge, falling edge or both edges).
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with
an individual trap (interrupt) number.
Table 3 shows all of the possible C165 interrupt sources and the corresponding
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.
Note: Interrupt nodes which are not used by associated peripherals, may be used to
generate software controlled interrupt requests by setting the respective interrupt
request bit (xIR).
Data Sheet
17
V2.0, 2000-12
C165
Table 3
C165 Interrupt Nodes
Source of Interrupt or Request
PEC Service Request Flag
Enable
Flag
Interrupt
Vector
Vector
Location
Trap
Number
External Interrupt 0
CC8IR
CC8IE
CC8INT
00’0060H
18H
External Interrupt 1
CC9IR
CC9IE
CC9INT
00’0064H
19H
External Interrupt 2
CC10IR
CC10IE
CC10INT
00’0068H
1AH
External Interrupt 3
CC11IR
CC11IE
CC11INT
00’006CH
1BH
External Interrupt 4
CC12IR
CC12IE
CC12INT
00’0070H
1CH
External Interrupt 5
CC13IR
CC13IE
CC13INT
00’0074H
1DH
External Interrupt 6
CC14IR
CC14IE
CC14INT
00’0078H
1EH
External Interrupt 7
CC15IR
CC15IE
CC15INT
00’007CH
1FH
GPT1 Timer 2
T2IR
T2IE
T2INT
00’0088H
22H
GPT1 Timer 3
T3IR
T3IE
T3INT
00’008CH
23H
GPT1 Timer 4
T4IR
T4IE
T4INT
00’0090H
24H
GPT2 Timer 5
T5IR
T5IE
T5INT
00’0094H
25H
GPT2 Timer 6
T6IR
T6IE
T6INT
00’0098H
26H
GPT2 CAPREL Reg.
CRIR
CRIE
CRINT
00’009CH
27H
ASC0 Transmit
S0TIR
S0TIE
S0TINT
00’00A8H
2AH
ASC0 Transmit Buffer
S0TBIR
S0TBIE
S0TBINT
00’011CH
47H
ASC0 Receive
S0RIR
S0RIE
S0RINT
00’00ACH
2BH
ASC0 Error
S0EIR
S0EIE
S0EINT
00’00B0H
2CH
SSC Transmit
SCTIR
SCTIE
SCTINT
00’00B4H
2DH
SSC Receive
SCRIR
SCRIE
SCRINT
00’00B8H
2EH
SSC Error
SCEIR
SCEIE
SCEINT
00’00BCH
2FH
Unassigned node
XP0IR
XP0IE
XP0INT
00’0100H
40H
Unassigned node
XP1IR
XP1IE
XP1INT
00’0104H
41H
Unassigned node
XP2IR
XP2IE
XP2INT
00’0108H
42H
Unassigned node
XP3IR
XP3IE
XP3INT
00’010CH
43H
Unassigned node
CC29IR
CC29IE
CC29INT
00’0110H
44H
Unassigned node
CC30IR
CC30IE
CC30INT
00’0114H
45H
Unassigned node
CC31IR
CC31IE
CC31INT
00’0118H
46H
Data Sheet
18
V2.0, 2000-12
C165
The C165 also provides an excellent mechanism to identify and to process exceptions
or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware
traps cause immediate non-maskable system reaction which is similar to a standard
interrupt service (branching to a dedicated vector table location). The occurence of a
hardware trap is additionally signified by an individual bit in the trap flag register (TFR).
Except when another higher prioritized trap service is in progress, a hardware trap will
interrupt any actual program execution. In turn, hardware trap services can normally not
be interrupted by standard or PEC interrupts.
Table 4 shows all of the possible exceptions or error conditions that can arise during runtime:
Table 4
Hardware Trap Summary
Exception Condition
Trap
Flag
Reset Functions:
– Hardware Reset
– Software Reset
– W-dog Timer Overflow
–
Class A Hardware Traps:
– Non-Maskable Interrupt NMI
– Stack Overflow
STKOF
– Stack Underflow
STKUF
Class B Hardware Traps:
– Undefined Opcode
– Protected Instruction
Fault
– Illegal Word Operand
Access
– Illegal Instruction
Access
– Illegal External Bus
Access
Trap
Vector
Vector
Location
Trap
Number
Trap
Priority
RESET
RESET
RESET
00’0000H
00’0000H
00’0000H
00H
00H
00H
III
III
III
NMITRAP 00’0008H
STOTRAP 00’0010H
STUTRAP 00’0018H
02H
04H
06H
II
II
II
UNDOPC BTRAP
PRTFLT BTRAP
00’0028H
00’0028H
0AH
0AH
I
I
ILLOPA
BTRAP
00’0028H
0AH
I
ILLINA
BTRAP
00’0028H
0AH
I
ILLBUS
BTRAP
00’0028H
0AH
I
Reserved
–
–
[2CH –
3CH]
[0BH –
0FH]
–
Software Traps
– TRAP Instruction
–
–
Any
Any
[00’0000H – [00H –
00’01FCH] 7FH]
in steps
of 4H
Data Sheet
19
Current
CPU
Priority
V2.0, 2000-12
C165
General Purpose Timer (GPT) Unit
The GPT unit represents a very flexible multifunctional timer/counter structure which
may be used for many different time related tasks such as event timing and counting,
pulse width and duty cycle measurements, pulse generation, or pulse multiplication.
The GPT unit incorporates five 16-bit timers which are organized in two separate
modules, GPT1 and GPT2. Each timer in each module may operate independently in a
number of different modes, or may be concatenated with another timer of the same
module.
Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for
one of four basic modes of operation, which are Timer, Gated Timer, Counter, and
Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from
the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer
to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the
operation of a timer is controlled by the ‘gate’ level on an external input pin. For these
purposes, each timer has one associated port pin (TxIN) which serves as gate or clock
input. The maximum resolution of the timers in module GPT1 is 16 TCL.
The count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal on a port pin (TxEUD) to
facilitate e.g. position tracking.
In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected
to the incremental position sensor signals A and B via their respective inputs TxIN and
TxEUD. Direction and count signals are internally derived from these two input signals,
so the contents of the respective timer Tx corresponds to the sensor position. The third
position sensor signal TOP0 can be connected to an interrupt input.
Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer overflow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out
monitoring of external hardware components, or may be used internally to clock timers
T2 and T4 for measuring long time periods with high resolution.
In addition to their basic operating modes, timers T2 and T4 may be configured as reload
or capture registers for timer T3. When used as capture or reload registers, timers T2
and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a
signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2
or T4 triggered either by an external signal or by a selectable state transition of its toggle
latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite
state transitions of T3OTL with the low and high times of a PWM signal, this signal can
be constantly generated without software intervention.
Data Sheet
20
V2.0, 2000-12
C165
U/D
T2EUD
fCPU
2n : 1
T2IN
Interrupt
Request
GPT1 Timer T2
T2
Mode
Control
Reload
Capture
fCPU
Interrupt
Request
n
2 :1
Toggle FF
T3
Mode
Control
T3IN
GPT1 Timer T3
T3OTL
T3OUT
U/D
T3EUD
Other
Timers
Capture
Reload
T4IN
fCPU
2n : 1
T4
Mode
Control
GPT1 Timer T4
Interrupt
Request
U/D
T4EUD
MCT02141
n = 3 … 10
Figure 6
Block Diagram of GPT1
With its maximum resolution of 8 TCL, the GPT2 module provides precise event control
and time measurement. It includes two timers (T5, T6) and a capture/reload register
(CAPREL). Both timers can be clocked with an input clock which is derived from the CPU
clock. The count direction (up/down) for each timer is programmable by software.
Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6,
which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer T5 and/or it may be output on pin
T6OUT. The overflows/underflows of timer T6 can cause a reload from the CAPREL
register. The CAPREL register may capture the contents of timer T5 based on an
external signal transition on the corresponding port pin (CAPIN), and timer T5 may
optionally be cleared after the capture procedure. This allows the C165 to measure
absolute time differences or to perform pulse multiplication without software overhead.
Data Sheet
21
V2.0, 2000-12
C165
The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of
GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3
operates in Incremental Interface Mode.
T5EUD
fCPU
2n : 1
T5IN
T5
Mode
Control
U/D
Interrupt
Request
GPT2 Timer T5
Clear
Capture
Interrupt
Request
T3
MUX
CAPIN
GPT2 CAPREL
Interrupt
Request
CT3
GPT2 Timer T6
T6IN
fCPU
2n :
1
T6OTL
T6OUT
U/D
T6
Mode
Control
Other
Timers
T6EUD
MCB03999
n=2…9
Figure 7
Data Sheet
Block Diagram of GPT2
22
V2.0, 2000-12
C165
Serial Channels
Serial communication with other microcontrollers, processors, terminals or external
peripheral components is provided by two serial interfaces with different functionality, an
Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous
Serial Channel (SSC).
The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller
families and supports full-duplex asynchronous communication at up to 781 KBaud and
half-duplex synchronous communication at up to 3.1 MBaud (@ 25 MHz CPU clock).
A dedicated baud rate generator allows to set up all standard baud rates without
oscillator tuning. For transmission, reception and error handling 4 separate interrupt
vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or
received, preceded by a start bit and terminated by one or two stop bits. For
multiprocessor communication, a mechanism to distinguish address from data bytes has
been included (8-bit data plus wake up bit mode).
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a
shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop
back option is available for testing purposes.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. A parity bit can automatically be generated on
transmission or be checked on reception. Framing error detection allows to recognize
data frames with missing stop bits. An overrun error will be generated, if the last
character received has not been read out of the receive buffer register at the time the
reception of a new character is complete.
The SSC supports full-duplex synchronous communication at up to 6.25 MBaud
(@ 25 MHz CPU clock). It may be configured so it interfaces with serially linked
peripheral components. A dedicated baud rate generator allows to set up all standard
baud rates without oscillator tuning. For transmission, reception, and error handling three
separate interrupt vectors are provided.
The SSC transmits or receives characters of 2 … 16 bits length synchronously to a shift
clock which can be generated by the SSC (master mode) or by an external master (slave
mode). The SSC can start shifting with the LSB or with the MSB and allows the selection
of shifting and latching clock edges as well as the clock polarity.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. Transmit and receive error supervise the correct handling
of the data buffer. Phase and baudrate error detect incorrect serial data.
Data Sheet
23
V2.0, 2000-12
C165
Watchdog Timer
The Watchdog Timer represents one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can only be
disabled in the time interval until the EINIT (end of initialization) instruction has been
executed. Thus, the chip’s start-up procedure is always monitored. The software has to
be designed to service the Watchdog Timer before it overflows. If, due to hardware or
software related failures, the software fails to do so, the Watchdog Timer overflows and
generates an internal hardware reset and pulls the RSTOUT pin low in order to allow
external hardware components to be reset.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by 2/128.
The high byte of the Watchdog Timer register can be set to a prespecified reload value
(stored in WDTREL) in order to allow further variation of the monitored time interval.
Each time it is serviced by the application software, the high byte of the Watchdog Timer
is reloaded. Thus, time intervals between 20 µs and 336 ms can be monitored
(@ 25 MHz).
The default Watchdog Timer interval after reset is 5.24 ms (@ 25 MHz).
Parallel Ports
The C165 provides up to 77 I/O lines which are organized into six input/output ports and
one input port. All port lines are bit-addressable, and all input/output lines are individually
(bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are
true bidirectional ports which are switched to high impedance state when configured as
inputs. The output drivers of three I/O ports can be configured (pin by pin) for push/pull
operation or open-drain operation via control registers. During the internal reset, all port
pins are configured as inputs.
All port lines have programmable alternate input or output functions associated with
them. All port lines that are not used for these alternate functions may be used as general
purpose IO lines.
PORT0 and PORT1 may be used as address and data lines when accessing external
memory, while Port 4 outputs the additional segment address bits A23/19/17 … A16 in
systems where segmentation is enabled to access more than 64 KBytes of memory.
Port 6 provides optional chip select signals.
Port 3 includes alternate functions of timers, serial interfaces, the optional bus control
signal BHE/WRH, and the system clock output CLKOUT.
Port 5 is used for timer control signals.
Data Sheet
24
V2.0, 2000-12
C165
Instruction Set Summary
Table 5 lists the instructions of the C165 in a condensed way.
The various addressing modes that can be used with a specific instruction, the operation
of the instructions, parameters for conditional execution of instructions, and the opcodes
for each instruction can be found in the “C166 Family Instruction Set Manual”.
This document also provides a detailed description of each instruction.
Table 5
Mnemonic
ADD(B)
ADDC(B)
SUB(B)
SUBC(B)
MUL(U)
DIV(U)
DIVL(U)
CPL(B)
NEG(B)
AND(B)
OR(B)
XOR(B)
BCLR
BSET
BMOV(N)
BAND, BOR,
BXOR
BCMP
BFLDH/L
CMP(B)
CMPD1/2
CMPI1/2
PRIOR
SHL / SHR
ROL / ROR
ASHR
Data Sheet
Instruction Set Summary
Description
Add word (byte) operands
Add word (byte) operands with Carry
Subtract word (byte) operands
Subtract word (byte) operands with Carry
(Un)Signed multiply direct GPR by direct GPR (16-16-bit)
(Un)Signed divide register MDL by direct GPR (16-/16-bit)
(Un)Signed long divide reg. MD by direct GPR (32-/16-bit)
Complement direct word (byte) GPR
Negate direct word (byte) GPR
Bitwise AND, (word/byte operands)
Bitwise OR, (word/byte operands)
Bitwise XOR, (word/byte operands)
Clear direct bit
Set direct bit
Move (negated) direct bit to direct bit
AND/OR/XOR direct bit with direct bit
Bytes
2/4
2/4
2/4
2/4
2
2
2
2
2
2/4
2/4
2/4
2
2
4
4
Compare direct bit to direct bit
Bitwise modify masked high/low byte of bit-addressable
direct word memory with immediate data
Compare word (byte) operands
Compare word data to GPR and decrement GPR by 1/2
Compare word data to GPR and increment GPR by 1/2
Determine number of shift cycles to normalize direct
word GPR and store result in direct word GPR
Shift left/right direct word GPR
Rotate left/right direct word GPR
Arithmetic (sign bit) shift right direct word GPR
4
4
25
2/4
2/4
2/4
2
2
2
2
V2.0, 2000-12
C165
Table 5
Instruction Set Summary (cont’d)
Mnemonic
MOV(B)
MOVBS
MOVBZ
JMPA, JMPI,
JMPR
JMPS
J(N)B
JBC
JNBS
CALLA, CALLI,
CALLR
CALLS
PCALL
TRAP
PUSH, POP
SCXT
RET
RETS
RETP
RETI
SRST
IDLE
PWRDN
SRVWDT
DISWDT
EINIT
ATOMIC
EXTR
EXTP(R)
EXTS(R)
NOP
Data Sheet
Description
Move word (byte) data
Move byte operand to word operand with sign extension
Move byte operand to word operand. with zero extension
Jump absolute/indirect/relative if condition is met
Bytes
2/4
2/4
2/4
4
Jump absolute to a code segment
Jump relative if direct bit is (not) set
Jump relative and clear bit if direct bit is set
Jump relative and set bit if direct bit is not set
Call absolute/indirect/relative subroutine if condition is met
4
4
4
4
4
Call absolute subroutine in any code segment
Push direct word register onto system stack and call
absolute subroutine
Call interrupt service routine via immediate trap number
Push/pop direct word register onto/from system stack
Push direct word register onto system stack und update
register with word operand
Return from intra-segment subroutine
Return from inter-segment subroutine
Return from intra-segment subroutine and pop direct
word register from system stack
Return from interrupt service subroutine
Software Reset
Enter Idle Mode
Enter Power Down Mode (supposes NMI-pin being low)
Service Watchdog Timer
Disable Watchdog Timer
Signify End-of-Initialization on RSTOUT-pin
Begin ATOMIC sequence
Begin EXTended Register sequence
Begin EXTended Page (and Register) sequence
Begin EXTended Segment (and Register) sequence
Null operation
4
4
26
2
2
4
2
2
2
2
4
4
4
4
4
4
2
2
2/4
2/4
2
V2.0, 2000-12
C165
Special Function Registers Overview
The following table lists all SFRs which are implemented in the C165 in alphabetical
order.
Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the
Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical
Address”. Registers within on-chip X-peripherals are marked with the letter “X” in column
“Physical Address”.
An SFR can be specified via its individual mnemonic name. Depending on the selected
addressing mode, an SFR can be accessed via its physical address (using the Data
Page Pointers), or via its short 8-bit address (without using the Data Page Pointers).
Table 6
C165 Registers, Ordered by Name
Name
Physical
Address
8-Bit Description
Addr.
Reset
Value
ADDRSEL1
FE18H
0CH
Address Select Register 1
0000H
ADDRSEL2
FE1AH
0DH
Address Select Register 2
0000H
ADDRSEL3
FE1CH
0EH
Address Select Register 3
0000H
ADDRSEL4
FE1EH
0FH
Address Select Register 4
0000H
BUSCON0 b FF0CH
86H
Bus Configuration Register 0
0XX0H
BUSCON1 b FF14H
8AH
Bus Configuration Register 1
0000H
BUSCON2 b FF16H
8BH
Bus Configuration Register 2
0000H
BUSCON3 b FF18H
8CH
Bus Configuration Register 3
0000H
BUSCON4 b FF1AH
8DH
Bus Configuration Register 4
0000H
CAPREL
FE4AH
25H
GPT2 Capture/Reload Register
0000H
CC10IC
b FF8CH
C6H
EX2IN Interrupt Control Register
0000H
CC11IC
b FF8EH
C7H
EX3IN Interrupt Control Register
0000H
CC12IC
b FF90H
C8H
EX4IN Interrupt Control Register
0000H
CC13IC
b FF92H
C9H
EX5IN Interrupt Control Register
0000H
CC14IC
b FF94H
CAH
EX6IN Interrupt Control Register
0000H
CC15IC
b FF96H
CBH
EX7IN Interrupt Control Register
0000H
CC29IC
b F184H
E C2H
Software Interrupt Control Register
0000H
CC30IC
E C6H
Software Interrupt Control Register
0000H
CC31IC
b F18CH
b F194H
E CAH
Software Interrupt Control Register
0000H
CC8IC
b FF88H
C4H
EX0IN Interrupt Control Register
0000H
CC9IC
b FF8AH
C5H
EX1IN Interrupt Control Register
0000H
Data Sheet
27
V2.0, 2000-12
C165
Table 6
C165 Registers, Ordered by Name (cont’d)
Name
Physical
Address
8-Bit Description
Addr.
CP
FE10H
08H
CPU Context Pointer Register
FC00H
b FF6AH
B5H
GPT2 CAPREL Interrupt Ctrl. Reg.
0000H
FE08H
04H
CPU Code Seg. Pointer Reg. (read only)
0000H
DP0H
b F102H
E 81H
P0H Direction Control Register
00H
DP0L
b F100H
E 80H
P0L Direction Control Register
00H
DP1H
b F106H
E 83H
P1H Direction Control Register
00H
DP1L
b F104H
E 82H
P1L Direction Control Register
00H
DP2
b FFC2H
E1H
Port 2 Direction Control Register
0000H
DP3
b FFC6H
E3H
Port 3 Direction Control Register
0000H
DP4
b FFCAH
E5H
Port 4 Direction Control Register
00H
DP6
b FFCEH
E7H
Port 6 Direction Control Register
00H
DPP0
FE00H
00H
CPU Data Page Pointer 0 Reg. (10 bits)
0000H
DPP1
FE02H
01H
CPU Data Page Pointer 1 Reg. (10 bits)
0001H
DPP2
FE04H
02H
CPU Data Page Pointer 2 Reg. (10 bits)
0002H
DPP3
FE06H
03H
CPU Data Page Pointer 3 Reg. (10 bits)
0003H
b F1C0H
F07CH
E E0H
External Interrupt Control Register
0000H
E 3EH
Identifier
05XXH
IDMANUF
F07EH
E 3FH
Identifier
1820H
IDMEM
F07AH
Identifier
0000H
IDMEM2
F076H
E 3DH
E 3BH
Identifier
0000H
IDPROG
F078H
Identifier
0000H
CPU Multiply Divide Control Register
0000H
CRIC
CSP
EXICON
IDCHIP
Reset
Value
MDC
b FF0EH
E 3CH
87H
MDH
FE0CH
06H
CPU Multiply Divide Reg. – High Word
0000H
MDL
FE0EH
07H
CPU Multiply Divide Reg. – Low Word
0000H
E E1H
Port 2 Open Drain Control Register
0000H
ODP3
b F1C2H
b F1C6H
E E3H
Port 3 Open Drain Control Register
0000H
ODP6
b F1CEH E E7H
Port 6 Open Drain Control Register
00H
ONES
b FF1EH
8FH
Constant Value 1’s Register (read only)
FFFFH
P0H
b FF02H
81H
Port 0 High Reg. (Upper half of PORT0)
00H
P0L
b FF00H
80H
Port 0 Low Reg. (Lower half of PORT0)
00H
ODP2
Data Sheet
28
V2.0, 2000-12
C165
Table 6
Name
C165 Registers, Ordered by Name (cont’d)
Physical
Address
8-Bit Description
Addr.
Reset
Value
P1H
b FF06H
83H
Port 1 High Reg. (Upper half of PORT1)
00H
P1L
b FF04H
82H
Port 1 Low Reg.(Lower half of PORT1)
00H
P2
b FFC0H
E0H
Port 2 Register
0000H
P3
b FFC4H
E2H
Port 3 Register
0000H
P4
b FFC8H
E4H
Port 4 Register (8 bits)
P5
b FFA2H
b FFCCH
D1H
Port 5 Register (read only)
E6H
Port 6 Register (8 bits)
PECC0
FEC0H
60H
PEC Channel 0 Control Register
0000H
PECC1
FEC2H
61H
PEC Channel 1 Control Register
0000H
PECC2
FEC4H
62H
PEC Channel 2 Control Register
0000H
PECC3
FEC6H
63H
PEC Channel 3 Control Register
0000H
PECC4
FEC8H
64H
PEC Channel 4 Control Register
0000H
PECC5
FECAH
65H
PEC Channel 5 Control Register
0000H
PECC6
FECCH
66H
PEC Channel 6 Control Register
0000H
PECC7
FECEH
67H
PEC Channel 7 Control Register
0000H
CPU Program Status Word
0000H
P6
00H
XXXXH
00H
PSW
b FF10H
88H
RP0H
b F108H
E 84H
System Startup Config. Reg. (Rd. only)
XXH
S0BG
FEB4H
5AH
Serial Channel 0 Baud Rate Generator
Reload Register
0000H
b FFB0H
b FF70H
D8H
Serial Channel 0 Control Register
0000H
B8H
Serial Channel 0 Error Interrupt Ctrl. Reg
0000H
FEB2H
59H
Serial Channel 0 Receive Buffer Reg.
(read only)
S0RIC
b FF6EH
B7H
Serial Channel 0 Receive Interrupt
Control Register
0000H
S0TBIC
b F19CH
E CEH
Serial Channel 0 Transmit Buffer
Interrupt Control Register
0000H
FEB0H
58H
Serial Channel 0 Transmit Buffer
Register (write only)
00H
b FF6CH
B6H
Serial Channel 0 Transmit Interrupt
Control Register
S0CON
S0EIC
S0RBUF
S0TBUF
S0TIC
Data Sheet
29
XXH
0000H
V2.0, 2000-12
C165
Table 6
C165 Registers, Ordered by Name (cont’d)
Name
Physical
Address
8-Bit Description
Addr.
SP
FE12H
09H
SSCBR
F0B4H
E 5AH
SSCEIC
b FFB2H
b FF76H
SSCRB
F0B2H
E 59H
SSCRIC
b FF74H
BAH
SSCTB
F0B0H
E 58H
SSCTIC
b FF72H
STKOV
STKUN
SSCCON
Reset
Value
CPU System Stack Pointer Register
FC00H
SSC Baudrate Register
0000H
D9H
SSC Control Register
0000H
BBH
SSC Error Interrupt Control Register
0000H
SSC Receive Buffer
XXXXH
SSC Receive Interrupt Control Register
0000H
SSC Transmit Buffer
0000H
B9H
SSC Transmit Interrupt Control Register
0000H
FE14H
0AH
CPU Stack Overflow Pointer Register
FA00H
FE16H
0BH
CPU Stack Underflow Pointer Register
FC00H
b FF12H
89H
CPU System Configuration Register
FE40H
20H
GPT1 Timer 2 Register
0000H
T2CON
b FF40H
A0H
GPT1 Timer 2 Control Register
0000H
T2IC
b FF60H
B0H
GPT1 Timer 2 Interrupt Control Register
0000H
FE42H
21H
GPT1 Timer 3 Register
0000H
T3CON
b FF42H
A1H
GPT1 Timer 3 Control Register
0000H
T3IC
b FF62H
B1H
GPT1 Timer 3 Interrupt Control Register
0000H
FE44H
22H
GPT1 Timer 4 Register
0000H
T4CON
b FF44H
A2H
GPT1 Timer 4 Control Register
0000H
T4IC
b FF64H
B2H
GPT1 Timer 4 Interrupt Control Register
0000H
FE46H
23H
GPT2 Timer 5 Register
0000H
T5CON
b FF46H
A3H
GPT2 Timer 5 Control Register
0000H
T5IC
b FF66H
B3H
GPT2 Timer 5 Interrupt Control Register
0000H
FE48H
24H
GPT2 Timer 6 Register
0000H
T6CON
b FF48H
A4H
GPT2 Timer 6 Control Register
0000H
T6IC
b FF68H
B4H
GPT2 Timer 6 Interrupt Control Register
0000H
TFR
b FFACH
D6H
Trap Flag Register
0000H
FEAEH
57H
Watchdog Timer Register (read only)
WDTCON
b FFAEH
D7H
Watchdog Timer Control Register
XP0IC
b F186H
E C3H
SYSCON
T2
T3
T4
T5
T6
WDT
Data Sheet
Software Interrupt Control Register
30
1)0XX0
H
0000H
2)00XX
H
0000H
V2.0, 2000-12
C165
Table 6
Name
C165 Registers, Ordered by Name (cont’d)
Physical
Address
8-Bit Description
Addr.
Reset
Value
XP1IC
b F18EH
E C7H
Software Interrupt Control Register
0000H
XP2IC
b F196H
E CBH
Software Interrupt Control Register
0000H
XP3IC
b F19EH
E CFH
Software Interrupt Control Register
0000H
ZEROS
b FF1CH
8EH
Constant Value 0’s Register (read only)
0000H
1)
The system configuration is selected during reset.
2)
The reset value depends on the indicated reset source.
Data Sheet
31
V2.0, 2000-12
C165
Absolute Maximum Ratings
Table 7
Absolute Maximum Rating Parameters
Parameter
Symbol
Limit Values
Unit Notes
min.
max.
TST
TJ
VDD
- 65
150
°C
–
- 40
150
°C
under bias
- 0.5
6.5
V
–
Voltage on any pin with
respect to ground (VSS)
VIN
- 0.5
VDD + 0.5 V
–
Input current on any pin
during overload condition
–
- 10
10
mA
–
Absolute sum of all input
currents during overload
condition
–
–
|100|
mA
–
Power dissipation
PDISS
–
1.5
W
–
Storage temperature
Junction temperature
Voltage on VDD pins with
respect to ground (VSS)
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS) the
voltage on VDD pins with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
Data Sheet
32
V2.0, 2000-12
C165
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation of the C165. All parameters specified in the following sections refer to these
operating conditions, unless otherwise noticed.
Table 8
Operating Condition Parameters
Parameter
Symbol
Standard
digital supply voltage
(5 V versions)
VDD
Reduced
digital supply voltage
(3 V versions)
VDD
VSS
IOV
Overload current
Absolute sum of overload Σ|IOV|
Limit Values
Unit Notes
min.
max.
4.5
5.5
V
Active mode,
fCPUmax = 25 MHz
2.51)
5.5
V
PowerDown mode
3.0
3.6
V
Active mode,
fCPUmax = 20 MHz
2.51)
3.6
V
PowerDown mode
V
Reference voltage
0
Digital ground voltage
–
±5
mA
Per pin2)3)
–
50
mA
3)
currents
External Load
Capacitance
CL
–
100
pF
–
Ambient temperature
TA
0
70
°C
SAB-C165 …
- 40
85
°C
SAF-C165 …
- 40
125
°C
SAK-C165 …
1)
Output voltages and output currents will be reduced when VDD leaves the range defined for active mode.
2)
Overload conditions occur if the standard operatings conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range (i.e. VOV > VDD + 0.5 V or VOV < VSS – 0.5 V). The absolute sum of input overload
currents on all pins may not exceed 50 mA. The supply voltage must remain within the specified limits.
Proper operation is not guaranteed if overload conditions occur on functional pins such as XTAL1, RD, WR,
etc.
3)
Not 100% tested, guaranteed by design and characterization.
Data Sheet
33
V2.0, 2000-12
C165
Parameter Interpretation
The parameters listed in the following partly represent the characteristics of the C165
and partly its demands on the system. To aid in interpreting the parameters right, when
evaluating them for a design, they are marked in column “Symbol”:
CC (Controller Characteristics):
The logic of the C165 will provide signals with the respective timing characteristics.
SR (System Requirement):
The external system must provide signals with the respective timing characteristics to
the C165.
DC Characteristics (Standard Supply Voltage Range)
(Operating Conditions apply)1)
Parameter
Symbol
Limit Values
min.
Unit Test Condition
max.
Input low voltage (TTL,
all except XTAL1)
VIL
0.2 VDD V
– 0.1
–
Input low voltage XTAL1
VIL2 SR – 0.5
0.3 VDD V
VIH SR 0.2 VDD VDD + V
–
Input high voltage (TTL,
all except RSTIN and XTAL1)
SR – 0.5
+ 0.9
–
0.5
Input high voltage RSTIN
(when operated as input)
VIH1 SR 0.6 VDD VDD +
Input high voltage XTAL1
VIH2 SR 0.7 VDD VDD +
V
–
V
–
0.5
0.5
Output low voltage
(PORT0, PORT1, Port 4, ALE,
RD, WR, BHE, RSTOUT,
RSTIN2))
VOL CC –
0.45
V
IOL = 2.4 mA
Output low voltage
(all other outputs)
VOL1 CC –
0.45
V
IOL = 1.6 mA
Output high voltage3)
(PORT0, PORT1, Port 4, ALE,
RD, WR, BHE, RSTOUT)
VOH CC 2.4
–
V
0.9 VDD –
V
IOH = - 2.4 mA
IOH = - 0.5 mA
Output high voltage3)
(all other outputs)
VOH1 CC 2.4
–
V
0.9 VDD –
V
IOZ1 CC –
Input leakage current (all other) IOZ2 CC –
RSTIN inactive current4)
IRSTH5) –
Input leakage current (Port 5)
Data Sheet
34
± 200
nA
± 500
nA
- 10
µA
IOH = - 1.6 mA
IOH = - 0.5 mA
0 V < VIN < VDD
0.45 V < VIN < VDD
VIN = VIH1
V2.0, 2000-12
C165
DC Characteristics (Standard Supply Voltage Range) (cont’d)
(Operating Conditions apply)1)
Parameter
RSTIN active
Symbol
current4)
READY/RD/WR inact. current7)
READY/RD/WR active current7)
ALE inactive current7)
ALE active current7)
Port 6 inactive current 7)
Port 6 active current7)
PORT0 configuration current8)
XTAL1 input current
Pin capacitance9)
(digital inputs/outputs)
6)
IRSTL
IRWH5)
IRWL6)
IALEL5)
IALEH6)
IP6H5)
IP6L6)
IP0H5)
IP0L6)
IIL CC
CIO CC
Limit Values
Unit Test Condition
min.
max.
- 100
–
µA
–
- 40
µA
- 500
–
µA
–
40
µA
500
–
µA
–
- 40
µA
- 500
–
µA
–
- 10
µA
- 100
–
µA
–
± 20
µA
–
10
pF
VIN = VIL
VOUT = 2.4 V
VOUT = VOLmax
VOUT = VOLmax
VOUT = 2.4 V
VOUT = 2.4 V
VOUT = VOL1max
VIN = VIHmin
VIN = VILmax
0 V < VIN < VDD
f = 1 MHz
TA = 25 °C
1)
Keeping signal levels within the levels specified in this table, ensures operation without overload conditions.
For signal levels outside these specifications also refer to the specification of the overload current IOV.
2)
Valid in bidirectional reset mode only.
3)
This specification is not valid for outputs which are switched to open drain mode. In this case the respective
output will float and the voltage results from the external circuitry.
4)
These parameters describe the RSTIN pullup, which equals a resistance of ca. 50 to 250 kΩ.
5)
The maximum current may be drawn while the respective signal line remains inactive.
6)
The minimum current must be drawn in order to drive the respective signal line active.
7)
This specification is valid during Reset and during Hold-mode or Adapt-mode. During Hold-mode Port 6 pins
are only affected, if they are used (configured) for CS output and the open drain function is not enabled. The
READY-pullup is always active, except for Powerdown mode.
8)
This specification is valid during Reset and during Adapt-mode.
9)
Not 100% tested, guaranteed by design and characterization.
Data Sheet
35
V2.0, 2000-12
C165
DC Characteristics (Reduced Supply Voltage Range)
(Operating Conditions apply)1)
Parameter
Symbol
Limit Values
min.
Input low voltage (TTL,
all except XTAL1)
VIL
Input low voltage XTAL1
VIL2 SR - 0.5
VIH SR 1.8
Input high voltage (TTL,
all except RSTIN and XTAL1)
SR - 0.5
Unit Test Condition
max.
0.8
V
–
0.3 VDD V
–
VDD +
V
–
V
–
V
–
0.5
Input high voltage RSTIN
(when operated as input)
VIH1 SR 0.6 VDD VDD +
Input high voltage XTAL1
VIH2 SR 0.7 VDD VDD +
0.5
0.5
Output low voltage
(PORT0, PORT1, Port 4, ALE,
RD, WR, BHE, RSTOUT,
RSTIN2))
VOL CC –
0.45
V
IOL = 1.6 mA
Output low voltage
(all other outputs)
VOL1 CC –
0.45
V
IOL = 1.0 mA
Output high voltage3)
(PORT0, PORT1, Port 4, ALE,
RD, WR, BHE, RSTOUT)
VOH CC 0.9 VDD –
V
IOH = - 0.5 mA
Output high voltage3)
(all other outputs)
VOH1 CC 0.9 VDD –
V
IOH = - 0.25 mA
IOZ1 CC
Input leakage current (all other) IOZ2 CC
RSTIN inactive current4)
IRSTH5)
RSTIN active current4)
IRSTL6)
READY/RD/WR inact. current7) IRWH5)
READY/RD/WR active current7) IRWL6)
ALE inactive current7)
IALEL5)
ALE active current7)
IALEH6)
IP6H5)
Port 6 inactive current 7)
IP6L6)
Port 6 active current7)
Input leakage current (Port 5)
Data Sheet
–
± 200
nA
0 V < VIN < VDD
–
± 500
nA
0.45 V < VIN < VDD
–
- 10
µA
- 100
–
µA
–
- 10
µA
- 500
–
µA
–
20
µA
500
–
µA
–
- 10
µA
- 500
–
µA
VIN = VIH1
VIN = VIL
VOUT = 2.4 V
VOUT = VOLmax
VOUT = VOLmax
VOUT = 2.4 V
VOUT = 2.4 V
VOUT = VOL1max
36
V2.0, 2000-12
C165
DC Characteristics (Reduced Supply Voltage Range) (cont’d)
(Operating Conditions apply)1)
Parameter
PORT0 configuration
Symbol
current8)
XTAL1 input current
Pin capacitance9)
(digital inputs/outputs)
5)
IP0H
IP0L6)
IIL CC
CIO CC
Limit Values
Unit Test Condition
min.
max.
–
-5
µA
- 100
–
µA
–
± 20
µA
–
10
pF
VIN = VIHmin
VIN = VILmax
0 V < VIN < VDD
f = 1 MHz
TA = 25 °C
1)
Keeping signal levels within the levels specified in this table, ensures operation without overload conditions.
For signal levels outside these specifications also refer to the specification of the overload current IOV.
2)
Valid in bidirectional reset mode only.
3)
This specification is not valid for outputs which are switched to open drain mode. In this case the respective
output will float and the voltage results from the external circuitry.
4)
These parameters describe the RSTIN pullup, which equals a resistance of ca. 50 to 250 kΩ.
5)
The maximum current may be drawn while the respective signal line remains inactive.
6)
The minimum current must be drawn in order to drive the respective signal line active.
7)
This specification is valid during Reset and during Hold-mode or Adapt-mode. During Hold-mode Port 6 pins
are only affected, if they are used (configured) for CS output and the open drain function is not enabled. The
READY-pullup is always active, except for Powerdown mode.
8)
This specification is valid during Reset and during Adapt-mode.
9)
Not 100% tested, guaranteed by design and characterization.
Data Sheet
37
V2.0, 2000-12
C165
Power Consumption C165 (Standard Supply Voltage Range)
(Operating Conditions apply)
Parameter
Symbol
Limit Values
min.
max.
Unit Test Condition
Power supply current (active)
with all peripherals active
IDD5
–
15 +
mA
1.8 × fCPU
RSTIN = VIL
fCPU in [MHz]1)
Idle mode supply current
with all peripherals active
IIDX5
–
2+
mA
0.4 × fCPU
RSTIN = VIH1
fCPU in [MHz]1)
Power-down mode supply
current
IPDO5
–
50
µA
VDD = VDDmax2)
1)
The supply current is a function of the operating frequency. This dependency is illustrated in Figure 8.
These parameters are tested at VDDmax and maximum CPU clock with all outputs disconnected and all inputs
at VIL or VIH.
2)
This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to
0.1 V or at VDD – 0.1 V to VDD, all outputs (including pins configured as outputs) disconnected.
Power Consumption C165 (Reduced Supply Voltage Range)
(Operating Conditions apply)
Parameter
Symbol
Limit Values
min.
max.
Unit Test Condition
Power supply current (active)
with all peripherals active
IDD3
–
3+
mA
1.3 × fCPU
Idle mode supply current
with all peripherals active
IIDX3
–
1+
mA
0.4 × fCPU
Power-down mode supply
current
IPDO3
–
30
µA
RSTIN = VIL
fCPU in [MHz]1)
RSTIN = VIH1
fCPU in [MHz]1)
VDD = VDDmax2)
1)
The supply current is a function of the operating frequency. This dependency is illustrated in Figure 8.
These parameters are tested at VDDmax and maximum CPU clock with all outputs disconnected and all inputs
at VIL or VIH.
2)
This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to
0.1 V or at VDD – 0.1 V to VDD, all outputs (including pins configured as outputs) disconnected.
Data Sheet
38
V2.0, 2000-12
C165
I [mA]
100
IDD5max
80
IDD5typ
IDD3max
60
IDD3typ
40
IIDX5max
IIDX3max
IIDX5typ
IIDX3typ
20
10
Figure 8
Data Sheet
20
30
40
fCPU [MHz]
Supply/Idle Current as a Function of Operating Frequency
39
V2.0, 2000-12
C165
AC Characteristics
Definition of Internal Timing
The internal operation of the C165 is controlled by the internal CPU clock fCPU. Both
edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)
operations.
The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called “TCL” (see Figure 9).
Direct Clock Drive
fOSC
TCL
fCPU
TCL
Prescaler Operation
fOSC
TCL
fCPU
TCL
Figure 9
MCT04826
Generation Mechanisms for the CPU Clock
The CPU clock signal fCPU can be generated from the oscillator clock signal fOSC via
different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate fCPU. This influence must
be regarded when calculating the timings for the C165.
The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG
in register RP0H.7-5. Upon a long hardware reset register RP0H is loaded with the logic
levels present on the upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the
logic levels on pins P0.15-13 (P0H.7-5).
Table 9 associates the combinations of these three bits with the respective clock
generation mode.
Data Sheet
40
V2.0, 2000-12
C165
Table 9
CLKCFG
(P0H.7-5)
0 X X
1 X X
C165 Clock Generation Modes
CPU Frequency External Clock
fCPU = fOSC × F Input Range1)
Notes
fOSC × 1
fOSC / 2
1 to 25 MHz
Direct drive2)
2 to 50 MHz
CPU clock via prescaler
1)
The external clock input range refers to a CPU clock range of 10 … 25 MHz (PLL operation).
2)
The maximum frequency depends on the duty cycle of the external clock signal.
Prescaler Operation
When prescaler operation is configured (CLKCFG = 1XXB) the CPU clock is derived
from the internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of fCPU is half the frequency of fOSC and the high and low time of fCPU (i.e.
the duration of an individual TCL) is defined by the period of the input clock fOSC.
The timings listed in the AC Characteristics that refer to TCLs therefore can be
calculated using the period of fOSC for any TCL.
Direct Drive
When direct drive is configured (CLKCFG = 0XXB) the on-chip phase locked loop is
disabled and the CPU clock is directly driven from the internal oscillator with the input
clock signal.
The frequency of fCPU directly follows the frequency of fOSC so the high and low time of
fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock
fOSC.
The timings listed below that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective circumstances. This minimum value
can be calculated via the following formula:
TCLmin = 1/fOSC × DCmin
(DC = duty cycle)
For two consecutive TCLs the deviation caused by the duty cycle of fOSC is compensated
so the duration of 2TCL is always 1/fOSC. The minimum value TCLmin therefore has to
be used only once for timings that require an odd number of TCLs (1, 3, …). Timings that
require an even number of TCLs (2, 4, …) may use the formula 2TCL = 1/fOSC.
Data Sheet
41
V2.0, 2000-12
C165
AC Characteristics
Table 10
External Clock Drive XTAL1 (Standard Supply Voltage Range)
(Operating Conditions apply)
Parameter
Symbol
Direct Drive
1:1
min.
Oscillator period tOSC SR 40
1)
High time
Low time1)
Rise time1)
Fall time1)
t1
t2
t3
t4
Prescaler
2:1
max.
min.
max.
Unit
–
20
–
ns
202)
–
6
–
ns
SR 202)
–
6
–
ns
SR –
10
–
6
ns
SR –
10
–
6
ns
SR
1)
The clock input signal must reach the defined levels VIL2 and VIH2.
2)
The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (fCPU) in
direct drive mode depends on the duty cycle of the clock input signal.
Table 11
Parameter
External Clock Drive XTAL1 (Reduced Supply Voltage Range)
(Operating Conditions apply)
Symbol
Direct Drive
1:1
min.
Prescaler
2:1
max.
min.
max.
Unit
Oscillator period tOSC SR 50
t1
SR 252)
High time1)
–
25
–
ns
–
8
–
ns
Low time1)
SR 252)
–
8
–
ns
SR –
10
–
6
ns
SR –
10
–
6
ns
Rise time1)
Fall time1)
t2
t3
t4
1)
The clock input signal must reach the defined levels VIL2 and VIH2.
2)
The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (fCPU) in
direct drive mode depends on the duty cycle of the clock input signal.
Data Sheet
42
V2.0, 2000-12
C165
t1
t3
t4
VIH2
0.5 VDD
VIL
t2
t OSC
MCT02534
Figure 10
External Clock Drive XTAL1
Note: If the on-chip oscillator is used together with a crystal, the oscillator frequency is
limited to a range of 4 MHz to 40 MHz.
It is strongly recommended to measure the oscillation allowance (or margin) in the
final target system (layout) to determine the optimum parameters for the oscillator
operation. Please refer to the limits specified by the crystal supplier.
When driven by an external clock signal it will accept the specified frequency
range. Operation at lower input frequencies is possible but is guaranteed by
design only (not 100% tested).
Data Sheet
43
V2.0, 2000-12
C165
Testing Waveforms
2.4 V
1.8 V
1.8 V
Test Points
0.8 V
0.8 V
’
0.45 V
’
’
AC inputs during testing are driven at 2.4 V for a logic 1’ and 0.45 V for a logic 0’.
Timing measurements are made at VIH min for a logic 1’ and VIL max for a logic 0’.
’
MCA04414
Figure 11
Input Output Waveforms
VLoad + 0.1 V
VOH - 0.1 V
Timing
Reference
Points
VLoad - 0.1 V
VOL + 0.1 V
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs,
but begins to float when a 100 mV change from the loaded VOH / VOL level occurs (I OH / I OL = 20 mA).
MCA00763
Figure 12
Data Sheet
Float Waveforms
44
V2.0, 2000-12
C165
Memory Cycle Variables
The timing tables below use three variables which are derived from the BUSCONx
registers and represent the special characteristics of the programmed memory cycle.
The following table describes, how these variables are to be computed.
Table 12
Memory Cycle Variables
Description
Symbol
Values
ALE Extension
tA
tC
tF
TCL × <ALECTL>
Memory Cycle Time Waitstates
Memory Tristate Time
2TCL × (15 - <MCTC>)
2TCL × (1 - <MTTC>)
Note: Please respect the maximum operating frequency of the respective derivative.
AC Characteristics
Multiplexed Bus (Standard Supply Voltage Range)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 25 MHz
1 / 2TCL = 1 to 25 MHz
min.
max.
min.
max.
ALE high time
t5
CC 10 + tA
–
TCL - 10
+ tA
–
ns
Address setup to ALE
t6
CC 4 + tA
–
TCL - 16
+ tA
–
ns
Address hold after ALE
t7
CC 10 + tA
–
TCL - 10
+ tA
–
ns
ALE falling edge to RD,
WR (with RW-delay)
t8
CC 10 + tA
–
TCL - 10
+ tA
–
ns
ALE falling edge to RD,
WR (no RW-delay)
t9
CC - 10 + tA –
- 10 + tA
–
ns
Address float after RD,
WR (with RW-delay)
t10 CC –
6
–
6
ns
Address float after RD,
WR (no RW-delay)
t11 CC –
26
–
TCL + 6
ns
RD, WR low time
(with RW-delay)
t12 CC 30 + tC
–
2TCL - 10
+ tC
–
ns
Data Sheet
45
V2.0, 2000-12
C165
Multiplexed Bus (Standard Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 25 MHz
1 / 2TCL = 1 to 25 MHz
min.
max.
min.
max.
RD, WR low time
(no RW-delay)
t13 CC 50 + tC
–
3TCL - 10
+ tC
–
ns
RD to valid data in
(with RW-delay)
t14 SR –
20 + tC
–
2TCL - 20
+ tC
ns
RD to valid data in
(no RW-delay)
t15 SR –
40 + tC
–
3TCL - 20
+ tC
ns
ALE low to valid data in
t16 SR –
40 + tA
+ tC
–
3TCL - 20
+ tA + tC
ns
Address to valid data in
t17 SR –
50 + 2tA –
+ tC
4TCL - 30
+ 2tA + tC
ns
Data hold after RD
rising edge
t18 SR 0
–
0
–
ns
Data float after RD
t19 SR –
26 + tF
–
2TCL - 14
+ tF
ns
Data valid to WR
t22 CC 20 + tC
–
2TCL - 20
+ tC
–
ns
Data hold after WR
t23 CC 26 + tF
–
2TCL - 14
+ tF
–
ns
ALE rising edge after RD, t25 CC 26 + tF
WR
–
2TCL - 14
+ tF
–
ns
t27 CC 26 + tF
–
2TCL - 14
+ tF
–
ns
10 - tA
- 4 - tA
10 - tA
ns
CS low to Valid Data In
t38 CC - 4 - tA
t39 SR –
40
–
+ tC+2tA
3TCL - 20
+ t C + 2 tA
ns
CS hold after RD, WR1)
t40 CC 46 + tF
–
3TCL - 14
+ tF
–
ns
ALE fall. edge to RdCS,
WrCS (with RW delay)
t42 CC 16 + tA
–
TCL - 4
+ tA
–
ns
ALE fall. edge to RdCS,
WrCS (no RW delay)
t43 CC - 4 + tA
–
-4
+ tA
–
ns
Address hold after RD,
WR
ALE falling edge to CS1)
1)
Data Sheet
46
V2.0, 2000-12
C165
Multiplexed Bus (Standard Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 25 MHz
1 / 2TCL = 1 to 25 MHz
min.
max.
min.
max.
Address float after RdCS, t44 CC –
WrCS (with RW delay)
0
–
0
ns
Address float after RdCS, t45 CC –
WrCS (no RW delay)
20
–
TCL
ns
RdCS to Valid Data In
(with RW delay)
t46 SR –
16 + tC
–
2TCL - 24
+ tC
ns
RdCS to Valid Data In
(no RW delay)
t47 SR –
36 + tC
–
3TCL - 24
+ tC
ns
RdCS, WrCS Low Time
(with RW delay)
t48 CC 30 + tC
–
2TCL - 10
+ tC
–
ns
RdCS, WrCS Low Time
(no RW delay)
t49 CC 50 + tC
–
3TCL - 10
+ tC
–
ns
Data valid to WrCS
t50 CC 26 + tC
–
2TCL - 14
+ tC
–
ns
Data hold after RdCS
t51 SR 0
t52 SR –
–
0
–
ns
20 + tF
–
2TCL - 20
+ tF
ns
Address hold after
RdCS, WrCS
t54 CC 20 + tF
–
2TCL - 20
+ tF
–
ns
Data hold after WrCS
t56 CC 20 + tF
–
2TCL - 20
+ tF
–
ns
Data float after RdCS
1)
These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
Data Sheet
47
V2.0, 2000-12
C165
AC Characteristics
Multiplexed Bus (Reduced Supply Voltage Range)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 20 MHz
1 / 2TCL = 1 to 20 MHz
min.
max.
min.
max.
ALE high time
t5
CC 11 + tA
–
TCL - 14
+ tA
–
ns
Address setup to ALE
t6
CC 5 + tA
–
TCL - 20
+ tA
–
ns
Address hold after ALE
t7
CC 15 + tA
–
TCL - 10
+ tA
–
ns
ALE falling edge to RD,
WR (with RW-delay)
t8
CC 15 + tA
–
TCL - 10
+ tA
–
ns
ALE falling edge to RD,
WR (no RW-delay)
t9
CC - 10 + tA –
-10 + tA
–
ns
Address float after RD,
WR (with RW-delay)
t10 CC –
6
–
6
ns
Address float after RD,
WR (no RW-delay)
t11 CC –
31
–
TCL + 6
ns
RD, WR low time
(with RW-delay)
t12 CC 34 + tC
–
2TCL - 16
+ tC
–
ns
RD, WR low time
(no RW-delay)
t13 CC 59 + tC
–
3TCL - 16
+ tC
–
ns
RD to valid data in
(with RW-delay)
t14 SR –
22 + tC
–
2TCL - 28
+ tC
ns
RD to valid data in
(no RW-delay)
t15 SR –
47 + tC
–
3TCL - 28
+ tC
ns
ALE low to valid data in
t16 SR –
45 + tA
+ tC
–
3TCL - 30
+ tA + tC
ns
Address to valid data in
t17 SR –
57 + 2tA –
+ tC
4TCL - 43
+ 2tA + tC
ns
Data hold after RD
rising edge
t18 SR 0
–
–
ns
Data Sheet
48
0
V2.0, 2000-12
C165
Multiplexed Bus (Reduced Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 20 MHz
1 / 2TCL = 1 to 20 MHz
min.
max.
min.
max.
Data float after RD
t19 SR –
36 + tF
–
2TCL - 14
+ tF
ns
Data valid to WR
t22 CC 24 + tC
–
2TCL - 26
+ tC
–
ns
Data hold after WR
t23 CC 36 + tF
–
2TCL - 14
+ tF
–
ns
ALE rising edge after RD, t25 CC 36 + tF
WR
–
2TCL - 14
+ tF
–
ns
Address hold after RD,
WR
t27 CC 36 + tF
–
2TCL - 14
+ tF
–
ns
ALE falling edge to CS1)
10 - tA
- 8 - tA
10 - tA
ns
CS low to Valid Data In1)
t38 CC - 8 - tA
t39 SR –
47+ tC
+ 2tA
–
3TCL - 28
+ t C + 2 tA
ns
CS hold after RD, WR1)
t40 CC 57 + tF
–
3TCL - 18
+ tF
–
ns
ALE fall. edge to RdCS,
WrCS (with RW delay)
t42 CC 19 + tA
–
TCL - 6
+ tA
–
ns
ALE fall. edge to RdCS,
WrCS (no RW delay)
t43 CC - 6 + tA
–
-6
+ tA
–
ns
Address float after RdCS, t44 CC –
WrCS (with RW delay)
0
–
0
ns
Address float after RdCS, t45 CC –
WrCS (no RW delay)
25
–
TCL
ns
RdCS to Valid Data In
(with RW delay)
t46 SR –
20 + tC
–
2TCL - 30
+ tC
ns
RdCS to Valid Data In
(no RW delay)
t47 SR –
45 + tC
–
3TCL - 30
+ tC
ns
RdCS, WrCS Low Time
(with RW delay)
t48 CC 38 + tC
–
2TCL - 12
+ tC
–
ns
RdCS, WrCS Low Time
(no RW delay)
t49 CC 63 + tC
–
3TCL - 12
+ tC
–
ns
Data Sheet
49
V2.0, 2000-12
C165
Multiplexed Bus (Reduced Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 20 MHz
1 / 2TCL = 1 to 20 MHz
min.
max.
min.
max.
Data valid to WrCS
t50 CC 28 + tC
–
2TCL - 22
+ tC
–
ns
Data hold after RdCS
t51 SR 0
t52 SR –
–
0
–
ns
30 + tF
–
2TCL - 20
+ tF
ns
Address hold after
RdCS, WrCS
t54 CC 30 + tF
–
2TCL - 20
+ tF
–
ns
Data hold after WrCS
t56 CC 30 + tF
–
2TCL - 20
+ tF
–
ns
Data float after RdCS
1)
These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
Data Sheet
50
V2.0, 2000-12
C165
t5
t16
t25
ALE
t38
t39
t40
CSxL
t17
A23-A16
(A15-A8)
BHE, CSxE
t27
Address
t6
t7
t54
t19
t18
Read Cycle
BUS
Address
t8
Data In
t10
t14
RD
t42
t44
t12
t51
t52
t46
RdCSx
t48
Write Cycle
BUS
t23
Address
t8
WR,
WRL,
WRH
t42
Data Out
t56
t10
t22
t12
t50
t44
WrCSx
t48
Figure 13
Data Sheet
External Memory Cycle:
Multiplexed Bus, With Read/Write Delay, Normal ALE
51
V2.0, 2000-12
C165
t5
t16
t25
t39
t40
t17
t27
ALE
t38
CSxL
A23-A16
(A15-A8)
BHE, CSxE
Address
t6
t7
t54
t19
t18
Read Cycle
BUS
Address
Data In
t10
t8
t14
RD
t4
t42
t12
t51
t52
t46
RdCSx
t48
Write Cycle
BUS
t23
Address
Data Out
t10
t8
WR,
WRL,
WRH
t44
t42
t56
t22
t12
t50
WrCSx
t48
Figure 14
External Memory Cycle:
Multiplexed Bus, With Read/Write Delay, Extended ALE
Data Sheet
52
V2.0, 2000-12
C165
t5
t16
t25
ALE
t38
t39
t40
CSxL
t17
A23-A16
(A15-A8)
BHE, CSxE
t27
Address
t6
t7
t54
t19
t18
Read Cycle
BUS
Address
t9
Data In
t11
t15
RD
t43
t13
t45
t47
RdCSx
t51
t52
t49
Write Cycle
BUS
t23
Address
t9
WR,
WRL,
WRH
t43
Data Out
t56
t11
t22
t45
t13
t50
WrCSx
t49
Figure 15
Data Sheet
External Memory Cycle:
Multiplexed Bus, No Read/Write Delay, Normal ALE
53
V2.0, 2000-12
C165
t5
t16
t25
t39
t40
t17
t27
ALE
t38
CSxL
A23-A16
(A15-A8)
BHE, CSxE
Address
t6
t7
t54
t19
t18
Read Cycle
BUS
Address
Data In
t9
t11
RD
t15
t13
t43
t45
RdCSx
t51
t52
t47
t49
Write Cycle
BUS
t23
Address
Data Out
t56
t9
WR,
WRL,
WRH
t43
t11
t22
t45
t13
t50
WrCSx
t49
Figure 16
External Memory Cycle:
Multiplexed Bus, No Read/Write Delay, Extended ALE
Data Sheet
54
V2.0, 2000-12
C165
AC Characteristics
Demultiplexed Bus (Standard Supply Voltage Range)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 25 MHz
min.
Variable CPU Clock Unit
1 / 2TCL = 1 to 25 MHz
max.
min.
max.
ALE high time
t5
CC 10 + tA
–
TCL - 10
+ tA
–
ns
Address setup to ALE
t6
CC 4 + tA
–
TCL - 16
+ tA
–
ns
ALE falling edge to RD,
WR (with RW-delay)
t8
CC 10 + tA
–
TCL - 10
+ tA
–
ns
ALE falling edge to RD,
WR (no RW-delay)
t9
CC - 10 + tA –
- 10
+ tA
–
ns
RD, WR low time
(with RW-delay)
t12 CC 30 + tC
–
2TCL - 10
+ tC
–
ns
RD, WR low time
(no RW-delay)
t13 CC 50 + tC
–
3TCL - 10
+ tC
–
ns
RD to valid data in
(with RW-delay)
t14 SR –
20 + tC
–
2TCL - 20
+ tC
ns
RD to valid data in
(no RW-delay)
t15 SR –
40 + tC
–
3TCL - 20
+ tC
ns
ALE low to valid data in
t16 SR –
40 +
tA + t C
–
3TCL - 20
+ tA + tC
ns
Address to valid data in
t17 SR –
50 +
2 tA + t C
–
4TCL - 30
+ 2tA + tC
ns
Data hold after RD
rising edge
t18 SR 0
–
0
–
ns
Data float after RD rising t20 SR –
edge (with RW-delay1))
26 +
–
1)
2 tA + t F
2TCL - 14
+ 22tA
+ tF1)
ns
Data float after RD rising t21 SR –
edge (no RW-delay1))
10 +
–
1)
2 tA + t F
TCL - 10
+ 22tA
+ tF1)
ns
Data Sheet
55
V2.0, 2000-12
C165
Demultiplexed Bus (Standard Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 25 MHz
min.
Variable CPU Clock Unit
1 / 2TCL = 1 to 25 MHz
max.
min.
max.
Data valid to WR
t22 CC 20 + tC
–
2TCL - 20
+ tC
–
ns
Data hold after WR
t24 CC 10 + tF
–
TCL - 10
+ tF
–
ns
ALE rising edge after
RD, WR
t26 CC - 10 + tF –
- 10 + tF
–
ns
Address hold after WR2) t28 CC 0 + tF
ALE falling edge to CS3) t38 CC - 4 - tA
–
0 + tF
–
ns
10 - tA
- 4 - tA
10 - tA
ns
CS low to Valid Data In3) t39 SR –
40 +
tC + 2tA
–
3TCL - 20
+ tC + 2tA
ns
CS hold after RD, WR3)
t41 CC 6 + tF
–
TCL - 14
+ tF
–
ns
ALE falling edge to
RdCS, WrCS (with RWdelay)
t42 CC 16 + tA
–
TCL - 4
+ tA
–
ns
ALE falling edge to
RdCS, WrCS (no RWdelay)
t43 CC - 4 + tA
–
-4
+ tA
–
ns
RdCS to Valid Data In
(with RW-delay)
t46 SR –
16 + tC
–
2TCL - 24
+ tC
ns
RdCS to Valid Data In
(no RW-delay)
t47 SR –
36 + tC
–
3TCL - 24
+ tC
ns
RdCS, WrCS Low Time
(with RW-delay)
t48 CC 30 + tC
–
2TCL - 10
+ tC
–
ns
RdCS, WrCS Low Time
(no RW-delay)
t49 CC 50 + tC
–
3TCL - 10
+ tC
–
ns
Data valid to WrCS
t50 CC 26 + tC
–
2TCL - 14
+ tC
–
ns
Data hold after RdCS
t51 SR 0
–
0
–
ns
Data Sheet
56
V2.0, 2000-12
C165
Demultiplexed Bus (Standard Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 25 MHz
min.
Data float after RdCS
(with RW-delay)1)
t53 SR –
Variable CPU Clock Unit
1 / 2TCL = 1 to 25 MHz
max.
min.
max.
20 + tF
–
2TCL - 20
+ 2tA + tF
ns
TCL - 20
+ 2tA + tF
ns
1)
Data float after RdCS
(no RW-delay)1)
t68 SR –
0 + tF
–
1)
Address hold after
RdCS, WrCS
t55 CC - 6 + tF
–
- 6 + tF
–
ns
Data hold after WrCS
t57 CC 6 + tF
–
TCL - 14
+ tF
–
ns
1)
RW-delay and tA refer to the next following bus cycle (including an access to an on-chip X-Peripheral).
2)
Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address changes before the end of RD have no impact on read cycles.
3)
These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
Data Sheet
57
V2.0, 2000-12
C165
AC Characteristics
Demultiplexed Bus (Reduced Supply Voltage Range)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 20 MHz
min.
Variable CPU Clock Unit
1 / 2TCL = 1 to 20 MHz
max.
min.
max.
ALE high time
t5
CC 11 + tA
–
TCL - 14
+ tA
–
ns
Address setup to ALE
t6
CC 5 + tA
–
TCL - 20
+ tA
–
ns
ALE falling edge to RD,
WR (with RW-delay)
t8
CC 15 + tA
–
TCL - 10
+ tA
–
ns
ALE falling edge to RD,
WR (no RW-delay)
t9
CC - 10 + tA –
- 10
+ tA
–
ns
RD, WR low time
(with RW-delay)
t12 CC 34 + tC
–
2TCL - 16
+ tC
–
ns
RD, WR low time
(no RW-delay)
t13 CC 59 + tC
–
3TCL - 16
+ tC
–
ns
RD to valid data in
(with RW-delay)
t14 SR –
22 + tC
–
2TCL - 28
+ tC
ns
RD to valid data in
(no RW-delay)
t15 SR –
47 + tC
–
3TCL - 28
+ tC
ns
ALE low to valid data in
t16 SR –
45 +
tA + t C
–
3TCL - 30
+ tA + tC
ns
Address to valid data in
t17 SR –
57 +
2 tA + t C
–
4TCL - 43
+ 2tA + tC
ns
Data hold after RD
rising edge
t18 SR 0
–
0
–
ns
Data float after RD rising t20 SR –
edge (with RW-delay1))
36 +
–
1)
2 tA + t F
2TCL - 14
+ 22tA
+ tF1)
ns
Data float after RD rising t21 SR –
edge (no RW-delay1))
15 +
–
1)
2 tA + t F
TCL - 10
+ 22tA
+ tF1)
ns
Data Sheet
58
V2.0, 2000-12
C165
Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 20 MHz
min.
Variable CPU Clock Unit
1 / 2TCL = 1 to 20 MHz
max.
min.
max.
Data valid to WR
t22 CC 24 + tC
–
2TCL - 26
+ tC
–
ns
Data hold after WR
t24 CC 15 + tF
–
TCL - 10
+ tF
–
ns
ALE rising edge after
RD, WR
t26 CC - 12 + tF –
- 12 + tF
–
ns
Address hold after WR2) t28 CC 0 + tF
ALE falling edge to CS3) t38 CC - 8 - tA
–
0 + tF
–
ns
10 - tA
- 8 - tA
10 - tA
ns
CS low to Valid Data In3) t39 SR –
47 +
tC + 2tA
–
3TCL - 28
+ tC + 2tA
ns
CS hold after RD, WR3)
t41 CC 9 + tF
–
TCL - 16
+ tF
–
ns
ALE falling edge to
RdCS, WrCS (with RWdelay)
t42 CC 19 + tA
–
TCL - 6
+ tA
–
ns
ALE falling edge to
RdCS, WrCS (no RWdelay)
t43 CC - 6 + tA
–
-6
+ tA
–
ns
RdCS to Valid Data In
(with RW-delay)
t46 SR –
20 + tC
–
2TCL - 30
+ tC
ns
RdCS to Valid Data In
(no RW-delay)
t47 SR –
45 + tC
–
3TCL - 30
+ tC
ns
RdCS, WrCS Low Time
(with RW-delay)
t48 CC 38 + tC
–
2TCL - 12
+ tC
–
ns
RdCS, WrCS Low Time
(no RW-delay)
t49 CC 63 + tC
–
3TCL - 12
+ tC
–
ns
Data valid to WrCS
t50 CC 28 + tC
–
2TCL - 22
+ tC
–
ns
Data hold after RdCS
t51 SR 0
–
0
–
ns
Data Sheet
59
V2.0, 2000-12
C165
Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 20 MHz
min.
Data float after RdCS
(with RW-delay)1)
t53 SR –
Variable CPU Clock Unit
1 / 2TCL = 1 to 20 MHz
max.
min.
max.
30 + tF
–
2TCL - 20
+ 2tA + tF
ns
TCL - 20
+ 2tA + tF
ns
1)
Data float after RdCS
(no RW-delay)1)
t68 SR –
5 + tF
–
1)
Address hold after
RdCS, WrCS
t55 CC - 16 + tF –
- 16 + tF
–
ns
Data hold after WrCS
t57 CC 9 + tF
TCL - 16
+ tF
–
ns
–
1)
RW-delay and tA refer to the next following bus cycle (including an access to an on-chip X-Peripheral).
2)
Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address changes before the end of RD have no impact on read cycles.
3)
These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
Data Sheet
60
V2.0, 2000-12
C165
t5
t16
t26
ALE
t38
t39
t41
CSxL
t17
A23-A16
A15-A0
BHE, CSxE
t28
Address
t6
t55
t20
t18
Read Cycle
BUS
(D15-D8)
D7-D0
Data In
t8
t14
RD
t12
t42
RdCSx
t51
t53
t46
t48
Write Cycle
BUS
(D15-D8)
D7-D0
WR,
WRL,
WRH
t24
Data Out
t57
t8
t22
t12
t50
t42
WrCSx
t48
Figure 17
Data Sheet
External Memory Cycle:
Demultiplexed Bus, With Read/Write Delay, Normal ALE
61
V2.0, 2000-12
C165
t5
t16
t26
ALE
t38
t39
t41
CSxL
t17
A23-A16
A15-A0
BHE,
CSxE
t28
Address
t6
t55
t20
t18
Read Cycle
BUS
(D15-D8)
D7-D0
Data In
t8
t14
RD
t12
t42
t51
t53
t46
RdCSx
t48
Write Cycle
BUS
(D15-D8)
D7-D0
WR,
WRL,
WRH
t24
Data Out
t57
t8
t22
t12
t50
t42
WrCSx
t48
Figure 18
Data Sheet
External Memory Cycle:
Demultiplexed Bus, With Read/Write Delay, Extended ALE
62
V2.0, 2000-12
C165
t5
t16
t26
ALE
t38
t39
t41
CSxL
t17
A23-A16
A15-A0
BHE, CSxE
t28
Address
t6
Read Cycle
BUS
(D15-D8)
D7-D0
t55
t21
t18
Data In
t9
t15
RD
t43
t13
t47
RdCSx
t51
t68
t49
Write Cycle
BUS
(D15-D8)
D7-D0
t24
Data Out
t57
t9
t22
WR,
WRL,WRH
t13
t50
t43
WrCSx
t49
Figure 19
External Memory Cycle:
Demultiplexed Bus, No Read/Write Delay, Normal ALE
Data Sheet
63
V2.0, 2000-12
C165
t5
t16
t26
ALE
t38
t39
t41
CSxL
t17
A23-A16
A15-A0
BHE,CSxE
t28
Address
t6
t55
t21
t18
Read Cycle
BUS
(D15-D8)
D7-D0
Data In
t9
t15
RD
t13
t43
t51
t68
t47
RdCSx
t49
Write Cycle
BUS
(D15-D8)
D7-D0
t24
Data Out
t57
t9
t22
WR,
WRL, WRH
t13
t50
t43
WrCSx
t49
Figure 20
Data Sheet
External Memory Cycle:
Demultiplexed Bus, No Read/Write Delay, Extended ALE
64
V2.0, 2000-12
C165
AC Characteristics
CLKOUT and READY (Standard Supply Voltage)
(Operating Conditions apply)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 25 MHz
1 / 2TCL = 1 to 25 MHz
min.
CLKOUT cycle time
CLKOUT high time
CLKOUT low time
CLKOUT rise time
CLKOUT fall time
CLKOUT rising edge to
ALE falling edge
t29
t30
t31
t32
t33
t34
max.
min.
max.
CC 40
40
2TCL
2TCL
ns
CC 14
–
TCL - 6
–
ns
CC 10
–
TCL - 10
–
ns
CC –
4
–
4
ns
CC –
4
–
4
ns
CC 0 + tA
10 + tA
0 + tA
10 + tA
ns
Synchronous READY
setup time to CLKOUT
t35 SR 14
–
14
–
ns
Synchronous READY
hold time after CLKOUT
t36 SR 4
–
4
–
ns
Asynchronous READY
low time
t37 SR 54
–
2TCL + t58 –
ns
Asynchronous READY
setup time1)
t58 SR 14
–
14
–
ns
Asynchronous READY
hold time1)
t59 SR 4
–
4
–
ns
0
+ 2tA +
0
TCL - 20
+ 2tA + tC
+ tF2)
ns
Async. READY hold time t60 SR 0
after RD, WR high
(Demultiplexed Bus)2)
tC
+ tF2)
1)
These timings are given for test purposes only, in order to assure recognition at a specific clock edge.
2)
Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This
adds even more time for deactivating READY.
The 2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle.
The maximum limit for t60 must be fulfilled if the next following bus cycle is READY controlled.
Data Sheet
65
V2.0, 2000-12
C165
AC Characteristics
CLKOUT and READY (Reduced Supply Voltage)
(Operating Conditions apply)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 20 MHz
1 / 2TCL = 1 to 20 MHz
min.
CLKOUT cycle time
CLKOUT high time
CLKOUT low time
CLKOUT rise time
CLKOUT fall time
CLKOUT rising edge to
ALE falling edge
t29
t30
t31
t32
t33
t34
max.
min.
max.
CC 50
50
2TCL
2TCL
ns
CC 15
–
TCL - 10
–
ns
CC 13
–
TCL - 12
–
ns
CC –
12
–
12
ns
CC –
8
–
8
ns
CC 0 + tA
8 + tA
0 + tA
8 + tA
ns
Synchronous READY
setup time to CLKOUT
t35 SR 18
–
18
–
ns
Synchronous READY
hold time after CLKOUT
t36 SR 4
–
4
–
ns
Asynchronous READY
low time
t37 SR 68
–
2TCL + t58 –
ns
Asynchronous READY
setup time1)
t58 SR 18
–
18
–
ns
Asynchronous READY
hold time1)
t59 SR 4
–
4
–
ns
0
+ 2tA +
0
TCL – 25
+ 2tA + tC
+ tF2)
ns
Async. READY hold time t60 SR 0
after RD, WR high
(Demultiplexed Bus)2)
tC
+ tF2)
1)
These timings are given for test purposes only, in order to assure recognition at a specific clock edge.
2)
Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This
adds even more time for deactivating READY.
The 2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle.
The maximum limit for t60 must be fulfilled if the next following bus cycle is READY controlled.
Data Sheet
66
V2.0, 2000-12
C165
Running Cycle
READY
Waitstate
1)
MUX/Tristate 6)
t32
t33
t30
t29
CLKOUT
t31
t34
ALE
7)
Command
RD, WR
2)
t36
t35
Sync
READY
t35
3)
3)
t59
t58
Async
READY
t36
t59
t60 4)
t58
3)
3)
t37 5)
see 6)
MCT04447
Figure 21
CLKOUT and READY
Notes
1)
2)
3)
4)
5)
6)
7)
Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).
The leading edge of the respective command depends on RW-delay.
READY sampled HIGH at this sampling point generates a READY controlled waitstate,
READY sampled LOW at this sampling point terminates the currently running bus cycle.
READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or
WR).
If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT
(e.g. because CLKOUT is not enabled), it must fulfill t37 in order to be safely synchronized. This is guaranteed,
if READY is removed in response to the command (see Note 4)).
Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may
be inserted here.
For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without
MTTC waitstate this delay is zero.
The next external bus cycle may start here.
Data Sheet
67
V2.0, 2000-12
C165
AC Characteristics
External Bus Arbitration (Standard Supply Voltage)
(Operating Conditions apply)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 25 MHz
1 / 2TCL = 1 to 25 MHz
min.
max.
min.
max.
20
–
20
–
ns
HOLD input setup time
to CLKOUT
t61 SR
CLKOUT to HLDA high
or BREQ low delay
t62 CC –
20
–
20
ns
CLKOUT to HLDA low
or BREQ high delay
t63 CC –
20
–
20
ns
CSx release
t64
t65
t66
t67
CSx drive
Other signals release
Other signals drive
CC
–
20
–
20
ns
CC
-4
24
-4
24
ns
CC
–
20
–
20
ns
CC
-4
24
-4
24
ns
External Bus Arbitration (Reduced Supply Voltage)
(Operating Conditions apply)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 20 MHz
1 / 2TCL = 1 to 20 MHz
min.
max.
min.
max.
30
–
30
–
ns
HOLD input setup time
to CLKOUT
t61 SR
CLKOUT to HLDA high
or BREQ low delay
t62 CC –
20
–
20
ns
CLKOUT to HLDA low
or BREQ high delay
t63 CC –
20
–
20
ns
CSx release
t64
t65
t66
t67
CSx drive
Other signals release
Other signals drive
Data Sheet
CC
–
20
–
20
ns
CC
-4
30
-4
30
ns
CC
–
20
–
20
ns
CC
-4
30
-4
30
ns
68
V2.0, 2000-12
C165
CLKOUT
t61
HOLD
t63
HLDA
see1)
t62
BREQ
2)
t64
3)
CSx
(On P6.x)
t66
Other
Signals
1)
Figure 22
MCT04448
External Bus Arbitration, Releasing the Bus
Notes
1)
The C165 will complete the currently running bus cycle before granting bus access.
2)
This is the first possibility for BREQ to get active.
3) The CS outputs will be resistive high (pullup) after t .
64
Data Sheet
69
V2.0, 2000-12
C165
CLKOUT
2)
t61
HOLD
t62
HLDA
t62
BREQ
t62
t63
1)
t65
CSx
(On P6.x)
t67
Other
Signals
MCT04449
Figure 23
External Bus Arbitration, (Regaining the Bus)
Notes
1)
This is the last chance for BREQ to trigger the indicated regain-sequence.
Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high.
Please note that HOLD may also be deactivated without the C165 requesting the bus.
2)
The next C165 driven bus cycle may start here.
Data Sheet
70
V2.0, 2000-12
C165
Package Outlines
GPR05365
P-MQFP-100 (SMD)
(Plastic Metric Quad Flat Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Data Sheet
71
Dimensions in mm
V2.0, 2000-12
C165
GPP05614
P-TQFP-100 (SMD)
(Plastic Thin Metric Quad Flat Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Data Sheet
72
Dimensions in mm
V2.0, 2000-12
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