C166S V1 SubSystem User Manual

Us er’s Ma nual, V 1 .6 , A ugust 2001
C166S V1 SubSystem
C166S V1 SubS R1
Microcontrollers
N e v e r
s t o p
t h i n k i n g .
Edition 2001-08
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 2001.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address
list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Us er’s Ma nual, V 1 .6 , A ugust 2001
C166S V1 SubSystem
C166S V1 SubS R1
Microcontrollers
N e v e r
s t o p
t h i n k i n g .
C166S V1 SubS R1
Revision History:
2001-08
Previous Version:
V 1.5
Page
Subjects (major changes since last revision)
2-12
Periodic Wake up from Idle or Sleep Mode
2-14
Clock Generation Unit, On-chip Bootstrap Loader
V 1.6
3-80..3-86 Particular Pipeline Effects
6-21
CALLA Instruction description
6-38
EINIT Instruction description
6-52
JMPA Instruction description
6-78
RETI Instruction description
6-91
SRVWDT Instruction description
6-96
TRAP Instruction description
8-1...8-29
RP0H Register
8-1, 8-34
DP3, P3, ODP4, ODP6 Registers
8-22
CLKEN System Clock Enable bit
8-31
External Bus Arbitration
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
[email protected]
User’s Manual
C166S V1 SubSystem
Table of Contents
Page
1
1.1
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
The Members of the 16-bit Microcontroller Family . . . . . . . . . . . . . . . . . 1-2
Summary of Basic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
2
2.1
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.2
2.2.1
2.2.2
2.2.3
2.2.3.1
2.2.3.2
2.2.3.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
2.2.9
System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Basic CPU Concepts and Mega Core . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
High Instruction Bandwidth / Fast Execution . . . . . . . . . . . . . . . . . . . . 2-2
High Function 8-bit and 16-bit Arithmetic and Logic Unit . . . . . . . . . . . 2-3
Extended Bit Processing and Peripheral Control . . . . . . . . . . . . . . . . . 2-4
Consistent and Optimized Instruction Formats . . . . . . . . . . . . . . . . . . 2-5
Programmable Multiple Priority Interrupt and PEC System . . . . . . . . . 2-6
The C166S System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Memory Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
The On-chip Peripheral Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Asynchronous / Synchronous Serial Channel (ASC0) . . . . . . . . . . . 2-9
High Speed Synchronous Serial Channel (SSC0) . . . . . . . . . . . . . 2-10
General Purpose Timer Unit (GPT12E) . . . . . . . . . . . . . . . . . . . . . 2-10
Parallel Ports (PPorts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Periodic Wakeup from Idle or Sleep Mode . . . . . . . . . . . . . . . . . . . . 2-12
OCDS and JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Core Control Block (CCB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Clock Generation Unit (CGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
On-chip Bootstrap Loader. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
3
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.4.1
3.4.4.2
3.4.5
3.4.5.1
Central Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Register Description Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
CPU Special-Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Instruction Fetch and Program Flow Control . . . . . . . . . . . . . . . . . . . . . . 3-7
Branch Target Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Sequential and Non-Sequential Instruction Flow . . . . . . . . . . . . . . . . 3-9
ATOMIC and EXTended Instructions . . . . . . . . . . . . . . . . . . . . . . . . 3-13
Code Addressing via Code Segment and Instruction Pointer . . . . . . 3-14
The CPU/System Configuration Register SYSCON . . . . . . . . . . . . . 3-17
Interrupt and Exception Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
Interrupt System Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
Interrupt Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
Interrupt Control Functions in the Processor Status Word . . . . . . . 3-22
Saving the Status during Interrupt Service . . . . . . . . . . . . . . . . . . 3-24
Context Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
Software Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
User’s Manual
I-1
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Table of Contents
3.4.5.2
3.4.6
3.4.6.1
3.4.6.2
3.4.6.3
3.4.6.4
3.4.6.5
3.4.6.6
3.4.6.7
3.5
3.5.1
3.6
3.6.1
3.6.2
3.6.2.1
3.6.2.2
3.6.2.3
3.6.2.4
3.6.3
3.6.3.1
3.6.3.2
3.6.3.3
3.7
3.7.1
3.7.2
3.7.3
3.7.4
3.7.5
3.7.6
3.8
3.8.1
3.8.1.1
3.8.1.2
3.8.1.3
3.8.2
3.9
3.10
3.10.1
3.10.2
3.10.3
3.10.4
Page
Hardware Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Event Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The PEC Source and Destination Pointers . . . . . . . . . . . . . . . . . .
PEC Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Long Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Link Mode for Data Chaining . . . . . . . . . . . . . . . . . . . . . .
PEC Channels Assignment and Arbitration . . . . . . . . . . . . . . . . . .
Programmable End of PEC Interrupt Level . . . . . . . . . . . . . . . . . .
Using General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Context Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Long and Indirect Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . .
Addressing via Data Page Pointer . . . . . . . . . . . . . . . . . . . . . . . . .
DPP Override Mechanism in the C166S . . . . . . . . . . . . . . . . . . . .
Long Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Indirect Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The System Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stack Overflow and Underflow . . . . . . . . . . . . . . . . . . . . . . . . . . .
Linear Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Circular (Virtual) Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The 16-bit Adder/Subtracter, Barrel Shifter
and the 16-bit Logic Unit 3-70
Bit-manipulation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiply and Divide Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Processor Status Word Register (PSW) . . . . . . . . . . . . . . . . . .
Instruction Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Particular Pipeline Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specific cases with core registers . . . . . . . . . . . . . . . . . . . . . . . . .
Common portable solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction State Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dedicated CSFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Summary of CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Core Special Function Registers Ordered by Name . . . . . . . . . . . . .
Core Special Function Registers ordered by Address . . . . . . . . . . .
Register Overview C166S Interrupt and Peripheral Event Controller
User’s Manual
I-2
3-26
3-32
3-33
3-36
3-38
3-39
3-41
3-43
3-44
3-46
3-50
3-52
3-52
3-54
3-55
3-57
3-58
3-59
3-61
3-62
3-64
3-65
3-68
3-68
3-70
3-70
3-72
3-76
3-80
3-80
3-81
3-81
3-86
3-87
3-89
3-91
3-91
3-93
3-94
3-95
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Table of Contents
Page
4
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.4
4.4.1
4.5
4.6
4.6.1
4.7
4.8
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Data Organization in Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Internal Local Memory Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
DPRAM and SFR-Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Data Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Special Function Register Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
PEC Source and Destination Pointers . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
External Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
External data accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Crossing Memory Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
System Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
Data Organization in General Purpose Registers . . . . . . . . . . . . . . . 4-10
SFR / ESFR Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43
5
5.1
5.2
5.3
5.4
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Short Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Instruction Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
6
Detailed Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
7
7.1
7.2
7.3
7.4
7.5
Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Alternate Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
PORT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
PORT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
8
8.1
8.2
8.2.1
8.2.2
8.2.3
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.4
The External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Single-chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
External Bus Modes
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Multiplexed Bus Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Demultiplexed Bus Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
Switching Among the Bus Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
Programmable Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16
ALE Length Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16
Programmable Memory Cycle Time . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
Programmable Memory Tri-State Time . . . . . . . . . . . . . . . . . . . . . . 8-17
Read/Write Signal Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
Early WR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
READY Controlled Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
Controlling the External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . 8-21
User’s Manual
I-3
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Table of Contents
Page
8.5
8.6
8.7
8.7.1
EBC Idle State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The XBUS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XBUS Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
9.1
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
Operation of the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
10
10.1
10.2
10.3
10.3.1
10.3.1.1
10.3.1.2
10.3.1.3
10.3.2
10.3.2.1
10.3.2.2
10.3.2.3
10.3.3
10.3.3.1
10.3.3.2
10.3.4
10.3.5
Asynchronous/Synchronous Serial Interface (ASC) . . . . . . . . . . . . 10-1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
Operational Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
Asynchronous Data Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
Asynchronous Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
Asynchronous Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
Synchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
Synchronous Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
Synchronous Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
Synchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
Baudrate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
Baudrate in Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
Baudrate in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . 10-21
Hardware Error Detection Capabilities . . . . . . . . . . . . . . . . . . . . . . 10-23
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23
11
11.1
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.2.6
High-Speed Synchronous Serial Interface (SSC) . . . . . . . . . . . . . . . 11-1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
Half-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
Continuous Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
Baudrate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
Error Detection Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
12
12.1
12.2
12.2.1
12.2.2
12.2.3
12.3
12.3.1
General Purpose Timer Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
Functional Description of Timer Block 1 . . . . . . . . . . . . . . . . . . . . . . . . 12-3
Core Timer T3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
Auxiliary Timers T2 and T4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16
Timer Concatenation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21
Functional Description of Timer Block 2 . . . . . . . . . . . . . . . . . . . . . . . 12-26
Core Timer T6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28
User’s Manual
I-4
8-30
8-31
8-35
8-37
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Table of Contents
12.3.2
12.3.3
Page
Auxiliary Timer T5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-34
Timer Concatenation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-38
13
Instruction Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
14
Keyword Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
User’s Manual
I-5
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
User’s Manual
I-6
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Introduction
1
Introduction
The rapidly growing area of embedded control applications is representing one of the
most time-critical operating environments for today’s microcontrollers. Complex control
algorithms have to be processed based on a large number of digital as well as analog
input signals, and the appropriate output signals must be generated within a defined
maximum response time. Embedded control applications also are often sensitive to
board space, power consumption, and overall system cost.
Embedded control applications therefore require microcontrollers, which...
•
•
•
•
offer a high level of system integration
eliminate the need for additional peripheral devices and the associated software overhead
provide system security and fail-safe mechanisms
provide effective means to control (and reduce) the device’s power consumption.
About this Manual
This manual describes the functionality of the 16-bit microcontroller-subsystem
C166S_R1 of the Infineon C166 Family, the C166S-class.
User’s Manual
1-1
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Introduction
1.1
The Members of the 16-bit Microcontroller Family
The microcontroller-subsystem of the Infineon 16-bit family has been designed to meet
the high performance requirements of real-time embedded control applications. The
architecture of this family has been optimized for high instruction throughput and
minimum response time to external stimuli (interrupts). Intelligent peripheral subsystems
have been integrated to reduce the need for CPU (Central Processing Unit) intervention
to a minimum extent. This also minimizes the need for communication via the external
bus interface. The high flexibility of this architecture allows to serve the diverse and
varying needs of different application areas such as automotive, industrial control, or
data communications.
The core of the 16-bit family has been developed with a modular family concept in mind.
All family members execute an efficient control-optimized instruction set (additional
instructions for members of the second generation). This allows an easy and quick
implementation of new family members with different internal memory sizes and
technologies, different sets of on-chip peripherals and/or different numbers of I/O (Input/
Output ) pins.
The Internal Bus Interface (IBI) concept opens a straight forward path for the integration
of application specific peripheral modules in addition to the standard on-chip peripherals
in order to build application specific derivatives.
As programs for embedded control applications become larger, high level languages are
favoured by programmers, because high level language programs are easier to write, to
debug and to maintain.
The 80C166-type microcontrollers were the first generation of the 16-bit controller
family. These devices have established the C166 architecture.
The C165-type and C167-type devices are members of the second generation of this
family. This second generation is even more powerful due to additional instructions for
HLL support, an increased address space, increased internal RAM (Random Access
Memory) and highly efficient management of various resources on the external bus.
The C166S-type devices are members of the third generation of this family. This third
generation is the synthesizable version of the second generation.
Enhanced derivatives of this second/third generation provide additional features like
additional internal high-speed RAM, an integrated CAN-Module (Controller Area
Network), an on-chip PLL (Phase Locked Loop), etc.
Utilizing integration to design efficient systems may require the integration of application
specific peripherals to boost system performance, while minimizing the part count.
These efforts are supported by the so-called Internal Bus Interface, defined for the
Infineon 16-bit microcontrollers (XBus second generation). This Internal Bus Interface is
an internal representation of the External Bus Interface that opens and simplifies the
integration of peripherals by standardizing the required interface.
User’s Manual
1-2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Introduction
1.2
Summary of Basic Features
The C166S is an improved representative of the Infineon family of full featured 16-bit
single-chip CMOS (Complementary Metal Oxide Silicon) microcontrollers. It combines
high CPU performance with high peripheral functionality.
Several key features contribute to the high performance of the C166S bases subsystem
(the indicated timings refer to a CPU clock of 50 MHz).
High Performance 16-Bit CPU With Four-Stage Pipeline
•
•
•
•
•
•
•
40 ns minimum instruction cycle time, with most instructions executed in 1 cycle
200 ns multiplication (16-bit *16-bit), 400 ns division (32-bit/16-bit)
Multiple high bandwidth internal data buses
Register based design with multiple variable register banks
Single cycle context switching support
16 MBytes linear address space for code and data (von Neumann architecture)
System stack cache support with automatic stack overflow/underflow detection
Control Oriented Instruction Set with High Efficiency
• Bit, byte, and word data types
• Flexible and efficient addressing modes for high code density
• Enhanced boolean bit manipulation with direct addressability of 6 Kbits
for peripheral control and user defined flags
• Hardware traps to identify exception conditions during runtime
• HLL support for semaphore operations and efficient data access
External Bus Interface
•
•
•
•
Multiplexed or demultiplexed bus configurations
Segmentation capability and chip slect signal generation
8-bit or 16-bit data bus
Bus cycle characteristics selectable for five programmable address areas
16-Priority-Level Interrupt System
• Up to 112 interrupt nodes with separate interrupt vectors
• 16 priority levels and 4(8) group levels
Up to 16-Channel Peripheral Event Controller (PEC)
•
•
•
•
•
Interrupt driven single cycle data transfer
Transfer count option (std. CPU interrupt after programmable number of PEC transfers)
Long Transfer Counter
Channel Linking
Eliminates overhead of saving and restoring system state for interrupt requests
User’s Manual
1-3
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Introduction
Intelligent On-chip Peripherals
• General Purpose Timer Unit Timer Block 1:
– fPDBUS+/4 maximum resolution
– 3 independent timers/counters
– Timer/counters can be concatenated
– 4 operation modes (timer, gated timer, counter, incremental)
– Seperate interrupt lines
• General Purpose Timer Unit Timer Block 2:
– fPDBUS+/2 maximum resolution
– 2 independent timers/counters
– Timer/counters can be concatenated
– 3 operation modes (timer, gated timer, counter)
– Extendend capture/reload functions
– Seperate interrupt lines
• Asynchronous/Sychronous Serial Channel (ASC0)
with baud rate generator, parity, framing, and overrun error detection
• High Speed Synchronous Serial Cannel (SSC0)
with baud rate generator, programmable data length and shift direction
• Watchdog Timer with programmable timer events
User’s Manual
1-4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Introduction
Complete Development Support
For the development tool support of its microcontrollers, Infineon follows a clear third
party concept. Currently around 120 tool suppliers world-wide, ranging from local niche
manufacturers to multinational companies with broad product portfolios, offer powerful
development tools for the Infineon C166/C166S microcontroller families, guaranteeing a
remarkable variety of price-performance classes as well as early availability of high
quality key tools such as compilers, assemblers, simulators, debuggers or in-circuit
emulators.
Infineon incorporates its strategic tool partners very early into the product development
process, making sure embedded system developers get reliable, well-tuned tool
solutions, which help them unleash the power of Infineon microcontrollers in the most
effective way and with the shortest possible learning curve.
The tool environment for the Infineon 16-bit microcontrollers includes the following tools:
•
•
•
•
•
•
•
•
•
•
•
•
Compilers (C, MODULA2, FORTH)
Macro-Assemblers, Linkers, Locaters, Library Managers, Format-Converters
Architectural Simulators
HLL debuggers
Real-Time operating systems
VERILOG chip models
In-Circuit Emulators (based on bondout or standard chips)
Plug-In emulators
Emulation and Clip-Over adapters, production sockets
Logic Analyzer disassemblers
Starter Kits
Evaluation Boards with monitor programs
User’s Manual
1-5
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Introduction
User’s Manual
1-6
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
System Overview
2
System Overview
The architecture of the C166S combines the advantages of both RISC (Reduced
Instruction Set Computing) and CISC (Complex Instruction Set Computing) processors
in a very well-balanced way. The sum of the features which are combined results in a
high performance microcontroller, which is the right choice not only for today’s
applications, but also for future engineering challenges. C166S based derivatives does
not only integrate a powerful CPU (Central Processing Unit) core and a set of peripheral
units into one chip, but also connects the units in a very efficient way. One of the four
buses used concurrently on the C166S is the Internal Bus Interface, an internal
representation of the external bus interface. This bus provides a standardized method of
integrating application-specific peripherals to produce derivatives of the standard
C166S. This manual specially describes the C166S Subsystem consists of the CPU,
Interrupt Controller (ITC), Bus Controller (BC), On-Chip Debug Support (OCDS) and
other system specific peripherals and modules. The following figure shows the principles
of a C166S based system.
DPRAM
Interface
32
&&%
CPU
PLL
Clock
Generation
Unit
CEG
Local Memory Bus
Interrupt/
PEC
Break
Trace
Interface Interface
OSC
RC
PSC
Interrupt
Controller
OCDS/
JTAG
Peripheral
....
WDT
Local
Memory
16
Internal Bus Interface
&6
6\VWHP
up to 3 kByte
DPRAM
16
PDBUS+
Memory
GPT12E
SSC0
BC
ASC0
Config.
Block
Peripheral
....
Bus Interface
External Internal
C166S
Subsystem
NMI
JTAG
CONFIG
RESET
Bus
PORT
Port
2-1
PORT
Port
User’s Manual
Port
External
PORT and dedicated Pins
0/1/4/6
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
System Overview
2.1
Basic CPU Concepts and Mega Core
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic
and logic unit (ALU) and dedicated Special Function Registers (SFRs). Additional
hardware is provided for a separate multiply and divide unit, a bit-mask generator and a
barrel shifter.
To meet the demand for greater performance and flexibility, a number of areas has been
optimized in the processor core. Functional blocks in the CPU core are controlled by
signals from the instruction decode logic. These are summarized below, and described
in detail in the following sections:
1) High Instruction Bandwidth / Fast Execution
2) High Function 8-bit and 16-bit Arithmetic and Logic Unit
3) Extended Bit Processing and Peripheral Control
4) High Performance Branch-, Call-, and Loop Processing
5) Consistent and Optimized Instruction Formats
6) Programmable Multiple Priority Interrupt Structure
2.1.1
High Instruction Bandwidth / Fast Execution
Based on the hardware provisions, most of the C166S’s instructions can be executed in
just one machine cycle, which requires 2 CPU clock cycles T1 and T2 (2 * 1/ICPU =
4 TCL). For example, shift and rotate instructions are always processed within one
machine cycle, independent of the number of bits to be shifted.
Branch-, multiply- and divide instructions normally take more than one machine cycle.
These instructions, however, have also been optimized.
A 32-bit / 16-bit division takes 20 CPU clock cycles, a 16-bit * 16-bit multiplication takes
10 CPU clock cycles.
The instruction cycle time has been dramatically reduced through the use of instruction
pipelining. This technique allows the core CPU to process portions of multiple sequential
instruction stages in parallel. The following four stage pipeline provides the optimum
balancing for the CPU core:
FETCH: In this stage, an instruction is fetched from the internal ROM (Read Only
Memory) or RAM (Random Access Memory) or from the external memory, based on the
current Instruction Pointer (IP) value.
DECODE: In this stage, the previously fetched instruction is decoded and the required
operands are fetched.
EXECUTE: In this stage, the specified operation is performed on the previously fetched
operands.
WRITE BACK: In this stage, the result is written to the specified location.
User’s Manual
2-2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
System Overview
If this technique were not used, each instruction would require four machine cycles. This
increased performance allows a greater number of tasks and interrupts to be processed.
Instruction Decoder
Instruction decoding is primarily generated from PLA (Programmable Logic Array)
outputs based on the selected opcode. No microcode is used and each pipeline stage
receives control signals staged in control registers from the decode stage PLAs. Pipeline
holds are primarily caused by waitstates for external memory accesses and cause the
holding of signals in the control registers. Multiple-cycle instructions are performed
through instruction injection and simple internal state machines which modify required
control signals.
2.1.2
High Function 8-bit and 16-bit Arithmetic and Logic Unit
All standard arithmetic and logical operations are performed in a 16-bit ALU. In addition,
for byte operations, signals are provided from bits six and seven of the ALU result to
correctly set the condition flags. Multiple precision arithmetic is provided through a
’CARRY-IN’ signal to the ALU from previously calculated portions of the desired
operation.
Most internal execution blocks have been optimized to perform operations on either 8bit or 16-bit quantities. Once the pipeline has been filled, one instruction is completed per
machine cycle, except for multiply and divide. An advanced Booth algorithm has been
incorporated to allow four bits to be multiplied and two bits to be divided per machine
cycle. Thus, these operations use two coupled 16-bit registers, MDL (Multiply Divide
Low Word) and MDH (Multiply Divide High Word), and require four and nine machine
cycles, respectively, to perform a 16-bit by 16-bit (or 32-bit by 16-bit) calculation plus one
machine cycle to setup and adjust the operands and the result. Even these longer
multiply and divide instructions can be interrupted during their execution to allow for very
fast interrupt response. Instructions have also been provided to allow byte packing in
memory while providing sign extension of bytes for word wide arithmetic operations. The
internal bus structure also allows transfers of bytes or words to or from peripherals based
on the peripheral requirements.
A set of consistent flags is automatically updated in the PSW (Program Status Word)
after each arithmetic, logical, shift, or movement operation. These flags allow branching
on specific conditions. Support for both signed and unsigned arithmetic is provided
through user-specifiable branch tests. These flags are also preserved automatically by
the CPU upon entry into an interrupt or trap routine. All targets for branch calculations
are also computed in the central ALU.
A 16-bit barrel shifter provides multiple bit shifts in a single cycle. Rotates and arithmetic
shifts are also supported.
User’s Manual
2-3
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
System Overview
2.1.3
Extended Bit Processing and Peripheral Control
A large number of instructions has been dedicated to bit processing. These instructions
provide efficient control and testing of peripherals while enhancing data manipulation.
Unlike other microcontrollers, these instructions provide direct access to two operands
in the bit-addressable space without requiring to move them into temporary flags.
The same logical instructions available for words and bytes are also supported for bits.
This allows the user to compare and modify a control bit for a peripheral in one
instruction. Multiple-bit shift instructions have been included to avoid long instruction
streams of single-bit shift operations. These are also performed in a single machine
cycle.
In addition, bit field instructions have been provided, which allow the modification of
multiple bits from one operand in a single instruction.
High Performance Branch-, Call-, and Loop Processing
Due to the high percentage of branching in controller applications, branch instructions
have been optimized to require one extra machine cycle only when a branch is taken.
This is implemented by precalculating the target address while decoding the instruction.
To decrease loop execution overhead, three enhancements have been provided:
• The first solution provides two cycle branch execution after the first iteration of a loop.
Thus, only one additional machine cycle is lost during the execution of the entire loop. In
loops which fall through upon completion, no additional machine cycles is lost when
exiting the loop. No special instructions are required to perform loops, and loops are
automatically detected during execution of branch instructions.
• The second loop enhancement allows the detection of the end of a table and avoids
the use of two compare instructions embedded in loops. One simply places the lowest
negative number at the end of the specific table, and specifies branching if neither this
value nor the compared value have been found. Otherwise the loop is terminated if either
condition has been met. The terminating condition can then be tested.
• The third loop enhancement provides a more flexible solution than the Decrement and
Skip on Zero instruction which is found in other microcontrollers. Through the use of
Compare and Increment or Decrement instructions, the user can make comparisons to
any value. This allows loop counters to cover any range. This is particularly
advantageous in table searching.
Saving of system state is automatically performed on the internal system stack avoiding
the use of instructions to preserve state upon entry and exit of interrupt or trap routines.
Call instructions push the value of the IP on the system stack, and require the same
execution time as branch instructions.
Instructions have also been provided to support indirect branch and call instructions.
This supports implementation of multiple CASE statement branching in assembler
macros and high level languages.
User’s Manual
2-4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
System Overview
2.1.4
Consistent and Optimized Instruction Formats
To obtain optimum performance in a pipelined design, an instruction set has been
designed which incorporates concepts from Reduced Instruction Set Computing (RISC).
These concepts primarily allow fast decoding of the instructions and operands while
reducing pipeline holds. These concepts, however, do not preclude the use of complex
instructions, which are required by microcontroller users. The following goals were used
to design the instruction set:
1. Provide powerful instructions to perform operations which currently require
sequences of instructions and are frequently used. Avoid transfer into and out of
temporary registers such as accumulators and carry bits. Perform tasks in parallel
such as saving state upon entry into interrupt routines or subroutines.
2. Avoid complex encoding schemes by placing operands in consistent fields for each
instruction. Also avoid complex addressing modes which are not frequently used. This
decreases the instruction decode time while also simplifying the development of
compilers and assemblers.
3. Provide most frequently used instructions with one-word instruction formats. All other
instructions are placed into two-word formats. This allows all instructions to be placed
on word boundaries, which alleviates the need for complex alignment hardware. It
also has the benefit of increasing the range for relative branching instructions.
The high performance offered by the hardware implementation of the CPU can efficiently
be utilized by a programmer via the highly functional C166S instruction set which
includes the following instruction classes:
•
•
•
•
•
•
•
•
•
•
•
•
Arithmetic Instructions
Logical Instructions
Boolean Bit Manipulation Instructions
Compare and Loop Control Instructions
Shift and Rotate Instructions
Prioritize Instruction
Data Movement Instructions
System Stack Instructions
Jump and Call Instructions
Return Instructions
System Control Instructions
Miscellaneous Instructions
Possible operand types are bits, bytes and words. Specific instruction support the
conversion (extension) of bytes to words. A variety of direct, indirect or immediate
addressing modes are provided to specify the required operands.
User’s Manual
2-5
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
System Overview
2.1.5
Programmable Multiple Priority Interrupt and PEC System
The following enhancements have been included to allow processing of a large number
of interrupt sources:
1. Peripheral Event Controller (PEC): This processor is used to off-load many interrupt
requests from the CPU. It avoids the overhead of entering and exiting interrupt or trap
routines by performing single-cycle interrupt-driven byte or word data transfers
between any two locations with an optional increment of either the PEC source or the
destination pointer. Just one cycle is ’stolen’ from the current CPU activity to perform
a PEC service.
2. Multiple Priority Interrupt Controller (ITC): This controller allows all interrupts to be
placed at any specified priority. Interrupts may also be grouped, which provides the
user with the ability to prevent similar priority tasks from interrupting each other. For
each of the possible interrupt sources there is a separate control register, which
contains an interrupt request flag, an interrupt enable flag and an interrupt priority
bitfield. Once having been accepted by the CPU, an interrupt service can only be
interrupted by a higher prioritized service request. For standard interrupt processing,
each of the possible interrupt sources has a dedicated vector location.
3. Multiple Register Banks: This feature allows the user to specify up to sixteen general
purpose registers located anywhere in the internal DPRAM (Dual Port RAM). A single
one-machine-cycle instruction allows to switch register banks from one task to
another.
4. Interruptible Multiple Cycle Instructions: Reduced interrupt latency is provided by
allowing multiple-cycle instructions (multiply, divide) to be interruptible.
5. Hardware Traps: The C166S also provides an excellent mechanism to identify and to
process exceptions or error conditions that arise during run-time, so called ’Hardware
Traps’. Hardware traps cause an immediate non-maskable system reaction which is
similar to a standard interrupt service (branching to a dedicated vector table location).
The occurrence of a hardware trap is additionally signified by an individual bit in the
Trap Flag Register (TFR). Except for another higher prioritized trap service being in
progress, a hardware trap will interrupt any current program execution. In turn,
hardware trap services can normally not be interrupted by standard or PEC interrupts.
6. Software Traps: Software interrupts are supported by means of the ’TRAP’ instruction
in combination with an individual trap (interrupt) number.
User’s Manual
2-6
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
System Overview
2.2
The C166S System Resources
The C166S based subsystem provides a number of powerful system resources
designed around the CPU. The combination of CPU and these resources results in the
high performance of the members of this controller family.
2.2.1
Memory Areas
The memory space of the C166S is configured in a Von Neumann architecture which
means that code memory, data memory, registers and I/O ports are organized within the
same linear address space which covers up to 16 MBytes. The entire memory space can
be accessed bytewise or wordwise. Particular portions of the on-chip memory have
additionally been made directly bit addressable.
An up to 3 KByte 16-bit wide internal DPRAM provides fast access to General
Purpose Registers (GPRs), user data (variables) and system stack. The DPRAM may
also be used for code. A unique decoding scheme provides flexible user register banks
in the internal memory while optimizing the remaining RAM for user data.
The CPU has an actual register context consisting of up to 16 wordwide and/or bytewide
GPRs at its disposal, which are physically located within the on-chip RAM area. A
Context Pointer (CP) register determines the base address of the active register bank to
be accessed by the CPU at a time. The number of register banks is only restricted by the
available DPRAM space. For easy parameter passing, a register bank may overlap
others.
A system stack is provided as a storage for temporary data. The system stack is also
located within the on-chip RAM area, and it is accessed by the CPU via the stack pointer
(SP) register. Two separate SFRs, STacK OVerflow (STKOV) and STacK UNderflow
(STKUN), are implicitly compared against the stack pointer value upon each stack
access for the detection of a stack overflow or underflow.
Hardware detection of the selected memory space is placed at the internal memory
decoders and allows the user to specify any address directly or indirectly and obtain the
desired data without using temporary registers or special instructions.
For Special Function Registers 1024 Bytes of the address space are reserved. The
standard Special Function Register area (SFR) uses 512 bytes, while the Extended
Special Function Register area (ESFR) uses the other 512 bytes. (E)SFRs are wordwide
registers which are used for controlling and monitoring functions of the different on-chip
units. Unused (E)SFR addresses are reserved for future members of the C166 family
with enhanced functionality.
An optional Local Memory is provided for both code and data storage. This memory
area is connected to the CPU via a 32-bit-wide local memory bus. Program execution
from Local Memory is the fastest of all possible alternatives.
The type of the on-chip Local Memory (Flash/ROM/SRAM/DRAM/none) depends on the
chosen derivative.
User’s Manual
2-7
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
System Overview
2.2.2
External Bus Interface
In order to meet the needs of designs where more memory is required than is provided
on chip, up to 16 MBytes of external RAM and/or ROM can be connected to the
microcontroller via its external bus interface. The integrated Bus Controller (BC) allows
to access external memory and/or peripheral resources in a very flexible way.
It can be programmed either to Single Chip Mode when no external memory is required,
or to one of four different external memory access modes, which are as follows:
–
–
–
–
16-/18-/20-/24-bit Addresses,
16-/18-/20-/24-bit Addresses,
16-/18-/20-/24-bit Addresses,
16-/18-/20-/24-bit Addresses,
16-bit Data,
16-bit Data,
8-bit Data,
8-bit Data,
Demultiplexed
Multiplexed
Multiplexed
Demultiplexed
In the demultiplexed bus modes, addresses are output on PORT1 and data is input/
output on PORT0. In the multiplexed bus modes both addresses and data use PORT0
for input/output.
Important timing characteristics of the external bus interface (Memory Cycle Time,
Memory Tri-State Time, Length of ALE, Read Write Delay CS and WR) have been made
programmable to allow the user the adaptation of a wide range of different types of
memories. In addition, different address ranges may be accessed with different bus
characteristics. Up to 5 external CS signals can be generated in order to save external
glue logic. Access to very slow memories is supported via a particular ‘Ready’ function.
For applications which require less than 16 MBytes of external memory space, this
address space can be restricted to 1MByte, 256 kByte or 64 kByte. In this case Port4
outputs four, two or no address (segment) lines at all. It outputs all 8 address, if an
address space of 16 MByte is used.
The on-chip Internal Bus Interface is an internal representation of the external bus and
allows to access integrated application-specific peripherals/modules in the same way as
external components. It provides a defined interface for these customized peripherals.
2.2.3
The On-chip Peripheral Blocks
The C166 Family clearly separates peripherals from the core. This structure permits the
maximum number of operations to be performed in parallel and allows peripherals to be
added or deleted from family members without modifications to the core. These built in
peripherals either allow the CPU to interface with the external world, or provide functions
on-chip that otherwise were to be added externally in the respective system. Each
functional block processes data independently and communicates information over
common buses. Individually selected clock signals are generated for each peripheral.
User’s Manual
2-8
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
System Overview
Peripheral Interfaces
The on-chip peripherals generally have two different types of interfaces, an interface to
the CPU and an interface to external hardware. Communication between CPU and
peripherals is performed through Special Function Registers (SFRs) and interrupts.
Each peripheral contains a set of Special Function Registers (SFRs), which control the
functionality of the peripheral and temporarily store intermediate data results. These
SFRs are located either within the standard SFR area (00’FE00H-00’FFFFH) or within
the extended ESFR area (00’F000H-00’F1FFH). Each peripheral has an associated set
of status flags.
Interrupt requests are generated by the peripherals based on specific events which
occur during their operation (e.g. operation complete, error, etc.).
For interfacing with external hardware, specific pins of the parallel ports are used, when
an input or output function has been selected for a peripheral. During this time, the port
pins are controlled by the peripheral (when used as outputs) or by the external hardware
which controls the peripheral (when used as inputs). This is called the 'alternate (input
or output) function' of a port pin, in contrast to its function as a general purpose IO pin.
Peripheral Timing
Internal operation of CPU and peripherals is based on the CPU clock (ICPU). The on-chip
oscillator derives the CPU clock from the crystal or from the external clock signal. The
clock signal (IPDBUS+) which is gated to the peripherals is independent from the clock
signal which feeds the CPU. During Idle mode the CPU’s clock is stopped while the
peripherals continue their operation. Peripheral SFRs may be accessed by the CPU
once per state. When an SFR is written to by software in the same state where it is also
to be modified by the peripheral, the software write operation has priority.
2.2.3.1
Asynchronous / Synchronous Serial Channel (ASC0)
Serial communication with other microcontrollers, processors, terminals or external
peripheral components is provided by a Asynchronous / Synchronous Serial Channel.
The ASC0 supports full-duplex asynchronous communication up to 3.125 MBaud and
half-duplex synchronous communication up to 6.25 MBaud (referred to a PDBUS+ clock
of 50 MHz).
A versatile baud rate generator allows to set up all standard baud rates without
subsystem clock tuning. For transmission, reception, and erroneous reception three
separate interrupt requests are provided.
In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by
a start bit and terminated by one or two stop bits. For multiprocessor communication, a
mechanism to distinguish address from data bytes has been included (8-bit data + wake
up bit mode).
User’s Manual
2-9
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
System Overview
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a
shift clock which is generated by the ASC0.
A loop back option is available for testing purposes.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. A parity bit can automatically be generated on
transmission or be checked on reception. Framing error detection allows to recognize
data frames with missing stop bits. An overrun error will be generated, if the last
character received has not been read out of the receive buffer register at the time the
reception of a new character is complete.
2.2.3.2
High Speed Synchronous Serial Channel (SSC0)
Serial communication with other microcontrollers, processors, terminals or external
peripheral components is provided by a High-Speed Synchronous Serial Channel.
The SSC0 allows full duplex synchronous communication up to 25 MBaud in master
mode and 12.5 MBaud in slave mode (referred to a PDBUS+ clock of 50 MHz).
A dedicated baud rate generator allows to set up all standard baud rates without
subsystem clock tuning. For transmission, reception, and erroneous reception three
separate interrupt requests are provided.
The SSC0 transmits or receives characters of 2...16 bits length synchronously to a shift
clock which can be generated by the SSC0 (master mode) or by an external master
(slave mode). The SSC0 can start shifting with LSB or with MSB. Fully SPI functionality
is supported. A loop back option is available for testing purposes.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. A parity bit can automatically be generated on
transmission or be checked on reception. Framing error detection allows to recognize
data frames with missing stop bits. An overrun error will be generated, if the last
character received has not been read out of the receive buffer register at the time the
reception of a new character is complete.
2.2.3.3
General Purpose Timer Unit (GPT12E)
The General Purpose Timer Unit (GPT12E) represents very flexible multifunctional timer
structures which may be used for timing, event counting, pulse width measurement,
pulse generation, frequency multiplication, and other purposes. They incorporate five
16-bit timers that are grouped into the two timer blocks GPT1 and GPT2. Each timer in
each block may operate independently in a number of different modes such as gated
timer or counter mode, or may be concatenated with another timer of the same block.
Block 1 contains 3 timers/counters with a maximum resolution of fPDBUS+/4. The auxiliary
timers of GPT1 may optionally be configured as reload or capture registers for the core
timer.
User’s Manual
2-10
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
System Overview
Block 2 contains 2 timers/counters with a maximum resolution of fPDBUS+/2. An
additional CAPREL register supports capture and reload operation with extended
functionality.
The following enumeration summarizes all features to be supported:
• Timer Block 1:
– fPDBUS+/4 maximum resolution
– 3 independent timers/counters.
– Timers/counters can be concatenated.
– 4 operating modes (timer, gated timer, counter, incremental).
– Separate interrupt request lines.
• Timer Block 2:
– fPDBUS+/2 maximum resolution
– 2 independent timers/counters.
– Timers/counters can be concatenated.
– 3 operating modes (timer, gated timer, counter).
– Extended capture/reload functions via 16-bit Capture/Reload register CAPREL.
– Separate interrupt request lines.
2.2.4
Parallel Ports (PPorts)
The C166S V1 SubS R1 provides up to 48 I/O lines which are organized into four input/
output ports. All port lines are bit-addressable and individually (bit-wise) programmable
as inputs or outputs via direction registers. The output driver is disabled when an I/O line
is configured as input. This allows true bidirectional ports which are switched to high
impedance state when configured as inputs.
Further features like output driver control, input characteristic selection, temperature
compensation and output mode selection (open drain or push/pull mode) are not
supported by the subsystem´s port module. However, these features can be easily
added by the product logic, because they are controlling the PADs directly and have no
influence on the port module.
The output drivers´ enable signals are switched asynchronously to inactive level as soon
as a subsystem reset occurs. In this case all pins are configured as inputs.
Most port lines have programmable alternate input or output functions associated with
them.
PORT0 and PORT1 may be used as address and data lines when accessing external
memory, while Port 4 outputs the additional segment address bits A23/19/17...A16 in
applications where segmentation is enabled to access more than 64 kBytes of memory.
Port 6 provides optional bus arbitration signals and chip select signals.
All port lines that are not used for these alternate functions may be used as general
purpose IO lines.
User’s Manual
2-11
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
System Overview
2.2.5
Periodic Wakeup from Idle or Sleep Mode
Periodic wakeup from Idle mode or from Sleep mode combines the drastically reduced
power consumption in Idle/Sleep mode (in conjunction with the additional power
management features) with a high level of system availability. External signals and
events can be scanned (at a lower rate) by periodically activating the CPU and selected
peripherals which then return to powersave mode after a short time. This greatly reduces
the system’s average power consumption. Idle/Sleep mode can also be terminated by
external interrupt signals.
2.2.6
OCDS and JTAG
The On-Chip Debug Support (OCDS) provides facilities to the debugger in order to
emulate resources and assists in application program debug. The main features are:
– real time emulation
– extended trigger capability including: instruction pointer events, data events on
address and/or value, external inputs, counters, chaining of events, timers, etc....
– software break support
– break and “break before make” (on IP events only)
– simple monitor mode or JTAG based debugging through instruction injection
The C166S OCDS is controlled by the debugger1) through a set of registers accessible
from the JTAG interface. The OCDS also receives informations (such as IP, data, status)
from the core for monitoring the activity and generating triggers. Finally, the OCDS
interacts with the core through a break interface to suspend program execution, and an
injection interface to allow execution of OCDS generated instructions.
2.2.7
Core Control Block (CCB)
The Core Control Block supports all central control tasks and all subsystem specific
features. The following typical sub-modules are implemented in this unit:
Reset Control (RC)
The reset function is controlled by the reset control unit. The reset block resets the
subsystem itself and provides three reset outputs to reset the complete c166S based
system according to the reset source.
• Hardware Reset:
The system enters the reset state immediately (asynchronous to its clock).
• Software Reset (synchronous to the CPU clock)
• Watchdog Timer Reset (synchronous to the CPU clock)
1)
Debugger refers to the tool connected to the emulator, and more specifically to the OCDS via the JTAG and
which manages the emulation/debugging task.
User’s Manual
2-12
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
System Overview
Power Saving Control (PSC)
The idle mode, and the power down mode mode are supported by the power saving
control block. Periodic wakeup from Idle mode combines the drastically reduced power
consumption in Idle mode (in conjunction with the additional power management
features) with a high level of system availability. External signals and events can be
scanned (at a lower rate) by periodically activating the CPU and selected peripherals
which then return to powersave mode after a short time. This greatly reduces the
system’s average power consumption.
Clock Enable Generator (CEG)
The clock enable generator module generates the clock enable signals used by the
different clock gates of the subsystem. These clock gates are used for the different clock
domains:
• CPU Clock
• Negative CPU Clock
• Peripheral Clock (PDBUS+ clock)
The CPU clock and the negative CPU clock shows the same frequency. However, both
clocks have a phase shift of 180°. This behavior is used for running the EBC protocol
state machine on two clock edges. Also the protocol of the local memory bus LM66-Bus
is based on two clock edges and needs this two clock domains.
The peripheral bus clock is limited to 50 MHz. For not limiting the core to this frequency
the peripherals are decoupled from the CPU by their own clock domain. The frequency
of the peripheral clock domain is either equal to or half of the CPU clock domain.
For generating all this enable signals, the clock enable generator needs to be supplied
by the double frequency of the CPU.
Watchdog Timer (WDT)
The watchdog timer represents one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning. However, the watchdog timer
can only detect long term malfunctioning.
The watchdog timer is enabled automatically by setting its enable control line. It is
recommended that any product enables the watchdog timer after internal chip
initialization. The watchdog timer can only be disabled by software in the time interval
until the EINIT (end of initialization) instruction has been executed. Thus, the application
startup code is always monitored. The software has to be designed to service the
watchdog timer before it overflows. If, due to hardware or software related failures, the
software fails to do so, the watchdog timer overflows and generates either an internal
subsystem reset, which is indicated on the subsystem boundary (general signals
interface) for further product related actions, or triggers an interrupt. Which action will be
triggered depends on a new control bit within the WDTCON register.
User’s Manual
2-13
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
System Overview
The Watchdog Timer is a 16-bit timer, which counts the PDBUS+ clock divided either by
2, 4, 128 or 256. The high byte of the Watchdog Timer register can be set to a predefined
reload value (stored in WDTREL) in order to allow further variation of the monitored time
interval. Each time it is serviced by the application software, the high byte of the
Watchdog Timer is reloaded. Thus, time intervals between 10 µs and 336 ms (default
after reset) can be monitored (referred to a PDBUS+ clock of 50 MHz).
2.2.8
Clock Generation Unit (CGU)
The C166S clock generation unit generates the system clock based on an oscillator or
crystal input. A programmable on-chip PLL adds a high flexibility on clock generation to
the C166S.
2.2.9
On-chip Bootstrap Loader.
An on-chip bootstrap loader allows to move the start code into internal memories via the
serial or other interfaces.
User’s Manual
2-14
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3
Central Processing Unit
The C166S Central Processing Unit (CPU) represents the synthesizable generation of
the well-known C166 core family. It has many powerful enhancements while remaining
compatible with the C166 family. The new architecture offers a high-performance CPU;
fast and efficient access to different kinds of memories; and efficient integration with
peripheral units.
.
CSP
IP
TFR
4-Stage
Pipeline
DPRAM
up to 3KByte
Instruction Fetch and Injection/Exception Handler
Division Unit Bit-Mask-Gen.
Multiply Unit
Barrel-Shifter
MDC
PSW
MDH
Zeros
+/-
DPP0
DPP1
DPP2
DPP3
SPSEG
SP
STKOV
STKUN
address
R15
R14
R15
R14
GPRs
MDL
Ones
GPRs
+/-
ALU
ADU
R1
R0
Register Bank
CPU
Figure 3-1
CP
R1
R0
data in
data out
CPU architecture
The new core architecture of the C166S results in higher CPU clock frequencies
compared to the C166 full custom cores.
C166S has 5 main units that are listed below. All these units have been optimized to
achieve maximum performance and flexibility.
• High Performance Instruction Fetch Unit (IFU)
– High bandwidth fetch interface
– Instruction FIFO (First In First Out Buffer)
– High-performance branch-, call-, and loop-processing with instruction flow
prediction
• Injection/Exception Handler
– Handling of interrupt requests
– Handling of hardware failures
• Instruction PIPeline (IPIP)
User’s Manual
3-1
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
– 4-stage execution pipeline
7. Address and Data Unit (ADU)
– 16-bit arithmetic unit for address generation
8. Arithmetic and Logic Unit (ALU)
– 8-bit and 16-bit arithmetic unit
– 16-bit barrel shifter
– Multiplication and division unit
– 8-bit and 16-bit logic unit
– Bit-manipulation unit
User’s Manual
3-2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.1
Register Description Format
The C166S contains a set of Special-Function Registers (SFRs) and Extended SpecialFunction Registers (ESFRs) that are described in the respective chapter of this manual.
The example below shows how to interpret the format and notation that are used to
describe SFRs and ESFRs.
A word register looks like this:
REG_NAME
Short Description
SFR/ESFR(A16H,A8H)
15
14
13
12
11
10
0
0
0
0
0
0
r
r
r
r
r
r
9
8
7
6
Reset value: *****H
5
4
3
2
1
0
bitfield
A
0
0
bit
C
bit
B
bit
A
rwh
r
r
rw
rw
rwh
A byte register looks like this:
REG_NAME
Short Description
7
SFR/ESFR(A16H,A8H)
6
5
4
Reset value: **H
3
2
1
0
0
bitfield
A
0
bit
C
bit
B
bit
A
r
rwh
r
rw
rw
rwh
Field
Bits
Type Description
bitfieldX
[m:n]
type
Description
value Function off(Default)
value Enable Function 1
...
...
bitX
[n]
type
Description
0
Function off(Default)
1
Enable Function
Elements:
REG_NAME
bitX
bitfieldX
A16 / A8
SFR/ESFR
Name of this register
Name of bit
Name of bitfield
Long 16-bit address / Short 8-bit address
Register space (SFR or ESFR Register)
(* *) * *
Register contents after reset
0/1
: defined value
User’s Manual
3-3
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
U
Y
: unchanged [undefined (X) after power up]
: defined by reset configuration
[n]
[m:n]
n
n
m
: bit number of bit
: bit number of first bit of the bitfield
: bit number of last bit of the bitfield
type
r
w
h
: readable by software
: writable by software
: writable by hardware
value
0/1
X
0
: defined value,
: undefined,
: reserved for future purpose, read access delivers ’0’,
must not be set to 1
User’s Manual
3-4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.2
CPU Special-Function Registers
The core CPU requires a set of CPU Special-Function Registers (CSFRs) to maintain
the system state information, to control system and bus configuration, and to manage
code memory segmentation and data memory paging. The CPU also uses CSFRs to
access the General-Purpose Registers (GPRs) and the System Stack, to supply the ALU
with register-addressable constants, and to support multiply and divide ALU operations.
The access mechanism for these CSFRs in the CPU core is identical to the access
mechanism for any other SFR. Since all SFRs can be controlled by any instruction that
is capable of addressing the SFR/CSFR memory space, there is no need for special
system control instructions.
However, to ensure proper processor operations, certain restrictions on the user access
to some CSFRs must be applied. For example, the Instruction Pointer (IP) and Code
Segment Pointer (CSP) registers cannot be accessed directly at all. They can only be
changed indirectly via branch instructions.
The Program Status Word (PSW), Stack Pointer (SP), and Multiply/Divide Control
Register (MDC) registers can be modified explicitly by the programmer, and implicitly by
the CPU during normal instruction processing.
Note: Note that any explicit write request (via software) to a (C)SFR supersedes a
simultaneous modification by hardware of the same register.
Note: All (C)SFRs may be accessed word-wise, or byte-wise (some of them even
bitwise). Reading bytes from word (C)SFRs is a non-critical operation. Any write
operation to a single byte of an (C)SFR clears the non-addressed complementary
byte within the specified (C)SFR.
Non-implemented (reserved) (C)SFR-Bits cannot be modified, and will always
supply a read value of 0. Non-implemented (C)SFR will always supply a read
value of FFFFH.
Programming Hints
Access to SFRs
All SFRs reside in dedicated page of the memory space. The following addressing
mechanisms allow to access the (C)SFRs:
• indirect or direct addressing with 16-bit (mem) addresses must guarantee that the
used data page pointer (DPP0...DPP3) selects data page 3.
• accesses via the Peripheral Event Controller (PEC) use the SRCPx and DSTPx
pointers instead of the data page pointers.
• short 8-bit (reg) addresses to the standard SFR area do not use the data page
pointers but directly access the registers within this 512 Byte area.
• short 8-bit (reg) addresses to the extended ESFR area require switching to the 512
Byte extended SFR area. This is done via the EXTension instructions EXTR,
EXTP(R), EXTS(R).
User’s Manual
3-5
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
Byte write operations to word wide SFRs via indirect or direct 16-bit (mem) addressing
or byte transfers via the PEC force zeros in the non-addressed byte. Byte write
operations via short 8-bit (reg) addressing can only access the low byte of an SFR and
force zeros in the high byte. It is therefore recommended, to use the bit field instructions
(BFLDL and BFLDH) to write to any number of bits in either byte of an SFR without
disturbing the non-addressed byte and the unselected bits.
Reserved Bits
Some of the bits which are contained in the C166S’s SFRs are marked as Reserved.
User software should never write 1s to reserved bits. These bits are currently not
implemented and may be used in future products to invoke new functions. In this case,
the active state for these functions will be 1, and the inactive state will be 0. Therefore
writing only 0s to reserved locations provides portability of the current software to future
devices. After read accesses reserved bits should be ignored or masked out.
User’s Manual
3-6
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.3
Instruction Fetch and Program Flow Control
The C166S can fetch on average one 32-bit or two 16-bit instructions via the 32-bit wide
Local Memory Bus (LM-Bus) every machine cycle (which equals two clock cycles T1 and
T2) to provide a continuous instruction flow. The instructions can be fetched via this new
internal LM-Bus from the internal local memories (ROM, FLASH, OTP, SRAM, DRAM)
every clock cycle. A waitstate mechanism allows the CPU to adapt to different kind of
memories. For example, this mechanism can be used to:
• Access slower memories
• Generate a power ramp up phase for flash modules
• Stall a DRAM access during the refresh cycles.
Note: Additionally, the LM-Bus provides 16-bit read and write data accesses with and
without waitstates to the internal local memory. Furthermore, read protection is
provided by the CPU to protect the internal local memories against illegal data
accesses.
3.3.1
Branch Target Addressing Modes
The target address and the segment of jump or call instructions can be specified by
several addressing modes. The IP register may be updated using relative, absolute, or
indirect modes. The CSP register can be updated only by using an absolute value. A
special mode is provided to address the interrupt and trap jump vector table, which
resides in the lowest portion of the code segment 0.
Table 3-1
Branch Target Addressing Modes
Mnemonic Target Address
Target Segment
Valid Address Range
caddr
(IP)
= caddr
-
caddr = 0000H...FFFEH
rel
(IP)
(IP)
= (IP) + 2*rel
= (IP) + 2*(rel+1)
-
rel
rel
[Rw]
(IP)
= (Rw)
-
Rw w = 0...15
seg
-
(CSP) = seg
seg
#trap7
(IP)
(CSP) = 0000H
trap7 = 00H...7FH
= 0000H + 4*trap7
= 00H...7FH
= 80H...FFH
= 0...255(3)
caddr:
Specifies an absolute 16-bit code address within the current segment.
Branches MAY NOT be taken to odd code addresses. Therefore, the least
significant bit of caddr must always contain a 0 or a hardware trap will occur.
rel:
This mnemonic represents an 8-bit signed word offset address relative to the
current IP contents, which point to the instruction after the branch instruction.
Depending on the offset address range, both forward (rel= 00H to 7FH) and
backward (rel= 80H to FFH) branches are possible. The branch instruction
itself is repeatedly executed, when rel = -1 (FFH) for a word-sized branch
User’s Manual
3-7
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
instruction, or rel = -2 (FEH) for a double-word-sized branch instruction.
[Rw]:
In this case, the 16-bit branch target instruction address is determined indirectly by the contents of a word GPR. In contrast to indirect data addresses,
indirectly-specified code addresses are NOT calculated via additional pointer
registers (eg. DPP registers). Branches MAY NOT be taken to odd code
addresses. Therefore, the least significant bit of the address pointer GPR
must always contain a 0 or a hardware trap would occur.
seg:
Specifies an absolute code segment number. The C166S supports 256 different code segments, so only the 8 lower bits (respectively) of the ’seg’ operand
value are used to update the CSP register.
#trap7: Specifies a particular interrupt or trap number for branching to the corresponding interrupt or trap service routine via a jump vector table. Trap numbers from
00H to 7FH can be specified to access any double-word code location within
the address range 00’0000H-00’01FCH in code segment 0 (i.e., the interrupt
jump vector table).
For the association of trap numbers with the corresponding interrupt or trap
sources, please refer to Section 3.4 “Interrupt and Trap Functions”.
User’s Manual
3-8
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.3.2
Sequential and Non-Sequential Instruction Flow
Since passing through one pipeline stage takes at least one machine cycle (which
equals two clock cycles T1 and T2), any isolated instruction takes at least four machine
cycles to be completed. Pipelining, however, allows parallel (i.e., simultaneous)
processing of up to four instructions. Therefore, most instructions will seem to be
processed during one machine cycle as soon as the pipeline has been filled once after
reset.
Pipelining increases the average instruction throughput. In this manual, any execution
time specification always refers to the average instruction execution time due to
pipelined parallel processing.
The execution time of a sequential and non-sequential instruction flow is mainly given by
the instruction fetch from different kind of memories (number of waitstates).
The following pipeline diagram (Table 3-2) shows the continuous execution of
instruction under the assumption of a fast Local Memory (0/1 waitstate).
Table 3-2
Sequential instruction execution (local memory, 0/1 waitstate)
Clock Cycle
T1
FETCH
In
In+1
In+2
In+3
In+4
In+6
DECODE
In-1
In
In+1
In+2
In+3
In+4
EXECUTE
In-2
In-1
In
In+1
In+2
In+3
WRITE BACK
In-3
In-2
In-1
In
In+1
In+2
Machine Cycle
Tm
Tm+1
Tm+2
Tm+3
Tm+4
Tm+5
T2
T1
T2
T1
T2
T1
T2
T1
T2
T1
T2
The fetch stage fetches instructions from the Local Memory (LM) via the 32-bit LM-Bus.
If 16-bit instructions are fetched from the LM-Bus, instructions can be buffered in the 3word FIFO. The fetch stage always prefetches instructions. If the buffer is filled with
instructions, LM-Bus accesses are stopped until the fetched instructions can be loaded
into the buffer again.
User’s Manual
3-9
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
Table 3-3 shows the standard unconditional branch (branch taken) instruction pipeline,
assuming a fast local memory (0/1 waitstates)..
Table 3-3
Unconditional branches (LM-Bus, 0/1 waitstate)
T1
Clock Cycle
T2
T1
T2
T1
T2
LM-Address
Ia_t
LM-Data 32bit
Id_t
FETCH
In
T1
T2
T1
T2
T1
T2
Id_t
In+1==
It
It+1
It+2
branch
DECODE
In-1
In
In+1==
-
It
It+1
branch
EXECUTE
In-2
In-1
In
In+1==
branch
-
It
WRITE BACK
In-3
In-2
In-1
In
In+1==
-
branch
Machine Cycle
Tm
Tm+1
Tm+2
Tm+3
Tm+4
Tm+5
In case of a branch to a 32-bit target instruction, which is not aligned to a 32-bit address,
one additional machine cycle (T1,T2) is required.
Table 3-4 shows a standard conditional branch (branch taken) instruction pipeline,
assuming a fast local memory (0/1 waitstates).
Table 3-4
Conditional branches (LM-Bus, 0/1 waitstate)
Clock Cycle
T1
T2
T1
T2
T1
T2
T1
T2
Address
Ia_t
Data 32bit
Id_t
FETCH
In
In+1==
T1
T2
T1
T2
Id_t
(In+2)
It
It+1
branch
DECODE
In-1
In
In+1==
branch
In+1==
branch
-
It
EXECUTE
In-2
In-1
In
In+1==
branch
In+1==
branch
-
WRITE BACK
In-3
In-2
In-1
In
In+1==
In+1==
branch
branch
Tm+4
Tm+5
Machine Cycle
User’s Manual
Tm
Tm+1
Tm+2
3-10
Tm+3
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
Cache Jump Instruction Processing
The C166S incorporates a jump cache to optimize conditional jumps, which are
processed repeatedly within a loop. Whenever a jump on cache is taken, the extra time
to fetch the branch target instruction can be saved and thus the corresponding cache
jump instruction in most cases takes only one (unconditional branch) or two (conditional
branch) machine cycles.
This performance is achieved by the following mechanism: Whenever a cache jump
instruction passes through the decode stage of the pipeline for the first time (and provided
that the jump condition is met), the jump target instruction is fetched as usual, causing a
time delay of one machine cycle. In contrast to standard branch instructions, however, the
target instruction of a cache jump instruction (JMPA, JMPR, JB, JBC, JNB, JNBS) is
additionally stored in the cache after having been fetched.
After each subsequent execution of the same cache jump instruction, the jump target
instruction is not fetched from program memory but taken from the cache and
immediately injected into the fetch/decode stage of the pipeline (see table below
Table 3-5).
A time-saving jump on cache is always taken after the second and any subsequent
occurrences of the same cache jump instruction, unless an instruction that has the
fundamental capability of changing the CSP register contents (JMPS, CALLS, RETS,
TRAP, RETI), or any standard interrupt has been processed during the period of time
between two following occurrences of the same cache jump instruction.
Table 3-5 shows a standard unconditional branch (branch taken and target cached)
instruction pipeline, assuming a fast local memory (0/1 waitstates). .
Table 3-5
Unconditional cached branches (LM-Bus, 0/1 waitstate)
Clock Cycle
T1
T2
T1
T2
T1
T2
LM-Address
Ia_t+1
LM-Data 32bit
Id_t+1
FETCH
In
In+1==
T1
T2
T1
T2
T1
T2
Id_t+1
It
It+1
It+2
It+3
branch
DECODE
In-1
In
In+1==
EXECUTE
In-2
In-1
In
It
It+1
It+2
In+1==
It
It+1
branch
branch
WRITE BACK
In-3
In-2
In-1
In
In+1==
branch
It
Machine Cycle
Tm
Tm+1
Tm+2
Tm+3
Tm+4
Tm+5
User’s Manual
3-11
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
Table 3-6 shows a standard conditional branch (branch taken and target cached)
instruction pipeline, assuming a fast local memory (0/1 waitstates).
Table 3-6
Conditional cached branches (LM-Bus, 0/1 waitstate)
Clock Cycle
T1
T2
T1
T2
T1
T2
T1
T2
Address
Ia_t+1
Data 32bit
Id_t+1
FETCH
In
In+1==
(In+2)
T1
T2
T1
T2
Id_t+1
It
It+1
It+2
branch
DECODE
In-1
In
In+1==
branch
In+1==
branch
It
It+1
EXECUTE
In-2
In-1
In
In+1==
branch
In+1==
branch
It
WRITE BACK
In-3
In-2
In-1
In
In+1==
In+1==
branch
branch
Tm+4
Tm+5
Machine Cycle
User’s Manual
Tm
Tm+1
Tm+2
3-12
Tm+3
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.3.3
ATOMIC and EXTended Instructions
ATOMIC and EXTended instructions (ATOMIC, EXTR, EXTP, EXTS, EXTPR, EXTSR)
disable the standard and PEC interrupts and class A traps until the completion of the next
sequence of instructions. The number of instructions in the sequence may vary from 1
to 4. The instruction number is coded in the 2-bit constant field #irang2 and takes values
from 0 to 3. The EXTended instructions additionally change the addressing mechanism
during this sequence (see instruction description).
ATOMIC and EXTended instructions become active immediately, so no additional NOP
instructions are required. All instructions requiring multiple cycles or hold states for
execution are considered as one instruction. ATOMIC and EXTended instructions can
be used with any instruction type.
Note: If a class B trap interrupt occurs during an ATOMIC or EXTended sequence, then
the sequence is terminated, an interrupt lock is removed, and the standard
condition is restored before the trap routine is executed. The remaining
instructions of the terminated sequence that are executed after returning from the
trap routine will run under standard conditions.
Note: Certain precautions are required when using nested ATOMIC and EXTended
instructions. There is only one counter to control the length of the sequence, i.e.,
issuing an ATOMIC or EXTended instruction within a sequence will reload the
counter with the value of the new instruction.
User’s Manual
3-13
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.3.4
Code Addressing via Code Segment and Instruction Pointer
The C166S provides a total addressable memory space of 16 MBytes. This address
space is arranged as 256 segments of 64 KBytes each. A dedicated 24-bit code address
pointer is used to access the memories for instruction fetches. This pointer has two parts:
An 8-bit Code Segment Pointer (CSP), and a 16-bit offset Instruction Pointer (IP). The
concatenation of the CSP and IP results directly in a correct 24-bit physical memory
address.
Memory organized in segments
255
254
1
0
Figure 3-2
User’s Manual
15
8 7
CSP
0
15
IP
0
FF’0000H
FE’0000H
23
01’0000H
0
16 15
segment
offset
00’0000H
Addressing via the Code Segment- and Instruction Pointers
3-14
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
The Instruction Pointer IP
This register determines the 16-bit intra-segment address of the currently fetched
instruction within the code segment selected by the CSP register. The IP register is not
mapped into the C166S’s address space, and thus it is not directly accessible by the
programmer. The IP can be modified indirectly by return instructions via the stack. The
IP register is updated implicitly by the C166S for branch instructions and after instruction
fetch operations.
IP
Instruction Pointer
15
14
13
12
(----H,--H)
11
10
9
8
7
Reset value: 0000H
6
5
4
3
2
1
0
IP
0
(r)(w)h
r
Field
Bits
Type Description
IP
[15:1]
rwh
Specifies the intra-segment offset from which the
current instruction is to be fetched; IP refers to the
current segment <SEGNR>.
0
[0]
r
IP is always word-aligned
The Code Segment Pointer CSP
This non-bit-addressable register selects the code segment being used at run-time to
access instructions. The lower 8 bits of register CSP select one of up 256 segments of
64 KBytes each, while the higher 8 bits are reserved for future use.
CSP
Code Segment Pointer
1)
Reset value: 000x1)H
SFR(FE08H,04H)
15
14
13
12
11
10
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
SEGNR
r
r
r
r
r
r
r
r
r(w)h
2
1
0
The reset value of the bitfield segnr[1:0] is product-specific. With an alternate boot mode feature, the code
execution can be started at different segments after reset.
Field
Bits
Type Description
SEGNR
[7:0]
rwh
User’s Manual
Specifies the code segment from which the current
instruction is to be fetched
3-15
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
The actual code memory address is generated by direct extension of the 16-bit contents
of the IP register by the lower byte of the CSP register, as shown in Figure 3-2.
There are two modes: Segmented and non-segmented. The mode is selected with the
SGTDIS bit in the SYSCON register. After reset, the segmented mode is selected.
SYSCON
System Control Register
15
14
13
12
11
SFR (FF12H / 89H)
10
9
8
7
5
4
3
2
1
0
ROM SGT ROM SYS SYS SYS SYS SYS SYS SYS SYS SYS SYS
S1
DIS
EN CON9 CON8 CON7 CON6 CON5 CON4 CON3 CON2 CON1 CON0
STKSZ
rw
rw
rw
rwh
rwh
rwh
Field
Bits
Type Description
SGTDIS
11
rw
Note:
6
(Reset value: 0xx0H)
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
Segmentation Disable/Enable Control
0
Segmentation enabled (CSP is saved/restored
during interrupt entry/exit)
1
Segmentation disabled (Only IP is saved/restored)
For summary of the SYSCON register please refer to Section 3.3.5.
Segmented Mode
The CSP register can be only read and may not be written by data operations. The CSP
is modified either directly by the JMPS and CALLS instructions, or indirectly via the stack
by the RETS and RETI instructions. Upon the acceptance of an interrupt or the execution
of a software TRAP instruction, the CSP register is automatically loaded with the
segment address of the vector location.
Non-Segmented Mode
In the non-segmented mode, the CSP is fixed to segment 0. It is no longer possible to
modify the CSP either directly by the JMPS or CALLS instructions, or indirectly via the
stack by the RETS (RETI) instruction. For non-segmented memory mode, the contents
of this register are not significant, because all code accesses are restricted automatically
to segment 0.
Note: When segmentation is disabled, the IP value is used directly as the 16-bit address.
User’s Manual
3-16
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.3.5
The CPU/System Configuration Register SYSCON
This register is used to configure the C166S. It is bit-addressable and provides general
system configuration and control functions. The reset value of register SYSCON
depends on the state of the configuration inputs during reset.
SYSCON
System Control Register
15
14
13
12
11
SFR (FF12H / 89H)
10
9
8
7
6
(Reset value: 0xx0H)
5
4
3
2
1
0
ROM SGTD ROM SYS SYS SYS SYS SYS SYS SYS SYS SYS SYS
S1
IS
EN CON9 CON8 CON7 CON6 CON5 CON4 CON3 CON2 CON1 CON0
STKSZ
rw
rw
rw
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
Field
Bits
Type Description
SYSCON0
.....
SYSCON9
0
....
9
rwh
SYStem CONfiguration
ROMEN
10
rwh
Internal ROM ENable (Set according to pin EA during
reset)
0 Internal local memory disabled: Accesses to the
Local memory area use the external bus
1 Internal local memory enabled
SGTDIS
11
rw
SeGmenTation DISable/enable control
0
Segmentation enabled (CSP is saved/restored
during interrupt entry/exit)
1
Segmentation disabled (Only IP is saved/restored)
ROMS1
12
rw
Internal local memory mapping
0
Internal local memory area mapped to segment 0
(00’0000H...00’7FFFH)
1
Internal Local Memory area mapped to segment 1
(01’0000H...01’7FFFH)
STKSZ
[15:13] rw
System STacK SiZe
Selects the size of the system stack (in the internal
DPRAM) from 32 to 1536 words
Note: The CPU SYSCON bits cannot be changed after execution of the EINIT
instruction.
User’s Manual
3-17
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.4
Interrupt and Exception Execution
An Interrupt and Exception Handler is responsible for managing all system and core
exceptions. There are four different kinds of exceptions that are executed in a similar
way:
•
•
•
•
Interrupts generated by the InTerrupt Controller (ITC)
DMA transfers issued by the Peripheral Event Controller (PEC).
Software traps caused by the TRAP instruction
Hardware traps issued by faults or specific system states
Normal Interrupt Processing
The CPU temporarily suspends the current program execution and branches to an
Interrupt Service Routine (ISR) in order to service an interrupt-requesting device. The
current program status [Instruction Pointer (IP), Processor Status Word (PSW), and in
segmentation mode, the Code Segment Pointer (CSP)] is saved on the internal system
stack. A prioritization scheme with 16 priority levels and with 4/8 sub-levels (4/8 group
levels) specifies the order of multiple interrupt-request handling. The maximum number
of interrupt requests is 112 (configured in steps of 16), wherein the lowest priority level
is reserved for the CPU and cannot be used for interrupts.
Software and Hardware Traps
Trap functions are activated in response to special conditions that occur during the
execution of instructions. A trap can also be caused externally by the Non-Maskable
Interrupt (NMI) pin. Several hardware trap functions are provided for handling erroneous
conditions and exceptions that arise during the program execution. Hardware traps
always have highest priority and cause immediate system reaction. The software trap
function is invoked by the TRAP instruction, which generates a software interrupt for a
specified interrupt vector. For all types of traps, the current program status is saved in
the system stack.
Interrupt Processing via the Peripheral Event Controller
A faster alternative to normal interrupt processing is servicing an interrupt requesting
device by the C166S's integrated PEC. Triggered by an interrupt request, the PEC
performs a single-word or byte data transfer between any two memory locations through
one of up to 16 programmable PEC service channels. During a PEC transfer, the normal
program execution of the CPU is halted. No internal program status information needs
to be saved. The same prioritization scheme is used for PEC service as for normal
interrupt processing.
User’s Manual
3-18
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.4.1
Interrupt System Structure
The C166S provides up to 112 separate interrupt nodes that may be assigned to 128
arbitration priority levels with 16 interrupt priority groups and 4/8 priorities inside each
group. In order to support modular and consistent software design techniques, most
sources of an interrupt or PEC request are supplied with a separate interrupt control
register and interrupt vector. The control register contains an interrupt request flag,
Interrupt Enable (IE) bit, and interrupt priority of the associated source. Each source
request is activated by one specific event, depending on the selected operating mode of
the respective device. In some cases, the multi-source interrupt nodes are incorporated
for efficient use of system resources. These nodes can be activated by several source
requests.
The C166S provides a vectored interrupt system. This system reserves specific vector
locations in the memory space for the reset, trap, and interrupt service functions.
Whenever a request occurs, the CPU branches to the location that is associated with the
respective interrupt source. The reserved vector locations build a jump table in the
C166S’s address space.
The arbitration winner is sent to the CPU together with its priority level and action
request. The CPU triggers the corresponding action, which depends on the required
functionality (normal interrupt, PEC etc.) of the arbitration winner.
An action request will be accepted by the CPU if the requesting source has a higher
priority than the current CPU priority level, and if interrupts are globally enabled. If the
requesting source has a lower (or equal) interrupt level priority, then the requested
interrupt stays pending.
3.4.2
Interrupt Arbitration
The C166S interrupt arbitration system can handle interrupt requests from up to 112
sources. Interrupt requests may be triggered either by the C166S peripherals or by
external inputs. The “End of PEC” interrupt for supporting enhanced PEC functionality is
connected internally to one of the interrupt request lines.
The arbitration process starts by an enabled interrupt request and stays active for as
long as interrupt request is pending. If nothing is pending then the arbitration logic
switches to the idle state to save power.
Each interrupt request line is controlled by its interrupt control register xxIC (here and
below, ’xx’ stands for the mnemonic of the respective interrupt source). An interrupt
request event sets the interrupt request flag to 1 in the corresponding interrupt control
register (bit xxIC.xxIR). The interrupt request can also be triggered by the software if the
program sets the respective interrupt request bit. This feature is used by operating
systems.
If the request bit has been set and this interrupt request is enabled by the IE bit of the
same control register (bit xxIC.xxIE), then an arbitration cycle starts on the next clock
User’s Manual
3-19
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
cycle. However, if an arbitration cycle is currently in progress, the new interrupt request
will be delayed till the next arbitration cycle. If an interrupt request (or PEC request) is
accepted by the core, the respective interrupt request flag is cleared automatically.
All interrupt requests that are pending at the beginning of a new arbitration cycle are
considered simultaneously. Within the arbitration cycle, the arbitration is independent of
the actual request time.
C166S uses a two-stage interrupt prioritization scheme for interrupt arbitration, as shown
in Figure 3-3.
Arbitration
Control
C166S CPU
(Interrupt
Control
Registers)
SRCP0
DSTP0
PECSN0
irq0IC
SRCP1
DSTP1
PECSN1
(PEC
Control
Registers)
SRCP15
DSTP15
PECSN15
PECC0
PEC Pointer
PEC
Control
irq1IC
irq112IC
PECC1
EOPIC
3eripheral
Interrupt
Request
Lines
(vent
PECC15
&ontroller
PECISNC
(PEC)
ILVL
TRAP
irq0
IEN
Arbitr.
irq1
EPEC
Winner
irq2
Arbitration
Internal Priorization
EOP
irq111
irqx
INT irq112
Internal Interrupt/PEC Handler
End of PEC Interrupt (EOPINT) is connected to one of the interrupt request lines.
Therefore, only up to 111 interrupt lines are available for peripheral request
handling.
Figure 3-3
Interrupt Arbitration
The first arbitration stage compares up to 128 priority levels of interrupt request lines.
The priority level of each request consists of Interrupt priority LeVeL (ILVL) and Group
priority LeVeL (GLVL). An interrupt priority level is programmed for each interrupt
request line by the 4-bit bitfield ILVL of the respective xxIC register. The group priority
level is programmed for each interrupt request line by the 2-bit bitfield GLVL and the
group extension bit xxGP of the register xxIC.
Note: All interrupt request sources that are enabled and programmed to the same ILVL
must have different group priority levels. Otherwise, an incorrect interrupt vector
may be generated.
In the second arbitration stage, the priority level of the first-stage winner is compared
with the priority of the current CPU task. An action request will be accepted by the CPU
if the requesting source has a higher priority level than the current CPU priority level (bits
ILVL of the PSW register), and if interrupts are enabled globally by the global IEN flag in
User’s Manual
3-20
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
PSW. The CPU denies all requests in case of a cleared IEN flag. If the requester has a
lower or equal priority level than current CPU task, the request stays pending.
Note: Priority level 0000B is the default level of the CPU. Therefore, a request on ILVL
0000B will be arbitrated, but the CPU will never accept an action request on this
level. However, every enabled interrupt request (including all denied interrupt
requests - also priority level 0000B requests) triggers a CPU wake-up from idle
state independent of the setting of the global interrupt enable bit PSW.IEN.
Note: The first 16 trap numbers are reserved for the CPU traps. The first usable interrupt
trap number starts with 10H . Therefore, the number of interrupt nodes is limited to
112.
All interrupt control registers are organized identically. The lower 8 bits of an interrupt
control register contain the complete interrupt control and status information of the
associated source, which is required during one round of prioritization (arbitration cycle).
The upper 8 bits of the respective register are reserved. All interrupt control registers are
bit-addressable, and all bits can be read or written via software. Therefore, each interrupt
source can be programmed or modified with just one instruction. When reading the
interrupt control registers with instructions that operate with word data types, the upper
8 bits (15...8) will return zeros. Zeros should always be written to these bit positions. The
layout of the interrupt control registers shown below is applicable to all xxIC registers.
xxIC
Interrupt Control Register
bSFR(xxxxH,xxH)
15
14
13
12
11
10
9
0
0
0
0
0
0
0
r
r
r
r
r
r
r
8
7
xxGP xxIR
rw
rwh
6
Reset value: 0000H
5
4
3
2
1
0
xxIE
ILVL
GLVL
rw
rw
rw
Field
Bits
Type Description
xxGP
[8]
rw
Group Priority Extension
Defines the value of high-order group level bit
xxIR1)
[7]
rwh
Interrupt Request Flag
0
No request pending
1
This source has raised an interrupt request
xxIE
[6]
rw
Interrupt Enable Control Bit
(individually enables/disables a specific source)
0
Interrupt request is disabled
1
Interrupt request is enabled
User’s Manual
3-21
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
Field
Bits
Type Description
ILVL
[5:2]
rw
Interrupt Priority Level
Highest priority level
FH
...
...
0H
Lowest priority level
GLVL
[1:0]
rw
Group Priority Level
Defines the internal order for simultaneous
requests of the same priority.
1)
Bit xxIR supports bit-protection
The arbitration scheme allows nesting of up to 15 ISRs of different priority levels (level 0
cannot be used; see note above).
Note: When no interrupt request is active, arbitration is stopped to reduce power
consumption.
3.4.3
Interrupt Vector Table
The C166S has a vectored interrupt system. This system reserves the specific vector
locations in the memory space for the reset, trap, and interrupt service functions.
Whenever a request occurs, the CPU branches to the location that is associated with the
respective interrupt source. This vector position directly identifies the source that caused
the request.
Note: The Class B hardware traps all share the same interrupt vector. The status flags
in the Trap Flag Register (TFR) are used to determine which exception caused the
trap. For details, see Section 3.4.5.2 “Hardware Traps”.
The reserved vector locations are assembled into a jump table that is located in the
C166S’s address space. The jump table contains the appropriate jump instructions that
transfer control to the interrupt or trap service routines. These routines may be located
anywhere within the address space. The vector table is located at the bottom in segment
0 of the address space. Each entry occupies 2 words to provide space for long jumps,
except for the reset vector and the hardware trap vectors, which occupy 4 or 8 words.
Each vector location has an offset address to the segment base address (00’0000H) of
the vector table. The offset address can be calculated easily. The offset is the trap
number shifted by 2.
3.4.4
Interrupt Control Functions in the Processor Status Word
The PSW is divided functionally into 2 parts. The lower byte of the PSW represents the
arithmetic status of the CPU; the upper byte of the PSW controls the interrupt system of
the C166S.
User’s Manual
3-22
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
PSW
Processor Status Word
15
14
13
12
SFR(FF10H,88H)
Reset value: 0000H
11
10
9
8
7
6
5
4
3
2
1
0
ILVL
IEN
PSW
S1
0
0
0
USR0
MUL
IP
E
Z
V
C
N
rwh
rw
rwh
r
r
r
rw
rwh
rwh
rwh
rwh
rwh
rwh
Field
Bits
Type Description
ILVL
[15:12] rwh
CPU Priority Level
0H
Lowest Priority
...
...
FH
Highest Priority
IEN
[11]
Interrupt/PEC Enable Flag (globally)
0
Interrupt/PEC requests are disabled
1
Interrupt/PEC requests are enabled
rw
Note: For a summary of the PSW register, please refer to Section 3.7.6
CPU Priority ILVL defines the current level for the CPU operation, i.e., this bit field
reflects the priority level of the routine currently being executed. When the CPU enters
an ISR, this bitfield is set to the priority level of the request that is being serviced. The
previous PSW is saved in the system stack before entering the ISR. To be serviced, any
interrupt request must have a higher priority level than the current CPU priority level. Any
request of the same or a lower level will not be acknowledged. The current CPU priority
level may be adjusted via software to select interrupt request sources that can be
serviced.
PEC transfers do not really interrupt the CPU, but rather “steal” some CPU cycles, so
PEC services do not influence the ILVL field in the PSW.
Hardware traps set the CPU level to the maximum priority (i.e., 15). Therefore, no
interrupt or PEC requests will be acknowledged while an exception trap service routine
is executed.
The TRAP instruction does not change the CPU level, so software trap service routines
may be interrupted by higher-level requests.
Interrupt ENable flag IEN globally enables or disables interrupts and PEC operations.
When IEN is cleared, no new interrupt requests are accepted by the CPU after IEN was
set to 0. However, the requests that have already entered the pipeline will be completed.
If IEN is set to 1, all interrupt sources are globally enabled.
Note: To generate requests, interrupt sources must be also enabled by the IEN bits in
their associated control registers.
Note: Traps are non-maskable and, therefore, they are not controlled by the IEN bit.
User’s Manual
3-23
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.4.4.1
Saving the Status during Interrupt Service
Before an operating system or ITC can actually service a task switch request or interrupt,
the CPU must save the current task status. The C166S saves the CPU status (PSW)
along with the return address in the system stack. The return address defines the point
where the execution of the interrupted task is to be resumed after returning from the
service routine. This return address is specified by the IP and, in the case of a
segmented memory mode, also by the CSP. Bit SGTDIS in the SYSCON register
defines which mode is used and, therefore, controls how the return address is stored.
In the case of non-segmented mode, the system stack stores the PSW first and then the
IP. In the segmented mode, PSW is followed by CSP and the IP. This order optimizes
the use of the system stack if segmentation is disabled.
The CPU priority field (ILVL in PSW) is updated with the priority of the interrupt request
that is to be serviced, so the CPU now executes on the new level.
.
Status of
Interrupted Task
SP
---1. System Stack before
Interrupt Entry
Figure 3-4
SP
PSW
IP
-2. System Stack after
Interrupt Entry
(Unsegmented)
PSW
CSP
IP
SP
3. System Stack after
Interrupt Entry
(Segmented)
Task Status saved on the System Stack
After accepting an interrupt request, the C166S sends an acknowledgement to the ITC
that the requested interrupt is being serviced. The vector associated with the requesting
source is loaded into the IP and CSP, and the first instruction of the service routine is
fetched. All other CPU resources such as data page pointers and the context pointer are
not affected.
When the CPU returns from the ISR [RETurn from Interrupt (RETI) is executed], the
status information is “popped” from the system stack in reverse order. The status
information contents depend on the SGTDIS bit value.
3.4.4.2
Context Switching
An ISR usually saves all the registers it uses on the stack, and restores them before
returning. The more registers a routine uses, the more time is wasted by saving and
restoring.
User’s Manual
3-24
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
The C166S makes it possible to switch the complete register bank of CPU registers
(GPRs) with a single instruction, so the service routine executes within its own separate
context. The instruction “SCXT CP, #New_Bank” pushes the contents of the Context
Pointer (CP) into the system stack and loads the CP with the immediate value
“New_Bank”. The new CP value sets a new register bank. The service routine may now
use its own registers. This register bank is preserved when the service routine is
terminated, i.e., its contents are available for the next call. Before returning (RETI), the
previous CP is simply popped from the system stack, which returns the registers to the
original register bank.
Note: Resources that are used by the interrupting program must eventually be saved
Pointers (DPP) and the registers of the multiply and divide unit.
Note: The first instruction following the SCXT CP,... instruction must not use a GPR.
User’s Manual
3-25
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.4.5
Traps
3.4.5.1
Software Traps
The TRAP instruction is used to cause a software call to an ISR. The trap number that
is specified in the operand field of the trap instruction determines which vector location
of the vector table will be used.
The TRAP instruction’s effect is similar to that of an interrupt request that uses the same
vector. PSW, CSP (in segmentation mode), and IP are pushed into the system stack and
then a jump is taken to the specified vector location. When a software trap is executed,
the CSP for the trap service routine is loaded with segment address 0. No Interrupt
Request flags are affected by the TRAP instruction. The ISR called by a TRAP
instruction must be terminated with a RETI instruction to ensure correct operation.
Note: The CPU priority level is not modified by the TRAP instruction, so the service
routine is executed with the same priority level as the interrupt task. Therefore, the
service routine entered by the TRAP instruction can be interrupted by other traps
or by higher priority interrupts, other than when triggered by a real hardware event.
3.4.5.2
Hardware Traps
Hardware traps are issued by faults or specific system states that occur during runtime
(not identified at assembly time). The C166S distinguishes eight different hardware trap
functions. When a hardware trap condition has been detected, the CPU branches to the
trap vector location for the respective trap condition. The instruction that caused the trap
event is either completed or canceled before the trap-handling routine is entered.
Hardware traps are not-maskable and always have a higher priority than any other CPU
task. If several hardware trap conditions are detected within the same machine cycle, the
highest-priority trap is serviced. In the case of a hardware trap, the injection unit injects
a TRAP instruction into the pipeline. The TRAP instruction performs the following
actions:
• Push PSW, CSP (in segmented mode) and IP onto the system stack
• Set CPU level in the PSW register to the highest possible priority level, which disables
all interrupts and DMA transfers
• Branch to the trap vector location specified by the trap number of the trap condition
The eight hardware functions of the C166S are divided in two Classes.
Class A traps are:
– External NMIs
– Stack overflow
– Stack underflow
These traps share the same trap priority, but have an individual vector address.
Class B traps are:
User’s Manual
3-26
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
–
–
–
–
–
Undefined opcode
Protection fault
Illegal word operand access
Illegal instruction access
Illegal external bus access
The Class B traps share the same interrupt node and interrupt vector. The bitaddressable Trap Flag Register (TFR) allows a trap service routine to identify the trap
that caused the exception.
The Trap Flag Register TFR
Each trap function is indicated by a separate request flag. When a hardware trap occurs,
the corresponding request flag in register TFR is set to 1.
TFR
Trap Flag Register
SFR(FFACH,D6H)
Reset value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NMI
STK
OF
STK
UF
0
0
0
0
0
UND
OPC
0
0
0
PRT
FLT
ILL
OPA
ILL
INA
ILL
BUS
rwh
rwh
rwh
r
r
r
r
r
rwh
r
r
r
rwh
rwh
rwh
rwh
Field
Bits
Type Description
NMI1)
[15]
rwh
Non-Maskable Interrupt flag
0
No non-maskable interrupt detected
1
Non-maskable interrupt detected
STKOF1)
[14]
rwh
STacK OverFlow flag
0
No stack overflow event detected
1
Stack overflow event detected
STKUF1)
[13]
rwh
STacK UnderFlow flag
0
No stack underflow event detected
1
Stack underflow event detected
UNDOPC1)
[7]
rwh
UNDefined OPCode
0
No undefined opcode event detected
1
Undefined opcode event detected
PRTFLT1)
[3]
rwh
PRoTection FauLT
0
No protection fault event detected
1
Protection fault event detected
User’s Manual
3-27
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
Field
Bits
Type Description
ILLOPA1)
[2]
rwh
ILLegal word OPerand Access
0
No illegal word operand access event
detected
1
Ilegal word operand access event detected
ILLINA1)
[1]
rwh
ILLegal INstruction Access
0
No illegal instruction access detected
1
A branch to an odd address has been
attempt.
ILLBUS
[0]
rwh
ILLegal External BUS Access
0
No illegal external bus access detected
1
An external access has been attempted with
no bus defined.
1)
This bit supports bit protection
Note: The trap service routine must clear the respective trap flag. Otherwise, a new trap
will be requested after exiting the service routine. Setting a trap request flag by
software causes the same effects as if it had been set by hardware.
The reset functions (hardware, software, watchdog) may be also regarded as a type of
trap. Reset functions have the highest trap priority (trap priority IV). The Debug trap has
the second-highest trap priority (trap priority III), followed by the third-highest trap priority
traps, Class A traps (trap priority II), and then by Class B traps (trap priority I). So the
Debug trap can interrupt a Class A and B trap and a Class A trap can interrupt a Class
B trap. The Debug trap is a special kind of interrupt-service channel for debug purposes
whose priority lies between the Class A trap and the reset function. This allows the
debugger to interrupt hardware traps and hardware interrupts
Exception Condition
Trap
Flag
Reset Functions:
Hardware Reset
Software Reset
Watchdog Timer Overflow
Debug Trap
User’s Manual
DEBUG
3-28
Trap
Vector
Trap
Number
Trap
Priority
RESET
RESET
RESET
00H
00H
00H
IV
IV
IV
DEBTRAP
08H
III
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
Exception Condition
Trap
Flag
Trap
Vector
Trap
Number
Trap
Priority
Class A Hardware Traps:
Non-Maskable Interrupt
STacK OverFlow
STacK UnderFlow
SOFTware BReaK
NMI
STKOF
STKUF
SOFTBRK
NMITRAP
STOTRAP
STUTRAP
SBRKTRAP
02H
04H
06H
08H
II.3
II.2
II.1
II.0
Class B Hardware Traps:
UNDefined OPCode
PRoTection FauLT
ILLegal word Operand Access
ILLegal INstruction Access
ILLegal external BUS access
UNDOPC
PRTFLT
ILLOPA
ILLINA
ILLBUS
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
0AH
0AH
0AH
0AH
0AH
I
I
I
I
I
Class A Trap
Class A traps are generated by the high-priority system NMI or by special CPU events
such as a software break, or a stack overflow or underflow event. Class A traps are not
used to indicate hardware failures. After a Class A event, a dedicated service routine is
called to react to the events. Each Class A trap has its own vector location in the vector
table. After finishing the service routine, the remainder of the instruction flow must be
executed correctly. This explains why Class A traps cannot interrupt atomic/extend
sequences.
In case of an atomic/extend sequence, the execution continues until sequence
completion. Upon completion, the IP of the instruction following the last executed one is
pushed onto the stack.
If more than one Class A trap occurs at a same time, they are prioritized internally. The
NMI trap has the highest priority, and the stack underflow trap has the lowest.
Note: When two different Class A traps occur simultaneously, both trap flags are set.
The trap with the higher priority is executed. After return from the service routine,
the IP is popped from the stack and immediately pushed again because of the
other pending Class A trap (unless the second trap flag in TFR has been cleared
by the first trap service routine).
External NMI Trap (NMI)
Whenever a high-to-low transition on the dedicated NMI is detected, the NMI flag in
register TFR is set, and the CPU will enter the NMI trap routine. The IP value pushed on
the system stack is the address of the instruction following the one after which normal
processing was interrupted by the NMI trap.
Note: The NMI is sampled with every CPU clock cycle to detect transitions.
User’s Manual
3-29
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
STacK OverFlow Trap (STKOF)
Whenever the stack pointer SP is decremented to a value less than the value in the stack
overflow register STKOV, the STKOF flag in register TFR is set and the CPU will enter
the stack overflow trap routine. Which IP value will be pushed onto the system stack
depends on which operation caused the decrement of the SP. When an implicit
decrement of the SP is made through a push or call instruction, or upon interrupt or trap
entry, the IP value pushed is the address of the following instruction. When the SP is
decremented by a subtract instruction, the IP value pushed represents the address of
the first or second instruction after the instruction following the subtract instruction.
For recovery from stack overflow, there must be enough excess space on the stack for
saving the current system state (PSW; IP; and, in segmented mode, the CSP) twice.
Otherwise, a system reset should be generated.
STacK UnderFlow Trap (STKUF)
Whenever the stack pointer is incremented to a value greater than the value in the stack
underflow register STKUN, the STKUF flag is set in register TFR and the CPU will enter
the stack underflow trap routine. Again, which IP value will be pushed onto the system
stack depends on which operation caused the increment of the SP. When an implicit
increment of the SP is made through a POP or return instruction, the IP value pushed is
the address of the following instruction. When the SP is incremented by an add
instruction, the pushed IP value represents the address of the first or second instruction
after the instruction following the add instruction.
Class B Trap
Class B traps are generated by unrecoverable hardware failures. In case of hardware
failure, the CPU must immediately start a failure service routine. Class B traps can
interrupt an atomic/extend sequence. After finishing a Class B service routine, the
interrupted instruction flow cannot be restored.
Note: If a Class A trap and a Class B occur simultaneously, both trap flags are set. If
this occurs during execution of an atomic/extend sequence, then the presence of
the Class B trap breaks the protection of atomic/extend operations, and the Class
A trap will be executed immediately without waiting for the sequence completion.
After return from the service routine, the IP is popped from the system stack and
immediately pushed again because of the other pending Class B trap. In this
situation, the interrupted instruction flow cannot be restored.
All Class B traps have the same trap priority (trap priority I). When several Class B traps
are active at the same time, the corresponding flags in the TFR are set, and the trap
service routine is entered. Since all Class B traps have the same vector, the priority of
service of Class B that occur simultaneously is determined by the software in the trap
service routine.
User’s Manual
3-30
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
During the execution of a Class A trap service routine, any Class B trap will not be
serviced until the Class A trap service routine is exited with a RETI instruction. In this
case, the Class B trap condition is stored in the TFR but the IP value of the instruction
that caused this trap will be lost.
UNDefined OPCode Trap (UNDOPC)
When the instruction currently decoded by the CPU does not contain a valid C166S
opcode, the UNDOPC flag is set in the TFR, and the CPU enters the undefined opcode
trap routine. The IP value pushed onto the system stack is the address of the instruction
that caused the trap.
This can be used to emulate unimplemented instructions. The trap service routine can
examine the faulting instruction to decode operands for unimplemented opcodes based
on the stacked IP. In order to resume processing, the stacked IP value must be
incremented by the size of the undefined instruction, which is determined by the user,
before a RETI instruction is executed.
PRoTection FauLT Trap (PRTFLT)
DISWDT, EINIT, IDLE, PWRDN, SRST, and SRVWDT are protected instructions.
Whenever one protected instruction is executed and the protection is broken, the
PRTFLT flag in register TFR is set and the CPU enters the protection fault trap routine.
The IP value pushed onto the system stack for the protection fault trap is the address of
the instruction that caused the trap.
ILLegal word OPerand Access Trap (ILLOPA)
Whenever a word operand read or write access is attempted to an odd byte address, the
ILLOPA flag in register TFR is set, and the CPU enters the illegal word operand access
trap routine. The IP value pushed onto the system stack is the address of the instruction
following the one that caused the trap.
ILLegal INstruction Access Trap (ILLINA)
Whenever a branch is made to an odd byte address, the ILLINA flag in register TFR is
set and the CPU enters the illegal instruction access trap routine. The IP value pushed
onto the system stack is the illegal odd target address of the branch instruction.
ILLegal external BUS access Trap (ILLBUS)
Whenever the CPU requests an external instruction fetch or a data read or a data write,
and no external bus configuration has been specified, the ILLBUS flag in register TFR is
set and the CPU enters the illegal bus access trap routine. The IP value pushed onto the
system stack is the address of the instruction following the one that caused the trap.
User’s Manual
3-31
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.4.6
Peripheral Event Controller
The Peripheral Event Controller (PEC) “decides” which CPU action is required to
manage an interrupt request. It may be either normal interrupt service, or fast data
transfer between two memory locations. The C166S PEC controls up to sixteen1) fast
data transfer channels.
If a normal interrupt is requested, the CPU temporarily suspends the current program
execution and branches to an Interrupt Service Routine (ISR). The current program
status and context must be preserved.
If a PEC channel is selected for servicing an interrupt request, a single word or byte data
transfer between any two memory locations is to be performed. During a PEC transfer,
the normal program execution of the CPU is halted for just 1 machine cycles. No internal
program status information needs to be saved. The PEC transfer is the fastest possible
interrupt response. In many cases, a PEC transfer is sufficient to service the peripheral
request (serial channels, for example).
The PEC channels can perform the following actions:
• Byte or word transfer
• Continuous data transfer
• PEC channel-specific interrupt request upon data transfer completion; or for all
channels a common End of PEC (EOP) interrupt for enhanced handling
• Automatic increment of source or destination pointers
• Channel linking of two PEC channels
Note: PEC transfer is executed if its priority level is higher than current CPU priority level.
1)
The number of PEC channels depends on the configuration of the product. Please refer to the product User
Manual.
User’s Manual
3-32
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.4.6.1
The PEC Source and Destination Pointers
The PEC channels’ source and destination pointers specify the locations between which
the data is to be moved. All pointers are 24 bits wide. The 24-bit source address is stored
in the internal DPRAM location SRCPx (lower 16 bits of address) and in the low byte of
register PECSNx (highest 8 address bits).
PECSNx
SRCSNx
15
DSTSNx
0
8 7
SRCPx
DSTPx
SRCPx
15
DSTPx
0
15
Source Pointer
23
16 15
Segment Address
0
Destination Pointer
0
23
Segment Offset
16 15
Segment Address
0
Segment Offset
'DWD7UDQVIHU
x = 15...0, depending on PEC channel number
Figure 3-5
PEC Pointer Address Handling
The 24-bit destination address is stored in the DPRAM location DSTPx (lower 16 bits of
address) and in the high byte of register PECSNx (highest 8 address bits). Only the lower
16 bits of the PEC address pointers (segment offset) can be modified (incremented) by
the PEC transfer mechanism. The highest 8 bits, which represent the segment number,
are not modified by hardware. Therefore, the PEC pointers may be incremented within
the address space of one segment and may not cross the segment border. If the offset
address pointer has a value of FFFFH in the case of byte transfers (BWT = 1) or FFFEH
in the case of word transfers (BWT = 0), the next increment will lead to an overflow. No
explicit error event is generated by the system in case of address pointer(s) overflow;
therefore, the user must prevent this condition from occurring.
User’s Manual
3-33
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
Note: If a word data transfer is selected for a specific PEC channel (i.e. BWT = 0), the
respective source and destination pointers must both contain a valid word address
that points to an even byte boundary. Otherwise, the Illegal Word Access trap will
be invoked when this channel is used.
SRCPx
PEC Source Pointer
15
14
13
12
DPRAM(H,H)
11
10
9
8
7
Reset value: 0000H
6
5
4
3
2
1
0
SRCPx
rwh
Field
Bits
Type Description
SRCPx
[15:0]
rwh
Source Pointer Address of Channel x
Source Address bits 15-0
DSTPx
PEC Destination Pointer
15
14
13
12
11
DPRAM(H,H)
10
9
8
7
Reset value: 0000H
6
5
4
3
2
1
0
DSTPx
rwh
Field
Bits
Type Description
DSTPx
[15:0]
rwh
Table 3-7
Destination Pointer Address of Channel x
Destination Address bits 15-0
DPRAM Addresses of PEC Source and Destination Pointer
Pointer
Address
Pointer
Address
Pointer
Address
Pointer
Address
DSTP7
00’FCFEH
SRCP7
00’FCFCH
DSTP11
00’FCDEH
SRCP11
00’FCDCH
DSTP6
00’FCFAH
SRCP6
00’FCF8H
DSTP10
00’FCDAH
SRCP10
00’FCD8H
DSTP5
00’FCF6H
SRCP5
00’FCF4H
DSTP9
00’FCD6H
SRCP9
00’FCD4H
DSTP4
00’FCF2H
SRCP4
00’FCF0H
DSTP8
00’FCD2H
SRCP8
00’FCD0H
DSTP3
00’FCEEH
SRCP3
00’FCECH
DSTP15
00’FCCEH
SRCP15
00’FCCCH
DSTP2
00’FCEAH
SRCP2
00’FCE8H
DSTP14
00’FCCAH
SRCP14
00’FCC8H
DSTP1
00’FCE6H
SRCP1
00’FCE4H
DSTP13
00’FCC6H
SRCP13
00’FCC4H
DSTP0
00’FCE2H
SRCP0
00’FCE0H
DSTP12
00’FCC2H
SRCP12
00’FCC0H
User’s Manual
3-34
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
PECSNx
PEC Segment Pointer
15
14
13
12
SFR(H,H)
11
10
9
8
7
Reset value: 0000H
6
5
4
3
DSTSNx
SRCSNx
rw
rw
2
1
0
Field
Bits
Type Description
DSTSNx
[15:8]
rw
Destination Pointer Segment Address of Channel
x
Destination Address bits 23-16
SRCSNx
[7:0]
rw
Source Pointer Segment Address of Channel x
Source Address bits 23-16
User’s Manual
3-35
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.4.6.2
PEC Control Registers
Each PEC channel is controlled by the respective PEC channel Control register (PECCx)
and a set of source and destination pointers (SRCPx, DSTPx and PECSNx), where “x”
stands for the PEC channel number. The PECCx registers control the arbitration priority
level assigned to the PEC channels and specifies the action to be performed.
PECCx
PEC Channel Control Register
13
12
11
10
SFR(H,H)
9
8
7
Reset value: 0000H
15
14
6
5
4
3
PT
EOP
INT
PLEV
CL
INC
BWT
COUNT
rw
rw
rw
rw
rw
rw
rwh
2
1
0
Field
Bits
Type Description
PT
[15]
rw
Transfer Mode1)
0
Short Transfer Mode
1
Long Transfer Mode
EOPINT
[14]
rw
End of PEC Interrupt Selection2)
0
EOP interrupt with the same level as the
PEC transfer is triggered
1
EOP interrupt is serviced by a separate
interrupt node with programmable interrupt level
(EOPIC) and interrupt sharing control register
(PECISNC)
PLEV
[13:12] rw
PEC Level Selection3)
This bitfield controls the PEC channel assignment
to an arbitration priority level.
(see section below)
CL
[11]
rw
Channel Link Control
0
PEC channels work independently
1
Pairs of channels are linked together
INC
[10:9]
rw
Increment Control
(Modification of source and destination pointer
after PEC transfer)
00
No modification
01
Increment of destination pointer DSTPx
by 1 (BWT = 1) or by 2 (BWT = 0)
10
Increment of source pointer SRCPx
by 1 (BWT = 1) or by 2 (BWT = 0)
11
Reserved
User’s Manual
3-36
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
Field
Bits
Type Description
BWT
[8]
rw
Byte / Word Transfer Selection
0
Transfer a word
1
Transfer a byte
COUNT
[7:0]
rwh
PEC Transfer Count4)
Counts PEC transfers and influences the
channel´s action
1)
The long transfer mode is an optional mode. If the product does not support the long transfer mode for this
specific PEC channel, the PT-bit is hardwired to zero. See Section 3.4.6.3 and Section 3.4.6.4
2)
See Section 3.4.6.7
3)
See Section 3.4.6.6
4)
See Section 3.4.6.3
The Byte/Word Transfer bit (BWT) of the PECCx register selects whether a byte or a
word is to be moved during a PEC service cycle, and defines an increment step size for
the pointer(s) to be modified.
The Increment Control Field (INC) of the PECCx register defines when either one or
both of the PEC pointers have to be incremented after the PEC transfer. If the pointers
are not to be modified (INC=00B), the respective channel will always move data from the
same source to the same destination.
User’s Manual
3-37
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.4.6.3
Short Transfer Mode
If the short transfer mode is enabled by the PT flag (PT = 0) in the PEC control register
PECCx, the PEC Transfer Count Field (COUNT) of the PECCx controls directly the
action of the respective PEC channel. The contents of the bitfield COUNT may specify
a certain number of PEC transfers, unlimited transfers, or no PEC service at all.
a) If the PEC transfer counter (COUNT) value is set to 00H, the normal interrupt
requests are processed instead of PEC data transfers, and the corresponding PEC
channel remains idle.
b) Continuous data transfers are selected by setting the bitfield COUNT to FFH. In this
case, COUNT is not decremented by the transfers, and the respective PEC channel
can serve unlimited number of PEC requests until it is modified by the program.
c) If the bitfield COUNT is set to service a specified number of requests by the
respective PEC channel, it is decremented with each PEC transfer, and the request
flag is cleared to indicate that the request has been serviced. When COUNT
reaches 00H it activates the ISR that has the same priority level (EOPINT = 0), or
triggers the EOP ISR with a different priority level (EOPINT = 1). When COUNT is
decremented from 01H to 00H after a data transfer, the request flag will be cleared
if EOPINT is set to 1. If EOPINT is 0, the request flag will not be cleared and another
interrupt request will be generated on the same priority level. The respective PEC
channel remains idle, and the associated ISR is activated instead of PEC transfer,
because COUNT contains the 00H value.
User’s Manual
3-38
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.4.6.4
Long Transfer Mode1)
If the long transfer mode is enabled by the PT flag (PT = 1) in the PEC control register
PECCx, the PEC Transfer Count Field (COUNT2) of the PECXCx register directly
controls the action of the respective PEC channel.
PEC Extended Count Register
PECXC0/2/4/6
15
14
13
12
11
10
SFR (H,H)
9
8
7
(Reset value: 0000H)
6
5
4
3
2
1
0
COUNT2
rwh
Field
Bits
Type Description
COUNT2
[15:0]
rwh
PEC Extended (Long) Transfer Count
PEC transfer count extension (see table below)
The long transfer mode is only available for PEC channels with an even PEC number.
Note: The channel link mode is independent of the long transfer mode. Both modes can
be combined.
Note: The PEC Transfer Count Field (COUNT) of the PECCx register must be set to
zero.
Note: Crossing of segment boundaries is not checked during data transfers with long
transfer count, and is not supported. A wrap around occurs when reaching the
segment boundary .
The contents of the bitfield COUNT2 may specify a certain number of PEC transfers or
no PEC service at all. The 16-bit transfer counter permits servicing up to 65536 byte
transfers or up to 32768 word transfers.
a) If the PEC transfer counter COUNT2 value is set to 0000H , the normal interrupt
requests are processed instead of PEC data transfers, and the corresponding PEC
channel remains idle.
b) If the bitfield COUNT2 is set to service a specified number of requests by the
respective PEC channel, it is decremented with each PEC transfer and the request
flag is cleared to indicate that the request has been serviced. When COUNT2
reaches 0000H, it activates the ISR that has the same priority level (EOPINT = 0),
or triggers the EOP ISR with a different priority level (EOPINT = 1). When COUNT2
is decremented from 0001H to 0000H after a data transfer, the request flag will be
1)
The long transfer mode is an optional mode for PEC channels with an even number. Please refer to the product
User Manual.
User’s Manual
3-39
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
cleared if EOPINT is set to 1. If EOPINT is 0, the request flag will not be cleared
and another interrupt request will be generated on the same priority level. The
respective PEC channel remains idle and the associated interrupt service routine is
activated instead of PEC transfer, because COUNT2 contains the 0000H value.
User’s Manual
3-40
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.4.6.5
Channel Link Mode for Data Chaining
Channel linking, if enabled, links two channels together to serve the data transfer
requests of one peripheral. The whole data transfer (for example a message) is divided
into separately-controlled block transfers. The two PEC channels that are linked together
handle chained block transfers alternately with one another. At the end of a data block
transfer controlled by one PEC channel, the other (linked) PEC channel is started
automatically to continue the transfer with the next data block. Channel linking and data
(block) chaining are supported within pairs of PEC channels (channels 0&1, 2&3, 4&5
etc.). Each data block is controlled by one PEC channel of the channel pair.
Channel linking is enabled if the Channel Link (CL) control bits of both PEC channels
are set to 1 in their PECCx registers . The data transfer of linked channels must always
be started always with the even numbered channel of the channel pair.
If in channel link mode the channel’s data block is completely transferred, the PEC
service request processing is automatically switched to the other PEC channel of the
pair. CL of the previously active PEC channel is then reset.
Every channel toggle is indicated to CPU by means of an EOP interrupt. This makes it
possible to set up multiple buffers for PEC transfers by changing pointer and count
values of one channel while the other channel is active. Inside the EOP interrupt, the
Channel Link Control bit CL must be set again before the channel is reactivated or the
channel link mode is finished.This EOP interrupt is requested, indicated, and enabled in
the respective PEC Interrupt Subnode Control Register (PECISNC or PECXISNC).
Thus, all EOP interrupts are controlled with the one EOP interrupt control register EOPIC
and therefore with the same interrupt priority level. This service request node requests
the CPU in case of one or more pending EOP interrupt requests if the respective enable
control bit(s) are set in the according subnode control register and in the interrupt control
register EOPIC.
If CL of the previous PEC channel is set to zero and the count field (COUNT=0 or
COUNT2=0, dependent on the mode) of the active channel is zero as well, the whole
data transfer is finished and the channel link interrupt represents a termination interrupt,
the End of PEC interrupt.
User’s Manual
3-41
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
The channel link feature is supported for all PEC channels, including the new PEC
channels 8-15. The following table shows the channels that can be linked together and
the channel numbers required to start transfers via linked channels.
Table 3-8
PEC Channels That Can Be Linked Together
Linked PEC Channels
PEC
Channel
A
PEC
Channel
B
Linked
PEC
Start
Channel
Linked PEC Channels
PEC
Channel
A
PEC
Channel
B
Linked
PEC
Start
Channel
channel 0
channel 1
channel 0
channel 8
channel 9
channel 8
channel 2
channel 3
channel 2
channel 10 channel 11 channel 10
channel 4
channel 5
channel 4
channel 12 channel 13 channel 12
channel 6
channel 7
channel 6
channel 14 channel 15 channel 14
The two PEC control registers of a pair are linked to one interrupt control register,
whereby in this IC register only the even-numbered PEC channel is indicated with the
priority/group bits.
User’s Manual
3-42
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.4.6.6
PEC Channels Assignment and Arbitration
The PEC channels can be assigned to arbitration priority levels. All requests with
interrupt priority levels 8 to 15 can be associated with the PEC functionality (up to a total
of sixteen PEC channels). The following formula shows how to program the bitfield
PECCx.PLEV to set up a link to a certain interrupt priority level and a group priority level.
PEC channel: x = (x.3,x.2,x.1,x.0)
linked to
Interrupt priority level: (1, ~PLEV.1, ~PLEV.0, x.2)
Group priority level: (x.3, x.1, x.0)
[3-1]
The following table lists all possible combinations:
Table 3-9
PEC interrupt level control with PLEV bits in PECCx registers
Priority Level
PEC Channel Selection (x)
Interrupt Level
ILVL3-0
Group Level
xxGP, GLVL1,0
PLEV[1,0]=
PLEV[1,0] =
00
01
10
11
15
7-4
15-12
-
-
-
15
3-0
7-4
-
-
-
14
7-4
11-8
-
-
-
14
3-0
3-0
-
-
-
13
7-4
-
15-12
-
-
13
3-0
-
7-4
-
-
12
7-4
-
11-8
-
-
12
3-0
-
3-0
-
-
11
7-4
-
-
15-12
-
11
3-0
-
-
7-4
-
10
7-4
-
-
11-8
-
10
3-0
-
-
3-0
-
9
7-4
-
-
-
15-12
9
3-0
-
-
-
7-4
8
7-4
-
-
-
11-8
8
3-0
-
-
-
3-0
PLEV[1,0] = PLEV[1,0] =
All interrupt requests that are not assigned to a PEC channel go directly to the interrupt
handler.
User’s Manual
3-43
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.4.6.7
Programmable End of PEC Interrupt Level
The programmable EOP interrupt supports PEC transfers, which need a high priority
level for the transfer request, and which do not need the same priority level for the
termination interrupt. One dedicated service request node with a programmable interrupt
level is shared among all PEC channels. This service request node is controlled by the
EOPIC interrupt control register.
EOPIC
Interrupt Control Register
1)
bSFR(xxxxH,xxH)1)
15
14
13
12
11
10
9
8
7
0
0
0
0
0
0
0
xxGP
r
r
r
r
r
r
r
rw
6
Reset value: 0000H
5
4
EOP EOP
IR
IE
rwh
rw
3
2
1
0
ILVL
GLVL
rw
rw
The EOPIC register is assigned to one of the 64 interrupt control registers. The assignment is product specific.
Field
Bits
Type Description
xxGP
[8]
rw
Group Priority Extension
Defines the value of high order group level bit
EOPIR1)
[7]
rwh
Interrupt Request Flag
0
No request pending
1
his source has raised an interrupt request
EOPIE
[6]
rw
Interrupt Enable Control Bit
0
Interrupt request is disabled
1
Interrupt request is enabled
ILVL
[5:2]
rw
Interrupt Priority Level
FH
Highest priority level
...
...
0H
Lowest priority level
GLVL
[1:0]
rw
Group Priority Level
3H
Highest priority level
...
...
0H
Lowest priority leve
1)
Bit xxIR supports bit-protection
The Register PECISNC and PECXISN contain flags of the EOP interrupt node. This
node is used when the enhanced End of PEC interrupt feature is invoked and control bit
EOPINT is set to 1 in the corresponding PECCx.
User’s Manual
3-44
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
PECISNC
PEC Interrupt Sub Node Control
15
14
13
12
11
10
SFR(H,H)
9
8
7
Reset value: 0000H
6
5
4
3
2
1
0
C7IR C7IE C6IR C6IE C5IR C5IE C4IR C4IE C3IR C3IE C2IR C2IE C1IR C1IE C0IR C0IE
rwh
rw
rwh
rw
rwh
rw
rwh
PECXISNC
PEC Interrupt Sub Node Control
rw
rwh
rw
rwh
rw
SFR(H,H)
rwh
rw
rwh
rw
Reset value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
C15
IR
C15
IE
C14
IR
C14
IE
C13
IR
C13
IE
C12
IR
C12
IE
C11
IR
C11
IE
C10
IR
C10
IE
C9
IR
C9
IE
C8
IR
C8
IE
rwh
rw
rwh
rw
rwh
rw
rwh
rw
rwh
rw
rwh
rw
rwh
rw
rwh
rw
Field
Bits
Type Description
CxIR
15, 13, rwh
11, 9,
7, 5, 3,
1
Interrupt Sub Node Request Flag of PEC Channel
x 1) 2)
0
No special EOP interrupt request is pending
for PEC channel x
1
PEC channel x has raised an EOP interrupt
request
CxIE
14, 12, rw
10, 8,
6, 4, 2,
0
Interrupt Sub Node Enable Control Bit
of PEC Channel x 1) 3)
(individually enables/disables a specific source)
0
EOP interrupt request of PEC channel x is
disabled
1
EOP interrupt request of PEC channel x is
enabled
1)
x = 15...0
2)
NOTE:
The EOP sub-node interrupt request flags are not cleared by hardware when entering the ISR (interrupt has
been accepted by the CPU), unlike the interrupt request flags of the interrupt nodes (request flags xxIC.xxIR).
The ISR has to check the request flags and to clear them before executing the RETI instruction.
3)
It is recommended that you clear an interrupt request flag (CxIR) before setting the respective enable flag
(CxIE). Otherwise, pending former requests will immediately trigger an interrupt request after setting the
enable bit.
User’s Manual
3-45
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.5
Using General-Purpose Registers
The C166S uses several banks of 16 dedicated General Purpose Registers (GPRs) R0,
R1, R2... R15 that can be accessed in one CPU cycle. The GPRs are the working
registers of the Arithmetic and Logic Units (ALU) and may also serve as address pointers
in indirect addressing modes.
Several banks of GPRs are memory-mapped. The banks of these GPRs are located in
the DPRAM. One bank uses a block of 16 consecutive words. A Context Pointer (CP)
register determines the base address of the currently selected bank.
The C166S can switch the complete GPR bank with a single instruction for time-critical
tasks. After switching, the new task is executed within its own separate context.
Internal DPRAM
(CP)+30
(CP)+28
0
15
16-Bit Context Pointer
…
(CP)+2
(CP)
Figure 3-6
Register Bank Selection via Register CP
There are 3 different ways to access the GPRs:
Short 4-bit GPR addresses (mnemonic: Rw or Rb) specify an address relative to the
memory location pointed to by the contents of the CP register, i.e., the base of contents
of the current register bank. Both byte-wise and word-wise GPR accesses are possible.
The short 4-bit GPR address is logically added to the contents of register CP if a byte
(Rb) GPR address is specified, or multiplied by two and then added to CP if a word (Rw)
GPR address is specified (see Figure 3-7).
User’s Manual
3-46
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
Note: If GPRs are used as indirect address pointers, they are always accessed wordwise.
For some instructions, only the first 4 GPRs (R0, R1, R2 and R3) can be used as indirect
address pointers. These GPRs are specified via short 2-bit GPR addresses. The
physical address calculation is identical to the one for the short 4-bit GPR addresses.
Short 8-bit register addresses (mnemonic: reg or bitoff) within a range from F0H to FFH
interpret the four least-significant bits as a short 4-bit GPR address, while the four most
significant bits are ignored. The physical GPR address is calculated in a similar fashion
as the short 4-bit GPR addresses. For single-bit GPR accesses, the GPR’s word address
is calculated in the same way. The accessed bit position within the word is specified by
a separate additional 4-bit value.
Specified by reg or bitoff
12-Bit Context Pointer
11
1 0
4-Bit GPR
Address
1111
For byte GPR
accesses
*1
*2
For word GPR
accesses
Internal
Core-RAM
+
Must be within
the internal CoreRAM area
GPRs
Figure 3-7
Implicit CP Use by logical Short GPR Addressing Modes
24-Bit memory addresses within a range from (CP)+0 to (CP)+30 can be used to
access GPRs directly. Both byte and word GPR accesses are possible. The 24-bit
memory address is generated according to the rules for long- and indirect-addressing
modes (Section 3.6.2).
User’s Manual
3-47
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
Table 3-10
Addressing modes to Access Word-GPRs
Name Physical 8-Bit
4-Bit
Description
Address Address Address
Reset
Value
R0
(CP)+0
F0H
0H
General-Purpose word Register R0
UUUUH
R1
(CP)+2
F1H
1H
General-Purpose word Register R1
UUUUH
R2
(CP)+4
F2H
2H
General-Purpose word Register R2
UUUUH
R3
(CP)+6
F3H
3H
General-Purpose word Register R3
UUUUH
R4
(CP)+8
F4H
4H
General-Purpose word Register R4
UUUUH
R5
(CP)+10 F5H
5H
General-Purpose word Register R5
UUUUH
R6
(CP)+12 F6H
6H
General-Purpose word Register R6
UUUUH
R7
(CP)+14 F7H
7H
General-Purpose word Register R7
UUUUH
R8
(CP)+16 F8H
8H
General-Purpose word Register R8
UUUUH
R9
(CP)+18 F9H
9H
General-Purpose word Register R9
UUUUH
R10
(CP)+20 FAH
AH
General-Purpose word Register R10 UUUUH
R11
(CP)+22 FBH
BH
General-Purpose word Register R11 UUUUH
R12
(CP)+24 FCH
CH
General-Purpose word Register R12 UUUUH
R13
(CP)+26 FDH
DH
General-Purpose word Register R13 UUUUH
R14
(CP)+28 FEH
EH
General-Purpose word Register R14 UUUUH
R15
(CP)+30 FFH
FH
General-Purpose word Register R15 UUUUH
Note: The first 8 GPRs (R7...R0) may also be accessed byte-wise.
Note: Writing to a GPR byte does not affect the other byte of the same GPR.
User’s Manual
3-48
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
Each half of the byte-wise accessible registers has a special name (see table below).
Table 3-11
Addressing modes to access Byte-GPRs
Name Physical 8-Bit
4-Bit
Description
Address Address Address
Reset
Value
RL0
(CP)+0
F0H
0H
General-Purpose byte Register RL0
UUH
RH0
(CP)+1
F1H
1H
General-Purpose byte Register RL1
UUH
RL1
(CP)+2
F2H
2H
General-Purpose byte Register RL2
UUH
RH1
(CP)+3
F3H
3H
General-Purpose byte Register RL3
UUH
RL2
(CP)+4
F4H
4H
General-Purpose byte Register RL4
UUH
RH2
(CP)+5
F5H
5H
General-Purpose byte Register RL5
UUH
RL3
(CP)+6
F6H
6H
General-Purpose byte Register RL6
UUH
RH3
(CP)+7
F7H
7H
General-Purpose byte Register RL7
UUH
RL4
(CP)+8
F8H
8H
General-Purpose byte Register RL8
UUH
RH4
(CP)+9
F9H
9H
General-Purpose byte Register RL9
UUH
RL5
(CP)+10 FAH
AH
General-Purpose byte Register RL10 UUH
RH5
(CP)+11 FBH
BH
General-Purpose byte Register RL11 UUH
RL6
(CP)+12 FCH
CH
General-Purpose byte Register RL12 UUH
RH6
(CP)+13 FDH
DH
General-Purpose byte Register RL13 UUH
RL7
(CP)+14 FEH
EH
General-Purpose byte Register RL14 UUH
RH7
(CP)+15 FFH
FH
General-Purpose byte Register RL15 UUH
User’s Manual
3-49
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.5.1
Context Switch
An Interrupt Service Routine (ISR) or a task scheduler of an operating system usually
saves the contents of all used registers into the stack, and restores them before
returning. The more registers a routine uses, the more time is wasted by saving and
restoring.
The contents of the register bank are switched by changing the base address of the
memory-mapped GPR bank. The base address is given by the contents of the Context
Pointer (CP) register.
The Context Pointer
The CP register is not bit-addressable. It can be updated via any instruction capable of
modifying SFRs.
CP
Context Pointer
SFR(FE10H,08H)
11
10
9
8
7
6
Reset value: FC00H
15
14
13
12
5
4
3
2
1
0
1
1
1
1
CP
0
r
r
r
r
rw
r
Field
Bits
Type Description
1
[15:12] r
CP always points in the DPRAM
CP
[11:1]
Modifiable portion of register CP
Specifies the (word) base address of the current
memory-mapped register bank.
rw
Note: When writing a value to register CP with
bits CP[11:9] = 000, bits CP[11:10] are
set to 11 by hardware.
0
[0]
r
CP is always word-aligned
Note: It is the user’s responsibility to ensure that the physical GPR address specified via
CP register plus short GPR address must always be an RAM location. If this
condition is not met, unexpected results may occur. Do not set CP below the
DPRAM start address.
Note: Due to the internal instruction pipeline, a new CP value cannot be used for GPR
address calculations for the instruction immediately following the instruction
updating the CP register.
User’s Manual
3-50
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
The C166S switches the complete memory-mapped GPR bank with a single instruction.
After switching, the service routine executes within its own separate context.
The instruction SCXT CP, #New_Bank pushes the value of the current context pointer
(CP) into the system stack and loads CP with the immediate value New_Bank, which
selects a new register bank. The service routine may now use its own registers. This
memory register bank is preserved when the service routine terminates, i.e. its contents
are available on the next call. Before returning from the service routine (RETI), the
previous CP is simply popped from the system stack, which returns the registers to the
original bank.
User’s Manual
3-51
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.6
Data Addressing
The C166S provides a lot of powerful addressing modes for word-wise, byte-wise and
bitwise data accesses (short, long, indirect). The different addressing modes use
different formats and have different scopes.
The following major tasks are performed:
• Address generation using short-, long- and indirect-addressing modes
• Data paging or overwriting mechanism
• System stack handling
3.6.1
Short Addressing Modes
All of these addressing modes use an implicit base offset address to specify a 24-bit
physical address. Short addressing modes allow access to the GPRs, SFRs, or bitaddressable memory space:
Physical Address = Base Address + ∆ * Short Address
Note: ∆ is 1 for byte-wise GPRs, ∆ is 2 for word-wise GPRs.
Table 3-12
Short addressing modes
Mnemonic Physical Address
Short Address
Range
Scope of Access
Rw
(CP) + 2*Rw or local
Rw
= 0...15
GPRs(Word)
Rb
(CP) + 1*Rb or local
Rb
= 0...15
GPRs(Byte)
reg
00’FE00H+ 2*reg
00’F000H+ 2*reg
(CP)+ 2*(reg∧0FH)
(CP)+ 1*(reg∧0FH)
reg
reg
reg
reg
= 00H...EFH
= 00H...EFH
= F0H...FFH
= F0H...FFH
SFRs (Word, Low byte)
ESFRs(Word, Low byte)
GPRs(Word)
GPRs(Bytes)
bitoff
00’FD00H+ 2*bitoff
00’FF00H+ 2*(bitoff∧7FH)
00’F100H+ 2*(bitoff∧7FH)
(CP) + 2*(bitoff∧0FH)
bitoff
bitoff
bitoff
bitoff
= 00H...7FH
= 80H...EFH
= 80H...EFH
= F0H...FFH
DPRAMBit word offset
SFR Bit word offset
ESFRBit word offset
GPR Bit word offset
bitaddr
Word offset as with bitoff. bitoff = 00H...FFH
immediate bit position.
bitpos= 0...15
Any single bit
Rw, Rb: Specifies direct access to any GPR in the currently active context. Both Rw
and Rb require 4 bits in the instruction format. The base address of the global
register bank is determined by the contents of register CP. Rw specifies a 4-bit
word GPR address relative to the base address (CP), while Rb specifies a 4bit byte GPR address relative to the base address (CP).
User’s Manual
3-52
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
reg:
Specifies direct access to any (E)SFR or GPR in the currently active context.
The reg value requires 8 bits in the instruction format. Short reg addresses in
the range from 00H to EFH always specify (E)SFRs. In that case, the factor ∆
equals 2, and the base address is 00’FE00H for the standard SFR area or
00’F000H for the extended ESFR area. The reg accesses to the ESFR area
require a preceding EXT*R instruction to switch the base address. Depending
on the opcode, either the total word (for word operations) or the low byte (for
byte operations) of an SFR can be addressed via reg. Note that the high byte
of an SFR cannot be accessed via the reg addressing mode. Short reg
addresses in the range from F0H to FFH always specify GPRs. In that case,
only the lower 4bits of reg are significant for physical address generation and,
therefore, the address calculation is identical to the address generation process described for the Rb and Rw addressing modes.
bitoff:
Specifies direct access to any word in the bit-addressable memory space. The
bitoff value requires 8 bits in the instruction format. Depending on the specified bitoff range, different base addresses are used to generate physical
addresses: Short bitoff addresses in the range from 00H to 7FH use 00’FD00H
as a base address to specify the 128 highest DPRAM word locations in the
range from 00’FD00Hh to 00’FDFEH. Short bitoff addresses in the range from
80H to EFH use base address 00’FF00H to specify the internal SFR word locations in the range from 00’FF00H to 00’FFDEH or base address 00’F100H to
specify the internal ESFR word locations in the range from 00’F100H to
00’F1DEH. The bitoff accesses to the ESFR area require a preceding EXT*R
instruction to switch the base address. For short bitoff addresses from F0H to
FFH, only the lowest four bits are used to generate the address of the selected
word GPR.
bitaddr: Any bit address is specified by a word address within the bit-addressable
memory space (see bitoff), and by a bit position (bitpos) within that word.
Therefore, bitaddr requires 12 bits in the instruction format.
User’s Manual
3-53
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.6.2
Long and Indirect Addressing Modes
These addressing modes use one of the 4 DPP registers to specify a 24-bit address. Any
word or byte data within the entire address space can be accessed with these modes.
Any long or indirect 16-bit address contains two parts that have different meanings. Bits
13-0 specify a 14-bit data page offset, while bits 15-14 specify the Data Page Pointer
(DPP) (1 of 4) register, which is used to generate the full 24-bit address (see figure
below).
The C166S also supports an override mechanism for the DPP addressing scheme
[EXTP(R) and EXTS(R) instructions].
15 14 13
0
16-bit Long Address
9
0
DPP0
DPP1
DPP2
DPP3
14-bit page offset
23
14 13
0
24-bit Physical Address
Figure 3-8
Interpretation of a 16-bit Long Address
Note: Word accesses on odd byte addresses are not executed. A hardware trap will be
triggered.
User’s Manual
3-54
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.6.2.1
Addressing via Data Page Pointer
The 4 non-bit-addressable DPP registers select up to 4 different data pages. The lower
10 bits of each DPP register select one of the 1024 possible 16-KByte data pages, while
the upper 6 bits are reserved for the future use. The DPP registers provide access to the
entire memory space in 16-KByte pages.
The DPP registers are used implicitly whenever data accesses to any memory location
are made via indirect or direct long 16-bit addressing modes (except for override
accesses via EXTended instructions and PEC data transfers).
Data paging is performed by concatenating the lower 14 bits of an indirect or direct long
16-bit address with the contents of the DDP register selected by the upper 2 bits of the
16-bit address. The contents of the selected DPP register specify one of the 1024
possible data pages. This data page base address together with the 14-bit page offset
forms the physical 24-bit address.
16-Bit Data Address
15 14
0
Memory
selects DPP
255
FF’0000H
9
DPP
0
DPP3 - 11
254
DPP2 - 10
FE’0000H
DPP1 - 01
DPP0 - 00
x
23
1
15 14
0
01’0000H
0
00’0000H
Figure 3-9
Page
Page offset
Segment
Segment offset
Addressing via the Data Page Pointer
After reset, the DPP registers select data pages 3-0 within segment 0. If the user does
not want to use any data paging, no further action is required.
User’s Manual
3-55
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
DPP0
Data Page Pointer 0
SFR(FE00H,00H)
15
14
13
12
11
10
0
0
0
0
0
0
DPP0PN
r
r
r
r
r
r
rw
DPP1
Data Page Pointer 1
9
8
7
6
Reset value: 0000H
5
4
SFR(FE02H,01H)
8
7
6
14
13
12
11
10
0
0
0
0
0
0
DPP1PN
r
r
r
r
r
r
rw
5
4
SFR(FE04H,02H)
8
7
6
14
13
12
11
10
0
0
0
0
0
0
DPP2PN
r
r
r
r
r
r
rw
5
4
SFR(FE06H,03H)
9
8
7
14
13
12
11
10
0
0
0
0
0
0
DPP3PN
r
r
r
r
r
r
rw
Bits
Type Description
DPPxPN
[9:0]
rw
0
3
2
1
0
3
2
1
0
Reset value: 0003H
15
Field
6
1
Reset value: 0002H
15
DPP3
Data Page Pointer 3
9
2
Reset value: 0001H
15
DPP2
Data Page Pointer 2
9
3
5
4
3
2
1
0
Data Page Number of DPP
Specifies the data page selected via DPP.
Note: In a non-segmented memory mode, the whole DPP register is still used for the
calculation of the physical 24-bit address.
A DPP register can be updated via any instruction that is capable of modifying an SFR.
Note: Due to the internal instruction pipeline, a new DPP value is not usable for the
operand address calculation of the instruction immediately following the
instruction updating the DPPx register.
User’s Manual
3-56
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.6.2.2
DPP Override Mechanism in the C166S
The C166S provides an override mechanism to temporarily bypass the DPP addressing
scheme.
The EXTP(R) and EXTS(R) instructions override this addressing mechanism. Instruction
EXTP(R) replaces the contents of the DPP register, while instruction EXTS(R)
concatenates the complete 16-bit long address with the specified segment base
address. The overriding page or segment may be specified directly as a constant (#pag,
#seg) or via a word GPR (Rw).
15 14 13
EXTP(R):
0
16-bit Long Address
#pag
14-bit page offset
24-bit Physical Address
15
EXTS(R):
0
16-bit Long Address
#seg
16-bit segment offset
24-bit Physical Address
Figure 3-10
User’s Manual
Overriding the DPP Mechanism
3-57
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.6.2.3
Long Addressing Mode
The long addressing mode uses a 16-bit constant value encoded in the instruction format
which specifies the data page offset and the DPP.
The long addressing mode is referred to by the mnemonic mem.
Table 3-13
Long addressing mode
Mnemonic
Physical Address
Scope of Access
mem
(DPP0)||
(DPP1)||
(DPP2)||
(DPP3)||
any word or byte
mem
pag
|| mem∧3FFFH
any word or byte
mem
seg
|| mem
any word or byte
mem∧3FFFH
mem∧3FFFH
mem∧3FFFH
mem∧3FFFH
Note: The long addressing mode may be used with the DPP overriding mechanism
(EXTP(R) and EXTS(R)).
User’s Manual
3-58
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.6.2.4
Indirect Addressing Modes
These addressing modes can be considered as a combination of short and long
addressing modes. This means that a long 16-bit address is provided indirectly by the
contents of a word GPR that is specified directly by a short 4-bit address (Rw = 0 to 15).
There are indirect addressing modes which add a constant value to the GPR contents
before the long 16-bit address is calculated. Other indirect addressing modes can
decrement or increment the indirect address pointers (GPR contents) by 2 or 1 (referring
to words or bytes).
In each case, one of the four DPP registers is used to specify physical 24-bit addresses.
Any word or byte data within the entire memory space can be addressed indirectly.
Note: Indirect addressing may be used with the DPP overriding mechanism (EXTP(R)
and EXTS(R)).
Some instructions use only the lowest 4-word GPRs (R3-R0) as indirect address
pointers, which are then specified via short 2-bit addresses.
Physical addresses are generated from indirect address pointers using the following
algorithm:
1)
Calculate the physical address of the word GPR, which is used as indirect
address pointer, using the specified short address (Rw) and
GPR Address = (CP) + 2 * Short Address
2)
If required, pre-decrement indirect address pointer (-Rw) by the data-typedependent value (∆=1 for byte operations, ∆=2 for word operations) before the
long 16-bit address is generated:
(GPR Address) = (GPR Address) - ∆ ; [optional step!]
3)
Calculate the long 16-bit address by adding a constant value (Rw+const16 if
selected) to the contents of the indirect address pointer:
Long Address = (GPR Pointer) + Constant ; [+Constant is optional]
4)
Calculate the physical 24-bit address using the resulting long address and the
corresponding DPP register contents (see long mem addressing modes).
Physical Address = (DPPi) + Page offset
5)
If required, post-in/decrement indirect address pointers (‘Rw±’) by the datatype-dependent value (∆=1 for byte operations, ∆=2 for word operations).
User’s Manual
3-59
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
(GPR Pointer) = (GPR Pointer) ± ∆; [optional step!]
The following indirect addressing modes are provided:
Table 3-14
Indirect addressing modes
Mnemonic
Particularities
[Rw]
Most instructions accept any GPR (R15...R0) as indirect address
pointer. Some instructions accept only the lower four GPRs (R3...R0).
[Rw+]
The specified indirect address pointer is automatically post-incremented
by 2 or 1 (for word or byte data operations) after the access.
[-Rw]
The specified indirect address pointer is automatically pre-decremented
by 2 or 1 (for word or byte data operations) before the access.
[Rw+#data16] The specified 16-bit constant is added to the indirect address pointer
before the long address is calculated.
User’s Manual
3-60
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.6.3
The System Stack
A system stack is provided to store return vectors, segment pointers, and processor
status for procedures and interrupt routines.
The internal system stack can also be used to store data temporarily, or pass it between
subroutines or tasks. Instructions are provided to push or pop registers on/from the
system stack. However, in most cases, the register banking scheme provides the best
performance for passing data between multiple tasks.
Note: The system stack allows the storage of words only. Bytes must either be
converted to words or the “unwanted” other byte must be disregarded.
Register SP can be loaded only with even byte addresses (The LSB of SP is
always 0).
The Stack Pointer (SP) addresses the stack within the DPRAM area.
The Stack Pointer Register
The non-bit-addressable Stack Pointer (SP) register is used to point to the Top Of the
System (TOS) stack. The SP register is pre-decremented whenever data is to be pushed
onto the stack, and it is post-incremented whenever data is to be popped from the stack.
Therefore, the system stack grows from higher toward lower memory locations.
Since the Least Significant Bit (LSB) of register SP is tied to 0, and bits 15-12 are tied to
1 by hardware, the SP register can contain values only from F000H to FFFEH. This
allows access to a physical stack within the DPRAM of the C166S. A virtual stack
(usually bigger) can be implemented via software. This mechanism is supported by
registers STKOV and STKUN (see descriptions below (Section 3.6.3.1).
The SP register can be updated via any instruction that is capable of modifying a 16-bit
SFR.
Note: Due to the internal instruction pipeline, a POP or RETurn instruction must not
immediately follow an instruction updating the SP register.
SP
Stack Pointer
15
14
13
SFR(FE12H,09H)
12
11
10
9
8
7
6
Reset value: FC00H
5
4
3
2
1
0
1111
SP
0
r
rwh
r
User’s Manual
3-61
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
Field
Bits
1111
[15:12] r
Fixed at 1111
SP
[11:1]
rwh
Modifiable portion of register SP
Specifies the top of the system stack.
0
[0]
r
Fixed at 0
3.6.3.1
Type Description
Stack Overflow and Underflow
Detection of stack overflow/underflow is supported by two registers, STKOV (STacK
OVerflow pointer) and STKUN (STacK UNderflow pointer). Specific system traps (Stack
Overflow trap, Stack Underflow trap) will be entered whenever the SP reaches either
boundary specified in these registers.
In many cases, the user will place a Software ReSeT instruction (SRST) into the stack
underflow and overflow trap service routines. This is an easy approach that does not
require special programming. However, this approach assumes that the defined internal
stack is sufficient for the current software, and that exceeding its upper or lower
boundary represents a fatal error (see Linear Stack).
It is also possible to use the stack underflow and stack overflow traps to cache portions
of a larger external stack. Only the portion of the system stack currently being used is
placed into the internal memory, thus allowing a greater portion of the internal RAM to
be used for program, data, or register banking. This approach assumes no error but
requires a set of control routines (see Circular Stack).
The STacK OVerflow Pointer Register STKOV
This non-bit-addressable STKOV pointer register is compared to the SP register after
each operation that pushes data onto the system stack (e.g., PUSH and CALL
instructions or interrupts), and after each substraction from the SP register. If the
contents of the SP register is less than the contents of the STKOV pointer register, a
stack overflow trap will occur.
STKOV
STacK OVerflow Pointer
15
14
13
12
11
SFR(FE14H,0AH)
10
9
8
7
6
Reset value: FA00H
5
4
3
2
1
0
1111
STKOV
0
r
rw
r
User’s Manual
3-62
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
Field
Bits
Type Description
1111
[15:12] r
Fixed at 1111
STKOV
[11:1]
rw
Modifiable portion of register STKOV
Specifies the segment offset address of the
lower limit of the system stack.
0
[0]
r
Fixed at ’0’
STKOV can be updated via any instruction that is capable of modifying an SFR.
Note: When a value is MOVED into the stack pointer, NO check against the overflow/
registers is performed.
• Fatal error indication treats the stack overflow as a system error and executes
associated trap service routine. Under these circumstances, data in the bottom of the
stack may have been overwritten by the status information stacked upon servicing the
stack overflow trap.
• Automatic system stack flushing allows the system stack to be used as a “Stack
Cache” for a bigger external user stack. In this case, STKOV should be initialized to a
value that represents the desired lowest Top Of Stack (TOS) address plus an offset
based on the selected maximum stack size. This offset considers the worst case that
will occur when a stack overflow condition is detected just during entry into an ISR, or
during an ATOMIC/EXTend sequence. Under these conditions, additional stack word
locations are required to push IP, PSW, and CSP for both the ISR and the hardware
trap service routine.
The STacK UNderflow Pointer Register STKUN
STKUN is a non-bit-addressable register that is compared to the SP register after each
operation that pops data from the system stack (e.g. POP and RET instructions), and
after each addition to the SP register. If the content of the SP register is greater than the
the content of STKUN, a stack underflow hardware trap will occur.
Since the LSB of STKUN is tied to 0 and bits 15 through 12 are tied to 1 by hardware,
STKUN register can only contain values from F000H to FFFEH.
STKUN
STacK UNderflow Pointer
15
14
13
12
11
SFR(FE16H,0BH)
10
9
8
7
6
Reset value: FC00H
5
4
3
2
1
0
1111
STKUN
0
r
rw
r
User’s Manual
3-63
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
Field
Bits
Type Description
1111
[15:12] r
Fixed at 1111
STKUN
[11:1]
rw
Modifiable portion of register STKUN
Specifies the segment offset address of the
upper limit of the system stack.
0
[0]
r
Fixed at 0
STKUN can be updated via any instruction capable of modifying an SFR.
Note: When a value is MOVED into the stack pointer, NO check against the overflow/
registers is performed.
• Fatal error indication treats the stack underflow as a system error and executes
associated trap service routine.
• Automatic system stack refilling allows the system stack to be used as a “Stack
Cache” for a bigger external user stack. In this case, STKUN should be initialized to a
value that represents the desired highest Bottom of Stack address.
Scope of Stack Limit Control
The stack limit control by the register pair STKOV and STKUN detects cases where SP
is moved outside the defined stack area either by ADD or SUB instructions, or by PUSH
or POP operations (explicit or implicit, e.g., CALL or RET instructions).
This control mechanism is not triggered and no stack trap is generated when:
• the stack pointer SP is directly updated via MOV instructions, or
• the limits of the stack area (STKOV, STKUN) are changed so that SP is outside the
new limits.
3.6.3.2
Linear Stack
The C166S offers a linear stack option (STKSZ = 111B) in which the system stack may
use the complete DPRAM area. This provides a large system stack without requiring
procedures to handle data transfers for a circular stack. However, this method also
leaves less RAM space for variables or code. The DPRAM area that may be consumed
by the system stack is defined via the STKUN and STKOV pointers. The underflow and
overflow traps in this case serve for fatal error detection only.
For the linear stack option, all modifiable bits of register SP are used to access the
physical stack. Although the stack pointer may cover addresses from 00’F000H up to
00’FFFEH, the (physical) system stack must be located within the DPRAM and therefore
may only use the address range 00’F600H to 00’FDFEH. It is the user’s responsibility to
restrict the system stack to the DPRAM range.
User’s Manual
3-64
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
Note: Stack accesses below the DPRAM area (ESFR space and reserved area) and
within address range 00’FE00H and 00’FFFEH (SFR space) will have
unpredictable results.
3.6.3.3
Circular (Virtual) Stack
This basic technique allows pushing until the overflow boundary of the internal stack is
reached. At this point, a portion of the stacked data must be saved into external memory
to create space for further stack pushes. This is called “stack flushing”. When executing
a number of return or pop instructions, the upper boundary (since the stack empties
upward to higher memory locations) is reached. The entries that have been previously
saved in external memory must now be restored. This is called “stack filling”. Because
procedure call instructions do not continue to nest infinitely and call and return
instructions alternate, flushing and filling normally occurs very infrequently. If this is not
true for a given program environment, this technique should not be used because of the
overhead of flushing and filling.
The basic mechanism is the transformation of the addresses of a virtual stack area
controlled via SP, STKOV, and STKUN to a defined physical stack area within the
DPRAM via hardware. This virtual stack area covers all possible locations that SP can
point to, i.e. 00’F000H through 00’FFFEH. STKOV and STKUN accept the same 4-KByte
address range. The size of the physical stack area within the DPRAM that is used for
standard stack operations is defined via bitfield STKSZ in register SYSCON (see below).
Table 3-15
Circular Stack Address Transformation
STKSZ
Stack Size DPRAM Addresses (Words)
(Words)
of Physical Stack
Significant Bits
of Stack Ptr. SP
000B
256
00’FBFEH-00’FA00H (Default after Reset)
SP.8-SP.0
001B
128
00’FBFEH-00’FB00H
SP.7-SP.0
010B
64
00’FBFEH-00’FB80H
SP.6-SP.0
011B
32
00’FBFEH-00’FBC0H
SP.5-SP.0
100B
512
00’FBFEH-00’F800H (not for 1KByte
DPRAM)
SP.9-SP.0
101B
---
Reserved. Do not use this combination.
---
110B
---
Reserved. Do not use this combination.
---
111B
1024
00’FDFEH-00’FX00H (Note: No circular stack) SP.11...SP.0
00’FX00H represents the lower DPRAM limit,
i.e.
1 KB: 00’FA00H, 2 KB: 00’F600H,
3 KB: 00’F200H
User’s Manual
3-65
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
The virtual stack addresses are transformed to physical stack addresses by
concatenating the significant bits of SP (see table Table 3-15) with the complementary
most significant bits of the upper limit of the physical stack area (00’FBFEH). This
transformation is done via hardware (see figure Figure 3-11).
The reset values (STKOV=FA00H, STKUN=FC00H, SP=FC00H, STKSZ=000B) map the
virtual stack area directly to the physical stack area, and allow using the internal system
stack without any changes, provided that the 256-word area is not exceeded.
FBFEH 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0
FBFEH 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0
FB80H 1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0
Phys.A.
FA00H 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0
FB80H 1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0
<SP>
F800H 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
After PUSH
After PUSH
FBFEH 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0
FBFEH 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0
FBFEH 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0
Phys.A.
FBFEH 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0
FB7EH 1 1 1 1 1 0 1 1 0 1 1 1 1 1 1 0
<SP>
F7FEH 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0
64 words
Stack Size
256 words
Figure 3-11 Physical Stack Address Generation
The following example demonstrates the circular stack mechanism that is also an effect
of this virtual stack mapping: First, register R1 is pushed onto the lowest physical stack
location according to the selected maximum stack size. The next instruction will push
register R2 onto the highest physical stack location, although the SP is decremented by
2 as for the previous push operation.
MOV
SP, #0F802H
...
PUSH
PUSH
R1
R2
;Set SP before last entry...
;...of physical stack of 256 words
;(SP)=F802H: Physical stack addr.=FA02H
;(SP)=F800H: Physical stack addr.=FA00H
;(SP)=F7FEH: Physical stack addr.=FBFEH
The effect of the address transformation is that the physical stack addresses wrap
around from the end of the defined area to its beginning. When flushing and filling the
User’s Manual
3-66
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
internal stack, this circular stack mechanism only requires moving that portion of stack
data that is to be re-used (i.e. the upper part of the defined stack area) instead of the
whole stack area. Stack data that remain in the lower part of the internal stack need not
be moved by the distance of the space being flushed or filled, as the stack pointer
automatically wraps around to the beginning of the freed part of the stack area.
Note: This circular stack technique is applicable for stack sizes of 32 to 512 words
(STKSZ = 000B to 100B). It does not work with option STKSZ = 111B, which uses
the complete DPRAM for system stack; in this case, the address transformation
mechanism is deactivated.
When a boundary is reached, the stack underflow or overflow trap is entered. Inside the
trap handler a predetermined portion of the internal stack is moved to or from the external
stack. The amount of data transferred is determined by the average stack space required
by routines and the frequency of calls, traps, interrupts, and returns. In most cases, this
will be approximately 1/4 to 1/10 the size of the internal stack. Once the transfer is
complete, the boundary pointers are updated to reflect the newly allocated space on the
internal stack. Thus, the user is free to write code without concern for the internal stack
limits. Only the execution time required by the trap routines affects user programs.
The following procedure initializes the controller for usage of the circular stack
mechanism:
1. Specify the size of the physical system stack area within the DPRAM (bitfield STKSZ
in register SYSCON).
2. Define two pointers that specify the upper and lower boundary of the external stack.
These values are then tested in the stack underflow and overflow trap routines when
moving data.
3. Set STKOV to the limit of the defined internal stack area plus six words (for the
reserved space to store two interrupt entries).
The internal stack will now fill until the overflow pointer is reached. After entry into the
overflow trap procedure, the top of the stack will be copied to the external memory. The
internal pointers will then be modified to reflect the newly-allocated space. After exiting
the trap procedure, the internal stack will wrap around to the top of the internal stack, and
continue to grow until the new value of the stack overflow pointer is reached.
When the underflow pointer is reached, while the stack is emptied, the bottom of stack
is reloaded from the external memory, and the internal pointers are adjusted accordingly.
User’s Manual
3-67
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.7
Data Processing
All standard arithmetic, shift, and logical operations are performed in the 16-bit
Arithmetic and Logic Unit (ALU). In addition to the standard ALU, the ALU of the C166S
includes bit manipulation, and a multiply-and-divide unit. Most internal execution blocks
have been optimized to perform operations on either 8-bit or 16-bit numbers. Once the
pipeline has been filled, most instructions are completed in one machine cycle.
The status flags are automatically updated in the PSW register (see Section 3.7.6) after
each ALU operation. These flags allow branching upon specific conditions. Support of
both signed and unsigned arithmetic is provided by the user-selectable branch test. The
status flags are also preserved automatically by the CPU upon entry into an interrupt or
trap routine.
3.7.1
Data Types
The C166S supports operations on boolean/bit, bit string, character, and integer data
types. Most instructions operate with specific data types, while others are useful for
manipulating several data types.
The C166S data formats support all ANSI C data types. In addition, some C compilers
support new types that allow the efficient use of the bit-manipulation instructions in
embedded control applications.
The C166S directly supports the following data formats:
Table 3-16
CPU data formats
CPU data format
Size (bytes) Range
BIT
1 bit
0 or 1
BYTE
1
0 to 255U or
-128 to +127
WORD
2
0 to 65535U or
-32768 to +32767
Table 3-17
ANSI C data types
ANSI C data types
Size (bytes) Range
CPU data format
bit
1bit
0 or 1
BIT
sfrbit
1bit
0 or 1
BIT
esfrbit
1bit
0 or 1
BIT
signed char
1
-128 to +127
BYTE
unsigned char
1
0 to 255U
BYTE
User’s Manual
3-68
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
Table 3-17
ANSI C data types
ANSI C data types
Size (bytes) Range
CPU data format
sfr
1
0 to 65535U
WORD
esfr
1
0 to 65535U
WORD
signed short
2
-32768 to +32767
WORD
unsigned short
2
0 to 65535U
WORD
bitword
2
0 to 65535U
WORD or BIT
signed int
2
-32768 to +32767
WORD
unsigned int
2
0 to 65535U
WORD
signed long
4
-2147483648 to
+2147483647
Not directly supported
unsigned long
4
0 to 4294967295UL Not directly supported
float
4
+/-1,176E-38 to
+/-3,402E+38
Not directly supported
double
8
+/- 2,225E-308 to
+/- 1,797E+308
Not directly supported
long double
8
+/- 2,225E-308 to
+/- 1,797E+308
Not directly supported
near pointer
2
16/14bits
depending on
memory model
WORD
far pointer
4
14bits (16k) in any
page
Not directly supported
huge pointer
4
24bits (16M)
Not directly supported
shuge pointer
4
24bits (16M), but
arithmetic is done
16-bit wide
Not directly supported
User’s Manual
3-69
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.7.2
Constants
In addition to the powerful addressing modes the C166S instruction set also supports
word-wide or byte-wide immediate constants. For an optimum utilization of the available
code storage, these constants are represented in the instruction formats by either 3, 4,
8 or 16 bits. The short constants are always zero-extended, while the long constants are
truncated if necessary to match the data format required for the particular operation (see
table below):
Table 3-18
Constant formats
Mnemonic
Word Operation
Byte Operation
#data3
0000H + data3
00H + data3
#data4
0000H + data4
00H + data4
#data8
0000H + data8
data8
#data16
data16
data16 ∧ FFH
#mask
0000H + mask
mask
Note: Immediate constants are always signified by a leading #.
3.7.3
The 16-bit Adder/Subtracter, Barrel Shifter
and the 16-bit Logic Unit
All standard arithmetic and logical operations are performed by a 16-bit ALU. In case of
byte operations signals from bits six and seven of the ALU result are used to control the
condition flags. Multiple precision arithmetic is supported by a CARRY-IN signal to the
ALU from previously calculated portions of the desired operation.
A 16-bit barrel shifter provides multiple bit shifts in a single machine cycle. Rotations and
arithmetic shifts are also supported.
3.7.4
Bit-manipulation Unit
The C166S offers a large number of instructions for bit processing. The special bitmanipulation unit was implemented for this purpose. The bit-manipulation instructions
are for efficient control and testing of peripherals. Unlike other microcontrollers, the
C166S has instructions that provide direct access to two operands in the bit-addressable
space without requiring them to be moved into temporary locations.
The same logical instructions that are available for words and bytes can also be used for
bits. The user can compare and modify a control bit for a peripheral in one instruction.
Multiple-bit shift instructions have been included to avoid long instruction streams of
single bit shift operations. These instructions require a single machine cycle. In addition,
bit field instructions are able to modify multiple bits of one operand in a single instruction.
User’s Manual
3-70
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
All instructions that manipulate single bits or bit groups internally use a read-modify-write
sequence that accesses the whole word, which contains the specified bit(s).
This method has several consequences:
• Bits can only be modified within the internal address areas, i.e. DPRAM and SFRs.
External locations cannot be used with bit instructions. The upper 256 bytes of the
SFR area, the ESFR area, and the DPRAM are bit-addressable (see “Memory
Organization” Chapter 4), i.e., those register bits located within the respective
sections can be manipulated directly using bit instructions. The other SFRs must be
accessed byte- or word-wise.
Note: All GPRs are bit-addressable independent of the allocation of the register bank via
the context pointer CP. Even GPRs which are allocated to not bit-addressable
RAM locations provide this feature.
• The read-modify-write approach may be critical with hardware-effected bits. In these
cases, the hardware may change specific bits while the read-modify-write operation is
in progress, where the write back would overwrite the new bit value generated by the
hardware. The solution is either to use the implemented hardware protection (see
below) or through special programming (see “Particular Pipeline Effects”
Section 3.8).
Protected bits are not changed during the read-modify-write sequence, i.e., when
hardware sets an interrupt request flag between the read and the write of the readmodify-write sequence, for example. The hardware protection logic guarantees that only
the intended bit(s) is/are affected by the write-back operation.
Note: If a conflict occurs between a bit manipulation generated by hardware and an
intended software access, the software access has priority and determines the
final value of the bit.
User’s Manual
3-71
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.7.5
Multiply and Divide Unit
The C166S has a separated multiply-and-divide unit. The multiplication is executed
within five machine cycles, while a division takes 20 machine cycles. The multiply-anddivide process is interruptible by an interrupt that has a higher priority level than the
current CPU level.
The Multiply/Divide High Word Register (MDH)
The non-bit-addressable Multiply/Divide High word register contains the high word of the
32-bit Multiply/Divide (MD) register, which is used by the CPU when it performs a
multiplication or a division using implicit addressing (DIV, DIVL, DIVLU, DIVU, MUL,
MULU). After an implicitly-addressed multiplication, this register represents the highorder 16 bits of the 32-bit result. For long divisions, MDH must be loaded with the highorder 16 bits of the 32-bit dividend before the division has started. After any division,
MDH represents the 16-bit remainder.
MDH
Multiply/Divide High Word
15
14
13
12
11
SFR(FE0CH,06H)
10
9
8
7
6
Reset value: 0000H
5
4
3
2
1
0
MDH
rwh
Field
Bits
Type Description
MDH
[15:0]
rwh
High part of MD
The high order 16 bits of the 32-bit multiply and
divide register MD.
Whenever this register is updated via software, the Multiply/Divide Register In Use
(MDRIU) flag in the Multiply/Divide Control (MDC) register is set to 1’
When a multiplication or division is interrupted before its completion and when a new
multiply or divide operation is to be performed within the Interrupt Service Routine (ISR),
the contents of MDH must be saved along with the contents of registers MDL and MDC
to avoid erroneous results.
The Multiply/Divide Low Word Register (MDL)
The non-bit-addressable Multiply/Divide Low word register contains the low word of the
32-bit multiply/divide MD register which is used by the CPU when it performs a
multiplication or a division using implicit addressing (DIV, DIVL, DIVLU, DIVU, MUL,
MULU). After a multiplication, this register represents the low-order 16 bits of the 32-bit
result. For long divisions, the MDL register must be loaded with the low-order 16 bits of
User’s Manual
3-72
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
the 32-bit dividend before the division has started. After any division, MDL represents the
16-bit quotient.
MDL
Multiply/Divide Low Word
15
14
13
12
11
SFR(FE0EH,07H)
10
9
8
7
6
Reset value: 0000H
5
4
3
2
1
0
MDL
rwh
Field
Bits
Type Description
MDL
[15:0]
rwh
Low part of MD
The low order 16 bits of the 32-bit multiply and
divide register MD.
Whenever this register is updated via software, the MDRIU flag in the MDC register is
set to 1. The MDRIU flag is cleared whenever the MDL register is read via software.
When a multiplication or division is interrupted before its completion and when a new
multiply or divide operation is to be performed within the ISR, the contents of MDL must
be saved along with the contents of registers MDH and MDC to avoid erroneous results.
The Multiply/Divide Control Register (MDC)
The bit-addressable 16-bit Multiply/Divide Control register is implicitly used by the CPU,
when it performs a multiplication or a division. It is used to store the required control
information for the corresponding multiply or divide operation. MDC is updated by
hardware during each single cycle of a multiply or divide instruction.
MDC
Multiply/Divide Control
SFR(FF0EH,87H)
Reset value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
!!
!!
!!
MDR
IU
!!
!!
!!
!!
r
r
r
r
r
r
r
r
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
User’s Manual
3-73
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
Field
Bits
Type Description
MDRIU
[4]
rwh
!!
[7],[6], rwh
[5],[3],
[2],[1],
[0]
Multiply/Divide Register In Use
0:
Cleared when register MDL is read via
software.
1:
Set when register MDL or MDH is written
via software, or when a multiply or divide
instruction is executed.
Internal Machine Status
The multiply/divide unit uses these bits to control
internal operations. Never modify these bits
without saving and restoring register MDC
When a division or multiplication was interrupted before its completion and the multiply/
divide unit is required, the MDC register must first be saved along with registers MDH
and MDL (to be able to restart the interrupted operation later), and then it must be
cleared for the new calculation. After completion of the new division or multiplication, the
state of the interrupted multiply or divide operation must be restored.
The MDRIU flag is the only portion of the MDC register that might be of interest for the
user. The remaining portions of the MDC register are reserved for dedicated use by the
hardware, and should never be modified by the user other than described above.
Otherwise, correct continuation of an interrupted multiply or divide operation cannot be
guaranteed.
Multiplication or division is performed simply by specifying the correct (signed or
unsigned) version of the multiply or divide instruction. The result is then stored in register
MD. The overflow flag (V) is set if the result of a multiply or divide instruction is greater
than 16 bits. This flag can be used to determine whether both word halves must be
transferred from register MD. The high portion of MD (MDH) must be moved into the
register file or memory first, in order to ensure that the MDRIU flag reflects the correct
state.
The following instruction sequence performs an unsigned 16-by-16-bit multiplication:
SAVE:
JNB
SCXT
BSET
PUSH
PUSH
START:
MULU
User’s Manual
MDRIU, START
MDC, #0010H
SAVED
MDH
MDL
;Test if MD was in use.
;Save and clear control register,
;leaving MDRIU set
;(only required for interrupted
;multiply/divide instructions)
;Indicate the save operation
;Save previous MD contents...
;...on system stack
R1, R2
;Multiply 16·16 unsigned, Sets MDRIU
3-74
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
JMPR
MOV
COPYL:
MOV
RESTORE:
JNB
POP
POP
POP
BCLR
cc_NV, COPYL
R3, MDH
;Test for only 16-bit result
;Move high portion of MD
R4, MDL
;Move low portion of MD, Clears MDRIU
SAVED, DONE
MDL
MDH
MDC
SAVED
;Test if MD registers were saved
;Restore registers
DONE:
...
;Multiplication is completed,
;program continues
The above save sequence and the restore sequence after COPYL are required only if
the current routine could have interrupted a previous routine that contained a MUL or DIV
instruction. Register MDC is also saved because it is possible that a previous routine’s
Multiply or Divide instruction was interrupted while in progress. In this case, the
information about how to restart the instruction is contained in this register. Register
MDC must be cleared to be initialized correctly for a subsequent multiplication or
division. The old MDC contents must be popped from the stack before the RETI
instruction is executed.
For a division, the user must first move the dividend into the MD register. If a 16/16-bit
division is specified, only the low portion of MD must be loaded. The result is also stored
in MD. The low portion (MDL) contains the integer result of the division, while the high
portion (MDH) contains the remainder.
The following instruction sequence performs a 32-by-16-bit division:
MOV
MOV
DIV
JMPR
MOV
MOV
MDH, R1
MDL, R2
R3
cc_V, ERROR
R3, MDH
R4, MDL
;Move dividend to MD register. Sets MDRIU
;Move low portion to MD
;Divide 32/16 signed, R3 holds divisor
;Test for divide overflow
;Move remainder to R3
;Move integer result to R4. Clears MDRIU
Whenever a multiply or divide instruction is interrupted while in progress, the address of
the interrupted instruction is pushed onto the stack and the MULIP flag in the PSW of the
interrupting routine is set. When the interrupt routine is exited with the RETI instruction,
this bit is tested implicitly before the old PSW is popped from the stack. If MULIP = 1, the
multiply/divide instruction is re-read from the location popped from the stack (return
address) and will be completed after the RETI instruction has been executed.
Note: The MULIP flag is part of the context of the interrupted task. When the
interrupting routine does not return to the interrupted task (e.g. scheduler switches
to another task), MULIP must be set or cleared according to the context of the task
that is switched to.
User’s Manual
3-75
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.7.6
The Processor Status Word Register (PSW)
The bit-addressable Processor Status Word register reflects the current status of the
microcontroller. Two groups of bits represent the current ALU status and the current
CPU interrupt status. One separate bit (USR0) within PSW is provided as a generalpurpose flag.
PSW
Processor Status Word
15
14
13
12
SFR(FF10H,88H)
Reset value: 0000H
11
10
9
8
7
6
5
4
3
2
1
0
ILVL
IEN
S1
0
0
0
USR0
MUL
IP
E
Z
V
C
N
rwh
rw
rw
r
r
r
rw
rwh
rwh
rwh
rwh
rwh
rwh
Field
Bits
ILVL
[15:12] rwh
CPU Priority LeVeL
0H
Lowest priority
...
...
Highest priority
FH
IEN
[11]
rw
Interrupt/PEC ENable Bit (globally)
0
Interrupt/PEC requests are disabled
1
Interrupt/PEC requests are enabled
S1
[10]
rw
Reserved for system
USR0
[6]
rwh
General Purpose Flag
May be used by application
MULIP
[5]
r
MULtiplication/division In Progress
0
No multiplication/division in process
1
Multiplication/division has been
interrupted
E
[4]
rwh
End of table Flag
0
Source operand is neither 8000h nor 80h
1
Source operand is 8000h or 80h
Z
[3]
rwh
Zero Flag
0
ALU result is not zero
1
ALU result is zero
V
[2]
rwh
OVerflow Flag
0
No overflow produced
0
Overflow produced
User’s Manual
Type Description
3-76
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
Field
Bits
Type Description
C
[1]
rwh
Carry Flag
0
No carry/borrow bit produced
1
Carry/borrow bit produced
N
[0]
rwh
Negative Result
0
ALU result is not negative
1
ALU result is negative
ALU Status (N, C, V, Z, E, MULIP)
The condition flags (N, C, V, Z, E) within the PSW indicate the ALU status resulting from
the ALU operation last performed. They are set by the majority of instructions according
to specific rules depending on the ALU operation or data movement.
After execution of an instruction that explicitly updates PSW, the condition flags may no
longer represent an actual CPU status. An explicit write operation to PSW supersedes
the condition flag values that are implicitly generated by the CPU. An explicit read access
to PSW returns the value of PSW after execution of the previous instruction.
Note: After reset, all of the ALU status bits are cleared.
• N-Flag: For the majority of ALU operations, the N-flag is set to 1 if the most significant
bit of the result contains a 1. Otherwise, it is cleared. In the case of integer operations,
the N-flag can be interpreted as the sign bit of the result (negative: N=1, positive: N=0).
Negative numbers are always represented as the 2's complement of the
corresponding positive number. The range of signed numbers extends from –8000H
to +7FFFH for the word data type, or from –80H to +7FH for the byte data type. For
Boolean bit operations with only one operand, the N-flag represents the previous state
of the specified bit. For Boolean bit operations with two operands, the N-flag
represents the logical XORing of the two specified bits.
• C-Flag: After an addition, the C-flag indicates that a “carry” from the most significant
bit of the specified word or byte data type has been generated. After a subtraction or
a comparison, the C-flag indicates a “borrow,” which represents the logical negation
of a carry for the addition. This means that the C-flag is set to 1 if no carry from the
Most Significant Bit (MSB) of the specified word or byte data type has been generated
during a subtraction. Subtraction is performed by the ALU as a 2's-complement
addition. The C-flag is cleared when this complement addition caused a carry.
The C-flag is always cleared for logical, multiply and divide ALU operations, because
these operations can not cause a carry flag to be set.
For shift and rotate operations, the C-flag represents the value of the bit shifted out
last. If a shift count of zero is specified, the C-flag will be cleared. The C-flag is also
cleared for a prioritize operation because a 1 is never shifted out of the MSB during
the normalization of an operand.
User’s Manual
3-77
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
For Boolean bit operations with only one operand, the C-flag is always cleared. For
Boolean bit operations with two operands, the C-flag represents the logical ANDing of
the two specified bits.
•
V-Flag: The addition, subtraction, and 2's complement operations set the V-flag to 1
if the result exceeds the range of 16-bit signed numbers for word operations (–8000H
to +7FFFH), or 8-bit signed numbers for byte operations (–80H to +7FH). Otherwise,
the V-flag is cleared. The result of an integer addition, integer subtraction, or 2's
complement operation is not valid if the V-flag indicates an arithmetic overflow.
For multiplication and division, the V-flag is set to 1 if the result can not be represented
in a word data type; otherwise, it is cleared. A division by zero will always cause an
overflow. Unlike the division result, the result of multiplication is valid regardless of Vflag value.
Since logical ALU operations cannot produce an invalid result, the V-flag is cleared by
these operations.
The V-flag is also used as a “sticky bit” for rotate-right and shift-right operations. By
only using the C-flag, a rounding error caused by a shift-right operation can be
estimated as up to one half of the LSB of the result. In conjunction with the V-flag, the
C-flag allows the rounding error to be evaluated with a finer resolution (see table
below).
For Boolean bit operations with only one operand, the V-flag is always cleared. For
Boolean bit operations with two operands, the V-flag represents the logical ORing of
the two specified bits.
Table 3-19
Shift Right Rounding Error Evaluation
C-Flag
V-Flag
0
0
1
1
0
1
0
1
Rounding Error Quantity
0<
No rounding error
Rounding error
Rounding error
Rounding error
<
=
>
1
/2 LSB
/2 LSB
1
/2 LSB
1
• Z-Flag: The Z-flag is normally set to 1 if the result of an ALU operation equals zero;
otherwise it is cleared.
For addition and subtraction with carry, the Z-flag is set to 1 only if the Z-flag already
contains a 1 as a result of a previous operation, and if the result of the current ALU
operation equals zero. This mechanism supports multiple precision calculations.
For Boolean bit operations with only one operand, the Z-flag represents the logical
negation of the previous state of the specified bit. For Boolean bit operations with two
operands, the Z-flag represents the logical NORing of the two specified bits. For the
prioritize operation, the Z-flag indicates whether or not the second operand was zero.
• E-Flag: End of table flag. The E-flag can be altered by instructions that perform ALU
or data movement operations. The E-flag is cleared by those instructions that can not
User’s Manual
3-78
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
be reasonably used for table search operations. In all other cases, the E-flag value
depends on the value of the source operand to signify whether or not the end of a
search table is reached. If the value of the source operand of an instruction equals the
lowest negative number that depends on the data format of the corresponding
instruction (8000H for the word data type, or 80H for the byte data type), the E-flag is
set to 1; otherwise it is cleared.
• MULIP-Flag: The MULIP-flag will be set to 1 by hardware upon the entrance into an
ISR when a multiply or divide ALU operation was interrupted before completion.
Depending on the state of the MULIP bit, the hardware decides whether a multiplication
or division must be continued or not after the end of an interrupt service. The MULIP bit
is overwritten with the contents of the stacked MULIP-flag when RETurn-from-Interruptinstruction (RETI) is executed. This normally means that the MULIP-flag is cleared again
after that.
Note: The MULIP flag is a part of the task environment. When the ISR does not return
to the interrupted multiply/divide instruction (e.g. in case of a task scheduler that
switches between independent tasks), the MULIP flag must be saved as part of
the task environment and must be updated accordingly for the new task before this
task is entered.
CPU Interrupt Status (IEN, ILVL)
The Interrupt ENable (IEN) bit makes it possible to enable (IEN=1) or disable (IEN=0)
interrupts globally. The four-bit LeVeL field (ILVL) specifies the priority of the current
CPU activity. The priority level is updated by hardware upon entry into an ISR, but it can
also be modified via software to prevent other interrupts from being acknowledged. If an
priority level 15 has been assigned to the CPU, it has the highest possible priority, and
thus the current CPU operation cannot be interrupted except by hardware traps or
external non-maskable interrupts. For details, please refer to Section 3.4 “Interrupt and
Trap Functions” .
After reset, all interrupts are disabled globally, and the lowest priority (ILVL=0) is
assigned to the initial CPU activity.
User’s Manual
3-79
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.8
Instruction Pipeline
The instruction pipeline of the C166S partitions instruction processing into four stages.
Each of these has a separate task:
1st –>FETCH: In this stage, the instruction selected by the Instruction Pointer (IP) and
the Code Segment Pointer (CSP) is fetched from either the internal local memory,
DPRAM, or external memory.
2nd –>DECODE: In this stage, the instructions are decoded and, if required, the
operand addresses are calculated and the respective operands are fetched. For all
instructions that implicitly access the system stack, the SP register is either decremented
or incremented, as specified. For branch instructions, the IP and the CSP are updated
with the desired branch target address (provided that the branch is taken).
3rd –>EXECUTE: In this stage, an operation is performed on the previously fetched
operands in the ALU. Additionally, the condition flags in the PSW register are updated
as specified by the instruction. All explicit writes to the SFR memory space, and all autoincrement or auto-decrement writes to GPRs used as indirect address pointers, are
performed during the execute stage of the instruction.
4th –>WRITE BACK: In this stage, all external operands and the remaining operands
within the DPRAM space are written back.
A particularity of the C166S are the so-called “injected instructions.” These injected
instructions are generated internally by the machine to provide the time needed to
process instructions that cannot be processed within one machine cycle. They are
automatically injected into the decode stage of the pipeline, and then they pass through
the remaining stages like every standard instruction. Program interrupts are performed
by means of injected instructions, too. Although these internally injected instructions will
not be noticed in reality, they are introduced here to ease the explanation of the pipeline
in the following.
3.8.1
Particular Pipeline Effects
Since up to 4 different instructions are processed simultaneously, additional hardware
has been included in the C166S to prevent a loss of performance when dealing with all
causal dependencies on instructions in different pipeline stages. This extra hardware
resolves most of the possible conflicts (e.g. multiple usage of buses) in a time-optimized
way, preventing the pipeline dependencies from becoming noticeable to the user in most
cases. However, in some rare cases, attention from the programmer is required
specifically because the C166S is a pipelined machine.
User’s Manual
3-80
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.8.1.1
General considerations
Due to pipeline, Read operation, performed by next instruction, can takes place before
a Write operation, performed by the earlier instruction. While this fact can lead to some
general problems, an extra CPU hardware - the forwarding mechanism - deals with the
operand read/write addresses, and also controls the pipeline when needed. Especially,
if there are sequential write and read operations on the same address, the read is hold
until write is executed. Thus in most cases the pipeline behavior is resolved and made
transparent. So the user is assured, that after writing to a location, next read from the
same location will return the correct result.
However, there are write operations, which are changing some important parameters of
the system: configuration, data pages, stack location, register banks etc. If they are not
followed by a read from the same address, the CPU will not recognize the need of
holding the pipeline while write is finished. So, the effect of this operation will not be seen
immediately within next instruction.
After writing to a memory location (MEMLOC), non-critical instruction(s) must follow,
before the first instruction, which will be affected by that write operation:
In
In+1
In+d
:Writing to MEMLOC
:Non-critical instruction(s)
:....
:Any instruction
;MEMLOC still holds the old value
;new MEMLOC-VALUE is already effective
Non-critical instruction means instruction, which execution does not depend on the
writing to MEMLOC. The most “non-critical” is NOP instruction, as doing nothing. The
programmer has to be always aware not to place some critical instruction within that gap
of one (or more) machine cycles, while the write operation still has no effect. Also, the
delays caused by pipeline conflicts can be used for other instructions in order to optimize
performance.
3.8.1.2
Specific cases with core registers
When writing to an internal core register, the time needed before the new value becomes
effective depends only on the pipeline. This time is usually one, as exception two
machine cycles, what means one or two non-critical instructions to be executed. Below
are described some specific situations when changing important system registers.
User’s Manual
3-81
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
• Address Pointer Updating
Indirect addressing modes use a GPR value to generate the address of the source and/
or destination operand. If this GPR is updated explicitly by the preceding instruction, one
NOP instruction is automatically inserted.
In
:ADD R0,#0002h
Iinject:NOP
In+1 :MOV R2,[R0]
;increment address pointer GPR 0
;automatically injected NOP
;use GPR 0 for indirect addressing
To improve performance, an instruction not using this new GPR as a destination operand
can be inserted between an explicit GPR-changing and a subsequent instruction using
an indirect addressing mode.
In
In+1
In+2
:ADD R0,#0002h
:....
:MOV R2,[R0]
;increment address pointer GPR 0
;must not be an instruction updating GPR 0
;use GPR 0 for indirect addressing
• Context Pointer Updating
An instruction that calculates a physical GPR operand address via the CP register is
incapable of using a new CP value that is to be updated by the preceding instruction.
Thus, to make sure that the new CP value is used, at least two instructions must be
inserted between an instruction that changes the CP and a subsequent instruction that
uses the GPR, as shown in the following example:
In
In+1
In+2
In+3
:SCXT CP,#0FC00h
:....
:....
:MOV R0,#dataX
;select a
;must not
;must not
;write to
new context
be an instruction using a GPR
be an instruction using a GPR
GPR 0 in the new context
• Data Page Pointer Updating
An instruction that calculates a physical operand address via a particular DPPn (n=0
to n=3) register is not capable of using a new DPPn register value that is to be updated
by the preceding instruction. Thus, to make sure that the new DPPn register value is
used, at least one instruction must be inserted between a DPPn-changing instruction
and a subsequent instruction that implicitly uses DPPn via a long or indirect addressing
mode, as shown in the following example:
In
In+1
In+2
:MOV DPP0,#4
;select data page 4 via DPP0
:....
;must not be an instruction using DPP0
:MOV DPP0:0000H,R1;move contents of R1 to address location 01’0000H
;(in data page 4) supposed segment. is enabled
User’s Manual
3-82
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
• Explicit Stack Pointer Updating
Neither the RET nor POP instruction is capable of correctly using a new SP register
value, which is to be updated by an immediately preceding instruction. Thus, in order to
use the new SP register value without erroneously performed stack accesses, at least
one instruction must be inserted between an instruction that explicitly writes to SP, and
any of the afore mentioned subsequent instructions that implicitly use the SP, as shown
in the following example:
In
In+1
:MOV SP,#0FA40H
:....
In+2
:POP
R0
;select a
;must not
;from the
;pop word
new top of stack
be an instruction popping operands
system stack
value from new top of stack into R0
Furthermore none of the RETI, RETS or RETP instructions are capable of correctly using
a new SP register value, which is to be updated by one or both of the two immediately
preceding instructions. Thus, in order to use the new SP register value without
erroneously performed stack accesses, at least two instructions must be inserted
between an instruction that explicitly writes to SP, and any of the afore mentioned
subsequent instructions that implicitly use the SP, as shown in the following example:
In
In+1
:MOV SP,#0FA40H
:....
In+2
:....
In+3
:RETP
R0
;select a new top of stack
;must not be an instruction popping operands
;from the system stack
;must not be an instruction popping operands
;from the system stack
;return from subroutine and pop word value from
;new top of stack into R0
Most of the potential conflicts, if a change of SP value is immediately followed by a
writing to the stack (instructions PUSH, CALL, SCXT, TRAP) are solved internally by
CPU logic. The only exceptions are CALLS and PCALL instructions, which require one
preceding instruction not using updated SP, as shown below:
In
In+1
In+2
:MOV SP,#0FA40H
:....
;select a new top of stack
;must not be an instruction using
;the new address of system stack
:PCALL R3,sub_addr ;push R3 value and return address at the new
;top of stack and call subroutine
User’s Manual
3-83
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
• Controlling Interrupts
Software modifications (implicit or explicit) of the PSW are done in the execute phase of
instructions. In order to maintain fast interrupt responses, however, the current interrupt
prioritization round does not consider these changes, i.e., an interrupt request may be
acknowledged after the instruction that disables interrupts via IEN or ILVL, or after the
following instructions. Therefore, time-critical instruction sequences should not begin
directly after the instruction disabling interrupts, as shown in the following examples:
INTERRUPTS_OFF:
BCLR
IEN
<Instr non-crit>
<Instr 1st-crit>
. . .
<Instr last-crit>
INTERRUPTS_ON:
BSET
IEN
CRITICAL_SEQUENCE:
ATOMIC #3
BCLR
IEN
. . .
BSET
IEN
;globally disable interrupts
;non-critical instruction
;begin of uninterruptable critical sequence
;end of uninterruptable critical sequence
;globally re-enable interrupts
;immediately block interrupts
;globally disable interrupts
;here is the uninterruptable sequence
;globally re-enable interrupts
Note: The described delay of 1 instruction also applies for enabling the interrupt system;
i.e., no interrupt requests are acknowledged until the instruction following the
enabling instruction.
• External Memory Access Sequences
The effect described here will only become noticeable when watching the external
memory access sequences on the external bus (e.g., by means of a logic analyzer).
Different pipeline stages can simultaneously put a request on the External Bus Controller
(EBC). The sequence of instructions processed by the CPU may diverge from the
sequence of the corresponding external memory accesses performed by the EBC, due
to the predefined priority of external memory accesses:
1. Write data
2. Fetch code
3. Read data
User’s Manual
3-84
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
• Initialization of Port Pins
Modifications of the direction of port pins (input or output) become effective only after the
instruction following the modifying instruction. As bit instructions (BSET, BCLR) use
internal read-modify-write sequences accessing the whole port, instructions modifying
the port direction should be followed by an instruction that does not access the same port
(see example below).
PORT_INIT_WRONG:
BSET
DP3.13
BSET
P3.9
PORT_INIT_RIGHT:
BSET
DP3.13
NOP
BSET
P3.9
;change direction of P3.13 to output
;P3.13 is still input,
;rd-mod-wr reads pin P3.13
;change direction of P3.13 to output
;any instruction not accessing port 3
;P3.13 is now output,
;rd-mod-wr reads P3.13’s output latch
• Changing the System Configuration
The instruction following an instruction that changes the system configuration via register
SYSCON (e.g. the mapping of the internal local memory, segmentation, stack size)
cannot use the new resources (e.g. local memory or stack). In these cases, an
instruction that does not access these resources should be inserted. Code accesses to
the new local memory area are only possible after an absolute branch to this area.
Note: As a rule, instructions that change local memory mapping should be executed
from DPRAM or external memory.
• BUSCON/ADDRSEL
The instruction following an instruction that changes the properties of an external
address area cannot access operands within the new area. In these cases, an instruction
that does not access this address area should be inserted. Code accesses to the new
address area should be made after an absolute branch to this area.
Note: As a rule, instructions that change external bus properties should not be executed
from the external memory area.
User’s Manual
3-85
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.8.1.3
Common portable solution
When writing to an external memory location, the time needed before the new value
becomes effective depends also on the overall system performance. In general more
extra cycle(s) will be needed in case of lower peripheral bus speed to cover the delay
additionally caused. Special attention has to be paid, when writing to external SFRs,
such as peripheral control registers, which have effect over the system behavior - for
example enabling/disabling transfer, interrupts etc.
To assure that the critical write operation has been completed, before making use of it,
it is recommended next to make a read operation on the same memory location. The
reasons are:
• the CPU will recognize the need of holding pipeline while the write operation is
completed;
• as reading from the same location, execution-time scales in respect to bus speed. So
there is no need to think about how fast that bus is and one instruction is enough in all
cases, to assure effectiveness of that write for the next instructions.
User’s Manual
3-86
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.8.2
Instruction State Times
Instruction pipelining usually reduces the average instruction processing time (typically
within a range of 1-4 machine cycles). However, there are some rare cases, where a
particular pipeline situation causes the processing time for a single instruction to be
extended either by a half or by one machine cycle. Although this additional time
represents only a tiny part of the total program execution time, it might be of interest to
avoid these pipeline-caused time delays in time-critical program modules.
The time to execute an instruction depends on where the instruction is fetched from, and
where possible operands are read from or written to. The fastest processing mode of the
C166S is to execute a program fetched from the internal code memory. In that case,
most of the instructions can be processed within just one machine cycle, which is also
the general minimum execution time.
All external memory accesses are performed by the EBC, which works in parallel with
the CPU. This section summarizes execution times.
The table below shows the minimum execution times required to process an instruction
fetched from the internal local memory, the DPRAM, or external memory. These
execution times apply to most instructions except some of the branches, the
multiplication, the division, and a special move instruction. In case of internal local
memory program execution, the execution time does not depend on the instruction
length except for some special branch situations. The numbers in the table are in units
of CPU clock cycles, and assume no waitstates.
Table 3-20
Minimum Execution Times
Instruction Fetch
Memory Area
Word Operand Access
Word
Instruction
Doubleword
Instruction
Read from
Write to
Internal local memory
11)
11)
11)
11)
DPRAM
11)
2
11)
11)
16-bit demux bus
2
4
2
2
16-bit mux bus
3
6
3
3
8-bit demux bus
4
8
4
4
8-bit mux bus
6
12
6
6
1)
Minimum execution time for instruction fetch and operand accesses. Nevertheless the minimum execution
time of an instruction remains 2 clock cycles (one machine cycle).
Execution from the DPRAM provides flexibility in terms of loadable and modifiable code.
The execution time from external memory depends strongly on the selected bus mode
and the programming of the bus cycles (waitstates).
User’s Manual
3-87
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
The operand and instruction accesses listed below can extend the execution time of an
instruction:
•
•
•
•
•
•
•
Internal Local Memory operand accesses (same for byte and word operand accesses)
DPRAM operand reads via indirect addressing modes
Internal SFR operand reads immediately after writing
External operand reads
External operand writes
Jumps to non-aligned double word instructions in the internal local memory space
Testing branch conditions immediately after PSW writes
User’s Manual
3-88
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.9
Dedicated CSFRs
The Constant Zeros Register ZEROS
All bits of this bit-addressable register are fixed at 0 by hardware. This register is readonly. Register ZEROS can be used as a register-addressable constant of all zeros for bit
manipulation or mask generation. It can be accessed via any instruction capable of
accessing an SFR.
Zeros
Constant Zeros Register
SFR(FF1CH,8EH)
Reset value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Field
Bits
Type Description
0
[all]
r
Fixed at Zero
The Constant Ones Register ONES
All bits of this bit-addressable register are fixed at 1 by hardware. This register is readonly. Register ONES can be used as a register-addressable constant of all ones for bit
manipulation or mask generation. It can be accessed via any instruction which is capable
of accessing an SFR.
ONES
Constant Ones Register
SFR(FF1EH,8FH)
Reset value: FFFFH
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Field
Bits
Type Description
1
[all]
r
User’s Manual
Fixed at 1
3-89
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
CPU Identification register CPUID
This 16-bit register contains the module and revision number of the implemented C166S
module.
CPUID
CPU Identification Register
15
14
13
12
11
10
ESFR(F00CH,E-06H)
9
8
7
6
Reset value: 04??H
5
4
3
CPUREVNO
CPUMODNO
r
r
2
Field
Bits
Type Description
CPUREVNO
[15:8]
r
Module Number
04H C166S core module number
CPUMODNO
[7:0]
r
Version Number
Version Number, starts with 01H and is
incremented with every new core version
User’s Manual
3-90
1
0
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.10
Summary of CPU Registers
This section summarizes all registers in the C166S. There are two kind of registers, the
General Purpose Registers (GPR) and the CPU-Special Function Registers (CSFR).
The GPRs are the working registers of the arithmetic and logic operations and may be
also used as address pointers indirect addressing modes. The CSFRs are the control
registers of the C166S.
For easy reference, the CSFRs are listed in this section by address (to identify a register
at a given. address) and by name (to find an address of a specific register).
3.10.1
General Purpose Registers
The GPRs are the working registers of the C166S. All GPRs are bit addressable.
Table 3-21
Addressing modes to access Word-GPRs
Name Physical 8-Bit
4-Bit
Description
Address Address Address
Reset
Value
R0
(CP)+0
F0H
0H
General-Purpose word Register R0
UUUUH
R1
(CP)+2
F1H
1H
General-Purpose word Register R1
UUUUH
R2
(CP)+4
F2H
2H
General-Purpose word Register R2
UUUUH
R3
(CP)+6
F3H
3H
General-Purpose word Register R3
UUUUH
R4
(CP)+8
F4H
4H
General-Purpose word Register R4
UUUUH
R5
(CP)+10 F5H
5H
General-Purpose word Register R5
UUUUH
R6
(CP)+12 F6H
6H
General-Purpose word Register R6
UUUUH
R7
(CP)+14 F7H
7H
General-Purpose word Register R7
UUUUH
R8
(CP)+16 F8H
8H
General-Purpose word Register R8
UUUUH
R9
(CP)+18 F9H
9H
General-Purpose word Register R9
UUUUH
R10
(CP)+20 FAH
AH
General-Purpose word Register R10 UUUUH
R11
(CP)+22 FBH
BH
General-Purpose word Register R11 UUUUH
R12
(CP)+24 FCH
CH
General-Purpose word Register R12 UUUUH
R13
(CP)+26 FDH
DH
General-Purpose word Register R13 UUUUH
R14
(CP)+28 FEH
EH
General-Purpose word Register R14 UUUUH
The first 8 GPRs (R7...R0) may be also accessed byte-wise. Unlike SFRs, writing to a
GPR byte does not affect another byte of the GPR.
User’s Manual
3-91
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
The following byte-wise accessible registers have special names. .
Table 3-22
Addressing modes to access Byte-GPRs
Name Physical 8-Bit
4-Bit
Description
Address Address Address
Reset
Value
RL0
(CP)+0
F0H
0H
General-Purpose byte Register RL0
UUH
RH0
(CP)+1
F1H
1H
General-Purpose byte Register RL1
UUH
RL1
(CP)+2
F2H
2H
General-Purpose byte Register RL2
UUH
RH1
(CP)+3
F3H
3H
General-Purpose byte Register RL3
UUH
RL2
(CP)+4
F4H
4H
General-Purpose byte Register RL4
UUH
RH2
(CP)+5
F5H
5H
General-Purpose byte Register RL5
UUH
RL3
(CP)+6
F6H
6H
General-Purpose byte Register RL6
UUH
RH3
(CP)+7
F7H
7H
General-Purpose byte Register RL7
UUH
RL4
(CP)+8
F8H
8H
General-Purpose byte Register RL8
UUH
RH4
(CP)+9
F9H
9H
General-Purpose byte Register RL9
UUH
RL5
(CP)+10 FAH
AH
General-Purpose byte Register RL10 UUH
RH5
(CP)+11 FBH
BH
General-Purpose byte Register RL11 UUH
RL6
(CP)+12 FCH
CH
General-Purpose byte Register RL12 UUH
RH6
(CP)+13 FDH
DH
General-Purpose byte Register RL13 UUH
RL7
(CP)+14 FEH
EH
General-Purpose byte Register RL14 UUH
RH7
(CP)+15 FFH
FH
General-Purpose byte Register RL15 UUH
User’s Manual
3-92
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.10.2
Core Special Function Registers Ordered by Name
The following table lists all CSFRs in alphabetical order. Bit-addressable CSFRs are
marked with the letter “b” in column “Name”.
CSFRs within the Extended CSFR-Space (ECSFRs) are marked with the letter “E” in
column “8-Bit Address”.
Name
Physical 8-Bit
Address Address
Description
Reset
Value
CP
FE10H
08H
Context Pointer
FC00H
CPUID
F00CH
E-06H
CPU Identification Register
CSP
FE08H
04H
Code Segment Pointer
(8 bits, not directly writable)
0000H
DPP0
FE00H
00H
Data Page Pointer 0 (10 bits)
0000H
DPP1
FE02H
01H
Data Page Pointer 1 (10 bits)
0001H
DPP2
FE04H
02H
Data Page Pointer 2 (10 bits)
0002H
DPP3
FE06H
03H
Data Page Pointer 3 (10 bits)
0003H
MDCb
FF0EH
87H
Multiply Divide Control Register
0000H
MDH
FE0CH
06H
Multiply Divide High Word
0000H
MDL
FE0EH
07H
Multiply Divide Low Word
0000H
ONESb
FF1EH
8FH
Constant Value 1’s Register (read only)
FFFFH
PSWb
FF10H
88H
Program Status Word
0000H
SP
FE12H
09H
Stack Pointer
FC00H
STKOV
FE14H
0AH
Stack Overflow Register
FA00H
STKUN
FE16H
0BH
Stack Underflow Register
FC00H
SYSCON
FF12H
89H
System/CPU Control Register
TFRb
FFACH
D6H
Trap Flag Register
0000H
ZEROSb
FF1CH
8EH
Constant Value 0’s Register (read only)
0000H
YYYYH
2)
1)
YY: defined by implemented CPU version
2)
YYYY: defined by reset and system configuration
User’s Manual
04YYH
1)
3-93
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.10.3
Core Special Function Registers ordered by Address
The following table lists all CSFRs which are implemented in the C166S ordered by their
physical address. Bit-addressable CSFRs are marked with the letter “b” in column
“Name”.
CSFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in
column “8-Bit Address”.
Name
Physical 8-Bit
Description
Address Address
CPUID
F00CH
E-06H
CPU Identification Register
DPP0
FE00H
00H
Data Page Pointer 0 (10 bits)
0000H
DPP1
FE02H
01H
Data Page Pointer 1 (10 bits)
0001H
DPP2
FE04H
02H
Data Page Pointer 2 (10 bits)
0002H
DPP3
FE06H
03H
Data Page Pointer 3 (10 bits)
0003H
CSP
FE08H
04H
Code Segment Pointer
(8 bits, not directly writable)
0000H
MDH
FE0CH
06H
Multiply Divide High Word
0000H
MDL
FE0EH
07H
Multiply Divide Low Word
0000H
CP
FE10H
08H
Context Pointer
FC00H
SP
FE12H
09H
Stack Pointer
FC00H
STKOV
FE14H
0AH
Stack Overflow Register
FA00H
STKUN
FE16H
0BH
Stack Underflow Register
FC00H
MDCb
FF0EH
87H
Multiply Divide Control Register
0000H
PSWb
FF10H
88H
Program Status Word
0000H
SYSCON
FF12H
89H
System/CPU Control Register
YYYYH
ZEROSb
FF1CH
8EH
Constant Value 0’s Register (read only)
0000H
ONESb
FF1EH
8FH
Constant Value 1’s Register (read only)
FFFFH
TFRb
FFACH
D6H
Trap Flag Register
0000H
04YYH
1)
2)
1)
YY: defined by implemented CPU version
2)
YYYY: defined by reset and system configuration
User’s Manual
Reset
Value
3-94
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
3.10.4
Register Overview C166S Interrupt and Peripheral Event
Controller
The following table lists all xSFRs which are implemented in the C166S Interrupt and
Peripheral Event Controller.
Table 3-23
Register Overview - C166S Interrupt and Peripheral Event Controller
Register Name
Register Description
Module Block
PECSN0
PEC Pointer 0 Segment Address Reg.
PEC Pointer
PECSN1
PEC Pointer 1 Segment Address Reg.
PEC Pointer
PECSN...
PEC Pointer ... Segment Address Reg.
PEC Pointer
PECSN7
PEC Pointer 7 Segment Address Reg.
PEC Pointer
PECSN81)
PEC Pointer 8 Segment Address Reg.
PEC Pointer
PECSN...1)
PEC Pointer ... Segment Address Reg.
PEC Pointer
PECSN151)
PEC Pointer 15 Segment Address Reg. PEC Pointer
PECC0
PEC Channel 0 Control Register
PEC Control
PECC...
PEC Channel ... Control Register
PEC Control
PECC7
PEC Channel 7 Control Register
PEC Control
PECC81)
PEC Channel 8 Control Register
PEC Control
PECC...1)
PEC Channel ... Control Register
PEC Control
PECC151)
PEC Channel 15 Control Register
PEC Control
IRQ0IC1)
Interrupt 0 Control Register
Arbitration Control
...
...
...
1)
IRQ63IC
Interrupt 63 Control Register
Arbitration Control
IRQ64IC1)
Interrupt 64 Control Register
Arbitration Control
IRQ65IC1)
Interrupt 65 Control Register
Arbitration Control
...
...
...
IRQ111IC1)
Interrupt 111 Control Register
Arbitration Control
1)
The implementation and assignment of these Interrupt/PEC Control Register is product specific.
User’s Manual
3-95
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Central Processing Unit
User’s Manual
3-96
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
4
Memory Organization
The memory space of the C166S has a “Von Neumann” architecture. This means that
code and data are accessed within the same linear address space. All of the physically
separated memory areas, including internal ROM/FLASH/DRAM (where integrated),
DPRAM, the internal Special Function Register (SFR) and Extended Special Function
Register (ESFR) areas, and external memory are mapped into one common address
space.
255
FF’FFFFH
255...2
254...129
128
01’FFFFH
80’0000H
Begin of
Local Memory
above 32KB
127
40’0000H
63
62...12
11
0A’FFFFH
10
8
08’0000H
Data Page 3
7
6
4
04’FFFFH
3
2
1
0
01’FFFFH
Data Page 2
Internal
Local Memory
Area
00’0000H
00’0000H
Total Address Space
16 MByte, Segments 255...0
User’s Manual
Alternate
Local Memory
Area
01’0000H
5
Figure 4-1
01’8000H
9
Segment 0
External Addressing Capability
16 MByte
64
Segment 1
126...65
Segments 1 and 0
64 + 64 KByte
C166S Address Space Overview
4-1
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
The C166S has a total addressable memory space of 16 MBytes. This address space is
arranged as 256 segments of 64 KBytes each, and each segment is again subdivided
into four data pages of 16 KBytes each (see Figure 4-1).
Most internal memory areas are mirrored into segment 0, the system segment. The
upper 4 KBytes of segment 0 (00’F000H-00’FFFFH) are the SFRs and ESFRs and the
DPRAM areas. The lower 32 KByte of segment 0 (00’0000H-00’7FFFH) may be
occupied by a part of the on-chip program memory and is called the internal Local
Memory (LM) area. This LM area can be remapped to segment 1 (01’0000H-01’7FFFH)
to enable external memory access in the lower half of segment 0, or the internal LM may
be disabled completely.
Code and data may be stored in any part of the internal memory areas except for the
SFR blocks, which may be used for control/data, but not for instructions.
Note: Accesses to the internal LM area on devices without LM will produce
unpredictable results.
User’s Manual
4-2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
4.1
Data Organization in Memory
Bytes are stored at even or odd byte addresses. Words are stored in ascending memory
locations with the low byte at an even byte address, followed by the high byte at the next
odd byte address. Instruction double-words are stored in ascending memory locations
as two subsequent words, without any restrictions (non-aligned). Single bits are always
stored in the specified bit position at a word address. The memory and registers store
data and instructions in little-endian byte order (the least significant bytes are at lower
addresses) The byte ordering is illustrated in Figure 4-2. Bit position 0 is the least
significant bit of the byte at an even byte address, and bit position 15 is the most
significant bit of the byte at the next odd byte address. Bit addressing is supported for a
part of the SFRs, a part of the DPRAM and for the General-Purpose Registers (GPRs).
º
xxxx’xxxAH
1 1 … Bits …
8
xxxx’xxx9H
7 6 … Bits …
0
xxxx’xxx8H
Byte
xxxx’xxx7H
Byte
xxxx’xxx6H
Word (High Byte)
xxxx’xxx5H
Word (Low Byte)
xxxx’xxx4H
Double Word (High
xxxx’xxx3H
Double Word (Third)
xxxx’xxx2H
Double
Word
xxxx’xxx1H
(Low
xxxx’xxx0H
Double
Word
º
Figure 4-2
xxxx’xxxFH
Storage of Words, Byte and Bits in a Byte Organized Memory
Note: Byte units forming a single word must always be stored within the same physical
(internal, external, ROM, RAM) and organizational (page, segment) memory area.
User’s Manual
4-3
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
4.2
Internal Local Memory Area
The C166S reserves an address area of variable size (depending on the device
configuration) for on-chip Local Memory (LM). The internal LM can be ROM, SRAM,
flash or DRAM.
The internal LM may be enabled, disabled or mapped into segment 0 or segment 1
under software control.
Internal LM accesses are enabled or disabled globally via bit ROMEN in the SYSCON
register. This bit is set during reset according to the level on external pin EA, or may be
altered via software. If enabled, the internal lower 32K of LM area occupies the lower
32 KByte of either segment 0 or segment 1. This mapping is controlled by bit ROMS1 in
register SYSCON.
Note: The size of the internal LM area may be independent of the size of the actual
implemented LM. Devices with less than 32 KBytes of LM or with no LM at all will
have this 32-KByte area occupied if the LM is enabled. Devices with a larger LM
provide the mapping option only for the internal LM area.
Devices with an LM size above 32 KByte expand the LM area from the middle of
segment 1, i.e., starting at address 01’8000H.
The internal LM can be used for both code (instructions) and data (constants, tables,
etc.) storage.
Code fetches are always made on even byte addresses. The highest possible code
storage location in the internal LM is either xx’xxFEH for single word instructions, or
xx’xxFCH for double word instructions. The respective location must contain a branch
instruction (unconditional), because sequential boundary crossing from internal LM to
external memory is not supported and causes erroneous results.
Any word and byte data read accesses may use the indirect or long 16-bit addressing
modes. There is no short-addressing mode for the LM operands. Any word data access
is made to an even byte address. Any double-word access is made to a modulo-4
address (even-word address). The highest possible word data storage location in the LM
is xxxx’xxFEH; the highest double-word location is xxxx’xxFCH.
The internal LM is not provided for single-bit storage, and therefore it is not bitaddressable.
Note: The x in the locations above depend on the available internal LM.
User’s Manual
4-4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
4.3
DPRAM and SFR-Area
The C166S differentiates between the internal data memory (DPRAM) and the internal
peripheral areas. The DPRAM and the SFR areas are located within data page 3, and
provide fast accesses using one dedicated Data Page Pointer (DPP) (see Figure 4-3).
Note: Code accesses are not possible from the SFR areas.
4.3.1
Data Memories
The DPRAM is a volatile memory available mainly for data storage. It serves for:
–
–
–
–
GPR banks
Variable and other data storage
System and user stacks
PEC source and destination pointers
A 3-KByte memory area (00‘F200H-00’FE00H) is reserved for the DPRAM. The upper
256 Bytes of the DPRAM (00’FD00H-00’FDFFH) and the GPRs of the current bank are
provided for single-bit storage, and thus they are bit addressable (see shaded blocks in
Figure 4-3). Any word and byte data in the DPRAM can be accessed via indirect or long
16-bit addressing modes if the selected DPP register points to data page 3. Any word
data access is made on an even byte address. The highest possible word data storage
location in the DPRAM is 00’FDFEH.
The highest possible code storage location in the DPRAM is either 00’FDFEH for singleword instructions, or 00’FDFCH for double-word instructions (but this is the bitaddressable area, which should not be used for code). The respective location must
contain a branch instruction (unconditional), because sequential boundary crossing from
DPRAM to the SFR area is not supported and causes erroneous results.
4.3.2
Special Function Register Areas
The functions of the CPU, the bus interface, the I/O ports, and the on-chip peripherals of
the C166S are controlled via a number of SFRs. These SFRs are arranged within two
512-Byte areas. The first register block, the SFR area, is located in the 512 Bytes above
the DPRAM (00’FFFFH-00’FE00H). The second register block, the ESFR area, is located
in the 512 Bytes below the DPRAM (00’F1FFH-00’F000H).
SFRs can be addressed via indirect and long 16-bit addressing modes. Using an 8-bit
offset together with an implicit base address makes it possible to address word SFRs
and their respective low bytes. However, this does not work for the respective high bytes.
User’s Manual
4-5
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
00’FFFFH
00’FFFFH
RAM / SFR
Area
Data Page 3
SFR
Area
00’F000H
00’FE00H
00’E000H
DPRAM
00’FD00H
External
00’C000H
Data Page 2
00’8000H
DPRAM
Data Page 1
Internal
Program
Memory
00’4000H
00’F200H
Data Page 0
ESFR
Area
System Segment 0
64KByte
Figure 4-3
00’F000H
00´0000H
DPRAM and SFR Areas
Note: High-byte accesses of SFRs using the 8-bit offset addressing mode are not
possible.
Note: Writing to any byte of an SFR causes the non-addressed complementary byte to
be cleared.
Note: GPRs can be accessed using the 8-bit offset addressing mode, but the GPRs are
not mapped into the SFR and ESFR memory area. Using the corresponding long
address instead of a GPR access executes an internal peripheral bus access.
The upper half of each register block is bit-addressable, so the respective control/status
bits can be modified directly, or checked using bit addressing.
User’s Manual
4-6
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
When accessing registers in the ESFR area using 8-bit addresses or direct bit
addressing, the EXTend Register (EXTR) instruction is required before accessing
registers in the ESFR area, in order to switch the short-addressing mechanism from the
standard SFR area to the ESFR area. This is not required for 16-bit and indirect
addresses. The GPRs R15...R0 are duplicated, i.e., they are accessible within both
register blocks via short 2-, 4- or 8-bit addresses without switching.
Example 1:
EXTR
MOV
BFLDL
BSET
MOV
#4
ODP2, #data16
DP6, #mask, #data8
DP6.7
T8REL, R1
;------MOV
;------------------T8REL, R1
;Switch to ESFR area for the next 4 instructions
;ODP2 (ESFR register) uses 8-bit reg addressing
;DP6 (ESFR register) bit addressing for bit fields
;DP6 (ESFR register) bit addressing for single bits
;T8REL uses 16-bit address, R1 is duplicated…
;…and also accessible via the ESFR mode
;(EXTR is not required for this access)
;The scope of the EXTR #4 instruction ends here!
;T8REL uses 16-bit address, R1 is duplicated…
;…and does not require switching
In order to minimize the switching of SFR banks, the ESFR area holds registers that are
mainly required for initialization and mode selection. Registers that need to be accessed
frequently are allocated to the standard SFR area, wherever possible.
Note: The tools are equipped to monitor accesses to the ESFR area and will
automatically insert EXTR instructions, switch the SFR bank address, or issue a
warning in case of missing or excessive EXTR instructions.
4.3.3
PEC Source and Destination Pointers
The 16 (24/32) word locations for the 8 (12/16) PEC channels in the DPRAM from
00’FCE0h (00’FCD0h/00’FCC0h) to 00’FCFEh (just below the bit-addressable section)
are provided as source and destination address pointers for data transfers on the PEC
channels. Each channel uses a pair of pointers stored in two subsequent word locations
with the SouRCe Pointer (SRCPx) on the lower and the DeSTination Pointer (DSTPx)
on the higher word address.
Whenever a PEC data transfer is performed, the pair of SRCPx and DSTPx selected by
the specified PEC channel number is accessed independent of the current DPP register
contents; also, the locations referred to by these pointers are accessed independently of
the current DPP register contents. If a PEC channel is not used, the corresponding
pointer location area is available and can be used for word or byte data storage or for
instructions.
For more details about use of SRCPx and DSTPx for PEC data transfer, see “Interrupt
and Exception Execution” Section 3.4.
User’s Manual
4-7
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
4.4
External Memory Space
The C166S CPU can use an address space of up to 16 MBytes. Only parts of this
address space are occupied by the internal LM, DPRAM and the IO/SFR area. All
addresses not used for this kind of on-chip memory or for registers may reference
external memory locations. This external memory space is accessed via the Bus
Controller (BC).
The BC is the bus-bridge between the C166S CPU and the external/internal bus
interfaces. The external bus interface allows access to external (off-chip) peripherals and
additional off-chip volatile and non-volatile memories. The external bus interface may
further limit the amount of addressable off-chip memory. The internal bus interface
provides an internal system bus that allows the on-chip integration of customer-specific
peripherals, volatile and non-volatile memories. The availability of the internal and
external bus interfaces depends on the functionality of the integrated BC.
4.4.1
External data accesses
External word and byte data can be accessed only via indirect or long 16-bit addressing
modes using one of the four DPP registers. There is no short-addressing mode for
external operands. Any word data access is made to an even byte address, and doubleword accesses to modulo-4 byte addresses (even word address).
External memory is not provided for single-bit storage and therefore it is not bitaddressable.
User’s Manual
4-8
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
4.5
Crossing Memory Boundaries
The address space of the C166S CPU is divided implicitly into equally-sized blocks of
different granularity and into logical memory areas. Crossing the boundaries between
these blocks (code or data) or areas requires special attention to ensure that the
controller executes the desired operations.
Memory Areas are partitions of the address space that represent different kinds of
memory (if provided at all). These memory areas are the DPRAM, the internal IO, the
internal LM (if available), and the external memory.
Accessing subsequent data locations that belong to different memory areas is not fully
supported, and may therefore lead to erroneous results. There is no problem if the
memory boundaries are word-aligned. However, when executing code, the different
memory areas (internal memory areas and external memory) must be switched explicitly
via branch instructions. Sequential boundary crossing is not supported and may lead to
erroneous results.
Segments are contiguous 64-KByte blocks. They are referenced via the Code Segment
Pointer (CSP) for code fetches, and via an explicit segment number for data accesses
overriding the standard DPP scheme.
During code fetching, segments are not changed automatically, but rather must be
switched explicitly. The instructions JMPS, CALLS and RETS will do this. Larger
sequential programs make sure that the highest used code location of a segment
contains an unconditional branch instruction to the next following segment, to prevent
the prefetcher from trying to leave the current segment.
Data Pages are contiguous 16-KByte blocks. They are referenced via the Data Page
Pointers DPP3...0 and via an explicit data page number for data accesses overriding the
standard DPP scheme. Each DPP register can select one of the possible 1024 data
pages. The DPP register that is used for the current access is selected via the two upper
bits of the 16-bit data address. Subsequent 16-bit data addresses that cross the 16KByte data page boundaries will use different data page pointers, while the physical
locations need not be contiguous within memory.
User’s Manual
4-9
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
4.6
System Stack
The system stack must be defined within the DPRAM. The size of the system stack is
controlled by bitfield STKSZ in register SYSCON (see table below).
Table 4-1
System stack size
<STKSZ>
Stack Size (Words) DPRAM Addresses (Words)
000B
256
00’FBFEH-00’FA00H (Default after Reset)
001B
128
00’FBFEH-00’FB00H
010B
64
00’FBFEH-00’FB80H
011B
32
00’FBFEH-00’FBC0H
100B
512
00’FBFEH-00’F800H
101B
---
Reserved. Do not use this combination.
110B
---
Reserved. Do not use this combination.
111B
1536
00’FDFEH-00’F200H (Note: No circular stack)
For all system stack operations, the stack memory is accessed via the Stack Pointer
(SP). The system stack implementation in the C166S is from high to low memory. The
system stack grows downward as it is filled. The SP register is decremented first each
time data is pushed on the system stack, and incremented after each time the data is
pulled from the system stack. Only word accesses are supported to the system stack.
The SP points to the address of the latest system stack entry, rather than to the next
available system stack address.
A STacK OVerflow (STKOV) register and a STacK UNderflow (STKUN) register are
provided to control the lower and upper limits of the selected stack area. These two stack
boundary registers can be used not only for protection against data destruction, but also
to implement a circular stack with hardware-supported system stack flushing and filling
(except for option STKSZ=111).
4.6.1
Data Organization in General Purpose Registers
The memory-mapped GPRs use a block of 16 consecutive words within the DPRAM
Segment 0. The Context Pointer (CP) register determines the base address of the
currently active register bank. This register bank may consist of up to 16 word GPRs (R0,
R1, …, R15), and/or up to 16 byte GPRs (RL0, RH0, …, RL7, RH7). The 16-byte GPRs
are mapped onto the first 8 word GPRs (see table below).
In contrast to the system stack, a register bank grows from lower towards higher address
locations and occupies a maximum space of 32 bytes. The GPRs are accessed via short
2-, 4- or 8-bit addressing modes using the CP register as base address (independent of
User’s Manual
4-10
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
the current DPP register contents). Additionally, each bit in the currently active register
bank can be accessed individually.
The C166S supports register bank (context) switching. Multiple memory-mapped
register banks can physically exist within the DPRAM at the same time. Only the register
bank selected by the CP register is active at a given time, however. Selecting a new
active register bank is simply done by updating the CP register.
Figure 4-4
Mapping of General-Purpose Registers to DPRAM Addresses
DPRAM Address
Byte Registers
Word Register
<CP> + 1EH
---
R15
<CP> + 1CH
---
R14
<CP> + 1AH
---
R13
<CP> + 18H
---
R12
<CP> + 16H
---
R11
<CP> + 14H
---
R10
<CP> + 12H
---
R9
<CP> + 10H
---
R8
<CP> + 0EH
RH7 RL7
R7
<CP> + 0CH
RH6 RL6
R6
<CP> + 0AH
RH5 RL5
R5
<CP> + 08H
RH4 RL4
R4
<CP> + 06H
RH3 RL3
R3
<CP> + 04H
RH2 RL2
R2
<CP> + 02H
RH1 RL1
R1
<CP> + 00H
RH0 RL0
R0
A particular Switch ConteXT (SCXT) instruction performs register bank switching and
automatic saving of the previous context. The number of implemented register banks
(arbitrary sizes) is limited only by the size of the available DPRAM.
User’s Manual
4-11
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
4.7
SFR / ESFR Table
The following table lists all SFRs/ESFRs which are implemented in the C166S V1 SubS
R1 ordered by their physical address.
Table 4-2
SFR/ESFR Table (ordered by physical address)
Physical Name
Address
Type1)
8-bit
Description
2)
Addr
Reset
Value
3)
F000H
reserved
ESFR
00H
reserved - do not use
F002H
reserved
ESFR
01H
reserved - do not use
F004H
reserved
ESFR
02H
reserved - do not use
F006H
reserved
ESFR
03H
reserved - do not use
F008H
reserved
ESFR
04H
reserved - do not use
F00AH
reserved
ESFR
05H
reserved - do not use
F00CH
CPUID
ESFR
06H
CPU Identification Register
F00EH
reserved
ESFR
07H
reserved - do not use
F010H
reserved
ESFR
08H
reserved - do not use
F012H
reserved
ESFR
09H
reserved - do not use
F014H
XADRS1
ESFR
0AH
XBUS Address Select Register 1 0000H
F016H
XADRS2
ESFR
0BH
XBUS Address Select Register 2 0000H
F018H
XADRS3
ESFR
0CH
XBUS Address Select Register 3 0000H
F01AH
XADRS4
ESFR
0DH
XBUS Address Select Register 4 0000H
F01CH
XADRS5
ESFR
0EH
XBUS Address Select Register 5 0000H
F01EH
XADRS6
ESFR
0FH
XBUS Address Select Register 6 0000H
F020H
ESFR
10H
F022H
ESFR
11H
ESFR
12H
F026H
ESFR
13H
F028H
ESFR
14H
F02AH
ESFR
15H
F02CH
ESFR
16H
F02EH
ESFR
17H
F024H
XPERCON
User’s Manual
XBUS Peripheral Control
Register
4-12
0410H
0000H
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-2
SFR/ESFR Table (ordered by physical address) (cont’d)
Physical Name
Address
Type1)
8-bit
Description
2)
Addr
Reset
Value
3)
F030H
ESFR
18H
F032H
ESFR
19H
F034H
ESFR
1AH
F036H
ESFR
1BH
F038H
ESFR
1CH
F03AH
ESFR
1DH
F03CH
ESFR
1EH
F03EH
ESFR
1FH
F040H
ESFR
20H
F042H
ESFR
21H
F044H
ESFR
22H
F046H
ESFR
23H
F048H
ESFR
24H
F04AH
ESFR
25H
F04CH
ESFR
26H
F04EH
ESFR
27H
F050H
ESFR
28H
F052H
ESFR
29H
F054H
ESFR
2AH
F056H
ESFR
2BH
F058H
ESFR
2CH
F05AH
ESFR
2DH
F05CH
ESFR
2EH
F05EH
ESFR
2FH
F060H
ESFR
30H
F062H
ESFR
31H
F064H
ESFR
32H
F066H
ESFR
33H
User’s Manual
4-13
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-2
SFR/ESFR Table (ordered by physical address) (cont’d)
Physical Name
Address
Type1)
8-bit
Description
2)
Addr
Reset
Value
3)
F068H
COMDATA
ESFR
34H
Cerberus Communication Mode
Register
0000H
F06AH
RWDATA
ESFR
35H
Cerberus RW Mode Data
Register
0000H
F06CH
IOSR
ESFR
36H
Cerberus status register
0000H
F06EH
ESFR
37H
F070H
ESFR
38H
F072H
ESFR
39H
F074H
ESFR
3AH
F076H
ESFR
3BH
F078H
ESFR
3CH
F07AH
ESFR
3DH
F07CH
ESFR
3EH
F07EH
ESFR
3FH
F080H
ESFR
40H
F082H
ESFR
41H
F084H
ESFR
42H
F086H
ESFR
43H
F088H
ESFR
44H
F08AH
ESFR
45H
F08CH
ESFR
46H
F08EH
ESFR
47H
F090H
ESFR
48H
F092H
ESFR
49H
F094H
ESFR
4AH
F096H
ESFR
4BH
F098H
ESFR
4CH
F09AH
ESFR
4DH
F09CH
ESFR
4EH
User’s Manual
4-14
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-2
SFR/ESFR Table (ordered by physical address) (cont’d)
Physical Name
Address
Type1)
8-bit
Description
2)
Addr
Reset
Value
3)
F09EH
ESFR
4FH
F0A0H
ESFR
50H
F0A2H
ESFR
51H
F0A4H
ESFR
52H
F0A6H
ESFR
53H
F0A8H
ESFR
54H
F0AAH
ESFR
55H
F0ACH
ESFR
56H
F0AEH
ESFR
57H
F0B0H
SSC0TB
ESFR
58H
SSC0 Transmit Buffer (WO)
0000H
F0B2H
SSC0RB
ESFR
59H
SSC0 Receive Buffer (RO)
0000H
F0B4H
SSC0BR
ESFR
5AH
SSC0 Baudrate Register
0000H
F0B6H
SSC0PISEL ESFR
5BH
SSC0 Port Input Selection
Register
0000H
F0B8H
IRQ96IC
ESFR
5CH
IRQ96 Interrupt Control Register
0000H
F0BAH
IRQ97IC
ESFR
5DH
IRQ97 Interrupt Control Register
0000H
F0BCH
IRQ98IC
ESFR
5EH
IRQ98 Interrupt Control Register
0000H
F0BEH
IRQ99IC
ESFR
5FH
IRQ99 Interrupt Control Register
0000H
F0C0H
IRQ100IC
ESFR
60H
IRQ100 Interrupt Control
Register
0000H
F0C2H
IRQ101IC
ESFR
61H
IRQ101 Interrupt Control
Register
0000H
F0C4H
IRQ102IC
ESFR
62H
IRQ102 Interrupt Control
Register
0000H
F0C6H
IRQ103IC
ESFR
63H
IRQ103 Interrupt Control
Register
0000H
F0C8H
IRQ104IC
ESFR
64H
IRQ104 Interrupt Control
Register
0000H
F0CAH
IRQ105IC
ESFR
65H
IRQ105 Interrupt Control
Register
0000H
User’s Manual
4-15
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-2
SFR/ESFR Table (ordered by physical address) (cont’d)
Physical Name
Address
Type1)
8-bit
Description
2)
Addr
Reset
Value
3)
F0CCH
IRQ106IC
ESFR
66H
IRQ106 Interrupt Control
Register
0000H
F0CEH
IRQ107IC
ESFR
67H
IRQ107 Interrupt Control
Register
0000H
F0D0H
IRQ108IC
ESFR
68H
IRQ108 Interrupt Control
Register
0000H
F0D2H
IRQ109IC
ESFR
69H
IRQ109 Interrupt Control
Register
0000H
F0D4H
IRQ110IC
ESFR
6AH
IRQ110 Interrupt Control
Register
0000H
F0D6H
IRQ111IC
ESFR
6BH
IRQ111 Interrupt Control
Register
0000H
F0D8H
DTIDR
ESFR
6CH
Task ID register
0000H
F0DAH
ESFR
6DH
F0DCH
ESFR
6EH
F0DEH
ESFR
6FH
F0E0H
ESFR
70H
F0E2H
ESFR
71H
F0E4H
ESFR
72H
F0E6H
ESFR
73H
F0E8H
ESFR
74H
F0EAH
ESFR
75H
F0ECH
DCMPSP
ESFR
76H
Select and Programming
Register for DCMPx
0000H
F0EEH
DCMPDP
ESFR
77H
Data Programming Register for
DCMPx
0000H
F0F0H
DTREVT
ESFR
78H
Specifies hardware triggers and
action
0000H
F0F2H
DEXEVT
ESFR
79H
Specifies action if external break
pin is asserted
0000H
User’s Manual
4-16
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-2
SFR/ESFR Table (ordered by physical address) (cont’d)
Physical Name
Address
Type1)
8-bit
Description
2)
Addr
Reset
Value
3)
F0F4H
DSWEVT
ESFR
7AH
Specifies action if DEBUG
instruction is executed
F0F6H
reserved
ESFR
7BH
reserved - do not use
F0F8H
DIP
ESFR
7CH
Instruction pointer register
0000H
F0FAH
DIPX
ESFR
7DH
Instruction pointer register
extension
3000H
F0FCH
DBGSR
ESFR
7EH
Debug status register
0000H
F0FEH
reserved
ESFR
7FH
reserved - do not use
F100H
DP0L
ESFR-b 80H
P0L Direction Control Register
00H
F102H
DP0H
ESFR-b 81H
P0H Direction Control Register
00H
F104H
DP1L
ESFR-b 82H
P1L Direction Control Register
00H
F106H
DP1H
ESFR-b 83H
P1H Direction Control Register
00H
F108H
reserved
ESFR-b 84H
reserved - do not use
F10AH
reserved
ESFR-b 85H
reserved - do not use
F10CH
reserved
ESFR-b 86H
reserved - do not use
F10EH
reserved
ESFR-b 87H
reserved - do not use
F110H
reserved
ESFR-b 88H
reserved - do not use
F112H
reserved
ESFR-b 89H
reserved - do not use
F114H
XBCON1
ESFR-b 8AH
XBUS Control register 1
0000H
F116H
XBCON2
ESFR-b 8BH
XBUS Control register 2
0000H
F118H
XBCON3
ESFR-b 8CH
XBUS Control register 3
0000H
F11AH
XBCON4
ESFR-b 8DH
XBUS Control register 4
0000H
F11CH
XBCON5
ESFR-b 8EH
XBUS Control register 5
0000H
F11EH
XBCON6
ESFR-b 8FH
XBUS Control register 6
0000H
F120H
IRQ64IC
ESFR-b 90H
IRQ64 Interrupt Control Register
0000H
F122H
IRQ65IC
ESFR-b 91H
IRQ65 Interrupt Control Register
0000H
F124H
IRQ66IC
ESFR-b 92H
IRQ66 Interrupt Control Register
0000H
F126H
IRQ67IC
ESFR-b 93H
IRQ67 Interrupt Control Register
0000H
User’s Manual
4-17
0000H
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-2
SFR/ESFR Table (ordered by physical address) (cont’d)
Physical Name
Address
Type1)
8-bit
Description
2)
Addr
Reset
Value
3)
F128H
IRQ68IC
ESFR-b 94H
IRQ68 Interrupt Control Register
0000H
F12AH
IRQ69IC
ESFR-b 95H
IRQ69 Interrupt Control Register
0000H
F12CH
IRQ70IC
ESFR-b 96H
IRQ70 Interrupt Control Register
0000H
F12EH
IRQ71IC
ESFR-b 97H
IRQ71 Interrupt Control Register
0000H
F130H
IRQ72IC
ESFR-b 98H
IRQ72 Interrupt Control Register
0000H
F132H
IRQ73IC
ESFR-b 99H
IRQ73 Interrupt Control Register
0000H
F134H
IRQ74IC
ESFR-b 9AH
IRQ74 Interrupt Control Register
0000H
F136H
IRQ75IC
ESFR-b 9BH
IRQ75 Interrupt Control Register
0000H
F138H
IRQ76IC
ESFR-b 9CH
IRQ76 Interrupt Control Register
0000H
F13AH
IRQ77IC
ESFR-b 9DH
IRQ77 Interrupt Control Register
0000H
F13CH
IRQ78IC
ESFR-b 9EH
IRQ78 Interrupt Control Register
0000H
F13EH
IRQ79IC
ESFR-b 9FH
IRQ79 Interrupt Control Register
0000H
F140H
IRQ80IC
ESFR-b A0H
IRQ80 Interrupt Control Register
0000H
F142H
IRQ81IC
ESFR-b A1H
IRQ81 Interrupt Control Register
0000H
F144H
IRQ82IC
ESFR-b A2H
IRQ82 Interrupt Control Register
0000H
F146H
IRQ83IC
ESFR-b A3H
IRQ83 Interrupt Control Register
0000H
F148H
IRQ84IC
ESFR-b A4H
IRQ84 Interrupt Control Register
0000H
F14AH
IRQ85IC
ESFR-b A5H
IRQ85 Interrupt Control Register
0000H
F14CH
IRQ86IC
ESFR-b A6H
IRQ86 Interrupt Control Register
0000H
F14EH
IRQ87IC
ESFR-b A7H
IRQ87 Interrupt Control Register
0000H
F150H
IRQ88IC
ESFR-b A8H
IRQ88 Interrupt Control Register
0000H
F152H
IRQ89IC
ESFR-b A9H
IRQ89 Interrupt Control Register
0000H
F154H
IRQ90IC
ESFR-b AAH
IRQ90 Interrupt Control Register
0000H
F156H
IRQ91IC
ESFR-b ABH
IRQ91 Interrupt Control Register
0000H
F158H
IRQ92IC
ESFR-b ACH
IRQ92 Interrupt Control Register
0000H
F15AH
IRQ93IC
ESFR-b ADH
IRQ93 Interrupt Control Register
0000H
F15CH
IRQ94IC
ESFR-b AEH
IRQ94 Interrupt Control Register
0000H
F15EH
IRQ95IC
ESFR-b AFH
IRQ95 Interrupt Control Register
0000H
F160H
IRQ48IC
ESFR-b B0H
IRQ48 Interrupt Control Register
0000H
User’s Manual
4-18
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-2
SFR/ESFR Table (ordered by physical address) (cont’d)
Physical Name
Address
Type1)
8-bit
Description
2)
Addr
Reset
Value
3)
F162H
IRQ49IC
ESFR-b B1H
IRQ49 Interrupt Control Register
0000H
F164H
IRQ50IC
ESFR-b B2H
IRQ50 Interrupt Control Register
0000H
F166H
IRQ51IC
ESFR-b B3H
IRQ51 Interrupt Control Register
0000H
F168H
IRQ52IC
ESFR-b B4H
IRQ52 Interrupt Control Register
0000H
F16AH
IRQ53IC
ESFR-b B5H
IRQ53 Interrupt Control Register
0000H
F16CH
IRQ54IC
ESFR-b B6H
IRQ54 Interrupt Control Register
0000H
F16EH
IRQ55IC
ESFR-b B7H
IRQ55 Interrupt Control Register
0000H
F170H
IRQ56IC
ESFR-b B8H
IRQ56 Interrupt Control Register
0000H
F172H
IRQ57IC
ESFR-b B9H
IRQ57 Interrupt Control Register
0000H
F174H
IRQ58IC
ESFR-b BAH
IRQ58 Interrupt Control Register
0000H
F176H
IRQ59IC
ESFR-b BBH
IRQ59 Interrupt Control Register
0000H
F178H
IRQ60IC
ESFR-b BCH
IRQ60 Interrupt Control Register
0000H
F17AH
IRQ40IC
ESFR-b BDH
IRQ40 Interrupt Control Register
0000H
F17CH
IRQ41IC
ESFR-b BEH
IRQ41 Interrupt Control Register
0000H
F17EH
IRQ15IC
ESFR-b BFH
IRQ15 Interrupt Control Register
0000H
F180H
EOPIC
ESFR-b C0H
End of PEC Transfer Interrupt
Control Register
0000H
F182H
IRQ42IC
ESFR-b C1H
IRQ42 Interrupt Control Register
0000H
F184H
IRQ61IC
ESFR-b C2H
IRQ61 Interrupt Control Register
0000H
F186H
IRQ36IC
ESFR-b C3H
IRQ36 Interrupt Control Register
0000H
F188H
IRQ47IC
ESFR-b C4H
IRQ47 Interrupt Control Register
0000H
F18AH
IRQ43IC
ESFR-b C5H
IRQ43 Interrupt Control Register
0000H
F18CH
IRQ62IC
ESFR-b C6H
IRQ62 Interrupt Control Register
0000H
F18EH
IRQ37IC
ESFR-b C7H
IRQ37 Interrupt Control Register
0000H
F190H
IRQ45IC
ESFR-b C8H
IRQ45 Interrupt Control Register
0000H
F192H
IRQ44IC
ESFR-b C9H
IRQ44 Interrupt Control Register
0000H
F194H
IRQ63IC
ESFR-b CAH
IRQ63 Interrupt Control Register
0000H
F196H
IRQ38IC
ESFR-b CBH
IRQ38 Interrupt Control Register
0000H
F198H
IRQ46IC
ESFR-b CCH
IRQ46 Interrupt Control Register
0000H
User’s Manual
4-19
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-2
SFR/ESFR Table (ordered by physical address) (cont’d)
Physical Name
Address
Type1)
8-bit
Description
2)
Addr
Reset
Value
3)
F19AH
WDTIC
ESFR-b CDH
Watchdog Timer Interrupt Control 0000H
Register
F19CH
S0TBIC
ESFR-b CEH
ASC0 Transmit Buffer Interrupt
Control Register
0000H
F19EH
IRQ39IC
ESFR-b CFH
IRQ39 Interrupt Control Register
0000H
ASC0 Port Input Selection
Register
0000H
F1A0H
ESFR-b D0H
F1A2H
ESFR-b D1H
F1A4H
ESFR-b D2H
F1A6H
ESFR-b D3H
F1A8H
ESFR-b D4H
F1AAH
ESFR-b D5H
F1ACH
ESFR-b D6H
F1AEH
ESFR-b D7H
F1B0H
ESFR-b D8H
F1B2H
ESFR-b D9H
F1B4H
ESFR-b DAH
F1B6H
ASC0PISEL ESFR-b DBH
F1B8H
ESFR-b DCH
F1BAH
ESFR-b DDH
F1BCH
ESFR-b DEH
F1BEH
ESFR-b DFH
F1C0H
ESFR-b E0H
F1C2H
ESFR-b E1H
F1C4H
ESFR-b E2H
F1C6H
ESFR-b E3H
F1C8H
ESFR-b E4H
F1CAH
ESFR-b E5H
F1CCH
ESFR-b E6H
User’s Manual
4-20
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-2
SFR/ESFR Table (ordered by physical address) (cont’d)
Physical Name
Address
Type1)
8-bit
Description
2)
Addr
Reset
Value
3)
F1CEH
ESFR-b E7H
F1D0H
ESFR-b E8H
F1D2H
ESFR-b E9H
F1D4H
ESFR-b EAH
F1D6H
ESFR-b EBH
F1D8H
ESFR-b ECH
F1DAH
ESFR-b EDH
F1DCH
ESFR-b EEH
F1DEH
ESFR-b EFH
F1E0H
reserved
reserved - do not use
F1E2H
reserved
reserved - do not use
F1E4H
reserved
reserved - do not use
F1E6H
reserved
reserved - do not use
F1E8H
reserved
reserved - do not use
F1EAH
reserved
reserved - do not use
F1ECH
reserved
reserved - do not use
F1EEH
reserved
reserved - do not use
F1F0H
reserved
reserved - do not use
F1F2H
reserved
reserved - do not use
F1F4H
reserved
reserved - do not use
F1F6H
reserved
reserved - do not use
F1F8H
reserved
reserved - do not use
F1FAH
reserved
reserved - do not use
F1FCH
reserved
reserved - do not use
F1FEH
reserved
reserved - do not use
FE00H
DPP0
SFR
00H
CPU Data Page Pointer 0
Register (10 bits)
0000H
FE02H
DPP1
SFR
01H
CPU Data Page Pointer 1
Register (10 bits)
0001H
User’s Manual
4-21
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-2
SFR/ESFR Table (ordered by physical address) (cont’d)
Physical Name
Address
Type1)
8-bit
Description
2)
Addr
Reset
Value
3)
FE04H
DPP2
SFR
02H
CPU Data Page Pointer 2
Register (10 bits)
0002H
FE06H
DPP3
SFR
03H
CPU Data Page Pointer 3
Register (10 bits)
0003H
FE08H
CSP
SFR
04H
CPU Code Segment Pointer
Register (8 bits)
0000H
FE0AH
reserved
SFR
05H
reserved - do not use
0000H
FE0CH
MDH
SFR
06H
CPU Multiply Divide Register High Word
0000H
FE0EH
MDL
SFR
07H
CPU Multiply Divide Register Low Word
0000H
FE10H
CP
SFR
08H
CPU Context Pointer Register
FC00H
FE12H
SP
SFR
09H
CPU System Stack Pointer
Register
FC00H
FE14H
STKOV
SFR
0AH
CPU Stack Overflow Pointer
Register
FA00H
FE16H
STKUN
SFR
0BH
CPU Stack Underflow Pointer
Register
FC00H
FE18H
ADDRSEL1
SFR
0CH
Address Select Register 1
0000H
FE1AH
ADDRSEL2
SFR
0DH
Address Select Register 2
0000H
FE1CH
ADDRSEL3
SFR
0EH
Address Select Register 3
0000H
FE1EH
ADDRSEL4
SFR
0FH
Address Select Register 4
0000H
FE20H
SFR
10H
FE22H
SFR
11H
FE24H
SFR
12H
FE26H
SFR
13H
FE28H
SFR
14H
FE2AH
SFR
15H
FE2CH
SFR
16H
FE2EH
SFR
17H
FE30H
SFR
18H
User’s Manual
4-22
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-2
SFR/ESFR Table (ordered by physical address) (cont’d)
Physical Name
Address
Type1)
8-bit
Description
2)
Addr
Reset
Value
3)
FE32H
SFR
19H
FE34H
SFR
1AH
FE36H
SFR
1BH
FE38H
SFR
1CH
FE3AH
SFR
1DH
FE3CH
SFR
1EH
FE3EH
SFR
1FH
FE40H
T2
SFR
20H
GPT Timer 2 Register
0000H
FE42H
T3
SFR
21H
GPT Timer 3 Register
0000H
FE44H
T4
SFR
22H
GPT Timer 4 Register
0000H
FE46H
T5
SFR
23H
GPT Timer 5 Register
0000H
FE48H
T6
SFR
24H
GPT Timer 6 Register
0000H
FE4AH
CAPREL
SFR
25H
GPT Capture/Reload Register
0000H
FE4CH
GPTIPISEL
SFR
26H
GPT Port Input Selection
Register
0000H
FE4EH
SFR
27H
FE50H
SFR
28H
FE52H
SFR
29H
FE54H
SFR
2AH
FE56H
SFR
2BH
FE58H
SFR
2CH
FE5AH
SFR
2DH
FE5CH
reserved
SFR
2EH
reserved - do not use
FE5EH
reserved
SFR
2FH
reserved - do not use
FE60H
SFR
30H
FE62H
SFR
31H
FE64H
SFR
32H
FE66H
SFR
33H
FE68H
SFR
34H
User’s Manual
4-23
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-2
SFR/ESFR Table (ordered by physical address) (cont’d)
Physical Name
Address
Type1)
8-bit
Description
2)
Addr
Reset
Value
3)
FE6AH
SFR
35H
FE6CH
SFR
36H
FE6EH
SFR
37H
FE70H
SFR
38H
FE72H
SFR
39H
FE74H
SFR
3AH
FE76H
SFR
3BH
FE78H
SFR
3CH
FE7AH
SFR
3DH
FE7CH
SFR
3EH
FE7EH
SFR
3FH
FE80H
SFR
40H
FE82H
SFR
41H
FE84H
SFR
42H
FE86H
SFR
43H
FE88H
SFR
44H
FE8AH
SFR
44H
FE8CH
SFR
46H
FE8EH
SFR
47H
FE90H
SFR
48H
FE92H
SFR
49H
FE94H
SFR
4AH
FE96H
SFR
4BH
FE98H
SFR
4CH
FE9AH
SFR
4DH
FE9CH
SFR
4EH
FE9EH
SFR
4FH
FEA0H
SFR
50H
FEA2H
SFR
51H
User’s Manual
4-24
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-2
SFR/ESFR Table (ordered by physical address) (cont’d)
Physical Name
Address
Type1)
8-bit
Description
2)
Addr
Reset
Value
3)
FEA4H
SFR
52H
FEA6H
SFR
53H
FEA8H
SFR
54H
FEAAH
SFR
55H
FEACH
SFR
56H
FEAEH
WDT
SFR
57H
Watchdog Timer Register (RO)
FEB0H
S0TBUF
SFR
58H
Serial Channel 0 Transmit Buffer 0000H
Register (WO)
FEB2H
S0RBUF
SFR
59H
Serial Channel 0 Receive Buffer
Register (RO)
0000H
FEB4H
S0BG
SFR
5AH
Serial Channel 0 Baud Rate
Generator Reload Register
0000H
FEB6H
FDV
SFR
5BH
Fractional Divider Register
0000H
FEB8H
PECSN12
SFR
5CH
PEC Segment No. Register
0000H
FEBAH
PECSN13
SFR
5DH
PEC Segment No. Register
0000H
FEBCH
PECSN14
SFR
5EH
PEC Segment No. Register
0000H
FEBEH
PECSN15
SFR
5FH
PEC Segment No. Register
0000H
FEC0H
PECC0
SFR
60H
PEC Channel 0 Control Register
0000H
FEC2H
PECC1
SFR
61H
PEC Channel 1 Control Register
0000H
FEC4H
PECC2
SFR
62H
PEC Channel 2 Control Register
0000H
FEC6H
PECC3
SFR
63H
PEC Channel 3 Control Register
0000H
FEC8H
PECC4
SFR
64H
PEC Channel 4 Control Register
0000H
FECAH
PECC5
SFR
65H
PEC Channel 5 Control Register
0000H
FECCH
PECC6
SFR
66H
PEC Channel 6 Control Register
0000H
FECEH
PECC7
SFR
67H
PEC Channel 7 Control Register
0000H
FED0H
PECSN0
SFR
68H
PEC Segment No. Register
0000H
FED2H
PECSN1
SFR
69H
PEC Segment No. Register
0000H
FED4H
PECSN2
SFR
6AH
PEC Segment No. Register
0000H
FED6H
PECSN3
SFR
6BH
PEC Segment No. Register
0000H
User’s Manual
4-25
0000H
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-2
SFR/ESFR Table (ordered by physical address) (cont’d)
Physical Name
Address
Type1)
8-bit
Description
2)
Addr
Reset
Value
3)
FED8H
PECSN4
SFR
6CH
PEC Segment No. Register
0000H
FEDAH
PECSN5
SFR
6DH
PEC Segment No. Register
0000H
FEDCH
PECSN6
SFR
6EH
PEC Segment No. Register
0000H
FEDEH
PECSN7
SFR
6FH
PEC Segment No. Register
0000H
FEE0H
PECSN8
SFR
70H
PEC Segment No. Register
0000H
FEE2H
PECSN9
SFR
71H
PEC Segment No. Register
0000H
FEE4H
PECSN10
SFR
72H
PEC Segment No. Register
0000H
FEE6H
PECSN11
SFR
73H
PEC Segment No. Register
0000H
FEE8H
PECC8
SFR
74H
PEC Channel 8 Control Register
0000H
FEEAH
PECC9
SFR
75H
PEC Channel 9 Control Register
0000H
FEECH
PECC10
SFR
76H
PEC Channel 10 Control Register 0000H
FEEEH
PECC11
SFR
77H
PEC Channel 11 Control Register 0000H
FEF0H
PECXC0
SFR
78H
PEC Channel 0 Extended Control 0000H
Register
FEF2H
PECXC2
SFR
79H
PEC Channel 2 Extended Control 0000H
Register
FEF4H
reserved
SFR
7AH
reserved - do not use
FEF6H
reserved
SFR
7BH
reserved - do not use
FEF8H
PECC12
SFR
7CH
PEC Channel 12 Control Register 0000H
FEFAH
PECC13
SFR
7DH
PEC Channel 13 Control Register 0000H
FEFCH
PECC14
SFR
7EH
PEC Channel 14 Control Register 0000H
FEFEH
PECC15
SFR
7FH
PEC Channel 15 Control Register 0000H
FF00H
P0L
SFR-b
80H
Port 0 Low Register (Lower half)
FF02H
P0H
SFR-b
81H
Port 0 High Register (Upper half) 00H
FF04H
P1L
SFR-b
82H
Port 1 Low Register (Lower half)
FF06H
P1H
SFR-b
83H
Port 1 High Register (Upper half) 00H
FF08H
reserved
SFR-b
84H
reserved - do not use
FF0AH
reserved
SFR-b
85H
reserved - do not use
FF0CH
BUSCON0
SFR-b
86H
Bus Configuration Register 0
User’s Manual
4-26
00H
00H
0000H
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-2
SFR/ESFR Table (ordered by physical address) (cont’d)
Physical Name
Address
Type1)
8-bit
Description
2)
Addr
Reset
Value
3)
FF0EH
MDC
SFR-b
87H
CPU Multiply Divide Control
Register
0000H
FF10H
PSW
SFR-b
88H
CPU Program Status Word
0000H
FF12H
SYSCON
SFR-b
89H
CPU System Configuration
Register
xxxxH
FF14H
BUSCON1
SFR-b
8AH
Bus Configuration Register 1
0000H
FF16H
BUSCON2
SFR-b
8BH
Bus Configuration Register 2
0000H
FF18H
BUSCON3
SFR-b
8CH
Bus Configuration Register 3
0000H
FF1AH
BUSCON4
SFR-b
8DH
Bus Configuration Register 4
0000H
FF1CH
ZEROS
SFR-b
8EH
Constant Value 0sRegister’
0000H
FF1EH
ONES
SFR-b
8FH
Constant Value 1sRegister’
FFFFH
FF20H
SFR-b
90H
FF22H
SFR-b
91H
FF24H
SFR-b
92H
FF26H
SFR-b
93H
FF28H
SFR-b
94H
FF2AH
SFR-b
95H
FF2CH
SFR-b
96H
FF2EH
SFR-b
97H
FF30H
SFR-b
98H
FF32H
SFR-b
99H
FF34H
SFR-b
9AH
FF36H
SFR-b
9BH
FF38H
SFR-b
9CH
FF3AH
SFR-b
9DH
FF3CH
SFR-b
9EH
FF3EH
SFR-b
9FH
FF40H
T2CON
SFR-b
A0H
GPT Timer 2 Control Register
0000H
FF42H
T3CON
SFR-b
A1H
GPT Timer 3 Control Register
0000H
User’s Manual
4-27
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-2
SFR/ESFR Table (ordered by physical address) (cont’d)
Physical Name
Address
Type1)
8-bit
Description
2)
Addr
Reset
Value
3)
FF44H
T4CON
SFR-b
A2H
GPT Timer 4 Control Register
0000H
FF46H
T5CON
SFR-b
A3H
GPT Timer 5 Control Register
0000H
FF48H
T6CON
SFR-b
A4H
GPT Timer 6 Control Register
0000H
FF4AH
SFR-b
A5H
FF4CH
SFR-b
A6H
FF4EH
SFR-b
A7H
FF50H
SFR-b
A8H
FF52H
SFR-b
A9H
FF54H
SFR-b
AAH
FF56H
SFR-b
ABH
FF58H
SFR-b
ACH
FF5AH
SFR-b
ADH
FF5CH
SFR-b
AEH
FF5EH
SFR-b
AFH
FF60H
T2IC
SFR-b
B0H
GPT12E Timer 2 Interrupt Control 0000H
Register
FF62H
T3IC
SFR-b
B1H
GPT12E Timer 3 Interrupt Control 0000H
Register
FF64H
T4IC
SFR-b
B2H
GPT12E Timer 4 Interrupt Control 0000H
Register
FF66H
T5IC
SFR-b
B3H
GPT12E Timer 5 Interrupt Control 0000H
Register
FF68H
T6IC
SFR-b
B4H
GPT12E Timer 6 Interrupt Control 0000H
Register
FF6AH
CRIC
SFR-b
B5H
GPT12E Capture/Reload
Interrupt Control Register
0000H
FF6CH
S0TIC
SFR-b
B6H
ASC0 Transmit Interrupt Control
Register
0000H
FF6EH
S0RIC
SFR-b
B7H
ASC0 Receive Interrupt Control
Register
0000H
User’s Manual
4-28
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-2
SFR/ESFR Table (ordered by physical address) (cont’d)
Physical Name
Address
Type1)
8-bit
Description
2)
Addr
Reset
Value
3)
FF70H
S0EIC
SFR-b
B8H
ASC0 Error Interrupt Control
Register
0000H
FF72H
SSC0TIC
SFR-b
B9H
SSC0 Transmit Interrupt Control
Register
0000H
FF74H
SSC0RIC
SFR-b
BAH
SSC0 Receive Interrupt Control
Register
0000H
FF76H
SSC0EIC
SFR-b
BBH
SSC0 Error Interrupt Control
Register
0000H
FF78H
IRQ16IC
SFR-b
BCH
IRQ16 Interrupt Control Register
0000H
FF7AH
IRQ17IC
SFR-b
BDH
IRQ17 Interrupt Control Register
0000H
FF7CH
IRQ18IC
SFR-b
BEH
IRQ18 Interrupt Control Register
0000H
FF7EH
IRQ19IC
SFR-b
BFH
IRQ19 Interrupt Control Register
0000H
FF80H
IRQ20IC
SFR-b
C0H
IRQ20 Interrupt Control Register
0000H
FF82H
IRQ21IC
SFR-b
C1H
IRQ21 Interrupt Control Register
0000H
FF84H
IRQ22IC
SFR-b
C2H
IRQ22 Interrupt Control Register
0000H
FF86H
IRQ23IC
SFR-b
C3H
IRQ23 Interrupt Control Register
0000H
FF88H
IRQ24IC
SFR-b
C4H
IRQ24 Interrupt Control Register
0000H
FF8AH
IRQ25IC
SFR-b
C5H
IRQ25 Interrupt Control Register
0000H
FF8CH
IRQ26IC
SFR-b
C6H
IRQ26 Interrupt Control Register
0000H
FF8EH
IRQ27IC
SFR-b
C7H
IRQ27 Interrupt Control Register
0000H
FF90H
IRQ28IC
SFR-b
C8H
IRQ28 Interrupt Control Register
0000H
FF92H
IRQ29IC
SFR-b
C9H
IRQ29 Interrupt Control Register
0000H
FF94H
IRQ30IC
SFR-b
CAH
IRQ30 Interrupt Control Register
0000H
FF96H
IRQ31IC
SFR-b
CBH
IRQ31 Interrupt Control Register
0000H
FF98H
IRQ34IC
SFR-b
CCH
IRQ34 Interrupt Control Register
0000H
FF9AH
IRQ35IC
SFR-b
CDH
IRQ35 Interrupt Control Register
0000H
FF9CH
IRQ32IC
SFR-b
CEH
IRQ32 Interrupt Control Register
0000H
FF9EH
IRQ33IC
SFR-b
CFH
IRQ33 Interrupt Control Register
0000H
FFA0H
SFR-b
D0H
FFA2H
SFR-b
D1H
User’s Manual
4-29
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-2
SFR/ESFR Table (ordered by physical address) (cont’d)
Physical Name
Address
Type1)
8-bit
Description
2)
Addr
Reset
Value
3)
FFA4H
SFR-b
D2H
FFA6H
SFR-b
D3H
SFR-b
D4H
SFR-b
D5H
FFA8H
PECISNC
FFAAH
PEC Interrupt Subnode Control
Register
0000H
0000H
FFACH
TFR
SFR-b
D6H
Trap Flag Register
FFAEH
WDTCON
SFR-b
D7H
Watchdog Timer Control Register 008xH
FFB0H
S0CON
SFR-b
D8H
Serial Channel 0 Control Register 0000H
FFB2H
SSC0CON
SFR-b
D9H
SSC0 Control Register
FFB4H
SFR-b
DAH
FFB6H
SFR-b
DBH
FFB8H
SFR-b
DCH
SFR-b
DDH
FFBCH
SFR-b
DEH
FFBEH
SFR-b
DFH
FFC0H
SFR-b
E0H
FFC2H
SFR-b
E1H
FFC4H
SFR-b
E2H
FFC6H
SFR-b
E3H
FFBAH
PECXISNC
0000H
PEC Extended Interrupt Subnode 0000H
Control Register
FFC8H
P4
SFR-b
E4H
Port 4 Register (8 bits)
00H
FFCAH
DP4
SFR-b
E5H
Port 4 Direction Control Register
00H
FFCCH
P6
SFR-b
E6H
Port 6 Register (8 bits)
00H
FFCEH
DP6
SFR-b
E7H
Port 6 Direction Control Register
00H
FFD0H
SFR-b
E8H
FFD2H
SFR-b
E9H
FFD4H
SFR-b
EAH
FFD6H
SFR-b
EBH
FFD8H
SFR-b
ECH
User’s Manual
4-30
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-2
SFR/ESFR Table (ordered by physical address) (cont’d)
Physical Name
Address
Type1)
8-bit
Description
2)
Addr
Reset
Value
3)
FFDAH
reserved
SFR-b
EDH
reserved - do not use
FFDCH
reserved
SFR-b
EEH
reserved - do not use
FFDEH
reserved
SFR-b
EFH
reserved - do not use
FFE0H
reserved
reserved - do not use
FFE2H
ASC0ID
ASC0 Identification Register
44xxH
FFE4H
SSC0ID
SSC0 Identification Register
45xxH
FFE6H
GPTID
GPT Identification Register
58xxH
FFE8H
reserved
reserved - do not use
0000H
FFEAH
reserved
reserved - do not use
0000H
FFECH
reserved
reserved - do not use
0000H
FFEEH
reserved
reserved - do not use
0000H
FFF0H
reserved
reserved - do not use
0000H
FFF2H
reserved
reserved - do not use
0000H
FFF4H
reserved
reserved - do not use
0000H
FFF6H
reserved
reserved - do not use
0000H
FFF8H
reserved
reserved - do not use
0000H
FFFAH
reserved
reserved - do not use
0000H
FFFCH
reserved
reserved - do not use
0000H
FFFEH
reserved
reserved - do not use
0000H
1)
The PDBUS+ chip select depends on the register type. Chip select "pd_cs_esfr" is used for register types
"ESFR" and "ESFR-b", whereas chip select "pd_cs_sfr" valid for register types "SFR" and "SFR-b"
2)
This address is identical to PDBUS+ address A[8:1]. However, for address ranges F1E0H to F1FFH and FFE0H
to FFFFH there is no 8-bit address, but a PDBUS+ address.
3)
NOTE: Reserved addresses are always read as FFFFH, except another reset value is explicitly documented
in this column. However, for enabling future enhancements without any compatibility problems, this addresses
should neither be written nor be used as read value by the software.
User’s Manual
4-31
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
The following table lists all SFRs/ESFRs which are implemented in the C166S V1 SubS
R1 ordered by their name.
Table 4-3
SFR/ESFR Table (ordered by name)
Name
Physical Type1)
Address
8-bit
Addr
Description
Reset
Value
2)
ADDRSEL1
FE18H
SFR
0CH
Address Select Register 1
0000H
ADDRSEL2
FE1AH
SFR
0DH
Address Select Register 2
0000H
ADDRSEL3
FE1CH
SFR
0EH
Address Select Register 3
0000H
ADDRSEL4
FE1EH
SFR
0FH
Address Select Register 4
0000H
ASC0ID
FFE2H
ASC0 Identification Register
44xxH
ASC0PISEL
F1B6H
SFR-b
DBH
ASC0 Port Input Selection
Register
0000H
BUSCON0
FF0CH
SFR-b
86H
Bus Configuration Register 0
0000H
BUSCON1
FF14H
SFR-b
8AH
Bus Configuration Register 1
0000H
BUSCON2
FF16H
SFR-b
8BH
Bus Configuration Register 2
0000H
BUSCON3
FF18H
SFR-b
8CH
Bus Configuration Register 3
0000H
BUSCON4
FF1AH
SFR-b
8DH
Bus Configuration Register 4
0000H
CAPREL
FE4AH
SFR
25H
GPT Capture/Reload Register
0000H
COMDATA
F068H
ESFR
34H
Cerberus Communication Mode
Register
0000H
CP
FE10H
SFR
08H
CPU Context Pointer Register
FC00H
CPUID
F00CH
ESFR
06H
CPU Identification Register
0410H
CRIC
FF6AH
SFR-b
B5H
GPT12E Capture/Reload
Interrupt Control Register
0000H
CSP
FE08H
SFR
04H
CPU Code Segment Pointer
Register (8 bits)
0000H
DBGSR
F0FCH
ESFR
7EH
Debug status register
0000H
DCMPDP
F0EEH
ESFR
77H
Data Programming Register for
DCMPx
0000H
DCMPSP
F0ECH
ESFR
76H
Select and Programming
Register for DCMPx
0000H
DEXEVT
F0F2H
ESFR
79H
Specifies action if external break 0000H
pin is asserted
User’s Manual
4-32
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-3
SFR/ESFR Table (ordered by name) (cont’d)
Name
Physical Type1)
Address
8-bit
Addr
Description
Reset
Value
2)
DIP
F0F8H
ESFR
7CH
Instruction pointer register
0000H
DIPX
F0FAH
ESFR
7DH
Instruction pointer register
extension
3000H
DP0H
F102H
ESFR-b 81H
P0H Direction Control Register
00H
DP0L
F100H
ESFR-b 80H
P0L Direction Control Register
00H
DP1H
F106H
ESFR-b 83H
P1H Direction Control Register
00H
DP1L
F104H
ESFR-b 82H
P1L Direction Control Register
00H
DP4
FFCAH
SFR-b
E5H
Port 4 Direction Control Register 00H
DP6
FFCEH
SFR-b
E7H
Port 6 Direction Control Register 00H
DPP0
FE00H
SFR
00H
CPU Data Page Pointer 0
Register (10 bits)
0000H
DPP1
FE02H
SFR
01H
CPU Data Page Pointer 1
Register (10 bits)
0001H
DPP2
FE04H
SFR
02H
CPU Data Page Pointer 2
Register (10 bits)
0002H
DPP3
FE06H
SFR
03H
CPU Data Page Pointer 3
Register (10 bits)
0003H
DSWEVT
F0F4H
ESFR
7AH
Specifies action if DEBUG
instruction is executed
0000H
DTIDR
F0D8H
ESFR
6CH
Task ID register
0000H
DTREVT
F0F0H
ESFR
78H
Specifies hardware triggers and
action
0000H
EOPIC
F180H
ESFR-b C0H
End of PEC Transfer Interrupt
Control Register
0000H
FDV
FEB6H
SFR
Fractional Divider Register
0000H
GPTID
FFE6H
GPT Identification Register
58xxH
GPTPISEL
FE4CH
SFR
26H
GPT Port Input Selection
Register
0000H
IOSR
F06CH
ESFR
36H
Cerberus status register
0000H
IRQ15IC
F17EH
ESFR-b BFH
IRQ15 Interrupt Control Register 0000H
IRQ16IC
FF78H
SFR-b
IRQ16 Interrupt Control Register 0000H
User’s Manual
5B
BCH
4-33
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-3
SFR/ESFR Table (ordered by name) (cont’d)
Name
Physical Type1)
Address
8-bit
Addr
Description
Reset
Value
2)
IRQ17IC
FF7AH
SFR-b
BDH
IRQ17 Interrupt Control Register 0000H
IRQ18IC
FF7CH
SFR-b
BEH
IRQ18 Interrupt Control Register 0000H
IRQ19IC
FF7EH
SFR-b
BFH
IRQ19 Interrupt Control Register 0000H
IRQ20IC
FF80H
SFR-b
C0H
IRQ20 Interrupt Control Register 0000H
IRQ21IC
FF82H
SFR-b
C1H
IRQ21 Interrupt Control Register 0000H
IRQ22IC
FF84H
SFR-b
C2H
IRQ22 Interrupt Control Register 0000H
IRQ23IC
FF86H
SFR-b
C3H
IRQ23 Interrupt Control Register 0000H
IRQ24IC
FF88H
SFR-b
C4H
IRQ24 Interrupt Control Register 0000H
IRQ25IC
FF8AH
SFR-b
C5H
IRQ25 Interrupt Control Register 0000H
IRQ26IC
FF8CH
SFR-b
C6H
IRQ26 Interrupt Control Register 0000H
IRQ27IC
FF8EH
SFR-b
C7H
IRQ27 Interrupt Control Register 0000H
IRQ28IC
FF90H
SFR-b
C8H
IRQ28 Interrupt Control Register 0000H
IRQ29IC
FF92H
SFR-b
C9H
IRQ29 Interrupt Control Register 0000H
IRQ30IC
FF94H
SFR-b
CAH
IRQ30 Interrupt Control Register 0000H
IRQ31IC
FF96H
SFR-b
CBH
IRQ31 Interrupt Control Register 0000H
IRQ32IC
FF9CH
SFR-b
CEH
IRQ32 Interrupt Control Register 0000H
IRQ33IC
FF9EH
SFR-b
CFH
IRQ33 Interrupt Control Register 0000H
IRQ34IC
FF98H
SFR-b
CCH
IRQ34 Interrupt Control Register 0000H
IRQ35IC
FF9AH
SFR-b
CDH
IRQ35 Interrupt Control Register 0000H
IRQ36IC
F186H
ESFR-b C3H
IRQ36 Interrupt Control Register 0000H
IRQ37IC
F18EH
ESFR-b C7H
IRQ37 Interrupt Control Register 0000H
IRQ38IC
F196H
ESFR-b CBH
IRQ38 Interrupt Control Register 0000H
IRQ39IC
F19EH
ESFR-b CFH
IRQ39 Interrupt Control Register 0000H
IRQ40IC
F17AH
ESFR-b BDH
IRQ40 Interrupt Control Register 0000H
IRQ41IC
F17CH
ESFR-b BEH
IRQ41 Interrupt Control Register 0000H
IRQ42IC
F182H
ESFR-b C1H
IRQ42 Interrupt Control Register 0000H
IRQ43IC
F18AH
ESFR-b C5H
IRQ43 Interrupt Control Register 0000H
IRQ44IC
F192H
ESFR-b C9H
IRQ44 Interrupt Control Register 0000H
IRQ45IC
F190H
ESFR-b C8H
IRQ45 Interrupt Control Register 0000H
User’s Manual
4-34
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-3
SFR/ESFR Table (ordered by name) (cont’d)
Name
Physical Type1)
Address
8-bit
Addr
Description
Reset
Value
2)
IRQ46IC
F198H
ESFR-b CCH
IRQ46 Interrupt Control Register 0000H
IRQ47IC
F188H
ESFR-b C4H
IRQ47 Interrupt Control Register 0000H
IRQ48IC
F160H
ESFR-b B0H
IRQ48 Interrupt Control Register 0000H
IRQ49IC
F162H
ESFR-b B1H
IRQ49 Interrupt Control Register 0000H
IRQ50IC
F164H
ESFR-b B2H
IRQ50 Interrupt Control Register 0000H
IRQ51IC
F166H
ESFR-b B3H
IRQ51 Interrupt Control Register 0000H
IRQ52IC
F168H
ESFR-b B4H
IRQ52 Interrupt Control Register 0000H
IRQ53IC
F16AH
ESFR-b B5H
IRQ53 Interrupt Control Register 0000H
IRQ54IC
F16CH
ESFR-b B6H
IRQ54 Interrupt Control Register 0000H
IRQ55IC
F16EH
ESFR-b B7H
IRQ55 Interrupt Control Register 0000H
IRQ56IC
F170H
ESFR-b B8H
IRQ56 Interrupt Control Register 0000H
IRQ57IC
F172H
ESFR-b B9H
IRQ57 Interrupt Control Register 0000H
IRQ58IC
F174H
ESFR-b BAH
IRQ58 Interrupt Control Register 0000H
IRQ59IC
F176H
ESFR-b BBH
IRQ59 Interrupt Control Register 0000H
IRQ60IC
F178H
ESFR-b BCH
IRQ60 Interrupt Control Register 0000H
IRQ61IC
F184H
ESFR-b C2H
IRQ61 Interrupt Control Register 0000H
IRQ62IC
F18CH
ESFR-b C6H
IRQ62 Interrupt Control Register 0000H
IRQ63IC
F194H
ESFR-b CAH
IRQ63 Interrupt Control Register 0000H
IRQ64IC
F120H
ESFR-b 90H
IRQ64 Interrupt Control Register 0000H
IRQ65IC
F122H
ESFR-b 91H
IRQ65 Interrupt Control Register 0000H
IRQ66IC
F124H
ESFR-b 92H
IRQ66 Interrupt Control Register 0000H
IRQ67IC
F126H
ESFR-b 93H
IRQ67 Interrupt Control Register 0000H
IRQ68IC
F128H
ESFR-b 94H
IRQ68 Interrupt Control Register 0000H
IRQ69IC
F12AH
ESFR-b 95H
IRQ69 Interrupt Control Register 0000H
IRQ70IC
F12CH
ESFR-b 96H
IRQ70 Interrupt Control Register 0000H
IRQ71IC
F12EH
ESFR-b 97H
IRQ71 Interrupt Control Register 0000H
IRQ72IC
F130H
ESFR-b 98H
IRQ72 Interrupt Control Register 0000H
IRQ73IC
F132H
ESFR-b 99H
IRQ73 Interrupt Control Register 0000H
IRQ74IC
F134H
ESFR-b 9AH
IRQ74 Interrupt Control Register 0000H
User’s Manual
4-35
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-3
SFR/ESFR Table (ordered by name) (cont’d)
Name
Physical Type1)
Address
8-bit
Addr
Description
Reset
Value
2)
IRQ75IC
F136H
ESFR-b 9BH
IRQ75 Interrupt Control Register 0000H
IRQ76IC
F138H
ESFR-b 9CH
IRQ76 Interrupt Control Register 0000H
IRQ77IC
F13AH
ESFR-b 9DH
IRQ77 Interrupt Control Register 0000H
IRQ78IC
F13CH
ESFR-b 9EH
IRQ78 Interrupt Control Register 0000H
IRQ79IC
F13EH
ESFR-b 9FH
IRQ79 Interrupt Control Register 0000H
IRQ80IC
F140H
ESFR-b A0H
IRQ80 Interrupt Control Register 0000H
IRQ81IC
F142H
ESFR-b A1H
IRQ81 Interrupt Control Register 0000H
IRQ82IC
F144H
ESFR-b A2H
IRQ82 Interrupt Control Register 0000H
IRQ83IC
F146H
ESFR-b A3H
IRQ83 Interrupt Control Register 0000H
IRQ84IC
F148H
ESFR-b A4H
IRQ84 Interrupt Control Register 0000H
IRQ85IC
F14AH
ESFR-b A5H
IRQ85 Interrupt Control Register 0000H
IRQ86IC
F14CH
ESFR-b A6H
IRQ86 Interrupt Control Register 0000H
IRQ87IC
F14EH
ESFR-b A7H
IRQ87 Interrupt Control Register 0000H
IRQ88IC
F150H
ESFR-b A8H
IRQ88 Interrupt Control Register 0000H
IRQ89IC
F152H
ESFR-b A9H
IRQ89 Interrupt Control Register 0000H
IRQ90IC
F154H
ESFR-b AAH
IRQ90 Interrupt Control Register 0000H
IRQ91IC
F156H
ESFR-b ABH
IRQ91 Interrupt Control Register 0000H
IRQ92IC
F158H
ESFR-b ACH
IRQ92 Interrupt Control Register 0000H
IRQ93IC
F15AH
ESFR-b ADH
IRQ93 Interrupt Control Register 0000H
IRQ94IC
F15CH
ESFR-b AEH
IRQ94 Interrupt Control Register 0000H
IRQ95IC
F15EH
ESFR-b AFH
IRQ95 Interrupt Control Register 0000H
IRQ96IC
F0B8H
ESFR
5CH
IRQ96 Interrupt Control Register 0000H
IRQ97IC
F0BAH
ESFR
5DH
IRQ97 Interrupt Control Register 0000H
IRQ98IC
F0BCH
ESFR
5EH
IRQ98 Interrupt Control Register 0000H
IRQ99IC
F0BEH
ESFR
5FH
IRQ99 Interrupt Control Register 0000H
IRQ100IC
F0C0H
ESFR
60H
IRQ100 Interrupt Control
Register
0000H
IRQ101IC
F0C2H
ESFR
61H
IRQ101 Interrupt Control
Register
0000H
User’s Manual
4-36
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-3
SFR/ESFR Table (ordered by name) (cont’d)
Name
Physical Type1)
Address
8-bit
Addr
Description
Reset
Value
2)
IRQ102IC
F0C4H
ESFR
62H
IRQ102 Interrupt Control
Register
0000H
IRQ103IC
F0C6H
ESFR
63H
IRQ103 Interrupt Control
Register
0000H
IRQ104IC
F0C8H
ESFR
64H
IRQ104 Interrupt Control
Register
0000H
IRQ105IC
F0CAH
ESFR
65H
IRQ105 Interrupt Control
Register
0000H
IRQ106IC
F0CCH
ESFR
66H
IRQ106 Interrupt Control
Register
0000H
IRQ107IC
F0CEH
ESFR
67H
IRQ107 Interrupt Control
Register
0000H
IRQ108IC
F0D0H
ESFR
68H
IRQ108 Interrupt Control
Register
0000H
IRQ109IC
F0D2H
ESFR
69H
IRQ109 Interrupt Control
Register
0000H
IRQ110IC
F0D4H
ESFR
6AH
IRQ110 Interrupt Control
Register
0000H
IRQ111IC
F0D6H
ESFR
6BH
IRQ111 Interrupt Control
Register
0000H
MDC
FF0EH
SFR-b
87H
CPU Multiply Divide Control
Register
0000H
MDH
FE0CH
SFR
06H
CPU Multiply Divide Register High Word
0000H
MDL
FE0EH
SFR
07H
CPU Multiply Divide Register Low Word
0000H
ONES
FF1EH
SFR-b
8FH
Constant Value 1sRegister’
FFFFH
P0H
FF02H
SFR-b
81H
Port 0 High Register (Upper half) 00H
P0L
FF00H
SFR-b
80H
Port 0 Low Register (Lower half) 00H
P1H
FF06H
SFR-b
83H
Port 1 High Register (Upper half) 00H
P1L
FF04H
SFR-b
82H
Port 1 Low Register (Lower half) 00H
P4
FFC8H
SFR-b
E4H
Port 4 Register (8 bits)
User’s Manual
4-37
00H
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-3
SFR/ESFR Table (ordered by name) (cont’d)
Name
Physical Type1)
Address
8-bit
Addr
Description
Reset
Value
00H
2)
P6
FFCCH
SFR-b
E6H
Port 6 Register (8 bits)
PECC0
FEC0H
SFR
60H
PEC Channel 0 Control Register 0000H
PECC1
FEC2H
SFR
61H
PEC Channel 1 Control Register 0000H
PECC2
FEC4H
SFR
62H
PEC Channel 2 Control Register 0000H
PECC3
FEC6H
SFR
63H
PEC Channel 3 Control Register 0000H
PECC4
FEC8H
SFR
64H
PEC Channel 4 Control Register 0000H
PECC5
FECAH
SFR
65H
PEC Channel 5 Control Register 0000H
PECC6
FECCH
SFR
66H
PEC Channel 6 Control Register 0000H
PECC7
FECEH
SFR
67H
PEC Channel 7 Control Register 0000H
PECC8
FEE8H
SFR
74H
PEC Channel 8 Control Register 0000H
PECC9
FEEAH
SFR
75H
PEC Channel 9 Control Register 0000H
PECC10
FEECH
SFR
76H
PEC Channel 10 Control
Register
0000H
PECC11
FEEEH
SFR
77H
PEC Channel 11 Control
Register
0000H
PECC12
FEF8H
SFR
7CH
PEC Channel 12 Control
Register
0000H
PECC13
FEFAH
SFR
7DH
PEC Channel 13 Control
Register
0000H
PECC14
FEFCH
SFR
7EH
PEC Channel 14 Control
Register
0000H
PECC15
FEFEH
SFR
7FH
PEC Channel 15 Control
Register
0000H
PECISNC
FFA8H
SFR-b
D4H
PEC Interrupt Subnode Control
Register
0000H
PECSN0
FED0H
SFR
68H
PEC Segment No. Register
0000H
PECSN1
FED2H
SFR
69H
PEC Segment No. Register
0000H
PECSN2
FED4H
SFR
6AH
PEC Segment No. Register
0000H
PECSN3
FED6H
SFR
6BH
PEC Segment No. Register
0000H
PECSN4
FED8H
SFR
6CH
PEC Segment No. Register
0000H
User’s Manual
4-38
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-3
SFR/ESFR Table (ordered by name) (cont’d)
Name
Physical Type1)
Address
8-bit
Addr
Description
Reset
Value
2)
PECSN5
FEDAH
SFR
6DH
PEC Segment No. Register
0000H
PECSN6
FEDCH
SFR
6EH
PEC Segment No. Register
0000H
PECSN7
FEDEH
SFR
6FH
PEC Segment No. Register
0000H
PECSN8
FEE0H
SFR
70H
PEC Segment No. Register
0000H
PECSN9
FEE2H
SFR
71H
PEC Segment No. Register
0000H
PECSN10
FEE4H
SFR
72H
PEC Segment No. Register
0000H
PECSN11
FEE6H
SFR
73H
PEC Segment No. Register
0000H
PECSN12
FEB8H
SFR
5CH
PEC Segment No. Register
0000H
PECSN13
FEBAH
SFR
5DH
PEC Segment No. Register
0000H
PECSN14
FEBCH
SFR
5EH
PEC Segment No. Register
0000H
PECSN15
FEBEH
SFR
5FH
PEC Segment No. Register
0000H
PECXC0
FEF0H
SFR
78H
PEC Channel 0 Extended
Control Register
0000H
PECXC2
FEF2H
SFR
79H
PEC Channel 2 Extended
Control Register
0000H
PECXISNC
FFBAH
SFR-b
DDH
PEC Extended Interrupt
Subnode Control Register
0000H
PSW
FF10H
SFR-b
88H
CPU Program Status Word
0000H
RWDATA
F06AH
ESFR
35H
Cerberus RW Mode Data
Register
0000H
S0BG
FEB4H
SFR
5AH
Serial Channel 0 Baud Rate
Generator Reload Register
0000H
S0CON
FFB0H
SFR-b
D8H
Serial Channel 0 Control
Register
0000H
S0EIC
FF70H
SFR-b
B8H
ASC0 Error Interrupt Control
Register
0000H
S0RBUF
FEB2H
SFR
59H
Serial Channel 0 Receive Buffer 0000H
Register (RO)
S0RIC
FF6EH
SFR-b
B7H
ASC0 Receive Interrupt Control
Register
User’s Manual
4-39
0000H
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-3
SFR/ESFR Table (ordered by name) (cont’d)
Name
Physical Type1)
Address
8-bit
Addr
Description
Reset
Value
0000H
2)
S0TBIC
F19CH
ESFR-b CEH
ASC0 Transmit Buffer Interrupt
Control Register
S0TBUF
FEB0H
SFR
58H
Serial Channel 0 Transmit Buffer 0000H
Register (WO)
S0TIC
FF6CH
SFR-b
B6H
ASC0 Transmit Interrupt Control 0000H
Register
SP
FE12H
SFR
09H
CPU System Stack Pointer
Register
FC00H
SSC0BR
F0B4H
ESFR
5AH
SSC0 Baudrate Register
0000H
SSC0CON
FFB2H
SFR-b
D9H
SSC0 Control Register
0000H
SSC0EIC
FF76H
SFR-b
BBH
SSC0 Error Interrupt Control
Register
0000H
SSC0ID
FFE4H
SSC0 Identification Register
45xxH
SSC0PISEL
F0B6H
ESFR
5BH
SSC0 Port Input Selection
Register
0000H
SSC0RB
F0B2H
ESFR
59H
SSC0 Receive Buffer (RO)
0000H
SSC0RIC
FF74H
SFR-b
BAH
SSC0 Receive Interrupt Control
Register
0000H
SSC0TB
F0B0H
ESFR
58H
SSC0 Transmit Buffer (WO)
0000H
SSC0TIC
FF72H
SFR-b
B9H
SSC0 Transmit Interrupt Control 0000H
Register
STKOV
FE14H
SFR
0AH
CPU Stack Overflow Pointer
Register
FA00H
STKUN
FE16H
SFR
0BH
CPU Stack Underflow Pointer
Register
FC00H
SYSCON
FF12H
SFR-b
89H
CPU System Configuration
Register
xxxxH
T2
FE40H
SFR
20H
GPT Timer 2 Register
0000H
T2CON
FF40H
SFR-b
A0H
GPT Timer 2 Control Register
0000H
T2IC
FF60H
SFR-b
B0H
GPT12E Timer 2 Interrupt
Control Register
0000H
User’s Manual
4-40
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-3
SFR/ESFR Table (ordered by name) (cont’d)
Name
Physical Type1)
Address
8-bit
Addr
Description
Reset
Value
2)
T3
FE42H
SFR
21H
GPT Timer 3 Register
0000H
T3CON
FF42H
SFR-b
A1H
GPT Timer 3 Control Register
0000H
T3IC
FF62H
SFR-b
B1H
GPT12E Timer 3 Interrupt
Control Register
0000H
T4
FE44H
SFR
22H
GPT Timer 4 Register
0000H
T4CON
FF44H
SFR-b
A2H
GPT Timer 4 Control Register
0000H
T4IC
FF64H
SFR-b
B2H
GPT12E Timer 4 Interrupt
Control Register
0000H
T5
FE46H
SFR
23H
GPT Timer 5 Register
0000H
T5CON
FF46H
SFR-b
A3H
GPT Timer 5 Control Register
0000H
T5IC
FF66H
SFR-b
B3H
GPT12E Timer 5 Interrupt
Control Register
0000H
T6
FE48H
SFR
24H
GPT Timer 6 Register
0000H
T6CON
FF48H
SFR-b
A4H
GPT Timer 6 Control Register
0000H
T6IC
FF68H
SFR-b
B4H
GPT12E Timer 6 Interrupt
Control Register
0000H
TFR
FFACH
SFR-b
D6H
Trap Flag Register
0000H
WDT
FEAEH
SFR
57H
Watchdog Timer Register (RO)
0000H
WDTCON
FFAEH
SFR-b
D7H
Watchdog Timer Control
Register
008xH
WDTIC
F19AH
ESFR-b CDH
Watchdog Timer Interrupt
Control Register
0000H
XADRS1
F014H
ESFR
0AH
XBUS Address Select Register 1 0000H
XADRS2
F016H
ESFR
0BH
XBUS Address Select Register 2 0000H
XADRS3
F018H
ESFR
0CH
XBUS Address Select Register 3 0000H
XADRS4
F01AH
ESFR
0DH
XBUS Address Select Register 4 0000H
XADRS5
F01CH
ESFR
0EH
XBUS Address Select Register 5 0000H
XADRS6
F01EH
ESFR
0FH
XBUS Address Select Register 6 0000H
XBCON1
F114H
ESFR-b 8AH
XBUS Control register 1
0000H
XBCON2
F116H
ESFR-b 8BH
XBUS Control register 2
0000H
User’s Manual
4-41
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-3
SFR/ESFR Table (ordered by name) (cont’d)
Name
Physical Type1)
Address
8-bit
Addr
Description
Reset
Value
2)
XBCON3
F118H
ESFR-b 8CH
XBUS Control register 3
0000H
XBCON4
F11AH
ESFR-b 8DH
XBUS Control register 4
0000H
XBCON5
F11CH
ESFR-b 8EH
XBUS Control register 5
0000H
XBCON6
F11EH
ESFR-b 8FH
XBUS Control register 6
0000H
XPERCON
F024H
ESFR
12H
XBUS Peripheral Control
Register
0000H
ZEROS
FF1CH
SFR-b
8EH
Constant Value 0sRegister’
0000H
1)
The PDBUS+ chip select depends on the register type. Chip select "pd_cs_esfr" is used for register types
"ESFR" and "ESFR-b", whereas chip select "pd_cs_sfr" valid for register types "SFR" and "SFR-b"
2)
This address is identical to PDBUS+ address A[8:1]. However, for address ranges F1E0H to F1FFH and FFE0H
to FFFFH there is no 8-bit address, but a PDBUS+ address.
User’s Manual
4-42
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
4.8
Interrupt Vector Table
The interrupt vector table is an instruction table. For each interrupt a 4 byte range is
reserved for instructions. Up to 112 interrupt nodes and 16 trap entries are defined for a
C166S V1 SubS R1 based product. The subsystem itself allocates 15 interrupt nodes.
All interrupt nodes above them can be used by the product.
The table below lists all possible 112 interrupts and traps sorted by the trap number. The
maximum number of interrupt nodes depends on the subsystem configuration.
Depending on this configured number of interrupts not all below listed interrupts are
available on product level.
Example:
PARAM_IC_NODES = 16
⇒ Only one interrupt source is available on product level (irq_n_i[15]).
PARAM_IC_NODES = 48
⇒ 23 interrupt sources are available on product level (irq_n_i[15...47]).
Table 4-4
Interrupt Vector Table (sorted by trap number)
Signal Name
(Interrupt IF)
Source of Interrupt
Interrupt Control Vector
Trap
Register
Location No
-
Reset
-
0000H
00H
-
0004H
01H
-
0008H
02H
-
000CH
03H
-
0010H
04H
-
0014H
05H
-
0018H
06H
-
001CH
07H
-
0020H
08H
-
0024H
09H
-
0028H
0AH
-
-
002CH
0BH
-
-
0030H
0CH
-
-
0034H
0DH
nmi_trap_n_i
1)
Non maskable interrupt
-
Stack overflow
-
Stack underflow
-
Software Break
-
User’s Manual
Class B Trap
4-43
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-4
Signal Name
(Interrupt IF)
Interrupt Vector Table (cont’d) (sorted by trap number)
Source of Interrupt
Interrupt Control Vector
Trap
Register
Location No
-
-
0038H
0EH
-
-
003CH
0FH
irq_i[16]
Product Interrupt Request 16
IRQ16IC
0040H
10H
irq_i[17]
Product Interrupt Request 17
IRQ17IC
0044H
11H
irq_i[18]
Product Interrupt Request 18
IRQ18IC
0048H
12H
irq_i[19]
Product Interrupt Request 19
IRQ19IC
004CH
13H
irq_i[20]
Product Interrupt Request 20
IRQ20IC
0050H
14H
irq_i[21]
Product Interrupt Request 21
IRQ21IC
0054H
15H
irq_i[22]
Product Interrupt Request 22
IRQ22IC
0058H
16H
irq_i[23]
Product Interrupt Request 23
IRQ23IC
005CH
17H
irq_i[24]
Product Interrupt Request 24
IRQ24IC
0060H
18H
irq_i[25]
Product Interrupt Request 25
IRQ25IC
0064H
19H
irq_i[26]
Product Interrupt Request 26
IRQ26IC
0068H
1AH
irq_i[27]
Product Interrupt Request 27
IRQ27IC
006CH
1BH
irq_i[28]
Product Interrupt Request 28
IRQ28IC
0070H
1CH
irq_i[29]
Product Interrupt Request 29
IRQ29IC
0074H
1DH
irq_i[30]
Product Interrupt Request 30
IRQ30IC
0078H
1EH
irq_i[31]
Product Interrupt Request 31
IRQ31IC
007CH
1FH
irq_i[32]
Product Interrupt Request 32
IRQ32IC
0080H
20H
irq_i[33]
Product Interrupt Request 33
IRQ33IC
0084H
21H
per_irq_i[2]2)
GPT12E Timer T2
T2IC
0088H
22H
per_irq_i[3]2)
GPT12E Timer T3
T3IC
008CH
23H
per_irq_i[4]2)
GPT12E Timer T4
T4IC
0090H
24H
per_irq_i[5]2)
GPT12E Timer T5
T5IC
0094H
25H
per_irq_i[6]2)
GPT12E Timer T6
T6IC
0098H
26H
per_irq_i[7]2)
GPT12E Capture/Reload
CRIC
009CH
27H
irq_i[34]
Product Interrupt Request 34
IRQ34IC
00A0H
28H
irq_i[35]
Product Interrupt Request 35
IRQ35IC
00A4H
29H
per_irq_i[11]2)
ASC0 Transmit
S0TIC
00A8H
2AH
User’s Manual
4-44
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-4
Interrupt Vector Table (cont’d) (sorted by trap number)
Signal Name
(Interrupt IF)
Source of Interrupt
Interrupt Control Vector
Trap
Register
Location No
per_irq_i[12]2)
ASC0 Receive
S0RIC
00ACH
2BH
per_irq_i[13]2)
ASC0 Error
S0EIC
00B0H
2CH
per_irq_i[8]2)
SSC0 Transmit
SSC0TIC
00B4H
2DH
SSC0 Receive
SSC0RIC
00B8H
2EH
per_irq_i[10]2)
SSC0 Error
SSC0EIC
00BCH
2FH
irq_i[48]
Product Interrupt Request 48
IRQ48IC
00C0H
30H
irq_i[49]
Product Interrupt Request 49
IRQ49IC
00C4H
31H
irq_i[50]
Product Interrupt Request 50
IRQ50IC
00C8H
32H
irq_i[51]
Product Interrupt Request 51
IRQ51IC
00CCH
33H
irq_i[52]
Product Interrupt Request 52
IRQ52IC
00D0H
34H
irq_i[53]
Product Interrupt Request 53
IRQ53IC
00D4H
35H
irq_i[54]
Product Interrupt Request 54
IRQ54IC
00D8H
36H
irq_i[55]
Product Interrupt Request 55
IRQ55IC
00DCH
37H
irq_i[56]
Product Interrupt Request 56
IRQ56IC
00E0H
38H
irq_i[57]
Product Interrupt Request 57
IRQ57IC
00E4H
39H
irq_i[58]
Product Interrupt Request 58
IRQ58IC
00E8H
3AH
irq_i[59]
Product Interrupt Request 59
IRQ59IC
00ECH
3BH
irq_i[60]
Product Interrupt Request 60
IRQ60IC
00F0H
3CH
irq_i[40]
Product Interrupt Request 40
IRQ40IC
00F4H
3DH
irq_i[41]
Product Interrupt Request 41
IRQ41IC
00F8H
3EH
irq_i[15]
Product Interrupt Request 15
IRQ15IC
00FCH
3FH
irq_i[36]
Product Interrupt Request 36
IRQ36IC
0100H
40H
irq_i[37]
Product Interrupt Request 37
IRQ37IC
0104H
41H
irq_i[38]
Product Interrupt Request 38
IRQ38IC
0108H
42H
irq_i[39]
Product Interrupt Request 39
IRQ39IC
010CH
43H
irq_i[61]
Product Interrupt Request 61
IRQ61IC
0110H
44H
irq_i[62]
Product Interrupt Request 62
IRQ62IC
0114H
45H
irq_i[63]
Product Interrupt Request 63
IRQ63IC
0118H
46H
per_irq_i[14]2)
ASC0 Transmit Buffer
S0TBIC
011CH
47H
per_irq_i[9]
2)
User’s Manual
4-45
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-4
Interrupt Vector Table (cont’d) (sorted by trap number)
Signal Name
(Interrupt IF)
Source of Interrupt
Interrupt Control Vector
Trap
Register
Location No
irq_i[42]
Product Interrupt Request 42
IRQ42IC
0120H
48H
irq_i[43]
Product Interrupt Request 43
IRQ43IC
0124H
49H
Product Interrupt Request 44
IRQ44IC
0128H
4AH
Watchdog Timer
WDTIC
0130H
4BH
per_irq_i[0]2)
End of PEC Transfer
EOPIC
012CH
4CH
irq_i[45]
Product Interrupt Request 45
IRQ45IC
0134H
4DH
irq_i[46]
Product Interrupt Request 46
IRQ46IC
0138H
4EH
irq_i[47]
Product Interrupt Request 47
IRQ47IC
013CH
4FH
irq_i[64]
Product Interrupt Request 64
IRQ64IC
0140H
50H
irq_i[65]
Product Interrupt Request 65
IRQ65IC
0144H
51H
irq_i[66]
Product Interrupt Request 66
IRQ66IC
0148H
52H
irq_i[67]
Product Interrupt Request 67
IRQ67IC
014CH
53H
irq_i[68]
Product Interrupt Request 68
IRQ68IC
0150H
54H
irq_i[69]
Product Interrupt Request 69
IRQ69IC
0154H
55H
irq_i[70]
Product Interrupt Request 70
IRQ70IC
0158H
56H
irq_i[71]
Product Interrupt Request 71
IRQ71IC
015CH
57H
irq_i[72]
Product Interrupt Request 72
IRQ72IC
0160H
58H
irq_i[73]
Product Interrupt Request 73
IRQ73IC
0164H
59H
irq_i[74]
Product Interrupt Request 74
IRQ74IC
0168H
5AH
irq_i[75]
Product Interrupt Request 75
IRQ75IC
016CH
5BH
irq_i[76]
Product Interrupt Request 76
IRQ76IC
0170H
5CH
irq_i[77]
Product Interrupt Request 77
IRQ77IC
0174H
5DH
irq_i[78]
Product Interrupt Request 78
IRQ78IC
0178H
5EH
irq_i[79]
Product Interrupt Request 79
IRQ79IC
017CH
5FH
irq_i[80]
Product Interrupt Request 80
IRQ50IC
0180H
60H
irq_i[81]
Product Interrupt Request 81
IRQ81IC
0184H
61H
irq_i[82]
Product Interrupt Request 82
IRQ82IC
0188H
62H
irq_i[83]
Product Interrupt Request 83
IRQ83IC
018CH
63H
irq_i[84]
Product Interrupt Request 84
IRQ84IC
0190H
64H
irq_i[44]
per_irq_i[1]
2)
User’s Manual
4-46
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-4
Interrupt Vector Table (cont’d) (sorted by trap number)
Signal Name
(Interrupt IF)
Source of Interrupt
Interrupt Control Vector
Trap
Register
Location No
irq_i[85]
Product Interrupt Request 85
IRQ85IC
0194H
65H
irq_i[86]
Product Interrupt Request 86
IRQ86IC
0198H
66H
irq_i[87]
Product Interrupt Request 87
IRQ87IC
019CH
67H
irq_i[88]
Product Interrupt Request 88
IRQ88IC
01A0H
68H
irq_i[89]
Product Interrupt Request 89
IRQ89IC
01A4H
69H
irq_i[90]
Product Interrupt Request 90
IRQ90IC
01A8H
6AH
irq_i[91]
Product Interrupt Request 91
IRQ91IC
01ACH
6BH
irq_i[92]
Product Interrupt Request 92
IRQ92IC
01B0H
6CH
irq_i[93]
Product Interrupt Request 93
IRQ93IC
01B4H
6DH
irq_i[94]
Product Interrupt Request 94
IRQ94IC
01B8H
6EH
irq_i[95]
Product Interrupt Request 95
IRQ95IC
01BCH
6FH
irq_i[96]
Product Interrupt Request 96
IRQ96IC
01C0H
70H
irq_i[97]
Product Interrupt Request 97
IRQ97IC
01C4H
71H
irq_i[98]
Product Interrupt Request 98
IRQ98IC
01C8H
72H
irq_i[99]
Product Interrupt Request 99
IRQ99IC
01CCH
73H
irq_i[100]
Product Interrupt Request 100
IRQ100IC
01D0H
74H
irq_i[101]
Product Interrupt Request 101
IRQ101IC
01D4H
75H
irq_i[102]
Product Interrupt Request 102
IRQ102IC
01D8H
76H
irq_i[103]
Product Interrupt Request 103
IRQ103IC
01DCH
77H
irq_i[104]
Product Interrupt Request 104
IRQ104IC
01E0H
78H
irq_i[105]
Product Interrupt Request 105
IRQ105IC
01E4H
79H
irq_i[106]
Product Interrupt Request 106
IRQ106IC
01E8H
7AH
irq_i[107]
Product Interrupt Request 107
IRQ107IC
01ECH
7BH
irq_i[108]
Product Interrupt Request 108
IRQ108IC
01F0H
7CH
irq_i[109]
Product Interrupt Request 109
IRQ109IC
01F4H
7DH
irq_i[110]
Product Interrupt Request 110
IRQ110IC
01F8H
7EH
irq_i[111]
Product Interrupt Request 111
IRQ111IC
01FCH
7FH
1)
This signal is part of the general signals interface and is handled by the CPU directly (not handled by the
interrupt controller).
2)
This signals are not part of the subsystem boundary, but included in the core macro´s interrupt interface.
User’s Manual
4-47
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
The following table lists all possible 97 interrupt source entries, which are available on
product level (listed by the interrupt interface signal name).
Note: Depending on the number of interrupt configuration not all entries are available
(see Page 4-43)
Table 4-5
Interrupt Vector Table (sorted by signal name)
Signal Name
(Interrupt IF)
Source of Interrupt
Interrupt Control Vector
Trap
Register
Location No
irq_i[15]
Product Interrupt Request 15
IRQ15IC
00FCH
3FH
irq_i[16]
Product Interrupt Request 16
IRQ16IC
0040H
10H
irq_i[17]
Product Interrupt Request 17
IRQ17IC
0044H
11H
irq_i[18]
Product Interrupt Request 18
IRQ18IC
0048H
12H
irq_i[19]
Product Interrupt Request 19
IRQ19IC
004CH
13H
irq_i[20]
Product Interrupt Request 20
IRQ20IC
0050H
14H
irq_i[21]
Product Interrupt Request 21
IRQ21IC
0054H
15H
irq_i[22]
Product Interrupt Request 22
IRQ22IC
0058H
16H
irq_i[23]
Product Interrupt Request 23
IRQ23IC
005CH
17H
irq_i[24]
Product Interrupt Request 24
IRQ24IC
0060H
18H
irq_i[25]
Product Interrupt Request 25
IRQ25IC
0064H
19H
irq_i[26]
Product Interrupt Request 26
IRQ26IC
0068H
1AH
irq_i[27]
Product Interrupt Request 27
IRQ27IC
006CH
1BH
irq_i[28]
Product Interrupt Request 28
IRQ28IC
0070H
1CH
irq_i[29]
Product Interrupt Request 29
IRQ29IC
0074H
1DH
irq_i[30]
Product Interrupt Request 30
IRQ30IC
0078H
1EH
irq_i[31]
Product Interrupt Request 31
IRQ31IC
007CH
1FH
irq_i[32]
Product Interrupt Request 32
IRQ32IC
0080H
20H
irq_i[33]
Product Interrupt Request 33
IRQ33IC
0084H
21H
irq_i[34]
Product Interrupt Request 34
IRQ34IC
00A0H
28H
irq_i[35]
Product Interrupt Request 35
IRQ35IC
00A4H
29H
irq_i[36]
Product Interrupt Request 36
IRQ36IC
0100H
40H
irq_i[37]
Product Interrupt Request 37
IRQ37IC
0104H
41H
irq_i[38]
Product Interrupt Request 38
IRQ38IC
0108H
42H
irq_i[39]
Product Interrupt Request 39
IRQ39IC
010CH
43H
User’s Manual
4-48
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-5
Interrupt Vector Table (cont’d) (sorted by signal name)
Signal Name
(Interrupt IF)
Source of Interrupt
Interrupt Control Vector
Trap
Register
Location No
irq_i[40]
Product Interrupt Request 40
IRQ40IC
00F4H
3DH
irq_i[41]
Product Interrupt Request 41
IRQ41IC
00F8H
3EH
irq_i[42]
Product Interrupt Request 42
IRQ42IC
0120H
48H
irq_i[43]
Product Interrupt Request 43
IRQ43IC
0124H
49H
irq_i[44]
Product Interrupt Request 44
IRQ44IC
0128H
4AH
irq_i[45]
Product Interrupt Request 45
IRQ45IC
0134H
4DH
irq_i[46]
Product Interrupt Request 46
IRQ46IC
0138H
4EH
irq_i[47]
Product Interrupt Request 47
IRQ47IC
013CH
4FH
irq_i[48]
Product Interrupt Request 48
IRQ48IC
00C0H
30H
irq_i[49]
Product Interrupt Request 49
IRQ49IC
00C4H
31H
irq_i[50]
Product Interrupt Request 50
IRQ50IC
00C8H
32H
irq_i[51]
Product Interrupt Request 51
IRQ51IC
00CCH
33H
irq_i[52]
Product Interrupt Request 52
IRQ52IC
00D0H
34H
irq_i[53]
Product Interrupt Request 53
IRQ53IC
00D4H
35H
irq_i[54]
Product Interrupt Request 54
IRQ54IC
00D8H
36H
irq_i[55]
Product Interrupt Request 55
IRQ55IC
00DCH
37H
irq_i[56]
Product Interrupt Request 56
IRQ56IC
00E0H
38H
irq_i[57]
Product Interrupt Request 57
IRQ57IC
00E4H
39H
irq_i[58]
Product Interrupt Request 58
IRQ58IC
00E8H
3AH
irq_i[59]
Product Interrupt Request 59
IRQ59IC
00ECH
3BH
irq_i[60]
Product Interrupt Request 60
IRQ60IC
00F0H
3CH
irq_i[61]
Product Interrupt Request 61
IRQ61IC
0110H
44H
irq_i[62]
Product Interrupt Request 62
IRQ62IC
0114H
45H
irq_i[63]
Product Interrupt Request 63
IRQ63IC
0118H
46H
irq_i[64]
Product Interrupt Request 64
IRQ64IC
0140H
50H
irq_i[65]
Product Interrupt Request 65
IRQ65IC
0144H
51H
irq_i[66]
Product Interrupt Request 66
IRQ66IC
0148H
52H
irq_i[67]
Product Interrupt Request 67
IRQ67IC
014CH
53H
irq_i[68]
Product Interrupt Request 68
IRQ68IC
0150H
54H
User’s Manual
4-49
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-5
Interrupt Vector Table (cont’d) (sorted by signal name)
Signal Name
(Interrupt IF)
Source of Interrupt
Interrupt Control Vector
Trap
Register
Location No
irq_i[69]
Product Interrupt Request 69
IRQ69IC
0154H
55H
irq_i[70]
Product Interrupt Request 70
IRQ70IC
0158H
56H
irq_i[71]
Product Interrupt Request 71
IRQ71IC
015CH
57H
irq_i[72]
Product Interrupt Request 72
IRQ72IC
0160H
58H
irq_i[73]
Product Interrupt Request 73
IRQ73IC
0164H
59H
irq_i[74]
Product Interrupt Request 74
IRQ74IC
0168H
5AH
irq_i[75]
Product Interrupt Request 75
IRQ75IC
016CH
5BH
irq_i[76]
Product Interrupt Request 76
IRQ76IC
0170H
5CH
irq_i[77]
Product Interrupt Request 77
IRQ77IC
0174H
5DH
irq_i[78]
Product Interrupt Request 78
IRQ78IC
0178H
5EH
irq_i[79]
Product Interrupt Request 79
IRQ79IC
017CH
5FH
irq_i[80]
Product Interrupt Request 80
IRQ50IC
0180H
60H
irq_i[81]
Product Interrupt Request 81
IRQ81IC
0184H
61H
irq_i[82]
Product Interrupt Request 82
IRQ82IC
0188H
62H
irq_i[83]
Product Interrupt Request 83
IRQ83IC
018CH
63H
irq_i[84]
Product Interrupt Request 84
IRQ84IC
0190H
64H
irq_i[85]
Product Interrupt Request 85
IRQ85IC
0194H
65H
irq_i[86]
Product Interrupt Request 86
IRQ86IC
0198H
66H
irq_i[87]
Product Interrupt Request 87
IRQ87IC
019CH
67H
irq_i[88]
Product Interrupt Request 88
IRQ88IC
01A0H
68H
irq_i[89]
Product Interrupt Request 89
IRQ89IC
01A4H
69H
irq_i[90]
Product Interrupt Request 90
IRQ90IC
01A8H
6AH
irq_i[91]
Product Interrupt Request 91
IRQ91IC
01ACH
6BH
irq_i[92]
Product Interrupt Request 92
IRQ92IC
01B0H
6CH
irq_i[93]
Product Interrupt Request 93
IRQ93IC
01B4H
6DH
irq_i[94]
Product Interrupt Request 94
IRQ94IC
01B8H
6EH
irq_i[95]
Product Interrupt Request 95
IRQ95IC
01BCH
6FH
irq_i[96]
Product Interrupt Request 96
IRQ96IC
01C0H
70H
irq_i[97]
Product Interrupt Request 97
IRQ97IC
01C4H
71H
User’s Manual
4-50
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
Table 4-5
Interrupt Vector Table (cont’d) (sorted by signal name)
Signal Name
(Interrupt IF)
Source of Interrupt
Interrupt Control Vector
Trap
Register
Location No
irq_i[98]
Product Interrupt Request 98
IRQ98IC
01C8H
72H
irq_i[99]
Product Interrupt Request 99
IRQ99IC
01CCH
73H
irq_i[100]
Product Interrupt Request 100
IRQ100IC
01D0H
74H
irq_i[101]
Product Interrupt Request 101
IRQ101IC
01D4H
75H
irq_i[102]
Product Interrupt Request 102
IRQ102IC
01D8H
76H
irq_i[103]
Product Interrupt Request 103
IRQ103IC
01DCH
77H
irq_i[104]
Product Interrupt Request 104
IRQ104IC
01E0H
78H
irq_i[105]
Product Interrupt Request 105
IRQ105IC
01E4H
79H
irq_i[106]
Product Interrupt Request 106
IRQ106IC
01E8H
7AH
irq_i[107]
Product Interrupt Request 107
IRQ107IC
01ECH
7BH
irq_i[108]
Product Interrupt Request 108
IRQ108IC
01F0H
7CH
irq_i[109]
Product Interrupt Request 109
IRQ109IC
01F4H
7DH
irq_i[110]
Product Interrupt Request 110
IRQ110IC
01F8H
7EH
irq_i[111]
Product Interrupt Request 111
IRQ111IC
01FCH
7FH
User’s Manual
4-51
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Memory Organization
User’s Manual
4-52
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Instruction Set
5
Instruction Set
5.1
Short Instruction Summary
The following compressed cross-reference tables quickly identify a specific instruction
and provide basic information about it. Two ordering schemes are included:
The first table (two pages) is a compressed cross-reference table that quickly identifies
a specific hexadecimal opcode with the respective mnemonic.
The second table lists the instructions by their mnemonic and identifies the addressing
modes that may be used with a specific instruction and the instruction length depending
on the selected addressing mode. This reference helps to optimize instruction
sequences in terms of code size and/or execution time.
Note: Both ordering schemes (hexadecimal opcode and mnemonic) are provided in
more detailed lists in the following sections of this manual.
•
0x
1x
2x
3x
4x
5x
6x
7x
x0
ADD
ADDC
SUB
SUBC
CMP
XOR
AND
OR
x1
ADDB
ADDCB
SUBB
SUBCB
CMPB
XORB
ANDB
ORB
x2
ADD
ADDC
SUB
SUBC
CMP
XOR
AND
OR
x3
ADDB
ADDCB
SUBB
SUBCB
CMPB
XORB
ANDB
ORB
x4
ADD
ADDC
SUB
SUBC
-
XOR
AND
OR
x5
ADDB
ADDCB
SUBB
SUBCB
-
XORB
ANDB
ORB
x6
ADD
ADDC
SUB
SUBC
CMP
XOR
AND
OR
x7
ADDB
ADDCB
SUBB
SUBCB
CMPB
XORB
ANDB
ORB
x8
ADD
ADDC
SUB
SUBC
CMP
XOR
AND
OR
x9
ADDB
ADDCB
SUBB
SUBCB
CMPB
XORB
ANDB
ORB
xA BFLDL
BFLDH
BCMP
BMOVN BMOV
BOR
BAND
BXOR
xB MUL
MULU
PRIOR
-
DIV
DIVU
DIVL
DIVLU
xC ROL
ROL
ROR
ROR
SHL
SHL
SHR
SHR
xD JMPR
JMPR
JMPR
JMPR
JMPR
JMPR
JMPR
JMPR
xE BCLR
BCLR
BCLR
BCLR
BCLR
BCLR
BCLR
BCLR
xF
BSET
BSET
BSET
BSET
BSET
BSET
BSET
BSET
User’s Manual
5-1
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Instruction Set
Note: Both ordering schemes (hexadecimal opcode and mnemonic) are provided in
more detailed lists in the following sections of this manual.
8x
9x
Ax
Bx
Cx
Dx
x0
CMPI1
CMPI2
CMPD1
CMPD2
MOVBZ
MOVBS MOV
MOV
x1
NEG
CPL
NEGB
CPLB
-
AT/
EXTR
MOVB
x2
CMPI1
CMPI2
CMPD1
CMPD2
MOVBZ
MOVBS PCALL
MOV
x3
-
-
-
-
-
-
-
MOVB
x4
MOV
MOV
MOVB
MOVB
MOV
MOV
MOVB
MOVB
x5
-
-
DIS
WDT
EINIT
MOVBZ
MOVBS -
-
x6
CMPI1
CMPI2
CMPD1
CMPD2
SCXT
SCXT
MOV
x7
IDLE
PWRDN SRV
WDT
SRST
-
EXTP/S/ MOVB
R
MOVB
x8
MOV
MOV
MOV
MOV
MOV
MOV
MOV
-
x9
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
-
xA JB
JNB
JBC
JNBS
CALLA
CALLS
JMPA
JMPS
xB -
TRAP
CALLI
CALLR
RET
RETS
RETP
RETI
xC -
JMPI
ASHR
ASHR
NOP
EXTP/S/ PUSH
R
POP
xD JMPR
JMPR
JMPR
JMPR
JMPR
JMPR
JMPR
JMPR
xE BCLR
BCLR
BCLR
BCLR
BCLR
BCLR
BCLR
BCLR
xF BSET
BSET
BSET
BSET
BSET
BSET
BSET
BSET
User’s Manual
5-2
Ex
Fx
MOVB
MOV
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Instruction Set
5.2
Instruction Set Summary
This chapter summarizes the instructions by listing them according to their functional
class. This allows to identify the right instruction(s) for a specific required function.
The following notes apply to this summary:
Data Addressing Modes
Rw:
–
Word GPR (R0, R1, … , R15)
Rb:
–
Byte GPR (RL0, RH0, …, RL7, RH7)
reg:
–
SFR or GPR
(in case of a byte operation on an SFR, only the low byte can be
accessed via ‘reg’)
mem:
–
Direct word or byte memory location
[…]:
–
Indirect word or byte memory location
(Any word GPR can be used as indirect address pointer, except for the
arithmetic, logical and compare instructions, where only R0 to R3 are
allowed)
bitaddr:
–
Direct bit in the bit-addressable memory area
bitoff:
–
Direct word in the bit-addressable memory area
#data:
–
Immediate constant
(The number of significant bits which can be specified by the user is
represented by the respective appendix ’x’)
#mask8: –
Immediate 8-bit mask used for bit-field modifications
Multiply and Divide Operations
The MDL and MDH registers are implicit source and/or destination operands of the
multiply and divide instructions.
Branch Target Addressing Modes
caddr:
–
Direct 16-bit jump target address (Updates the Instruction Pointer)
seg:
–
Direct 2-bit segment address
(Updates the Code Segment Pointer)
rel:
–
Signed 8-bit jump target word offset address relative to the Instruction
Pointer of the following instruction
User’s Manual
5-3
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Instruction Set
#trap7:
–
Immediate 7-bit trap or interrupt number.
Extension Operations
The EXT* instructions override the standard DPP addressing scheme:
#pag10:
–
Immediate 10-bit page address.
#seg8:
–
Immediate 8-bit segment address.
Branch Condition Codes
cc:
Symbolically specifiable condition codes
cc_UC
cc_Z
cc_NZ
cc_V
cc_NV
cc_N
cc_NN
cc_C
cc_NC
cc_EQ
cc_NE
cc_ULT
cc_ULE
cc_UGE
cc_UGT
cc_SLE
cc_SGE
cc_SGT
cc_NET
User’s Manual
–Unconditional
–Zero
–Not Zero
–Overflow
–No Overflow
–Negative
–Not Negative
–Carry
–No Carry
–Equal
–Not Equal
–Unsigned Less Than
–Unsigned Less Than or Equal
–Unsigned Greater Than or Equal
–Unsigned Greater Than
–Signed Less Than or Equal
–Signed Greater Than or Equal
–Signed Greater Than
–Not Equal and Not End-of-Table
5-4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Instruction Set
Mnemonic
ADD[B]
ADDC[B]
AND[B]
OR[B]
SUB[B]
SUBC[B]
XOR[B]
Addressing ModesBytes
Rwn
Rwm
Rwn
[Rwi]
Rwn
[Rwi+]
Rwn
#data3
reg
reg
mem
#data16
mem
reg
4
4
4
ASHR
ROL / ROR
SHL / SHR
BAND
BCMP
BMOV
BMOVN
BOR /
BXOR
BCLR
BSET
BFLDH
BFLDL
MOV[B]
Rwn
Rwn
Rwm
#data4
2
2
Mnemonic
CPL[B]
NEG[B]
DIV
DIVL
DIVLU
DIVU
MUL
MULU
CMPD1/2
CMPI1/2
bitaddrZ.z
bitaddrQ.q
4
CMP[B]
2
CALLA
JMPA
CALLI
JMPI
CALLS
JMPS
CALLR
JMPR
JB
JBC
JNB
JNBS
PCALL
POP
PUSH
RETP
SCXT
MOVBS
MOVBZ
EXTS
EXTSR
NOP
RET
RETI
RETS
1)
2)
1)
1)
1)
1)
bitaddrQ.q
2
2
2
2
bitoffQ
#mask8 #data8 4
Rwn
Rwn
Rwn
Rwn
[Rwm]
[-Rwm]
[Rwn]
[Rwn+]
[Rwn]
Rwm
#data4
[Rwm]
[Rwm+]
Rwn
Rwn
[Rwm]
[Rwm]
[Rwm+]
1)
1)
1)
1)
1)
1)
2
2
2
2
2
2
2
2
2
reg
Rwn
[Rwm+#d16]
[Rwn]
mem
reg
mem
Rwn
reg
mem
#data16
[Rwm+#d16]
Rwn
mem
[Rwn]
mem
reg
Rbm
mem
reg
2)
1)
1)
4
4
4
4
4
4
4
2
4
4
Rwm
#seg
-
#irang2
#irang2
PRIOR
TRAP
ATOMIC
EXTR
EXTP
EXTPR
SRST/IDLE
PWRDN
SRVWDT
DISWDT
EINIT
2
4
2
Addressing ModesBytes
Rwn
1)
Rwn
2
2
Rwn
Rwm
2
Rwn
Rwn
Rwn
Rwn
Rwn
Rwn
Rwn
reg
reg
cc
#data4
#data16
mem
Rwm
[Rwi]
[Rwi+]
#data3
#data16
mem
caddr
2
4
4
2
2
2
2
4
4
4
cc
[Rwn]
2
seg
caddr
4
rel
cc
bitaddrQ.q
rel
rel
2
2
4
1)
1)
1)
1)
2)
reg
reg
caddr
4
2
reg
reg
Rwn
#data16
mem
Rwm
4
4
2
#trap7
#irang2
Rwm
#pag
-
2
2
#irang2
#irang2
2
4
4
Byte oriented instructions (suffix ‘B’) use Rb instead of Rw (not with [Rwn]!).
Byte oriented instructions (suffix ‘B’) use #data8 instead of #data16.
User’s Manual
5-5
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Instruction Set
Instruction Set Summary
Mnemonic
Description
Bytes
Arithmetic Operations
ADD
Rw, Rw
Add direct word GPR to direct GPR
2
ADD
Rw, [Rw]
Add indirect word memory to direct GPR
2
ADD
Rw, [Rw +]
Add indirect word memory to direct GPR and postincrement source pointer by 2
2
ADD
Rw, #data3
Add immediate word data to direct GPR
2
ADD
reg, #data16
Add immediate word data to direct register
4
ADD
reg, mem
Add direct word memory to direct register
4
ADD
mem, reg
Add direct word register to direct memory
4
ADDB
Rb, Rb
Add direct byte GPR to direct GPR
2
ADDB
Rb, [Rw]
Add indirect byte memory to direct GPR
2
ADDB
Rb, [Rw +]
Add indirect byte memory to direct GPR and
post-increment source pointer by 1
2
ADDB
Rb, #data3
Add immediate byte data to direct GPR
2
ADDB
reg, #data8
Add immediate byte data to direct register
4
ADDB
reg, mem
Add direct byte memory to direct register
4
ADDB
mem, reg
Add direct byte register to direct memory
4
ADDC
Rw, Rw
Add direct word GPR to direct GPR with Carry
2
ADDC
Rw, [Rw]
Add indirect word memory to direct GPR with Carry
2
ADDC
Rw, [Rw +]
Add indirect word memory to direct GPR with Carry and
post-increment source pointer by 2
2
ADDC
Rw, #data3
Add immediate word data to direct GPR with Carry
2
ADDC
reg, #data16
Add immediate word data to direct register with Carry
4
ADDC
reg, mem
Add direct word memory to direct register with Carry
4
ADDC
mem, reg
Add direct word register to direct memory with Carry
4
ADDCB
Rb, Rb
Add direct byte GPR to direct GPR with Carry
2
ADDCB
Rb, [Rw]
Add indirect byte memory to direct GPR with Carry
2
ADDCB
Rb, [Rw +]
Add indirect byte memory to direct GPR with Carry and
post-increment source pointer by 1
2
ADDCB
Rb, #data3
Add immediate byte data to direct GPR with Carry
2
ADDCB
reg, #data8
Add immediate byte data to direct register with Carry
4
ADDCB
reg, mem
Add direct byte memory to direct register with Carry
4
User’s Manual
5-6
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Instruction Set
Instruction Set Summary (cont’d)
Mnemonic
Description
Bytes
Arithmetic Operations (cont’d)
ADDCB
mem, reg
Add direct byte register to direct memory with Carry
4
SUB
Rw, Rw
Subtract direct word GPR from direct GPR
2
SUB
Rw, [Rw]
Subtract indirect word memory from direct GPR
2
SUB
Rw, [Rw +]
Subtract indirect word memory from direct GPR and
post-increment source pointer by 2
2
SUB
Rw, #data3
Subtract immediate word data from direct GPR
2
SUB
reg, #data16
Subtract immediate word data from direct register
4
SUB
reg, mem
Subtract direct word memory from direct register
4
SUB
mem, reg
Subtract direct word register from direct memory
4
SUBB
Rb, Rb
Subtract direct byte GPR from direct GPR
2
SUBB
Rb, [Rw]
Subtract indirect byte memory from direct GPR
2
SUBB
Rb, [Rw +]
Subtract indirect byte memory from direct GPR and
post-increment source pointer by 1
2
SUBB
Rb, #data3
Subtract immediate byte data from direct GPR
2
SUBB
reg, #data8
Subtract immediate byte data from direct register
4
SUBB
reg, mem
Subtract direct byte memory from direct register
4
SUBB
mem, reg
Subtract direct byte register from direct memory
4
SUBC
Rw, Rw
Subtract direct word GPR from direct GPR with Carry
2
SUBC
Rw, [Rw]
Subtract indirect word memory from direct GPR with Carry
2
SUBC
Rw, [Rw +]
Subtract indirect word memory from direct GPR with
Carry and post-increment source pointer by 2
2
SUBC
Rw, #data3
Subtract immediate word data from direct GPR with Carry
2
SUBC
reg, #data16
Subtract immediate word data from direct register with
Carry
4
SUBC
reg, mem
Subtract direct word memory from direct register with Carry 4
SUBC
mem, reg
Subtract direct word register from direct memory with Carry 4
SUBCB
Rb, Rb
Subtract direct byte GPR from direct GPR with Carry
2
SUBCB
Rb, [Rw]
Subtract indirect byte memory from direct GPR with Carry
2
SUBCB
Rb, [Rw +]
Subtract indirect byte memory from direct GPR with Carry
and post-increment source pointer by 1
2
SUBCB
Rb, #data3
Subtract immediate byte data from direct GPR with Carry
2
SUBCB
reg, #data8
Subtract immediate byte data from direct register with Carry 4
User’s Manual
5-7
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Instruction Set
Instruction Set Summary (cont’d)
Mnemonic
Description
Bytes
Arithmetic Operations (cont’d)
SUBCB
reg, mem
Subtract direct byte memory from direct register with Carry
4
SUBCB
mem, reg
Subtract direct byte register from direct memory with Carry
4
MUL
Rw, Rw
Signed multiply direct GPR by direct GPR (16-16-bit)
2
MULU
Rw, Rw
Unsigned multiply direct GPR by direct GPR (16-16-bit)
2
DIV
Rw
Signed divide register MDL by direct GPR (16-/16-bit)
2
DIVL
Rw
Signed long divide register MD by direct GPR (32-/16-bit)
2
DIVLU
Rw
Unsigned long divide register MD by direct GPR
(32-/16-bit)
2
DIVU
Rw
Unsigned divide register MDL by direct GPR (16-/16-bit)
2
CPL
Rw
Complement direct word GPR
2
CPLB
Rb
Complement direct byte GPR
2
NEG
Rw
Negate direct word GPR
2
NEGB
Rb
Negate direct byte GPR
2
Logical Instructions
AND
Rw, Rw
Bitwise AND direct word GPR with direct GPR
2
AND
Rw, [Rw]
Bitwise AND indirect word memory with direct GPR
2
AND
Rw, [Rw +]
Bitwise AND indirect word memory with direct GPR and
post-increment source pointer by 2
2
AND
Rw, #data3
Bitwise AND immediate word data with direct GPR
2
AND
reg, #data16
Bitwise AND immediate word data with direct register
4
AND
reg, mem
Bitwise AND direct word memory with direct register
4
AND
mem, reg
Bitwise AND direct word register with direct memory
4
ANDB
Rb, Rb
Bitwise AND direct byte GPR with direct GPR
2
ANDB
Rb, [Rw]
Bitwise AND indirect byte memory with direct GPR
2
ANDB
Rb, [Rw +]
Bitwise AND indirect byte memory with direct GPR
and post-increment source pointer by 1
2
ANDB
Rb, #data3
Bitwise AND immediate byte data with direct GPR
2
ANDB
reg, #data8
Bitwise AND immediate byte data with direct register
4
ANDB
reg, mem
Bitwise AND direct byte memory with direct register
4
ANDB
mem, reg
Bitwise AND direct byte register with direct memory
4
User’s Manual
5-8
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Instruction Set
Instruction Set Summary (cont’d)
Mnemonic
Description
Bytes
Logical Instructions (cont’d)
OR
Rw, Rw
Bitwise OR direct word GPR with direct GPR
2
OR
Rw, [Rw]
Bitwise OR indirect word memory with direct GPR
2
OR
Rw, [Rw +]
Bitwise OR indirect word memory with direct GPR
and post-increment source pointer by 2
2
OR
Rw, #data3
Bitwise OR immediate word data with direct GPR
2
OR
reg, #data16
Bitwise OR immediate word data with direct register
4
OR
reg, mem
Bitwise OR direct word memory with direct register
4
OR
mem, reg
Bitwise OR direct word register with direct memory
4
ORB
Rb, Rb
Bitwise OR direct byte GPR with direct GPR
2
ORB
Rb, [Rw]
Bitwise OR indirect byte memory with direct GPR
2
ORB
Rb, [Rw +]
Bitwise OR indirect byte memory with direct GPR and
post-increment source pointer by 1
2
ORB
Rb, #data3
Bitwise OR immediate byte data with direct GPR
2
ORB
reg, #data8
Bitwise OR immediate byte data with direct register
4
ORB
reg, mem
Bitwise OR direct byte memory with direct register
4
ORB
mem, reg
Bitwise OR direct byte register with direct memory
4
XOR
Rw, Rw
Bitwise XOR direct word GPR with direct GPR
2
XOR
Rw, [Rw]
Bitwise XOR indirect word memory with direct GPR
2
XOR
Rw, [Rw +]
Bitwise XOR indirect word memory with direct GPR and
post-increment source pointer by 2
2
XOR
Rw, #data3
Bitwise XOR immediate word data with direct GPR
2
XOR
reg, #data16
Bitwise XOR immediate word data with direct register
4
XOR
reg, mem
Bitwise XOR direct word memory with direct register
4
XOR
mem, reg
Bitwise XOR direct word register with direct memory
4
XORB
Rb, Rb
Bitwise XOR direct byte GPR with direct GPR
2
XORB
Rb, [Rw]
Bitwise XOR indirect byte memory with direct GPR
2
XORB
Rb, [Rw +]
Bitwise XOR indirect byte memory with direct GPR and
post-increment source pointer by 1
2
XORB
Rb, #data3
Bitwise XOR immediate byte data with direct GPR
2
XORB
reg, #data8
Bitwise XOR immediate byte data with direct register
4
XORB
reg, mem
Bitwise XOR direct byte memory with direct register
4
XORB
mem, reg
Bitwise XOR direct byte register with direct memory
4
User’s Manual
5-9
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Instruction Set
Instruction Set Summary (cont’d)
Mnemonic
Description
Bytes
Boolean Bit Manipulation Operations
BCLR
bitaddr
Clear direct bit
2
BSET
bitaddr
Set direct bit
2
BMOV
bitaddr, bitaddr
Move direct bit to direct bit
4
BMOVN
bitaddr, bitaddr
Move negated direct bit to direct bit
4
BAND
bitaddr, bitaddr
AND direct bit with direct bit
4
BOR
bitaddr, bitaddr
OR direct bit with direct bit
4
BXOR
bitaddr, bitaddr
XOR direct bit with direct bit
4
BCMP
bitaddr, bitaddr
Compare direct bit to direct bit
4
BFLDH
bitoff, #mask8,
#data8
Bitwise modify masked high byte of bit-addressable
direct word memory with immediate data
4
BFLDL
bitoff, #mask8,
#data8
Bitwise modify masked low byte of bit-addressable
direct word memory with immediate data
4
CMP
Rw, Rw
Compare direct word GPR to direct GPR
2
CMP
Rw, [Rw]
Compare indirect word memory to direct GPR
2
CMP
Rw, [Rw +]
Compare indirect word memory to direct GPR and
post-increment source pointer by 2
2
CMP
Rw, #data3
Compare immediate word data to direct GPR
2
CMP
reg, #data16
Compare immediate word data to direct register
4
CMP
reg, mem
Compare direct word memory to direct register
4
CMPB
Rb, Rb
Compare direct byte GPR to direct GPR
2
CMPB
Rb, [Rw]
Compare indirect byte memory to direct GPR
2
CMPB
Rb, [Rw +]
Compare indirect byte memory to direct GPR and
post-increment source pointer by 1
2
CMPB
Rb, #data3
Compare immediate byte data to direct GPR
2
CMPB
reg, #data8
Compare immediate byte data to direct register
4
CMPB
reg, mem
Compare direct byte memory to direct register
4
Compare and Loop Control Instructions
CMPD1
Rw, #data4
Compare immediate word data to direct GPR and
decrement GPR by 1
2
CMPD1
Rw, #data16
Compare immediate word data to direct GPR and
decrement GPR by 1
4
User’s Manual
5-10
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Instruction Set
Instruction Set Summary (cont’d)
Mnemonic
Description
Bytes
Compare and Loop Control Instructions (cont’d)
CMPD1
Rw, mem
Compare direct word memory to direct GPR and
decrement GPR by 1
4
CMPD2
Rw, #data4
Compare immediate word data to direct GPR and
decrement GPR by 2
2
CMPD2
Rw, #data16
Compare immediate word data to direct GPR and
decrement GPR by 2
4
CMPD2
Rw, mem
Compare direct word memory to direct GPR and
decrement GPR by 2
4
CMPI1
Rw, #data4
Compare immediate word data to direct GPR and
increment GPR by 1
2
CMPI1
Rw, #data16
Compare immediate word data to direct GPR and
increment GPR by 1
4
CMPI1
Rw, mem
Compare direct word memory to direct GPR and
increment GPR by 1
4
CMPI2
Rw, #data4
Compare immediate word data to direct GPR and
increment GPR by 2
2
CMPI2
Rw, #data16
Compare immediate word data to direct GPR and
increment GPR by 2
4
CMPI2
Rw, mem
Compare direct word memory to direct GPR and
increment GPR by 2
4
Determine number of shift cycles to normalize direct
word GPR and store result in direct word GPR
2
Prioritize Instruction
PRIOR
Rw, Rw
Shift and Rotate Instructions
SHL
Rw, Rw
Shift left direct word GPR;
number of shift cycles specified by direct GPR
2
SHL
Rw, #data4
Shift left direct word GPR;
number of shift cycles specified by immediate data
2
SHR
Rw, Rw
Shift right direct word GPR;
number of shift cycles specified by direct GPR
2
User’s Manual
5-11
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Instruction Set
Instruction Set Summary (cont’d)
Mnemonic
Description
Bytes
Shift and Rotate Instructions (cont’d)
SHR
Rw, #data4
Shift right direct word GPR;
number of shift cycles specified by immediate data
2
ROL
Rw, Rw
Rotate left direct word GPR;
number of shift cycles specified by direct GPR
2
ROL
Rw, #data4
Rotate left direct word GPR;
number of shift cycles specified by immediate data
2
ROR
Rw, Rw
Rotate right direct word GPR;
number of shift cycles specified by direct GPR
2
ROR
Rw, #data4
Rotate right direct word GPR;
number of shift cycles specified by immediate data
2
ASHR
Rw, Rw
Arithmetic (sign bit) shift right direct word GPR;
number of shift cycles specified by direct GPR
2
ASHR
Rw, #data4
Arithmetic (sign bit) shift right direct word GPR;
number of shift cycles specified by immediate data
2
Data Movement
MOV
Rw, Rw
Move direct word GPR to direct GPR
2
MOV
Rw, #data4
Move immediate word data to direct GPR
2
MOV
reg, #data16
Move immediate word data to direct register
4
MOV
Rw, [Rw]
Move indirect word memory to direct GPR
2
MOV
Rw, [Rw +]
Move indirect word memory to direct GPR and
post-increment source pointer by 2
2
MOV
[Rw], Rw
Move direct word GPR to indirect memory
2
MOV
[-Rw], Rw
Pre-decrement destination pointer by 2 and move direct
word GPR to indirect memory
2
MOV
[Rw], [Rw]
Move indirect word memory to indirect memory
2
MOV
[Rw +], [Rw]
Move indirect word memory to indirect memory and
post-increment destination pointer by 2
2
MOV
[Rw], [Rw +]
Move indirect word memory to indirect memory and
post-increment source pointer by 2
2
MOV
Rw,
[Rw + #data16]
Move indirect word memory by base plus constant to
direct GPR
4
MOV
[Rw + #data16],
Rw
Move direct word GPR to indirect memory by base plus
constant
4
User’s Manual
5-12
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Instruction Set
Instruction Set Summary (cont’d)
Mnemonic
Description
Bytes
Data Movement (cont’d)
MOV
[Rw], mem
Move direct word memory to indirect memory
4
MOV
mem, [Rw]
Move indirect word memory to direct memory
4
MOV
reg, mem
Move direct word memory to direct register
4
MOV
mem, reg
Move direct word register to direct memory
4
MOVB
Rb, Rb
Move direct byte GPR to direct GPR
2
MOVB
Rb, #data4
Move immediate byte data to direct GPR
2
MOVB
reg, #data8
Move immediate byte data to direct register
4
MOVB
Rb, [Rw]
Move indirect byte memory to direct GPR
2
MOVB
Rb, [Rw +]
Move indirect byte memory to direct GPR and
post-increment source pointer by 1
2
MOVB
[Rw], Rb
Move direct byte GPR to indirect memory
2
MOVB
[-Rw], Rb
Pre-decrement destination pointer by 1 and move
direct byte GPR to indirect memory
2
MOVB
[Rw], [Rw]
Move indirect byte memory to indirect memory
2
MOVB
[Rw +], [Rw]
Move indirect byte memory to indirect memory and
post-increment destination pointer by 1
2
MOVB
[Rw], [Rw +]
Move indirect byte memory to indirect memory and
post-increment source pointer by 1
2
MOVB
Rb,
[Rw + #data16]
Move indirect byte memory by base plus constant to
direct GPR
4
MOVB
[Rw + #data16],
Rb
Move direct byte GPR to indirect memory by base plus
constant
4
MOVB
[Rw], mem
Move direct byte memory to indirect memory
4
MOVB
mem, [Rw]
Move indirect byte memory to direct memory
4
MOVB
reg, mem
Move direct byte memory to direct register
4
MOVB
mem, reg
Move direct byte register to direct memory
4
MOVBS
Rw, Rb
Move direct byte GPR with sign extension to direct
word GPR
2
MOVBS
reg, mem
Move direct byte memory with sign extension to direct
word register
4
MOVBS
mem, reg
Move direct byte register with sign extension to direct
word memory
4
User’s Manual
5-13
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Instruction Set
Instruction Set Summary (cont’d)
Mnemonic
Description
Bytes
Data Movement (cont’d)
MOVBZ
Rw, Rb
Move direct byte GPR with zero extension to direct
word GPR
2
MOVBZ
reg, mem
Move direct byte memory with zero extension to direct
word register
4
MOVBZ
mem, reg
Move direct byte register with zero extension to direct
word memory
4
Jump and Call Operations
JMPA
cc, caddr
Jump absolute if condition is met
4
JMPI
cc, [Rw]
Jump indirect if condition is met
2
JMPR
cc, rel
Jump relative if condition is met
2
JMPS
seg, caddr
Jump absolute to a code segment
4
JB
bitaddr, rel
Jump relative if direct bit is set
4
JBC
bitaddr, rel
Jump relative and clear bit if direct bit is set
4
JNB
bitaddr, rel
Jump relative if direct bit is not set
4
JNBS
bitaddr, rel
Jump relative and set bit if direct bit is not set
4
CALLA
cc, caddr
Call absolute subroutine if condition is met
4
CALLI
cc, [Rw]
Call indirect subroutine if condition is met
2
CALLR
rel
Call relative subroutine
2
CALLS
seg, caddr
Call absolute subroutine in any code segment
4
PCALL
reg, caddr
Push direct word register onto system stack and call
absolute subroutine
4
TRAP
#trap7
Call interrupt service routine via immediate trap number
2
System Stack Operations
POP
reg
Pop direct word register from system stack
2
PUSH
reg
Push direct word register onto system stack
2
SCXT
reg, #data16
Push direct word register onto system stack und update
register with immediate data
4
SCXT
reg, mem
Push direct word register onto system stack und update
register with direct memory
4
User’s Manual
5-14
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Instruction Set
Instruction Set Summary (cont’d)
Mnemonic
Description
Bytes
RET
Return from intra-segment subroutine
2
RETS
Return from inter-segment subroutine
2
Return from intra-segment subroutine and pop direct
word register from system stack
2
Return from interrupt service subroutine
2
SRST
Software Reset
4
IDLE
Enter Idle Mode
4
PWRDN
Enter Power Down Mode
(supposes NMI-pin being low)
4
SRVWDT
Service Watchdog Timer
4
DISWDT
Disable Watchdog Timer
4
EINIT
Signify End-of-Initialization on RSTOUT-pin
4
Return Operations
RETP
reg
RETI
System Control
ATOMIC
#irang2
Begin ATOMIC sequence
*)
2
EXTR
#irang2
Begin EXTended Register sequence
*)
2
EXTP
Rw, #irang2
Begin EXTended Page sequence
*)
2
4
EXTP
#pag10, #irang2
Begin EXTended Page sequence
*)
EXTPR
Rw, #irang2
Begin EXTended Page and Register sequence
*)
2
EXTPR
#pag10, #irang2
Begin EXTended Page and Register sequence
*)
4
EXTS
Rw, #irang2
Begin EXTended Segment sequence
*)
2
Begin EXTended Segment sequence
*)
4
2
4
EXTS
#seg8, #irang2
EXTSR
Rw, #irang2
Begin EXTended Segment and Register sequence
*)
EXTSR
#seg8, #irang2
Begin EXTended Segment and Register sequence
*)
Miscellaneous
NOP
User’s Manual
Null operation
2
5-15
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Instruction Set
5.3
Instruction Opcodes
The following pages list the instructions of the C166S ordered by their hexadecimal
opcodes. This helps to identify specific instructions when reading executable code, ie.
during the debugging phase.
Notes for Opcode Lists
1. These instructions are encoded by means of additional bits in the operand field of the
instruction
x0H – x7H:
Rw, #data3 or
Rb, #data3
x8H – xBH:
Rw, [Rw]
or
Rb, [Rw]
xCH – xFH:
Rw, [Rw +] or
Rb, [Rw +]
For these instructions only the lowest four GPRs, R0 to R3, can be used as indirect
address pointers.
2. These instructions are encoded by means of additional bits in the operand field of the
instruction
00xx.xxxxB:
EXTS
or
ATOMIC
EXTP
01xx.xxxxB:
10xx.xxxxB:
EXTSR
or
EXTR
11xx.xxxxB:
EXTPR
Notes on the JMPR Instructions
The condition code to be tested for the JMPR instructions is specified by the opcode.
Two mnemonic representation alternatives exist for some of the condition codes.
Notes on the BCLR and BSET Instructions
The position of the bit to be set or to be cleared is specified by the opcode. The operand
‘bitoff.n’ (n = 0 to 15) refers to a particular bit within a bit-addressable word.
Notes on the Undefined Opcodes
A hardware trap occurs when one of the undefined opcodes signified by ‘----’ is decoded
by the CPU.
User’s Manual
5-16
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Instruction Set
Hexcode
Mnemonic
Operands
00
01
02
03
04
Number of
Bytes
2
2
4
4
4
ADD
ADDB
ADD
ADDB
ADD
Rw, Rw
Rb, Rb
reg, mem
reg, mem
mem, reg
05
06
07
08
4
4
4
2
ADDB
ADD
ADDB
ADD
09
2
ADDB
0A
4
BFLDL
0B
0C
0D
2
2
2
MUL
ROL
JMPR
0E
0F
10
11
12
13
14
15
16
17
18
2
2
2
2
4
4
4
4
4
4
2
BCLR
BSET
ADDC
ADDCB
ADDC
ADDCB
ADDC
ADDCB
ADDC
ADDCB
ADDC
19
2
ADDCB
1A
4
BFLDH
1B
1C
1D
2
2
2
1E
1F
2
2
User’s Manual
Hex- Numcode ber of
Bytes
20
2
21
2
22
4
23
4
24
4
Mnemonic
Operands
SUB
SUBB
SUB
SUBB
SUB
Rw, Rw
Rb, Rb
reg, mem
reg, mem
mem, reg
mem, reg
reg, #data16
reg, #data8
Rw, [Rw +] or
Rw, [Rw] or
Rw, #data3
Rb, [Rw +] or
Rb, [Rw] or
Rb, #data3
bitoff, #mask8,
#data8
Rw, Rw
Rw, Rw
cc_UC, rel
25
26
27
28
4
4
4
2
SUBB
SUB
SUBB
SUB
29
2
SUBB
2A
4
BCMP
mem, reg
reg, #data16
reg, #data8
Rw, [Rw +] or
Rw, [Rw] or
Rw, #data3
Rb, [Rw +] or
Rb, [Rw] or
Rb, #data3
bitaddr, bitaddr
2B
2C
2D
2
2
2
PRIOR
ROR
JMPR
2E
2F
30
31
32
33
34
35
36
37
38
2
2
2
2
4
4
4
4
4
4
2
BCLR
BSET
SUBC
SUBCB
SUBC
SUBCB
SUBC
SUBCB
SUBC
SUBCB
SUBC
39
2
SUBCB
3A
4
BMOVN
MULU
ROL
JMPR
bitoff.0
bitoff.0
Rw, Rw
Rb, Rb
reg, mem
reg, mem
mem, reg
mem, reg
reg, #data16
reg, #data8
Rw, [Rw +] or
Rw, [Rw] or
Rw, #data3
Rb, [Rw +] or
Rb, [Rw] or
Rb, #data3
bitoff, #mask8,
#data8
Rw, Rw
Rw, #data4
cc_NET, rel
3B
3C
3D
2
2
ROR
JMPR
BCLR
BSET
bitoff.1
bitoff.1
3E
3F
2
2
BCLR
BSET
5-17
Rw, Rw
Rw, Rw
cc_EQ, rel or
cc_Z, rel
bitoff.2
bitoff.2
Rw, Rw
Rb, Rb
reg, mem
reg, mem
mem, reg
mem, reg
reg, #data16
reg, #data8
Rw, [Rw +] or
Rw, [Rw] or
Rw, #data3
Rb, [Rw +] or
Rb, [Rw] or
Rb, #data3
bitaddr, bitaddr
Rw, #data4
cc_NE, rel or
cc_NZ, rel
bitoff.3
bitoff.3
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Instruction Set
Hexcode
Mnemonic
Operands
40
41
42
43
44
Number of
Bytes
2
2
4
4
-
Hex- Numcode ber of
Bytes
60
2
61
2
62
4
63
4
64
4
Mnemonic
Operands
CMP
CMPB
CMP
CMPB
-
Rw, Rw
Rb, Rb
reg, mem
reg, mem
-
AND
ANDB
AND
ANDB
AND
Rw, Rw
Rb, Rb
reg, mem
reg, mem
mem, reg
45
46
47
48
4
4
2
CMP
CMPB
CMP
65
66
67
68
4
4
4
2
ANDB
AND
ANDB
AND
69
2
ANDB
BMOV
reg, #data16
reg, #data8
Rw, [Rw +] or
Rw, [Rw] or
Rw, #data3
Rb, [Rw +] or
Rb, [Rw] or
Rb, #data3
bitaddr, bitaddr
6A
4
BAND
mem, reg
reg, #data16
reg, #data8
Rw, [Rw +] or
Rw, [Rw] or
Rw, #data3
Rb, [Rw +] or
Rb, [Rw] or
Rb, #data3
bitaddr, bitaddr
49
2
CMPB
4A
4
4B
4C
4D
2
2
2
DIV
SHL
JMPR
Rw
Rw, Rw
cc_V, rel
6B
6C
6D
2
2
2
DIVL
SHR
JMPR
Rw
Rw, Rw
cc_N, rel
4E
4F
50
51
52
53
54
55
56
57
58
2
2
2
2
4
4
4
4
4
4
2
BCLR
BSET
XOR
XORB
XOR
XORB
XOR
XORB
XOR
XORB
XOR
6E
6F
70
71
72
73
74
75
76
77
78
2
2
2
2
4
4
4
4
4
4
2
BCLR
BSET
OR
ORB
OR
ORB
OR
ORB
OR
ORB
OR
59
2
XORB
79
2
ORB
5A
4
BOR
bitoff.4
bitoff.4
Rw, Rw
Rb, Rb
reg, mem
reg, mem
mem, reg
mem, reg
reg, #data16
reg, #data8
Rw, [Rw +] or
Rw, [Rw] or
Rw, #data3
Rb, [Rw +] or
Rb, [Rw] or
Rb, #data3
bitaddr, bitaddr
7A
4
BXOR
bitoff.6
bitoff.6
Rw, Rw
Rb, Rb
reg, mem
reg, mem
mem, reg
mem, reg
reg, #data16
reg, #data8
Rw, [Rw +] or
Rw, [Rw] or
Rw, #data3 1)
Rb, [Rw +] or
Rb, [Rw] or
Rb, #data3
bitaddr, bitaddr
5B
5C
5D
2
2
2
DIVU
SHL
JMPR
Rw
Rw, #data4
cc_NV, rel
7B
7C
7D
2
2
2
DIVLU
SHR
JMPR
Rw
Rw, #data4
cc_NN, rel
5E
5F
2
2
BCLR
BSET
bitoff.5
bitoff.5
7E
7F
2
2
BCLR
BSET
bitoff.7
bitoff.7
User’s Manual
5-18
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Instruction Set
Hexcode
Mnemonic
Operands
80
81
82
83
84
Number of
Bytes
2
2
4
4
4
Hex- Numcode ber of
Bytes
A0
2
A1
2
A2
4
A3
4
A4
4
Mnemonic
Operands
CMPI1
NEG
CMPI1
CoXXX
MOV
Rw, #data4
Rw
Rw, mem
xx
[Rw], mem
CMPD1
NEGB
CMPD1
CoXXX
MOVB
Rw, #data4
Rb
Rw, mem
xx
[Rw], mem
85
86
87
88
4
4
2
CMPI1
IDLE
MOV
Rw, #data16
[-Rw], Rw
A5
A6
A7
A8
4
4
4
2
DISWDT
CMPD1
SRVWDT
MOV
89
2
MOVB
[-Rw], Rb
A9
2
MOVB
Rb, [Rw]
8A
4
JB
bitaddr, rel
AA
4
JBC
bitaddr, rel
8B
8C
8D
2
JMPR
AB
AC
AD
2
2
2
CALLI
ASHR
JMPR
cc, [Rw]
Rw, Rw
cc_SGT, rel
8E
8F
90
91
2
2
2
2
BCLR
BSET
CMPI2
CPL
cc_C, rel or
cc_ULT, rel
bitoff.8
bitoff.8
Rw, #data4
Rw
AE
AF
B0
B1
2
2
2
2
BCLR
BSET
CMPD2
CPLB
bitoff.10
bitoff.10
Rw, #data4
Rb
92
93
94
4
4
4
CMPI2
MOV
Rw, mem
mem, [Rw]
B2
B3
B4
4
4
4
CMPD2
MOVB
Rw, mem
mem, [Rw]
95
96
97
4
4
CMPI2
PWRDN
Rw, #data16
B5
B6
B7
4
4
4
EINIT
CMPD2
SRST
Rw, #data16
98
99
9A
2
2
4
MOV
MOVB
JNB
Rw, [Rw+]
Rb, [Rw+]
bitaddr, rel
B8
B9
BA
2
2
4
MOV
MOVB
JNBS
[Rw], Rw
[Rw], Rb
bitaddr, rel
9B
9C
2
2
TRAP
JMPI
#trap7
cc, [Rw]
BB
BC
2
2
CALLR
ASHR
rel
Rw, #data4
9D
2
JMPR
BD
2
JMPR
cc_SLE, rel
9E
9F
2
2
BCLR
BSET
cc_NC, rel or
cc_UGE, rel
bitoff.9
bitoff.9
BE
BF
2
2
BCLR
BSET
bitoff.11
bitoff.11
User’s Manual
5-19
Rw, #data16
Rw, [Rw]
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Instruction Set
Hexcode
Mnemonic
Operands
C0
C1
C2
C3
C4
Number of
Bytes
2
4
4
4
Hex- Numcode ber of
Bytes
E0
2
E1
2
E2
4
E3
E4
4
Mnemonic
Operands
MOVBZ
MOVBZ
MOV
C5
C6
C7
C8
4
4
2
MOVBZ
SCXT
MOV
Rw, Rb
reg, mem
[Rw+#data16],
Rw
mem, reg
reg, #data16
[Rw], [Rw]
MOV
MOVB
PCALL
MOVB
E5
E6
E7
E8
4
4
2
MOV
MOVB
MOV
Rw, #data4
Rb, #data4
reg, caddr
[Rw+#data16],
Rb
reg, #data16
reg, #data8
[Rw], [Rw+]
C9
2
MOVB
[Rw], [Rw]
E9
2
MOVB
[Rw], [Rw+]
CA
4
CALLA
cc, addr
EA
4
JMPA
cc, caddr
CB
CC
CD
2
2
2
RET
NOP
JMPR
cc_SLT, rel
EB
EC
ED
2
2
2
RETP
PUSH
JMPR
reg
reg
cc_UGT, rel
CE
CF
D0
D1
2
2
2
2
D2
D3
D4
4
4
4
BCLR
BSET
MOVBS
ATOMIC or
EXTR
MOVBS
MOV
bitoff.12
bitoff.12
Rw, Rb
#irang2
EE
EF
F0
F1
2
2
2
2
BCLR
BSET
MOV
MOVB
bitoff.14
bitoff.14
Rw, Rw
Rb, Rb
F2
F3
F4
4
4
4
MOV
MOVB
MOVB
MOVBS
SCXT
EXTP(R),
EXTS(R)
reg, mem
Rw,
[Rw + #data16]
mem, reg
reg, mem
#pag10,#irang2
#seg8, #irang2
F5
F6
F7
4
4
MOV
MOVB
reg, mem
reg, mem
Rb,
[Rw + #data16]
mem, reg
mem, reg
D5
D6
D7
4
4
4
D8
D9
DA
2
2
4
MOV
MOVB
CALLS
[Rw+], [Rw]
[Rw+], [Rw]
seg, caddr
F8
F9
FA
4
JMPS
seg, caddr
DB
DC
2
2
Rw, #irang2
FB
FC
2
2
RETI
POP
reg
DD
2
RETS
EXTP(R),
EXTS(R)
JMPR
cc_SGE, rel
FD
2
JMPR
cc_ULE, rel
DE
DF
2
2
BCLR
BSET
bitoff.13
bitoff.13
FE
FF
2
2
BCLR
BSET
bitoff.15
bitoff.15
User’s Manual
5-20
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Instruction Set
5.4
Instruction Description
This chapter describes each instruction in details. The instructions are listed
alphabetically, and the description contains the following elements.
• Instruction Name: Specifies the mnemonic opcode of the instruction in oversized
bold lettering for easy reference. The mnemonics have been chosen with regard to the
particular operation performed by the instruction.
• Syntax: Specifies the mnemonic opcode and the required formal operands of the
instruction as used in the following subsection 'Operation'. There are instructions with
either none, one, two or three operands, which must be separated from each other by
commas:
MNEMONIC
{op1 {,op2 {,op3 } } }
The syntax for the actual operands of an instruction depends on the selected addressing
mode. All of the available addressing modes are summarized at the end of each single
instruction description. In contrast to the syntax for the instructions described in the
following, the assembler provides much more flexibility in writing C166S programs (e.g.
by generic instructions and by automatically selecting appropriate addressing modes
whenever possible), and thus it eases the use of the instruction set. For more information
about this item please refer to the Assembler manual.
• Operation: This part presents a logical description of the operation performed by an
instruction as a symbolic formula or a high level language construct.
The following symbols are used to represent data movement, arithmetic or logical
operators.
Diadic operations: (opX)
operator (opY)
←
(opY)
is
MOVED into (opX)
+
(opX)
is
ADDED to (opY)
-
(opY)
is
SUBTRACTED from (opX)
*
(opX)
is
MULTIPLIED by (opY)
/
(opX)
is
DIVIDED by (opY)
∧
(opX)
is
logically ANDed with (opY)
∨
(opX)
is
logically ORed with (opY)
⊕
(opX)
is
logically EXCLUSIVELY ORed with (opY)
⇔
(opX)
is
COMPARED against (opY)
mod
(opX)
is
divided MODULO (opY)
User’s Manual
5-21
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Instruction Set
Monadic operations:
¬
(opX)
operator (opX)
is
logically COMPLEMENTED
Parentheses indicate a method of the used operand addressing as follows:
opX
Specifies the immediate constant value of opX
(opX)
Specifies the contents of opX
(opX[n])
Specifies the contents of bit n of opX
((opX))
Specifies the contents of the contents of opX
(ie. opX is used as pointer to the actual operand)
The following operands notation will also be used in the operational description:
CP
Context Pointer
CSP
Code Segment Pointer
IP
Instruction Pointer
MD
Multiply/Divide register
(32 bits wide, consists of MDH and MDL)
MDL, MDH
Multiply/Divide Low and High registers
(each 16 bit wide)
PSW
Program Status Word
SP
System Stack Pointer
SYSCON
SYSCON Configuration register
C
Carry condition flag in the PSW register
V
Overflow condition flag in the PSW register
SGTDIS
Segmentation Disable bit in the SYSCON register
count
Temporary variable for an intermediate storage of
the number of shift or rotate cycles which remain
to complete the shift or rotate operation
tmp
Temporary variable for an intermediate result
0, 1, 2,...
Constant values due to the data format
of the specified operation
Data Types: This part specifies the particular data type according to the instruction.
Basically, the following data types are possible:
BIT, BYTE, WORD
User’s Manual
5-22
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Instruction Set
Only instructions which extend byte data to word change data type. Note that the data
types mentioned in this subsection do not cover accesses to indirect address pointers or
to the system stack. These accesses are always performed with word data. Moreover,
no data type is specified for System Control Instructions and for those of the branch
instructions which do not access any explicitly addressed data.
• Description: This part provides a brief description of the action that is executed by
the respective instruction.
• Condition Code: The Condition code indicates that respective instruction is
executed, if the specified condition exists, and is skipped, if it does not. The table
below summarizes the 16 possible condition codes that can be used within Call and
Branch instructions. The table shows the abbreviations, the test that is executed for a
specific condition and a 4-bit number associated with condition code.
Condition
Code
Mnemonic cc
Test
Description
Condition Code
Number c
cc_UC
1=1
Unconditional
0H
cc_Z
Z=1
Zero
2H
cc_NZ
Z=0
Not zero
3H
cc_V
V=1
Overflow
4H
cc_NV
V=0
No overflow
5H
cc_N
N=1
Negative
6H
cc_NN
N=0
Not negative
7H
cc_C
C=1
Carry
8H
cc_NC
C=0
No carry
9H
cc_EQ
Z=1
Equal
2H
cc_NE
Z=0
Not equal
3H
cc_ULT
C=1
Unsigned less than
8H
cc_ULE
(Z∨C) = 1
Unsigned less than or equal
FH
cc_UGE
C=0
Unsigned greater than or equal
9H
cc_UGT
(Z∨C) = 0
Unsigned greater than
EH
cc_SLT
(N⊕V) = 1
Signed less than
CH
cc_SLE
(Z∨(N⊕V)) = 1 Signed less than or equal
BH
cc_SGE
(N⊕V) = 0
DH
User’s Manual
Signed greater than or equal
5-23
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Instruction Set
Condition
Code
Mnemonic cc
Test
Description
cc_SGT
(Z∨(N⊕V)) = 0 Signed greater than
AH
cc_NET
(Z∨E) = 0
1H
Not equal AND not end of table
Condition Code
Number c
• Condition Flags: This part reflects the state of the N, C, V, Z and E flags in the PSW
register which is the state after execution of the corresponding instruction, except if
the PSW register itself was specified as the destination operand of that instruction
(see Note).
The resulting state of the flags is represented by symbols as follows:
'*'
The flag is set due to the following standard rules for the corresponding flag:
N=1:
MSB of the result is set
N=0:
MSB of the result is not set
C=1:
Carry occurred during operation
C=0:
No Carry occurred during operation
V=1:
Arithmetic Overflow occurred during operation
V=0:
No Arithmetic Overflow occurred during operation
Z=1:
Result equals zero
Z=0:
Result does not equal zero
E=1:
Source operand represents the lowest negative number
(either 8000h for word data or 80h for byte data)
E=0:
Source operand does not represent the lowest negative
number for the specified data type
'S'
The flag is set due to rules which deviate from the described standard.
For more details see instruction pages (below) or the ALU status flags
description.
'-'
The flag is not affected by the operation.
'0'
The flag is cleared by the operation.
'NOR'
The flag contains the logical NORing of the two specified bit operands.
'AND'
The flag contains the logical ANDing of the two specified bit operands.
'OR'
The flag contains the logical ORing of the two specified bit operands.
'XOR'
The flag contains the logical XORing of the two specified bit operands.
User’s Manual
5-24
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Instruction Set
’B’
The flag contains the original value of the specified bit operand.
’B’
The flag contains the complemented value of the specified bit operand.
Note: If the PSW register was specified as the destination operand of an instruction, the
condition flags can not be interpreted as just described, because the PSW register
is modified depending on the data format of the instruction as follows:
For word operations, the PSW register is overwritten with the word result. For byte
operations, the non-addressed byte is cleared and the addressed byte is
overwritten. For bit or bit-field operations on the PSW register, only the specified
bits are modified. Supposed that the condition flags were not selected as
destination bits, they stay unchanged. This means that they keep the state after
execution of the previous instruction.
In any case, if the PSW was the destination operand of an instruction, the PSW
flags do NOT represent the condition flags of this instruction as usual.
• Addressing Modes: This part specifies which combinations of different addressing
modes are available for the required operands. The selected addressing mode
combination is mostly specified by the opcode of the corresponding instruction.
However, there are some arithmetic and logical instructions where the addressing
mode combination is not specified by the (identical) opcodes but by particular bits
within the operand field.
The addressing mode entries are made up of three elements:
Mnemonic Shows accepted operands for the respective instruction.
Format This part specifies the format of the instructions as it is represented in the
assembler listing. The Figure 5-1 shows the relation between the instruction format
representation of the assembler and the corresponding internal organization of such an
instruction format (N = nibble = 4 bits).
The following symbols are used to describe the instruction formats:
00H through FFH: Instruction Opcodes
0, 1
: Constant Values
:....
: Each of the 4 characters immediately following a colon represents a single bit
:..ii
: 2-bit short GPR address (Rwi)
SS
: Code segment number
:..##
: 2-bit immediate constant (#irang2)
:.###
: 3-bit immediate constant (#data3)
User’s Manual
5-25
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Instruction Set
...#:#
: 5-bit immediate constant (#data5)
c
: 4-bit condition code specification (cc)
n
: 4-bit short GPR address (Rwn or Rbn)
m
: 4-bit short GPR address (Rwm or Rbm)
q
: 4-bit position of the source bit within the word specified by QQ
z
: 4-bit position of the destination bit within the word specified by ZZ
#
: 4-bit immediate constant (#data4)
t:ttt0
: 7-bit trap number (#trap7)
QQ
: 8-bit word address of the source bit (bitoff)
rr
: 8-bit relative target address word offset (rel)
RR
: 8-bit word address reg
ZZ
: 8-bit word address of the destination bit (bitoff)
##
: 8-bit immediate constant (#data8)
## xx
: 8-bit immediate constant (represented by #data16, byte xx is not significant)
@@
: 8-bit immediate constant (#mask8)
MMMM : 16-bit address (mem or caddr; low byte, high byte)
## ##
: 16-bit immediate constant (#data16; low byte, high byte)
Number of Bytes All C166S instructions are either 2 or 4 bytes. According to the
instruction size, all instructions can be classified as either single word or double word
instructions.
User’s Manual
5-26
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Instruction Set
Representation in the
Assembler Listing:
N2N1
N4N3
N6N5
N8N7
High Byte 2nd word
Low Byte 2nd word
High Byte 1st word
Low Byte 1st word
Internal Organization:
MSB
N8
Figure 5-1
Bits in ascending order LSB
N7
N6
N5
N4
N3
N2
N1
Instruction Format Representation
The following pages of this section contain a detailed description of each instruction in
alphabetical order.
User’s Manual
5-27
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Instruction Set
User’s Manual
5-28
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
6
Detailed Instruction Set
The following pages of this section contain a detailed description of each instruction in
alphabetical order.
User’s Manual
6-1
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
ADD
ADD
Integer Addition
Group
Arithmetic Instructions
Syntax
ADD op1, op2
Source Operand(s)
op1, op2 → WORD
Destination Operand(s)
op1 → WORD
Operation
(op1) ← (op1) + (op2)
Description
Performs a 2’s complement binary addition of the source operand specified by op2 and
the destination operand specified by op1. The result is then stored in op1.
CPU Flags
E
*
E
Z
V
C
N
Z
*
V
*
C
*
N
*
Set if the value of op2 represents the lowest possible negative number.
Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Set if an arithmetic overflow occurred, i.e. the result cannot be
represented in the word data type. Cleared otherwise.
Set if a carry is generated from the most significant bit of the word data
type. Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
Encoding
Mnemonic
ADD
ADD
ADD
ADD
ADD
ADD
ADD
User’s Manual
Rwn , #data3
Rwn , Rwm
Rwn , [Rwi+]
Rwn , [Rwi]
mem , reg
reg , #data16
reg , mem
Format
08 n:0###
00 nm
08 n:11ii
08 n:10ii
04 RR MM MM
06 RR ## ##
02 RR MM MM
6-2
Bytes
2
2
2
2
4
4
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
ADDB
ADDB
Integer Addition
Group
Arithmetic Instructions
Syntax
ADDB op1, op2
Source Operand(s)
op1, op2 → BYTE
Destination Operand(s)
op1 → BYTE
Operation
(op1) ← (op1) + (op2)
Description
Performs a 2’s complement binary addition of the source operand specified by op2 and
the destination operand specified by op1. The result is then stored in op1.
CPU Flags
E
*
E
Z
V
C
N
Z
*
V
*
C
*
N
*
Set if the value of op2 represents the lowest possible negative number.
Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Set if an arithmetic overflow occurred, i.e. the result cannot be
represented in the byte data type. Cleared otherwise.
Set if a carry is generated from the most significant bit of the byte data
type. Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
Encoding
Mnemonic
ADDB
ADDB
ADDB
ADDB
ADDB
ADDB
ADDB
User’s Manual
Rbn , #data3
Rbn , Rbm
Rbn , [Rwi+]
Rbn , [Rwi]
mem , reg
reg , #data8
reg , mem
Format
09 n:0###
01 nm
09 n:11ii
09 n:10ii
05 RR MM MM
07 RR ## xx
03 RR MM MM
6-3
Bytes
2
2
2
2
4
4
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
ADDC
ADDC
Integer Addition with Carry
Group
Arithmetic Instructions
Syntax
ADDC op1, op2
Source Operand(s)
op1, op2 → WORD
Destination Operand(s)
op1 → WORD
Operation
(op1) ← (op1) + (op2) + (C)
Description
Performs a 2’s complement binary addition of the source operand specified by op2, the
destination operand specified by op1 and the previously generated carry bit. The sum is
then stored in op1. This instruction can be used to perform multiple precision arithmetic.
CPU Flags
E
*
E
Z
V
C
N
Z
S
V
*
C
*
N
*
Set if the value of op2 represents the lowest possible negative number.
Cleared otherwise. Used to signal the end of a table.
Set if result equals zero and previous Z flag was set. Cleared otherwise.
Set if an arithmetic overflow occurred, i.e. the result cannot be
represented in the word data type. Cleared otherwise.
Set if a carry is generated from the most significant bit of the word data
type. Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
Encoding
Mnemonic
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
User’s Manual
Rwn , #data3
Rwn , Rwm
Rwn , [Rwi+]
Rwn , [Rwi]
mem , reg
reg , #data16
reg , mem
Format
18 n:0###
10 nm
18 n:11ii
18 n:10ii
14 RR MM MM
16 RR ## ##
12 RR MM MM
6-4
Bytes
2
2
2
2
4
4
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
ADDCB
ADDCB
Integer Addition with Carry
Group
Arithmetic Instructions
Syntax
ADDCB op1, op2
Source Operand(s)
op1, op2 → BYTE
Destination Operand(s)
op1 → BYTE
Operation
(op1) ← (op1) + (op2) + (C)
Description
Performs a 2’s complement binary addition of the source operand specified by op2, the
destination operand specified by op1 and the previously generated carry bit. The sum is
then stored in op1. This instruction can be used to perform multiple precision arithmetic.
CPU Flags
E
*
E
Z
V
C
N
Z
S
V
*
C
*
N
*
Set if the value of op2 represents the lowest possible negative number.
Cleared otherwise. Used to signal the end of a table.
Set if result equals zero and previous Z flag was set. Cleared otherwise.
Set if an arithmetic overflow occurred, i.e. the result cannot be
represented in the byte data type. Cleared otherwise.
Set if a carry is generated from the most significant bit of the byte data
type. Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
Encoding
Mnemonic
ADDCB
ADDCB
ADDCB
ADDCB
ADDCB
ADDCB
ADDCB
User’s Manual
Rbn , #data3
Rbn , Rbm
Rbn , [Rwi+]
Rbn , [Rwi]
mem , reg
reg , #data8
reg , mem
Format
19 n:0###
11 nm
19 n:11ii
19 n:10ii
15 RR MM MM
17 RR ## xx
13 RR MM MM
6-5
Bytes
2
2
2
2
4
4
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
AND
AND
Logical AND
Group
Logical Instructions
Syntax
AND op1, op2
Source Operand(s)
op1, op2 → WORD
Destination Operand(s)
op1 → WORD
Operation
(op1) ← (op1) ∧ (op2)
Description
Performs a bitwise logical AND of the source operand specified by op2 and the
destination operand specified by op1. The result is then stored in op1.
CPU Flags
E
*
E
Z
V
C
N
Z
*
V
0
C
0
N
*
Set if the value of op2 represents the lowest possible negative number.
Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Always cleared.
Always cleared.
Set if the most significant bit of the result is set. Cleared otherwise.
Encoding
Mnemonic
AND
AND
AND
AND
AND
AND
AND
User’s Manual
Rwn , #data3
Rwn , Rwm
Rwn , [Rwi+]
Rwn , [Rwi]
mem , reg
reg , #data16
reg , mem
Format
68 n:0###
60 nm
68 n:11ii
68 n:10ii
64 RR MM MM
66 RR ## ##
62 RR MM MM
6-6
Bytes
2
2
2
2
4
4
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
ANDB
ANDB
Logical AND
Group
Logical Instructions
Syntax
ANDB op1, op2
Source Operand(s)
op1, op2 → BYTE
Destination Operand(s)
op1 → BYTE
Operation
(op1) ← (op1) ∧ (op2)
Description
Performs a bitwise logical AND of the source operand specified by op2 and the
destination operand specified by op1. The result is then stored in op1.
CPU Flags
E
*
E
Z
V
C
N
Z
*
V
0
C
0
N
*
Set if the value of op2 represents the lowest possible negative number.
Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Always cleared.
Always cleared.
Set if the most significant bit of the result is set. Cleared otherwise.
Encoding
Mnemonic
ANDB
ANDB
ANDB
ANDB
ANDB
ANDB
ANDB
User’s Manual
Rbn , #data3
Rbn , Rbm
Rbn , [Rwi+]
Rbn , [Rwi]
mem , reg
reg , #data8
reg , mem
Format
69 n:0###
61 nm
69 n:11ii
69 n:10ii
65 RR MM MM
67 RR ## xx
63 RR MM MM
6-7
Bytes
2
2
2
2
4
4
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
ASHR
ASHR
Arithmetic Shift Right
Group
Shift and Rotate Instructions
Syntax
ASHR op1, op2
Source Operand(s)
op1 → WORD
op2 → shift counter
Destination Operand(s)
op1 → WORD
Operation
(count) ← (op2)
(V) ← 0
(C) ← 0
DO WHILE ((count) ≠ 0)
(V) ← (C) ∨ (V)
(C) ← (op1[0])
(op1[n]) ← (op1[n+1]) [n=0...14]
(count) ← (count) - 1
END WHILE
Description
Arithmetically shifts the destination word operand op1 right by the number of times as
specified by the source operand op2. To preserve the sign of the original operand op1,
the most significant bits of the result are filled with zeros if the original most significant
bit was a 0 or with ones if the original most significant bit was a 1. The Overflow flag is
used as a Rounding flag. The least significant bit is shifted into the Carry. Only shift
values between 0 and 15 are allowed. When using a GPR as the count control, only the
least significant 4 bits are used.
CPU Flags
E
0
E
Z
V
C
N
User’s Manual
Z
*
V
*
C
*
N
*
Always cleared.
Set if result equals zero. Cleared otherwise.
Set if in any cycle of the shift operation a 1 is shifted out of the carry flag.
Cleared in case of a shift count equal 0.
The carry flag is set according to the last least significant bit shifted out of
op1. Cleared for a shift count of zero.
Set if the most significant bit of the result is set. Cleared otherwise.
6-8
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
Encoding
Mnemonic
ASHR
ASHR
User’s Manual
Rwn , #data4
Rwn , Rwm
Format
BC #n
AC nm
6-9
Bytes
2
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
ATOMIC
ATOMIC
Begin ATOMIC Sequence
Group
System Control Instructions
Syntax
ATOMIC op1
Source Operand(s)
op1 → 2-bit instruction counter
Destination Operand(s)
none
Operation
(count) ← (op1) [1 ≤ op1 ≤ 4]
Disable interrupts and Class A traps
DO WHILE ((count) ≠ 0 AND Class_B_Trap_Condition ≠ TRUE)
Next Instruction
(count) ← (count) - 1
END WHILE
(count) ← 0
Enable interrupts and traps
Description
Causes standard and PEC interrupts and class A hardware traps to be disabled for a
specified number of instructions. The ATOMIC instruction becomes immediately active.
No NOPs are required for normal ATOMIC execution. Depending on the value of op1,
the period of validity of the ATOMIC sequence extends over the sequence of the next 1
to 4 instructions being executed after the ATOMIC instruction. All instructions requiring
multiple cycles or hold states to be executed are regarded as one instruction in this
sense. Any instruction type can be used with the ATOMIC instruction.
CPU Flags
E
E
Z
V
C
N
Z
-
V
-
C
-
N
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Encoding
Mnemonic
ATOMIC
User’s Manual
#irang2
Format
D1 :00##-0
6-10
Bytes
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
BAND
BAND
Bit Logical AND
Group
Boolean Bit Manipulation Instructions
Syntax
BAND op1, op2
Source Operand(s)
op1, op2 → BIT
Destination Operand(s)
op1 → BIT
Operation
(op1) ← (op1) ∧ (op2)
Description
Performs a single bit logical AND of the source bit specified by op2 and the destination
bit specified by op1. The result is then stored in op1.
CPU Flags
E
0
E
Z
V
C
N
Z
NOR
V
OR
C
AND
N
XOR
Always cleared.
Contains the logical NOR of the two specified bits.
Contains the logical OR of the two specified bits.
Contains the logical AND of the two specified bits.
Contains the logical XOR of the two specified bits.
Encoding
Mnemonic
BAND
User’s Manual
bitaddrZ.z , bitaddrQ.q
Format
6A QQ ZZ qz
6-11
Bytes
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
BCLR
BCLR
Bit Clear
Group
Boolean Bit Manipulation Instructions
Syntax
BCLR op1
Source Operand(s)
none
Destination Operand(s)
op1 → BIT
Operation
(op1) ← 0
Description
Clears the bit specified by op1. This instruction is primarily used for peripheral and
system control.
CPU Flags
E
0
E
Z
V
C
N
Z
B
V
0
C
0
N
B
Always cleared.
Contains the logical negation of the previous state of the specified bit.
Always cleared.
Always cleared.
Contains the previous state of the specified bit.
Encoding
Mnemonic
BCLR
User’s Manual
bitaddrQ.q
Format
qE QQ
6-12
Bytes
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
BCMP
BCMP
Bit to Bit Compare
Group
Boolean Bit Manipulation Instructions
Syntax
BCMP op1, op2
Source Operand(s)
op1, op2 → BIT
Destination Operand(s)
none
Operation
(op1) ⇔ (op2)
Description
Performs a single bit comparison of the source bit specified by op1 and the source bit
specified by op2. No result is written by this instruction. Only the flags are updated.
CPU Flags
E
0
E
Z
V
C
N
Z
NOR
V
OR
C
AND
N
XOR
Always cleared.
Contains the logical NOR of the two specified bits.
Contains the logical OR of the two specified bits.
Contains the logical AND of the two specified bits.
Contains the logical XOR of the two specified bits.
Encoding
Mnemonic
BCMP
User’s Manual
bitaddrZ.z , bitaddrQ.q
Format
2A QQ ZZ qz
6-13
Bytes
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
BFLDH
BFLDH
Bit Field High Byte
Group
Boolean Bit Manipulation Instructions
Syntax
BFLDH op1, op2, op3
Source Operand(s)
op1 → WORD
op2, op3 → BYTE
Destination Operand(s)
op1 → WORD
Operation
(count) ← 0
DO WHILE ((count) <8)
IF (op2[(count)] = 1)
(op1[(count) + 8]) ← op3[(count)]
ENDIF
(count) ← (count) + 1
END WHILE
Description
Replaces those bits in the high byte of the destination word operand op1 which are
selected by an ’1’ in the mask specified by op2 with the bits at the corresponding
positions in “op3”.
CPU Flags
E
0
E
Z
V
C
N
Z
*
V
0
C
0
N
*
Always cleared.
Set if result equals zero. Cleared otherwise.
Always cleared.
Always cleared.
Set if the most significant bit of the result is set. Cleared otherwise.
Encoding
Mnemonic
BFLDH
User’s Manual
bitoffQ , #mask8 , #data8
Format
1A QQ ## @@
6-14
Bytes
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
BFLDL
BFLDL
Bit Field Low Byte
Group
Boolean Bit Manipulation Instructions
Syntax
BFLDL op1, op2, op3
Source Operand(s)
op1 → WORD
op2, op3 → BYTE
Destination Operand(s)
op1 → WORD
Operation
(count) ← 0
DO WHILE ((count) <8)
IF op2[(count)] = 1
(op1[(count)]) ← op3[(count)]
ENDIF
(count) ← (count) + 1
END WHILE
Description
Replaces those bits in the low byte of the destination word operand op1 which are
selected by an ’1’ in the mask specified by op2 with the bits at the corresponding
positions in “op3”.
CPU Flags
E
0
E
Z
V
C
N
Z
*
V
0
C
0
N
*
Always cleared.
Set if result equals zero. Cleared otherwise.
Always cleared.
Always cleared.
Set if the most significant bit of the result is set. Cleared otherwise.
Encoding
Mnemonic
BFLDL
User’s Manual
bitoffQ , #mask8 , #data8
Format
0A QQ @@ ##
6-15
Bytes
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
BMOV
BMOV
Bit to Bit Move
Group
Boolean Bit Manipulation Instructions
Syntax
BMOV op1, op2
Source Operand(s)
op2 → BIT
Destination Operand(s)
op1 → BIT
Operation
(op1) ← (op2)
Description
Moves a single bit from the source operand specified by op2 into the destination
operand specified by op1. The source bit is examined and the flags are updated
accordingly.
CPU Flags
E
0
E
Z
V
C
N
Z
B
V
0
C
0
N
B
Always cleared.
Contains the logical negation of the source bit.
Always cleared.
Always cleared.
Contains the state of the source bit.
Encoding
Mnemonic
BMOV
User’s Manual
bitaddrZ.z , bitaddrQ.q
Format
4A QQ ZZ qz
6-16
Bytes
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
BMOVN
BMOVN
Bit to Bit Move and Negate
Group
Boolean Bit Manipulation Instructions
Syntax
BMOVN op1, op2
Source Operand(s)
op2 → BIT
Destination Operand(s)
op1 → BIT
Operation
(op1) ← ¬(op2)
Description
Moves the complement of a single bit from the source operand specified by op2 into the
destination operand specified by op1. The source bit is examined and the flags are
updated accordingly.
CPU Flags
E
0
E
Z
V
C
N
Z
B
V
0
C
0
N
B
Always cleared.
Contains the logical negation of the source bit.
Always cleared.
Always cleared.
Contains the state of the source bit.
Encoding
Mnemonic
BMOVN
User’s Manual
bitaddrZ.z , bitaddrQ.q
Format
3A QQ ZZ qz
6-17
Bytes
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
BOR
BOR
Bit Logical OR
Group
Boolean Bit Manipulation Instructions
Syntax
BOR op1, op2
Source Operand(s)
op1, op2 → BIT
Destination Operand(s)
op1 → BIT
Operation
(op1) ← (op1) ∨ (op2)
Description
Performs a single bit logical OR of the source bit specified by op2 and the destination
bit specified by op1. The result is then stored in op1.
CPU Flags
E
0
E
Z
V
C
N
Z
NOR
V
OR
C
AND
N
XOR
Always cleared.
Contains the logical NOR of the two specified bits.
Contains the logical OR of the two specified bits.
Contains the logical AND of the two specified bits.
Contains the logical XOR of the two specified bits.
Encoding
Mnemonic
BOR
User’s Manual
bitaddrZ.z , bitaddrQ.q
Format
5A QQ ZZ qz
6-18
Bytes
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
BSET
BSET
Bit Set
Group
Boolean Bit Manipulation Instructions
Syntax
BSET op1
Source Operand(s)
none
Destination Operand(s)
op1 → BIT
Operation
(op1) ← 1
Description
Sets the bit specified by op1.
CPU Flags
E
0
E
Z
V
C
N
Z
B
V
0
C
0
N
B
Always cleared.
Contains the logical negation of the previous state of the specified bit.
Always cleared.
Always cleared.
Contains the previous state of the specified bit.
Encoding
Mnemonic
BSET
User’s Manual
bitaddrQ.q
Format
qF QQ
6-19
Bytes
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
BXOR
BXOR
Bit Logical XOR
Group
Boolean Bit Manipulation Instructions
Syntax
BXOR op1, op2
Source Operand(s)
op1, op2 → BIT
Destination Operand(s)
op1 → BIT
Operation
(op1) ← (op1) ⊕ (op2)
Description
Performs a single bit logical EXCLUSIVE OR of the source bit specified by op2 and the
destination bit specified by op1. The result is then stored in op1.
CPU Flags
E
0
E
Z
V
C
N
Z
NOR
V
OR
C
AND
N
XOR
Always cleared.
Contains the logical NOR of the two specified bits.
Contains the logical OR of the two specified bits.
Contains the logical AND of the two specified bits.
Contains the logical XOR of the two specified bits.
Encoding
Mnemonic
BXOR
User’s Manual
bitaddrZ.z , bitaddrQ.q
Format
7A QQ ZZ qz
6-20
Bytes
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
CALLA
CALLA
Call Subroutine Absolute
Group
Call Instructions
Syntax
CALLA op1, op2
Source Operand(s)
op1 → extended condition code
op2 → 16-bit address offset
Destination Operand(s)
none
Operation
IF (op1) THEN
(SP) ← (SP) - 2
((SP)) ← (IP)
(IP) ← op2
ELSE
next instruction
END IF
Description
If the condition specified by op1 is met, a branch to the absolute memory location
specified by the second operand op2 is taken. The value of the instruction pointer IP is
placed into the system stack. Because the IP always points to the instruction following
the branch instruction, the value stored in the system stack represents the return
address of the calling routine. If the condition is not met, no action is taken and the next
instruction is executed normally.
CPU Flags
E
E
Z
V
C
N
Z
-
V
-
C
-
N
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Encoding
Mnemonic
CALLA
User’s Manual
xcc , caddr
Format
CA d00a MM MM
6-21
Bytes
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
CALLI
CALLI
Call Subroutine Indirect
Group
Call Instructions
Syntax
CALLI op1, op2
Source Operand(s)
op1 → condition code
op2 → 16-bit address offset
Destination Operand(s)
none
Operation
IF (op1) THEN
(SP) ← (SP) - 2
((SP)) ← (IP)
(IP) ← op2
ELSE
next instruction
END IF
Description
If the condition specified by op1 is met, a branch to the location specified indirectly by
the second operand op2 is taken. The value of the instruction pointer IP is placed onto
the system stack. Because the IP always points to the instruction following the branch
instruction, the value stored in the system stack represents the return address of the
calling routine. If the condition is not met, no action is taken and the next instruction is
executed normally.
CPU Flags
E
E
Z
V
C
N
Z
-
V
-
C
-
N
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Encoding
Mnemonic
CALLI
User’s Manual
cc , [Rwn]
Format
AB cn
6-22
Bytes
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
CALLR
CALLR
Call Subroutine Relative
Group
Call Instructions
Syntax
CALLR op1
Source Operand(s)
op1 → 8-bit signed displacement
Destination Operand(s)
none
Operation
(SP) ← (SP) - 2
((SP)) ← (IP)
(IP) ← (IP) + 2*sign_extend(op1)
Description
A branch is taken to the location specified by the instruction pointer IP plus the relative
displacement op1. The displacement is a two’s complement number which is sign
extended and counts the relative distance in words. The value of the instruction pointer
(IP) is placed into the system stack. Because the IP always points to the instruction
following the branch instruction, the value stored in the system stack represents the
return address of the calling routine. The value of the IP used in the target address
calculation is the address of the instruction following the CALLR instruction.
CPU Flags
E
E
Z
V
C
N
Z
-
V
-
C
-
N
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Encoding
Mnemonic
CALLR
User’s Manual
rel
Format
BB rr
6-23
Bytes
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
CALLS
CALLS
Call Inter-Segment Subroutine
Group
Call Instructions
Syntax
CALLS op1, op2
Source Operand(s)
op1 → segment number
op2 → 16-bit address offset
Destination Operand(s)
none
Operation
(SP) ← (SP) - 2
((SP)) ← (CSP)
(SP) ← (SP) - 2
((SP)) ← (IP)
(CSP) ← op1
(IP) ← op2
Description
A branch is taken to the absolute location specified by op2 within the segment specified
by op1. The previous value of the CSP is placed into the system stack to insure correct
return to the calling segment. The value of the instruction pointer (IP) is also placed into
the system stack. Because the IP always points to the instruction following the branch
instruction, the value stored on the system stack represents the return address to the
calling routine.
CPU Flags
E
E
Z
V
C
N
Z
-
V
-
C
-
N
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Encoding
Mnemonic
CALLS
User’s Manual
seg , caddr
Format
DA SS MM MM
6-24
Bytes
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
CMP
CMP
Integer Compare
Group
Boolean Bit Manipulation Instructions
Syntax
CMP op1, op2
Source Operand(s)
op1, op2 → WORD
Destination Operand(s)
none
Operation
(op1) ⇔ (op2)
Description
The source operand specified by op1 is compared to the source operand specified by
op2 by performing a 2’s complement binary subtraction of op2 from op1. The flags are
set according to the rules of subtraction. The operands remain unchanged.
CPU Flags
E
*
E
Z
V
C
N
Z
*
V
*
C
S
N
*
Set if the value of op2 represents the lowest possible negative number.
Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Set if an arithmetic underflow occurred, i.e. the result cannot be
represented in the word data type. Cleared otherwise.
Set if a borrow is generated. Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
Encoding
Mnemonic
CMP
CMP
CMP
CMP
CMP
CMP
User’s Manual
Rwn , #data3
Rwn , Rwm
Rwn , [Rwi+]
Rwn , [Rwi]
reg , #data16
reg , mem
Format
48 n:0###
40 nm
48 n:11ii
48 n:10ii
46 RR ## ##
42 RR MM MM
6-25
Bytes
2
2
2
2
4
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
CMPB
CMPB
Integer Compare
Group
Boolean Bit Manipulation Instructions
Syntax
CMPB op1, op2
Source Operand(s)
op1, op2 → BYTE
Destination Operand(s)
none
Operation
(op1) ⇔ (op2)
Description
The source operand specified by op1 is compared to the source operand specified by
op2 by performing a 2’s complement binary subtraction of op2 from op1. The flags are
set according to the rules of subtraction. The operands remain unchanged.
CPU Flags
E
*
E
Z
V
C
N
Z
*
V
*
C
S
N
*
Set if the value of op2 represents the lowest possible negative number.
Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Set if an arithmetic underflow occurred, i.e. the result cannot be
represented in the byte data type. Cleared otherwise.
Set if a borrow is generated. Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
Encoding
Mnemonic
CMPB
CMPB
CMPB
CMPB
CMPB
CMPB
User’s Manual
Rbn , #data3
Rbn , Rbm
Rbn , [Rwi+]
Rbn , [Rwi]
reg , #data8
reg , mem
Format
49 n:0###
41 nm
49 n:11ii
49 n:10ii
47 RR ## xx
43 RR MM MM
6-26
Bytes
2
2
2
2
4
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
CMPD1
Integer Compare and Decrement by 1
Group
Compare and Loop Control Instructions
Syntax
CMPD1 op1, op2
Source Operand(s)
op1, op2 → WORD
Destination Operand(s)
op1 → WORD
CMPD1
Operation
(op1) ⇔ (op2)
(op1) ← (op1) - 1
Description
This instruction is used to enhance the performance and flexibility of loops. The source
operand specified by op1 is compared to the source operand specified by op2 by
performing a 2’s complement binary subtraction of op2 from op1. Operand op1 may
specify ONLY GPR registers. Once the subtraction has completed, the operand op1 is
decremented by one. Using the set flags, a branch instruction can then be used in
conjunction with this instruction to form common high level language FOR loops of any
range.
CPU Flags
E
*
E
Z
V
C
N
Z
*
V
*
C
S
N
*
Set if the value of op2 represents the lowest possible negative number.
Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Set if an arithmetic underflow occurred, i.e. the result cannot be
represented in the word data type. Cleared otherwise.
Set if a borrow is generated. Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
Encoding
Mnemonic
CMPD1
CMPD1
CMPD1
User’s Manual
Rwn , #data16
Rwn , #data4
Rwn , mem
Format
A6 Fn ## ##
A0 #n
A2 Fn MM MM
6-27
Bytes
4
2
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
CMPD2
Integer Compare and Decrement by 2
Group
Compare and Loop Control Instructions
Syntax
CMPD2 op1, op2
Source Operand(s)
op1, op2 → WORD
Destination Operand(s)
op1 → WORD
CMPD2
Operation
(op1) ⇔ (op2)
(op1) ← (op1) - 2
Description
This instruction is used to enhance the performance and flexibility of loops. The source
operand specified by op1 is compared to the source operand specified by op2 by
performing a 2’s complement binary subtraction of op2 from op1. Operand op1 may
specify ONLY GPR registers. Once the subtraction has completed, the operand op1 is
decremented by two. Using the set flags, a branch instruction can then be used in
conjunction with this instruction to form common high level language FOR loops of any
range.
CPU Flags
E
*
E
Z
V
C
N
Z
*
V
*
C
S
N
*
Set if the value of op2 represents the lowest possible negative number.
Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Set if an arithmetic underflow occurred, i.e. the result cannot be
represented in the word data type. Cleared otherwise.
Set if a borrow is generated. Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
Encoding
Mnemonic
CMPD2
CMPD2
CMPD2
User’s Manual
Rwn , #data16
Rwn , #data4
Rwn , mem
Format
B6 Fn ## ##
B0 #n
B2 Fn MM MM
6-28
Bytes
4
2
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
CMPI1
Integer Compare and Increment by 1
Group
Compare and Loop Control Instructions
Syntax
CMPI1 op1, op2
Source Operand(s)
op1, op2 → WORD
Destination Operand(s)
op1 → WORD
CMPI1
Operation
(op1) ⇔ (op2)
(op1) ← (op1) + 1
Description
This instruction is used to enhance the performance and flexibility of loops. The source
operand specified by op1 is compared to the source operand specified by op2 by
performing a 2’s complement binary subtraction of op2 from op1. Operand op1 may
specify ONLY GPR registers. Once the subtraction has completed, the operand op1 is
incremented by one. Using the set flags, a branch instruction can then be used in
conjunction with this instruction to form common high level language FOR loops of any
range.
CPU Flags
E
*
E
Z
V
C
N
Z
*
V
*
C
S
N
*
Set if the value of op2 represents the lowest possible negative number.
Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Set if an arithmetic underflow occurred, i.e. the result cannot be
represented in the word data type. Cleared otherwise.
Set if a borrow is generated. Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
Encoding
Mnemonic
CMPI1
CMPI1
CMPI1
User’s Manual
Rwn , #data16
Rwn , #data4
Rwn , mem
Format
86 Fn ## ##
80 #n
82 Fn MM MM
6-29
Bytes
4
2
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
CMPI2
Integer Compare and Increment by 2
Group
Compare and Loop Control Instructions
Syntax
CMPI2 op1, op2
Source Operand(s)
op1, op2 → WORD
Destination Operand(s)
op1 → WORD
CMPI2
Operation
(op1) ⇔ (op2)
(op1) ← (op1) + 2
Description
This instruction is used to enhance the performance and flexibility of loops. The source
operand specified by op1 is compared to the source operand specified by op2 by
performing a 2’s complement binary subtraction of op2 from op1. Operand op1 may
specify ONLY GPR registers. Once the subtraction has completed, the operand op1 is
incremented by two. Using the set flags, a branch instruction can then be used in
conjunction with this instruction to form common high level language FOR loops of any
range.
CPU Flags
E
*
E
Z
V
C
N
Z
*
V
*
C
S
N
*
Set if the value of op2 represents the lowest possible negative number.
Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Set if an arithmetic underflow occurred, i.e. the result cannot be
represented in the word data type. Cleared otherwise.
Set if a borrow is generated. Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
Encoding
Mnemonic
CMPI2
CMPI2
CMPI2
User’s Manual
Rwn , #data16
Rwn , #data4
Rwn , mem
Format
96 Fn ## ##
90 #n
92 Fn MM MM
6-30
Bytes
4
2
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
CPL
CPL
Integer One’s Complement
Group
Arithmetic Instructions
Syntax
CPL op1
Source Operand(s)
op1 → WORD
Destination Operand(s)
op1 → WORD
Operation
(op1) ← ¬(op1)
Description
Performs a 1’s complement of the source operand specified by op1. The result is stored
back into op1.
CPU Flags
E
*
E
Z
V
C
N
Z
*
V
0
C
0
N
*
Set if the value of op1 represents the lowest possible negative number.
Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Always cleared.
Always cleared.
Set if the most significant bit of the result is set. Cleared otherwise.
Encoding
Mnemonic
CPL
User’s Manual
Rwn
Format
91 n0
6-31
Bytes
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
CPLB
CPLB
Integer One’s Complement
Group
Arithmetic Instructions
Syntax
CPLB op1
Source Operand(s)
op1 → BYTE
Destination Operand(s)
op1 → BYTE
Operation
(op1) ← ¬(op1)
Description
Performs a 1’s complement of the source operand specified by op1. The result is stored
back into op1.
CPU Flags
E
*
E
Z
V
C
N
Z
*
V
0
C
0
N
*
Set if the value of op1 represents the lowest possible negative number.
Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Always cleared.
Always cleared.
Set if the most significant bit of the result is set. Cleared otherwise.
Encoding
Mnemonic
CPLB
User’s Manual
Rbn
Format
B1 n0
6-32
Bytes
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
DISWDT
DISWDT
Disable Watchdog Timer
Group
System Control Instructions
Syntax
DISWDT
Source Operand(s)
none
Destination Operand(s)
none
Operation
Disable the watchdog timer
Description
This instruction disables the watchdog timer. If the WDTCTL bit is cleared, the DISWDT
instruction can be executed at any time between the Reset and the first execution of
either EINIT or SRVWDT. Once either an EINIT or a SRVWDT has been executed, the
DISWDT instruction will have no effect. If the WDTCTL bit is set, the DISWDT
instruction can always be executed regardless of the execution of EINIT or SRVWDT.
To insure that this instruction is not accidentally executed, it is implemented as a
protected instruction.
CPU Flags
E
E
Z
V
C
N
Z
-
V
-
C
-
N
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Encoding
Mnemonic
DISWDT
User’s Manual
Format
A5 5A A5 A5
6-33
Bytes
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
DIV
DIV
16-by-16 Signed Division
Group
Arithmetic Instructions
Syntax
DIV op1
Source Operand(s)
op1 → WORD
MDL → WORD
Destination Operand(s)
MD → DOUBLEWORD
Operation
(MDL) ← (MDL) / (op1)
(MDH) ← (MDL) mod (op1)
Description
Performs a signed 16-bit by 16-bit division of the low order word stored in the MD
register by the source word operand op1. The signed quotient is then stored in the low
order word of the MD register (MDL) and the remainder is stored in the high order word
of the MD register (MDH).
CPU Flags
E
0
E
Z
V
C
N
Z
*
V
*
C
0
N
*
Always cleared.
Set if quotient, stored in the MDL register, equals zero. Cleared
otherwise. Undefined if the V flag is set.
Set if an arithmetic overflow occurred, i.e. the quotient cannot be
represented in a word data type, or if the divisor op1 was zero. Cleared
otherwise.
Always cleared.
Set if the most significant bit of the quotient, stored in the MDL register, is
set. Cleared otherwise. Undefined if the V flag is set.
Encoding
Mnemonic
DIV
User’s Manual
Rwn
Format
4B nn
6-34
Bytes
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
DIVL
DIVL
32-by-16 Signed Division
Group
Arithmetic Instructions
Syntax
DIVL op1
Source Operand(s)
op1 → WORD
MD → DOUBLEWORD
Destination Operand(s)
MD → DOUBLEWORD
Operation
(MDL) ← (MD) / (op1)
(MDH) ← (MD) mod (op1)
Description
Performs an extended signed 32-bit by 16-bit division of the two words stored in the MD
register by the source word operand op1. The signed quotient is then stored in the low
order word of the MD register (MDL) and the remainder is stored in the high order word
of the MD register (MDH).
CPU Flags
E
0
E
Z
V
C
N
Z
*
V
*
C
0
N
*
Always cleared.
Set if quotient, stored in the MDL register, equals zero. Cleared
otherwise. Undefined if the V flag is set.
Set if an arithmetic overflow occurred, i.e. the quotient cannot be
represented in a word data type, or if the divisor op1 was zero. Cleared
otherwise.
Always cleared.
Set if the most significant bit of the quotient, stored in the MDL register, is
set. Cleared otherwise. Undefined if the V flag is set.
Encoding
Mnemonic
DIVL
User’s Manual
Rwn
Format
6B nn
6-35
Bytes
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
DIVLU
DIVLU
32-by-16 Unsigned Division
Group
Arithmetic Instructions
Syntax
DIVLU op1
Source Operand(s)
op1 → WORD
MD → DOUBLEWORD
Destination Operand(s)
MD → DOUBLEWORD
Operation
(MDL) ← (MD) / op1
(MDH) ← (MD) mod (op1)
Description
Performs an extended unsigned 32-bit by 16-bit division of the two words stored in the
MD register by the source word operand op1. The unsigned quotient is then stored in
the low order word of the MD register (MDL) and the remainder is stored in the high
order word of the MD register (MDH).
CPU Flags
E
0
E
Z
V
C
N
Z
*
V
*
C
0
N
*
Always cleared.
Set if quotient, stored in the MDL register, equals zero. Cleared
otherwise. Undefined if the V flag is set.
Set if an arithmetic overflow occurred, i.e. the quotient cannot be
represented in a word data type, or if the divisor op1 was zero. Cleared
otherwise.
Always cleared.
Set if the most significant bit of the quotient, stored in the MDL register, is
set. Cleared otherwise. Undefined if the V flag is set.
Encoding
Mnemonic
DIVLU
User’s Manual
Rwn
Format
7B nn
6-36
Bytes
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
DIVU
DIVU
16-by-16 Unsigned Division
Group
Arithmetic Instructions
Syntax
DIVU op1
Source Operand(s)
op1 → WORD
MDL → WORD
Destination Operand(s)
MD → DOUBLEWORD
Operation
(MDL) ← (MDL) / (op1)
(MDH) ← (MDL) mod (op1)
Description
Performs an unsigned 16-bit by 16-bit division of the low order word stored in the MD
register by the source word operand op1. The unsigned quotient is then stored in the
low order word of the MD register (MDL) and the remainder is stored in the high order
word of the MD register (MDH).
CPU Flags
E
0
E
Z
V
C
N
Z
*
V
*
C
0
N
*
Always cleared.
Set if quotient, stored in the MDL register, equals zero. Cleared
otherwise. Undefined if the V flag is set.
Set if the divisor op1 was zero.
Always cleared.
Set if the most significant bit of the quotient, stored in the MDL register, is
set. Cleared otherwise. Undefined if the V flag is set.
Encoding
Mnemonic
DIVU
User’s Manual
Rwn
Format
5B nn
6-37
Bytes
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
EINIT
EINIT
End of Initialization
Group
System Control Instructions
Syntax
EINIT
Source Operand(s)
none
Destination Operand(s)
none
Operation
End of Initialization
Description
After a reset, the reset output pin RSTOUT is pulled low. It remains low until the EINIT
instruction has been executed at which time it goes high. This enables the software to
signal the external circuitry that it has successfully initialized the microcontroller.
Execution of the Disable Watchdog Timer (DISWDT) instruction after the execution of
the EINIT instruction has no effect. To insure that this instruction is not accidentally
executed, it is implemented as a protected instruction.
CPU Flags
E
E
Z
V
C
N
Z
-
V
-
C
-
N
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Encoding
Mnemonic
EINIT
User’s Manual
Format
B5 4A B5 B5
6-38
Bytes
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
EXTP
EXTP
Begin EXTended Page Sequence
Group
System Control Instructions
Syntax
EXTP op1, op2
Source Operand(s)
op1 → 10-bit page number
op2 → 2-bit instruction counter
Destination Operand(s)
none
Operation
(count) ← (op2) [1 ≤ op2 ≤ 4]
Disable interrupts and Class A traps
Data_Page ← (op1)
DO WHILE ((count) ≠ 0 AND Class_B_Trap_Condition ≠ TRUE)
Next Instruction
(count) ← (count) - 1
END WHILE
(count) ← 0
Data_Page ← (DPPx)
Enable interrupts and traps
Description
Overrides the standard DPP addressing scheme of the long and indirect addressing
modes for a specified number of instructions. During their execution, both standard and
PEC interrupts and class A hardware traps are locked. The EXTP instruction becomes
immediately active such that no additional NOPs are required. For any long (’mem’) or
indirect ([...]) address in the EXTP instruction sequence, the 10-bit page number
(address bits A23-A14) is not determined by the contents of a DPP register but by the
value of op1 itself. The 14-bit page offset (address bits A13-A0) is derived from the long
or indirect address as usual. The value of op2 defines the length of the effected
instruction sequence.
CPU Flags
E
E
Z
V
C
N
User’s Manual
Z
-
V
-
C
-
N
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
6-39
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
Encoding
Mnemonic
EXTP
EXTP
User’s Manual
#pag , #irang2
Rwm , #irang2
Format
D7 :01##-0 pp 0:00pp
DC :01##-m
6-40
Bytes
4
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
EXTPR
EXTPR
Begin EXTended Page and Register Sequence
Group
System Control Instructions
Syntax
EXTPR op1, op2
Source Operand(s)
op1 → 10-bit page number
op2 → 2-bit instruction counter
Destination Operand(s)
none
Operation
(count) ← (op2) [1 ≤ op2 ≤ 4]
Disable interrupts and Class A traps
Data_Page ← (op1)
SFR_range ← Extended
DO WHILE ((count) ≠ 0 AND Class_B_Trap_Condition ≠ TRUE)
Next Instruction
(count) ← (count) - 1
END WHILE
(count) ← 0
Data_Page ← (DPPx)
SFR_range ← Standard
Enable interrupts and traps
Description
Overrides the standard DPP addressing scheme of the long and indirect addressing
modes and causes all SFR or SFR bit accesses via the ’reg’, ’bitoff’ or ’bitaddr’
addressing modes being made to the Extended SFR space for a specified number of
instructions. During their execution, both standard and PEC interrupts and class A
hardware traps are locked. For any long (’mem’) or indirect ([...]) address in the EXTP
instruction sequence, the 10-bit page number (address bits A23-A14) is not determined
by the contents of a DPP register but by the value of op1 itself. The 14-bit page offset
(address bits A13-A0) is derived from the long or indirect address as usual. The value
of op2 defines the length of the effected instruction sequence.
CPU Flags
E
E
Z
V
User’s Manual
Z
-
V
-
C
-
N
-
Not affected.
Not affected.
Not affected.
6-41
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
C
N
Not affected.
Not affected.
Encoding
Mnemonic
EXTPR
EXTPR
User’s Manual
#pag , #irang2
Rwm , #irang2
Format
D7 :11##-0 pp 0:00pp
DC :11##-m
6-42
Bytes
4
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
EXTR
EXTR
Begin EXTended Register Sequence
Group
System Control Instructions
Syntax
EXTR op1
Source Operand(s)
op1 → 2-bit instruction counter
Destination Operand(s)
none
Operation
(count) ← (op1) [1 ≤ op1 ≤ 4]
Disable interrupts and Class A traps
SFR_range ← Extended
DO WHILE ((count) ≠ 0 AND Class_B_Trap_Condition ≠ TRUE)
Next Instruction
(count) ← (count) - 1
END WHILE
(count) ← 0
SFR_range ← Standard
Enable interrupts and traps
Description
Causes all SFR or SFR bit accesses via the ’reg’, ’bitoff’ or ’bitaddr’ addressing modes
being made to the Extended SFR space for a specified number of instructions. During
their execution, both standard and PEC interrupts and class A hardware traps are
locked. The value of op1 defines the length of the effected instruction sequence.
CPU Flags
E
E
Z
V
C
N
Z
-
V
-
C
-
N
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Encoding
Mnemonic
EXTR
User’s Manual
#irang2
Format
D1 :10##-0
6-43
Bytes
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
EXTS
EXTS
Begin EXTended Segment Sequence
Group
System Control Instructions
Syntax
EXTS op1, op2
Source Operand(s)
op1 → segment number
op2 → 2-bit instruction counter
Destination Operand(s)
none
Operation
(count) ← (op2) [1 ≤ op2 ≤ 4]
Disable interrupts and Class A traps
Data_Segment ← (op1)
DO WHILE ((count) ≠ 0 AND Class_B_Trap_Condition ≠ TRUE)
Next Instruction
(count) ← (count) - 1
END WHILE
(count) ← 0
Data_Page ← (DPPx)
Enable interrupts and traps
Description
Overrides the standard DPP addressing scheme of the long and indirect addressing
modes for a specified number of instructions. During their execution, both standard and
PEC interrupts and class A hardware traps are locked. The EXTS instruction becomes
immediately active such that no additional NOPs are required. For any long (’mem’) or
indirect ([...]) address in an EXTS instruction sequence, the value of op1 determines the
8-bit segment (address bits A23-A16) valid for the corresponding data access. The long
or indirect address itself represents the 16-bit segment offset (address bits A15-A0).
The value of op2 defines the length of the effected instruction sequence.
CPU Flags
E
E
Z
V
C
N
User’s Manual
Z
-
V
-
C
-
N
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
6-44
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
Encoding
Mnemonic
EXTS
EXTS
User’s Manual
#seg , #irang2
Rwm , #irang2
Format
D7 :00##-0 ss 00
DC :00##-m
6-45
Bytes
4
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
EXTSR
EXTSR
Begin EXTended Segment and Register Sequence
Group
System Control Instructions
Syntax
EXTSR op1, op2
Source Operand(s)
op1 → segment number
op2 → 2-bit instruction counter
Destination Operand(s)
none
Operation
(count) ← (op2) [1 ≤ op2 ≤ 4]
Disable interrupts and Class A traps
Data_Segment ← (op1)
SFR_range ← Extended
DO WHILE ((count) ≠ 0 AND Class_B_Trap_Condition ≠ TRUE)
Next Instruction
(count) ← (count) - 1
END WHILE
(count) ← 0
Data_Page ← (DPPx)
SFR_range ← Standard
Enable interrupts and traps
Description
Overrides the standard DPP addressing scheme of the long and indirect addressing
modes and causes all SFR or SFR bit accesses via the ’reg’, ’bitoff’ or ’bitaddr’
addressing modes being made to the Extended SFR space for a specified number of
instructions. During their execution, both standard and PEC interrupts and class A
hardware traps are locked. The EXTSR instruction becomes immediately active such
that no additional NOPs are required. For any long (’mem’) or indirect ([...]) address in
an EXTSR instruction sequence, the value of op1 determines the 8-bit segment
(address bits A23-A16) valid for the corresponding data access. The long or indirect
address itself represents the 16-bit segment offset (address bits A15-A0). The value of
op2 defines the length of the effected instruction sequence.
CPU Flags
E
E
Z
User’s Manual
Z
-
V
-
C
-
N
-
Not affected.
Not affected.
6-46
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
V
C
N
Not affected.
Not affected.
Not affected.
Encoding
Mnemonic
EXTSR
EXTSR
User’s Manual
#seg , #irang2
Rwm , #irang2
Format
D7 :10##-0 ss 00
DC :10##-m
6-47
Bytes
4
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
IDLE
Enter Idle Mode
Group
System Control Instructions
Syntax
IDLE
Source Operand(s)
none
Destination Operand(s)
none
IDLE
Operation
Enter Idle Mode
Description
This instruction causes the part to enter the idle mode. In this mode, the CPU is
powered down while the peripherals remain running. It remains powered down until a
peripheral interrupt or external interrupt occurs. To insure that this instruction is not
accidentally executed, it is implemented as a protected instruction.
CPU Flags
E
E
Z
V
C
N
Z
-
V
-
C
-
N
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Encoding
Mnemonic
IDLE
User’s Manual
Format
87 78 87 87
6-48
Bytes
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
JB
JB
Relative Jump if Bit Set
Group
Jump Instructions
Syntax
JB op1, op2
Source Operand(s)
op1 → BIT
op2 → 8-bit signed displacement
Destination Operand(s)
none
Operation
IF ((op1) = 1) THEN
(IP) ← (IP) + 2*sign_extend(op2)
ELSE
Next Instruction
END IF
Description
If the bit specified by op1 is set, program execution continues at the location of the
instruction pointer IP, plus the specified displacement op2. The displacement is a two’s
complement number which is sign extended and counts the relative distance in words.
The value of the IP used in the target address calculation is the address of the
instruction following the JB instruction. If the specified bit is cleared, program execution
continues normally with the instruction following the JB instruction.
CPU Flags
E
E
Z
V
C
N
Z
-
V
-
C
-
N
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Encoding
Mnemonic
JB
User’s Manual
bitaddrQ.q , rel
Format
8A QQ rr q0
6-49
Bytes
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
JBC
Relative Jump if Bit Set and Clear Bit
Group
Jump Instructions
Syntax
JBC op1, op2
Source Operand(s)
op1 → BIT
op2 → 8-bit signed displacement
Destination Operand(s)
none
JBC
Operation
IF ((op1) = 1) THEN
(op1) ← 0
(IP) ← (IP) + 2*sign_extend(op2)
ELSE
Next Instruction
END IF
Description
If the bit specified by op1 is set, program execution continues at the location of the
instruction pointer IP, plus the specified displacement op2. The bit specified by op1 is
cleared, allowing implementation of semaphore operations. The displacement is a two’s
complement number which is sign extended and counts the relative distance in words.
The value of the IP used in the target address calculation is the address of the
instruction following the JBC instruction. If the specified bit was clear, program
execution continues normally with the instruction following the JBC instruction.
Note
Flags are always updated by this instruction.
CPU Flags
E
0
E
Z
V
C
N
User’s Manual
Z
B
V
0
C
0
N
B
Always cleared.
Contains the logical negation of the previous state of the specified bit.
Always cleared.
Always cleared.
Contains the previous state of the specified bit.
6-50
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
Encoding
Mnemonic
JBC
User’s Manual
bitaddrQ.q , rel
Format
AA QQ rr q0
6-51
Bytes
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
JMPA
JMPA
Absolute Conditional Jump
Group
Jump Instructions
Syntax
JMPA op1, op2
Source Operand(s)
op1 → extended condition code
op2 → 16-bit address offset
Destination Operand(s)
none
Operation
IF ((op1) = 1) THEN
(IP) ← op2
ELSE
Next Instruction
END IF
Description
If the condition specified by op1 is met, a branch to the absolute address specified by
op2 is taken. If the condition is not met, no action is taken, and the instruction following
the JMPA instruction is executed normally.
CPU Flags
E
E
Z
V
C
N
Z
-
V
-
C
-
N
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Encoding
Mnemonic
JMPA
User’s Manual
xcc , caddr
Format
EA d0la MM MM
6-52
Bytes
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
JMPI
JMPI
Indirect Conditional Jump
Group
Jump Instructions
Syntax
JMPI op1, op2
Source Operand(s)
op1 → condition code
op2 → 16-bit address offset
Destination Operand(s)
none
Operation
IF ((op1) = 1) THEN
(IP) ← (op2)
ELSE
Next Instruction
END IF
Description
If the condition specified by op1 is met, a branch to the absolute address specified by
op2 is taken. If the condition is not met, no action is taken, and program execution
continues normally with the instruction following the JMPI instruction.
CPU Flags
E
E
Z
V
C
N
Z
-
V
-
C
-
N
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Encoding
Mnemonic
JMPI
User’s Manual
cc , [Rwn]
Format
9C cn
6-53
Bytes
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
JMPR
JMPR
Relative Conditional Jump
Group
Jump Instructions
Syntax
JMPR op1, op2
Source Operand(s)
op1 → condition code
op2 → 8-bit signed displacement
Destination Operand(s)
none
Operation
IF ((op1) = 1) THEN
(IP) ← (IP) + 2*sign_extend(op2)
ELSE
Next Instruction
END IF
Description
If the extended condition specified by op1 is met, program execution continues at the
location of the instruction pointer, IP, plus the specified displacement, op2. The
displacement is a two’s complement number which is sign-extended and counts the
relative distance in words. The value of the IP used in the target address calculation is
the address of the instruction following the JMPR instruction. If the specified condition is
not met, program execution continues normally with the instruction following the JMPR
instruction.
CPU Flags
E
E
Z
V
C
N
Z
-
V
-
C
-
N
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Encoding
Mnemonic
JMPR
User’s Manual
cc , rel
Format
cD rr
6-54
Bytes
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
JMPS
JMPS
Absolute Inter-Segment Jump
Group
Jump Instructions
Syntax
JMPS op1, op2
Source Operand(s)
op1 → segment number
op2 → 16-bit address offset
Destination Operand(s)
none
Operation
(CSP) ← op1
(IP) ← op2
Description
Branches unconditionally to the absolute address specified by op2 within the segment
specified by op1.
CPU Flags
E
E
Z
V
C
N
Z
-
V
-
C
-
N
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Encoding
Mnemonic
JMPS
User’s Manual
seg , caddr
Format
FA SS MM MM
6-55
Bytes
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
JNB
JNB
Relative Jump if Bit Clear
Group
Jump Instructions
Syntax
JNB op1, op2
Source Operand(s)
op1 → BIT
op2 → 8-bit signed displacement
Destination Operand(s)
none
Operation
IF ((op1) = 0) THEN
(IP) ← (IP) + 2*sign_extend(op2)
ELSE
Next Instruction
END IF
Description
If the bit specified by op1 is clear, program execution continues at the location of the
instruction pointer IP, plus the specified displacement op2. The displacement is a two’s
complement number which is sign-extended and counts the relative distance in words.
The value of the IP used in the target address calculation is the address of the
instruction following the JNB instruction. If the specified bit is set, program execution
continues normally with the instruction following the JNB instruction.
CPU Flags
E
E
Z
V
C
N
Z
-
V
-
C
-
N
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Encoding
Mnemonic
JNB
User’s Manual
bitaddrQ.q , rel
Format
9A QQ rr q0
6-56
Bytes
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
JNBS
Relative Jump if Bit Clear and Set Bit
Group
Jump Instructions
Syntax
JNBS op1, op2
Source Operand(s)
op1 → BIT
op2 → 8-bit signed displacement
Destination Operand(s)
none
JNBS
Operation
IF ((op1) = 0) THEN
(op1) ← 1
(IP) ← (IP) + 2*sign_extend(op2)
ELSE
Next Instruction
END IF
Description
If the bit specified by op1 is clear, program execution continues at the location of the
instruction pointer IP, plus the specified displacement op2. The bit specified by op1 is
set, allowing implementation of semaphore operations. The displacement is a two’s
complement number which is sign-extended and counts the relative distance in words.
The value of the IP used in the target address calculation is the address of the
instruction following the JNBS instruction. If the specified bit was set, program
execution continues normally with the instruction following the JNBS instruction.
Note
Flags are always updated by this instruction.
CPU Flags
E
0
E
Z
V
C
N
Z
B
V
0
C
0
N
B
Always cleared.
Contains the logical negation of the previous state of the specified bit.
Always cleared.
Always cleared.
Contains the previous state of the specified bit.
Encoding
Mnemonic
JNBS
User’s Manual
bitaddrQ.q , rel
Format
BA QQ rr q0
6-57
Bytes
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
MOV
MOV
Move Data
Group
Data Movement Instructions
Syntax
MOV op1, op2
Source Operand(s)
op2 → WORD
Destination Operand(s)
op1 → WORD
Operation
(op1) ← (op2)
Description
Moves the contents of the source operand specified by op2 to the location specified by
the destination operand op1. The contents of the moved data is examined, and the
flags are updated accordingly.
CPU Flags
E
*
E
Z
V
C
N
Z
*
V
-
C
-
N
*
Set if the value of op2 represents the lowest possible negative number.
Cleared otherwise. Used to signal the end of a table.
Set if the value of the source operand op2 equals zero. Cleared
otherwise.
Not affected.
Not affected.
Set if the most significant bit of the source operand op2 is set. Cleared
otherwise.
Encoding
Mnemonic
MOV
MOV
MOV
MOV
MOV
MOV
MOV
User’s Manual
Rwn , #data4
Rwn , Rwm
Rwn , [Rwm+#data16]
Rwn , [Rwm+]
Rwn , [Rwm]
[-Rwm] , Rwn
[Rwm+#data16] , Rwn
Format
E0 #n
F0 nm
D4 nm ## ##
98 nm
A8 nm
88 nm
C4 nm ## ##
6-58
Bytes
2
2
4
2
2
2
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
User’s Manual
[Rwm] , Rwn
[Rwn+] , [Rwm]
[Rwn] , [Rwm+]
[Rwn] , [Rwm]
[Rwn] , mem
mem , [Rwn]
mem , reg
reg , #data16
reg , mem
B8 nm
D8 nm
E8 nm
C8 nm
84 0n MM MM
94 0n MM MM
F6 RR MM MM
E6 RR ## ##
F2 RR MM MM
6-59
2
2
2
2
4
4
4
4
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
MOVB
MOVB
Move Data
Group
Data Movement Instructions
Syntax
MOVB op1, op2
Source Operand(s)
op2 → BYTE
Destination Operand(s)
op1 → BYTE
Operation
(op1) ← (op2)
Description
Moves the contents of the source operand specified by op2 to the location specified by
the destination operand op1. The contents of the moved data is examined, and the
flags are updated accordingly.
CPU Flags
E
*
E
Z
V
C
N
Z
*
V
-
C
-
N
*
Set if the value of op2 represents the lowest possible negative number.
Cleared otherwise. Used to signal the end of a table.
Set if the value of the source operand op2 equals zero. Cleared
otherwise.
Not affected.
Not affected.
Set if the most significant bit of the source operand op2 is set. Cleared
otherwise.
Encoding
Mnemonic
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
User’s Manual
Rbn , #data4
Rbn , Rbm
Rbn , [Rwm + #data16]
Rbn , [Rwm+]
Rbn , [Rwm]
[-Rwm] , Rbn
[Rwm + #data16] , Rbn
Format
E1 #n
F1 nm
F4 nm ## ##
99 nm
A9 nm
89 nm
E4 nm ## ##
6-60
Bytes
2
2
4
2
2
2
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
User’s Manual
[Rwm] , Rbn
[Rwn+] , [Rwm]
[Rwn] , [Rwm+]
[Rwn] , [Rwm]
[Rwn] , mem
mem , [Rwn]
mem , reg
reg , #data8
reg , mem
B9 nm
D9 nm
E9 nm
C9 nm
A4 0n MM MM
B4 0n MM MM
F7 RR MM MM
E7 RR ## xx
F3 RR MM MM
6-61
2
2
2
2
4
4
4
4
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
MOVBS
MOVBS
Move Byte Sign Extend
Group
Data Movement Instructions
Syntax
MOVBS op1, op2
Source Operand(s)
op2 → BYTE
Destination Operand(s)
op1 → WORD
Operation
(low byte op1) ← (op2)
IF ((op2[7]) = 1) THEN
(high byte op1) ← FFH
ELSE
(high byte op1) ← 00H
END IF
Description
Moves and sign-extends the contents of the source byte operand specified by op2 to
the word location specified by the destination operand op1. The contents of the moved
data is examined, and the flags are updated accordingly.
CPU Flags
E
0
E
Z
V
C
N
Z
*
V
-
C
-
N
*
Always cleared.
Set if the value of the source byte operand op2 equals zero. Cleared
otherwise.
Not affected.
Not affected.
Set if the most significant bit of the source operand op2 is set. Cleared
otherwise.
Encoding
Mnemonic
MOVBS
MOVBS
MOVBS
User’s Manual
Rwn , Rbm
mem , reg
reg , mem
Format
D0 mn
D5 RR MM MM
D2 RR MM MM
6-62
Bytes
2
4
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
MOVBZ
MOVBZ
Move Byte Zero Extend
Group
Data Movement Instructions
Syntax
MOVBZ op1, op2
Source Operand(s)
op2 → BYTE
Destination Operand(s)
op1 → WORD
Operation
(low byte op1) ← (op2)
(high byte op1) ← 00H
Description
Moves and zero-extends the contents of the source byte operand specified by op2 to
the word location specified by the destination operand op1. The contents of the moved
data is examined, and the flags are updated accordingly.
CPU Flags
E
0
E
Z
V
C
N
Z
*
V
-
C
-
N
0
Always cleared.
Set if the value of the source byte operand op2 equals zero. Cleared
otherwise.
Not affected.
Not affected.
Always cleared.
Encoding
Mnemonic
MOVBZ
MOVBZ
MOVBZ
User’s Manual
Rwn , Rbm
mem , reg
reg , mem
Format
C0 mn
C5 RR MM MM
C2 RR MM MM
6-63
Bytes
2
4
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
MUL
MUL
Signed Multiplication
Group
Arithmetic Instructions
Syntax
MUL op1, op2
Source Operand(s)
op1, op2 → WORD
Destination Operand(s)
MD → DOUBLEWORD
Operation
(MD) ← (op1) * (op2)
Description
Performs a 16-bit by 16-bit signed multiplication using the two words specified by
operands op1 and op2 respectively. The signed 32-bit result is placed in the MD
register.
CPU Flags
E
0
E
Z
V
C
N
Z
*
V
*
C
0
N
*
Always cleared.
Set if result equals zero. Cleared otherwise.
This bit is set if the result cannot be represented in a word data type.
Cleared otherwise.
Always cleared.
Set if the most significant bit of the result is set. Cleared otherwise.
Encoding
Mnemonic
MUL
User’s Manual
Rwn , Rwm
Format
0B nm
6-64
Bytes
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
MULU
MULU
Unsigned Multiplication
Group
Arithmetic Instructions
Syntax
MULU op1, op2
Source Operand(s)
op1, op2 → WORD
Destination Operand(s)
MD → DOUBLEWORD
Operation
(MD) ← (op1) * (op2)
Description
Performs a 16-bit by 16-bit unsigned multiplication using the two words specified by
operands op1 and op2 respectively. The unsigned 32-bit result is placed in the MD
register.
CPU Flags
E
0
E
Z
V
C
N
Z
*
V
*
C
0
N
*
Always cleared.
Set if result equals zero. Cleared otherwise.
This bit is set if the result cannot be represented in a word data type.
Cleared otherwise.
Always cleared.
Set if the most significant bit of the result is set. Cleared otherwise.
Encoding
Mnemonic
MULU
User’s Manual
Rwn , Rwm
Format
1B nm
6-65
Bytes
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
NEG
NEG
Integer Two’s Complement
Group
Arithmetic Instructions
Syntax
NEG op1
Source Operand(s)
op1 → WORD
Destination Operand(s)
op1 → WORD
Operation
(op1) ← 0 - (op1)
Description
Performs a binary 2’s complement of the source operand specified by op1. The result is
then stored in op1.
CPU Flags
E
*
E
Z
V
C
N
Z
*
V
*
C
*
N
*
Set if the value of op1 represents the lowest possible negative number.
Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Set if an arithmetic underflow occurred, i.e. the result cannot be
represented in the word data type. Cleared otherwise.
Set if a borrow is generated. Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
Encoding
Mnemonic
NEG
User’s Manual
Rwn
Format
81 n0
6-66
Bytes
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
NEGB
NEGB
Integer Two’s Complement
Group
Arithmetic Instructions
Syntax
NEGB op1
Source Operand(s)
op1 → BYTE
Destination Operand(s)
op1 → BYTE
Operation
(op1) ← 0 - (op1)
Description
Performs a binary 2’s complement of the source operand specified by op1. The result is
then stored in op1.
CPU Flags
E
*
E
Z
V
C
N
Z
*
V
*
C
*
N
*
Set if the value of op1 represents the lowest possible negative number.
Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Set if an arithmetic underflow occurred, i.e. the result cannot be
represented in the byte data type. Cleared otherwise.
Set if a borrow is generated. Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
Encoding
Mnemonic
NEGB
User’s Manual
Rbn
Format
A1 n0
6-67
Bytes
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
NOP
NOP
No Operation
Group
Null operation
Syntax
NOP
Source Operand(s)
none
Destination Operand(s)
none
Operation
No Operation
Description
This instruction causes a null operation to be performed. A null operation causes no
change in the status of the flags.
CPU Flags
E
E
Z
V
C
N
Z
-
V
-
C
-
N
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Encoding
Mnemonic
NOP
User’s Manual
Format
CC 00
6-68
Bytes
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
OR
OR
Logical OR
Group
Logical Instructions
Syntax
OR op1, op2
Source Operand(s)
op1, op2 → WORD
Destination Operand(s)
op1 → WORD
Operation
(op1) ← (op1) ∨ (op2)
Description
Performs a bitwise logical OR of the source operand specified by op2 and the
destination operand specified by op1. The result is then stored in op1.
CPU Flags
E
*
E
Z
V
C
N
Z
*
V
0
C
0
N
*
Set if the value of op2 represents the lowest possible negative number.
Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Always cleared.
Always cleared.
Set if the most significant bit of the result is set. Cleared otherwise.
Encoding
Mnemonic
OR
OR
OR
OR
OR
OR
OR
User’s Manual
Rwn , #data3
Rwn , Rwm
Rwn , [Rwi+]
Rwn , [Rwi]
mem , reg
reg , #data16
reg , mem
Format
78 n:0###
70 nm
78 n:11ii
78 n:10ii
74 RR MM MM
76 RR ## ##
72 RR MM MM
6-69
Bytes
2
2
2
2
4
4
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
ORB
ORB
Logical OR
Group
Logical Instructions
Syntax
ORB op1, op2
Source Operand(s)
op1, op2 → BYTE
Destination Operand(s)
op1 → BYTE
Operation
(op1) ← (op1) ∨ (op2)
Description
Performs a bitwise logical OR of the source operand specified by op2 and the
destination operand specified by op1. The result is then stored in op1.
CPU Flags
E
*
E
Z
V
C
N
Z
*
V
0
C
0
N
*
Set if the value of op2 represents the lowest possible negative number.
Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Always cleared.
Always cleared.
Set if the most significant bit of the result is set. Cleared otherwise.
Encoding
Mnemonic
ORB
ORB
ORB
ORB
ORB
ORB
ORB
User’s Manual
Rbn , #data3
Rbn , Rbm
Rbn , [Rwi+]
Rbn , [Rwi]
mem , reg
reg , #data8
reg , mem
Format
79 n:0###
71 nm
79 n:11ii
79 n:10ii
75 RR MM MM
77 RR ## xx
73 RR MM MM
6-70
Bytes
2
2
2
2
4
4
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
PCALL
Push Word and Call Subroutine Absolute
Group
Call Instructions
Syntax
PCALL op1, op2
Source Operand(s)
op1 → WORD
op2 → 16-bit address offset
Destination Operand(s)
none
PCALL
Operation
(tmp) ← (op1)
(SP) ← (SP) - 2
((SP)) ← (tmp)
(SP) ← (SP) - 2
((SP)) ← (IP)
(IP) ← op2
Description
Pushes the word specified by operand op1 and the value of the instruction pointer, IP,
onto the system stack, and branches to the absolute memory location specified by the
second operand op2. Because IP always points to the instruction following the branch
instruction, the value stored on the system stack represents the return address of the
calling routine.
CPU Flags
E
*
E
Z
V
C
N
User’s Manual
Z
*
V
-
C
-
N
*
Set if the value of the pushed operand op1 represents the lowest
possible negative number. Cleared otherwise. Used to signal the end of a
table.
Set if the value of the pushed operand op1 equals zero. Cleared
otherwise.
Not affected.
Not affected.
Set if the most significant bit of the pushed operand op1 is set. Cleared
otherwise.
6-71
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
Encoding
Mnemonic
PCALL
User’s Manual
reg , caddr
Format
E2 RR MM MM
6-72
Bytes
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
POP
POP
Pop Word from System Stack
Group
System Stack Instructions
Syntax
POP op1
Source Operand(s)
none
Destination Operand(s)
op1 → WORD
Operation
(tmp) ← ((SP))
(SP) ← (SP) + 2
(op1) ← (tmp)
Description
Pops one word from the system stack specified by the Stack Pointer into the operand
specified by op1. The Stack Pointer is then incremented by two.
CPU Flags
E
*
E
Z
V
C
N
Z
*
V
-
C
-
N
*
Set if the value of the popped word represents the lowest possible
negative number. Cleared otherwise. Used to signal the end of a table.
Set if the value of the popped word equals zero. Cleared otherwise.
Not affected.
Not affected.
Set if the most significant bit of the popped word is set. Cleared
otherwise.
Encoding
Mnemonic
POP
User’s Manual
reg
Format
FC RR
6-73
Bytes
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
PRIOR
PRIOR
Prioritize Register
Group
Prioritize Instruction
Syntax
PRIOR op1, op2
Source Operand(s)
op2 → WORD
Destination Operand(s)
op1 → WORD
Operation
(tmp) ← (op2)
(count) ← 0
DO WHILE (((tmp[15]) ≠ 1) AND ((op2) ≠ 0)))
(tmp[n]) ← (tmp[n-1]) [n=15...1]
(count) ← (count) + 1
END WHILE
(op1) ← (count)
Description
This instruction stores a count value in the word operand specified by op1. This count
value indicates the number of single bit shifts required to normalize the word operand
op2 so that its most significant bit is equal to one. If the source operand op2 equals
zero, a zero is written to operand op1 and the zero flag is set. Otherwise the zero flag is
cleared.
CPU Flags
E
0
E
Z
V
C
N
Z
*
V
0
C
0
N
0
Always cleared.
Set if the value of the source operand op2 equals zero. Cleared
otherwise.
Always cleared.
Always cleared.
Always cleared.
Encoding
Mnemonic
PRIOR
User’s Manual
Rwn , Rwm
Format
2B nm
6-74
Bytes
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
PUSH
PUSH
Push Word on System Stack
Group
System Stack Instructions
Syntax
PUSH op1
Source Operand(s)
op1 → WORD
Destination Operand(s)
none
Operation
(tmp) ← (op1)
(SP) ← (SP) - 2
((SP)) ← (tmp)
Description
Moves the word specified by operand op1 to the location in the system stack specified
by the Stack Pointer, after the Stack Pointer has been decremented by two.
CPU Flags
E
*
E
Z
V
C
N
Z
*
V
-
C
-
N
*
Set if the value of the pushed operand op1 represents the lowest
possible negative number. Cleared otherwise. Used to signal the end of a
table.
Set if the value of the pushed operand op1 equals zero. Cleared
otherwise.
Not affected.
Not affected.
Set if the most significant bit of the pushed operand op1 is set. Cleared
otherwise.
Encoding
Mnemonic
PUSH
User’s Manual
reg
Format
EC RR
6-75
Bytes
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
PWRDN
PWRDN
Enter Power Down Mode
Group
System Control Instructions
Syntax
PWRDN
Source Operand(s)
none
Destination Operand(s)
none
Operation
Enter Power Down Mode
Description
This instruction causes the part to enter the power down mode. In this mode, all
peripherals and the CPU are powered down until the part is externally reset. To insure
that this instruction is not accidentally executed, it is implemented as a protected
instruction. To further control the action of this instruction, the PWRDN instruction is
only enabled when the non-maskable interrupt pin (NMI) is in the low state. Otherwise,
this instruction has no effect.
CPU Flags
E
E
Z
V
C
N
Z
-
V
-
C
-
N
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Encoding
Mnemonic
PWRDN
User’s Manual
Format
97 68 97 97
6-76
Bytes
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
RET
RET
Return from Subroutine
Group
Return Instructions
Syntax
RET
Source Operand(s)
none
Destination Operand(s)
none
Operation
(IP) ← ((SP))
(SP) ← (SP) + 2
Description
Returns from a subroutine. The IP is popped from the system stack.
CPU Flags
E
E
Z
V
C
N
Z
-
V
-
C
-
N
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Encoding
Mnemonic
RET
User’s Manual
Format
CB 00
6-77
Bytes
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
RETI
RETI
Return from Interrupt Subroutine
Group
Return Instructions
Syntax
RETI
Source Operand(s)
none
Destination Operand(s)
none
Operation
(IP) ← ((SP))
(SP) ← (SP) + 2
IF (SYSCON.SGTDIS = 0) THEN
(CSP) ← ((SP))
(SP) ← (SP) + 2
END IF
(PSW) ← ((SP))
(SP) ← (SP) + 2
Description
Returns from an interrupt routine. The IP, CSP, and PSW are popped off the system
stack. The CSP is only popped if segmentation is enabled. This is indicated by the
SGTDIS bit in the SYSCON register.
CPU Flags
E
*
E
Z
V
C
N
Z
*
V
*
C
*
N
*
Restored from the PSW popped from stack.
Restored from the PSW popped from stack.
Restored from the PSW popped from stack.
Restored from the PSW popped from stack.
Restored from the PSW popped from stack.
Encoding
Mnemonic
RETI
User’s Manual
Format
FB 88
6-78
Bytes
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
RETP
Return from Subroutine and Pop Word
Group
Return Instructions
Syntax
RETP op1
Source Operand(s)
none
Destination Operand(s)
op1 → WORD
RETP
Operation
(IP) ← ((SP))
(SP) ← (SP) + 2
(tmp) ← ((SP))
(SP) ← (SP) + 2
(op1) ← (tmp)
Description
Returns from a subroutine. First the IP is popped from the system stack and then the
next word is popped from the system stack into the operand specified by op1.
CPU Flags
E
*
E
Z
V
C
N
Z
*
V
-
C
-
N
*
Set if the value of the popped word represents the lowest possible
negative number. Cleared otherwise. Used to signal the end of a table.
Set if the value of the popped word equals zero. Cleared otherwise.
Not affected.
Not affected.
Set if the most significant bit of the popped word is set. Cleared
otherwise.
Encoding
Mnemonic
RETP
User’s Manual
reg
Format
EB RR
6-79
Bytes
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
RETS
Return from Inter-Segment Subroutine
Group
Return Instructions
Syntax
RETS
Source Operand(s)
none
Destination Operand(s)
none
RETS
Operation
(IP) ← ((SP))
(SP) ← (SP) + 2
(CSP) ← ((SP))
(SP) ← (SP) + 2
Description
Returns from an inter-segment subroutine. The IP and CSP are popped from the
system stack.
CPU Flags
E
E
Z
V
C
N
Z
-
V
-
C
-
N
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Encoding
Mnemonic
RETS
User’s Manual
Format
DB 00
6-80
Bytes
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
ROL
ROL
Rotate Left
Group
Shift and Rotate Instructions
Syntax
ROL op1, op2
Source Operand(s)
op1 → WORD
op2 → shift counter
Destination Operand(s)
op1 → WORD
Operation
(count) ← (op2)
(C) ← 0
DO WHILE ((count) ≠ 0)
(C) ← (op1[15])
(op1[n]) ← (op1[n-1]) [n=15...1]
(op1[0]) ← (C)
(count) ← (count) - 1
END WHILE
Description
Rotates the destination word operand op1 the number of times as specified by the
source operand op2. Bit 15 is rotated into Bit 0 and into the Carry. Only shift values
between 0 and 15 are allowed. When using a GPR as the count control, only the least
significant 4 bits are used.
CPU Flags
E
0
E
Z
V
C
N
User’s Manual
Z
*
V
0
C
S
N
*
Always cleared.
Set if result equals zero. Cleared otherwise.
Always cleared.
The carry flag is set according to the last most significant bit shifted out of
op1. Cleared for a shift count of zero.
Set if the most significant bit of the result is set. Cleared otherwise.
6-81
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
Encoding
Mnemonic
ROL
ROL
User’s Manual
Rwn , #data4
Rwn , Rwm
Format
1C #n
0C nm
6-82
Bytes
2
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
ROR
ROR
Rotate Right
Group
Shift and Rotate Instructions
Syntax
ROR op1, op2
Source Operand(s)
op1 → WORD
op2 → shift counter
Destination Operand(s)
op1 → WORD
Operation
(count) ← (op2)
(C) ← 0
(V) ← 0
DO WHILE ((count) ≠ 0)
(V) ← (V) ∨ (C)
(C) ← (op1[0])
(op1[n]) ← (op1[n+1]) [n=0...14]
(op1[15]) ← (C)
(count) ← (count) - 1
END WHILE
Description
Rotates the destination word operand op1 right by the number of times as specified by
the source operand op2. Bit 0 is rotated into Bit 15 and into the Carry. Only shift values
between 0 and 15 are allowed. When using a GPR as the count control, only the least
significant 4 bits are used.
CPU Flags
E
0
E
Z
V
C
N
User’s Manual
Z
*
V
S
C
S
N
*
Always cleared.
Set if result equals zero. Cleared otherwise.
Set if in any cycle of the rotate operation a 1 is shifted out of the carry
flag. Cleared for a rotate count of zero.
The carry flag is set according to the last least significant bit shifted out of
op1. Cleared for a shift count of zero.
Set if the most significant bit of the result is set. Cleared otherwise.
6-83
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
Encoding
Mnemonic
ROR
ROR
User’s Manual
Rwn , #data4
Rwn , Rwm
Format
3C #n
2C nm
6-84
Bytes
2
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
SCXT
SCXT
Switch Context
Group
System Stack Instructions
Syntax
SCXT op1, op2
Source Operand(s)
op1, op2 → WORD
Destination Operand(s)
op1 → WORD
Operation
(tmp1) ← (op1)
(tmp2) ← (op2)
(SP) ← (SP) - 2
((SP)) ← (tmp1)
(op1) ← (tmp2)
Description
Switches contexts of any register. Switching context is a push and load operation. The
contents of the register specified by the first operand op1, are pushed onto the stack.
That register is then loaded with the value specified by the second operand, op2.
CPU Flags
E
E
Z
V
C
N
Z
-
V
-
C
-
N
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Encoding
Mnemonic
SCXT
SCXT
User’s Manual
reg , #data16
reg , mem
Format
C6 RR ## ##
D6 RR MM MM
6-85
Bytes
4
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
SHL
SHL
Shift Left
Group
Shift and Rotate Instructions
Syntax
SHL op1, op2
Source Operand(s)
op1 → WORD
op2 → shift counter
Destination Operand(s)
op1 → WORD
Operation
(count) ← (op2)
(C) ← 0
DO WHILE ((count) ≠ 0)
(C) ← (op1[15])
(op1[n]) ← (op1[n-1]) [n=15...1]
(op1[0]) ← 0
(count) ← (count) - 1
END WHILE
Description
Shifts the destination word operand op1 the number of times as specified by the source
operand op2. The least significant bits of the result are filled with zeros accordingly. The
least The most significant bit is shifted into the Carry. Only shift values between 0 and
15 are allowed. When using a GPR as the count control, only the least significant 4 bits
are used.
CPU Flags
E
0
E
Z
V
C
N
User’s Manual
Z
*
V
0
C
S
N
*
Always cleared.
Set if result equals zero. Cleared otherwise.
Always cleared.
The carry flag is set according to the last most significant bit shifted out of
op1. Cleared for a shift count of zero.
Set if the most significant bit of the result is set. Cleared otherwise.
6-86
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
Encoding
Mnemonic
SHL
SHL
User’s Manual
Rwn , #data4
Rwn , Rwm
Format
5C #n
4C nm
6-87
Bytes
2
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
SHR
SHR
Shift Right
Group
Shift and Rotate Instructions
Syntax
SHR op1, op2
Source Operand(s)
op1 → WORD
op2 → shift counter
Destination Operand(s)
op1 → WORD
Operation
(count) ← (op2)
(C) ← 0
(V) ← 0
DO WHILE ((count) ≠ 0)
(V) ← (C) ∨ (V)
(C) ← (op1[0])
(op1[n]) ← (op1[n+1]) [n=0...14]
(op1[15]) ← 0
(count) ← (count) - 1
END WHILE
Description
Shifts the destination word operand op1 right by the number of times as specified by the
source operand op2. The most significant bits of the result are filled with zeros
accordingly. Since the bits shifted out effectively represent the remainder, the Overflow
flag is used instead as a Rounding flag. A shift right is a division by a power of two. The
overflow flag with the carry flag allows to determine whether the fractional part of the
division result is greater than, less than or equal to one half (0.5 in decimal base). This
allows to round the division result accordingly. Only shift values between 0 and 15 are
allowed. When using a GPR as the count control, only the least significant 4 bits are
used.
CPU Flags
E
0
E
Z
V
User’s Manual
Z
*
V
S
C
S
N
*
Always cleared.
Set if result equals zero. Cleared otherwise.
Set if in any cycle of the shift operation a 1 is shifted out of the carry flag.
Cleared in case of a shift count equal 0.
6-88
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
C
N
The carry flag is set according to the last least significant bit shifted out of
op1. Cleared for a shift count of zero.
Set if the most significant bit of the result is set. Cleared otherwise.
Encoding
Mnemonic
SHR
SHR
User’s Manual
Rwn , #data4
Rwn , Rwm
Format
7C #n
6C nm
6-89
Bytes
2
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
SRST
SRST
Software Reset
Group
System Control Instructions
Syntax
SRST
Source Operand(s)
none
Destination Operand(s)
none
Operation
Software Reset
Description
This instruction is used to perform a software reset. A software reset has the same
effect on the microcontroller as an externally applied hardware reset. To insure that this
instruction is not accidentally executed, it is implemented as a protected instruction.
CPU Flags
E
0
E
Z
V
C
N
Z
0
V
0
C
0
N
0
Always cleared.
Always cleared.
Always cleared.
Always cleared.
Always cleared.
Encoding
Mnemonic
SRST
User’s Manual
Format
B7 48 B7 B7
6-90
Bytes
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
SRVWDT
SRVWDT
Service Watchdog Timer
Group
System Control Instructions
Syntax
SRVWDT
Source Operand(s)
none
Destination Operand(s)
none
Operation
Service Watchdog Timer
Description
This instruction reloads the high order byte of the Watchdog Timer with a preset value
and clears the low byte. Once this instruction has been executed, the watchdog timer
cannot be disabled. To insure that this instruction is not accidentally executed, it is
implemented as a protected instruction.
CPU Flags
E
E
Z
V
C
N
Z
-
V
-
C
-
N
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Encoding
Mnemonic
SRVWDT
User’s Manual
Format
A7 58 A7 A7
6-91
Bytes
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
SUB
SUB
Integer Subtraction
Group
Arithmetic Instructions
Syntax
SUB op1, op2
Source Operand(s)
op1, op2 → WORD
Destination Operand(s)
op1 → WORD
Operation
(op1) ← (op1) - (op2)
Description
Performs a 2’s complement binary subtraction of the source operand specified by op2
and the destination operand specified by op1. The result is then stored in op1.
CPU Flags
E
*
E
Z
V
C
N
Z
*
V
*
C
S
N
*
Set if the value of op2 represents the lowest possible negative number.
Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Set if an arithmetic underflow occurred, i.e. the result cannot be
represented in the word data type. Cleared otherwise.
Set if a borrow is generated. Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
Encoding
Mnemonic
SUB
SUB
SUB
SUB
SUB
SUB
SUB
User’s Manual
Rwn , #data3
Rwn , Rwm
Rwn , [Rwi+]
Rwn , [Rwi]
mem , reg
reg , #data16
reg , mem
Format
28 n:0###
20 nm
28 n:11ii
28 n:10ii
24 RR MM MM
26 RR ## ##
22 RR MM MM
6-92
Bytes
2
2
2
2
4
4
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
SUBB
SUBB
Integer Subtraction
Group
Arithmetic Instructions
Syntax
SUBB op1, op2
Source Operand(s)
op1, op2 → BYTE
Destination Operand(s)
op1 → BYTE
Operation
(op1) ← (op1) - (op2)
Description
Performs a 2’s complement binary subtraction of the source operand specified by op2
and the destination operand specified by op1. The result is then stored in op1.
CPU Flags
E
*
E
Z
V
C
N
Z
*
V
*
C
S
N
*
Set if the value of op2 represents the lowest possible negative number.
Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Set if an arithmetic underflow occurred, i.e. the result cannot be
represented in the word data type. Cleared otherwise.
Set if a borrow is generated. Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
Encoding
Mnemonic
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
User’s Manual
Rbn , #data3
Rbn , Rbm
Rbn , [Rwi+]
Rbn , [Rwi]
mem , reg
reg , #data8
reg , mem
Format
29 n:0###
21 nm
29 n:11ii
29 n:10ii
25 RR MM MM
27 RR ## xx
23 RR MM MM
6-93
Bytes
2
2
2
2
4
4
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
SUBC
SUBC
Integer Subtraction with Carry
Group
Arithmetic Instructions
Syntax
SUBC op1, op2
Source Operand(s)
op1, op2 → WORD
Destination Operand(s)
op1 → WORD
Operation
(op1) ← (op1) - (op2) - (C)
Description
Performs a 2’s complement binary subtraction of the source operand specified by op2
and the previously generated carry bit from the destination operand specified by op1.
The result is then stored in op1. This instruction can be used to perform multiple
precision arithmetic.
CPU Flags
E
*
E
Z
V
C
N
Z
S
V
*
C
S
N
*
Set if the value of op2 represents the lowest possible negative number.
Cleared otherwise. Used to signal the end of a table.
Set if result equals zero and previous Z flag was set. Cleared otherwise.
Set if an arithmetic underflow occurred, i.e. the result cannot be
represented in the word data type. Cleared otherwise.
Set if a borrow is generated. Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
Encoding
Mnemonic
SUBC
SUBC
SUBC
SUBC
SUBC
SUBC
SUBC
User’s Manual
Rwn , #data3
Rwn , Rwm
Rwn , [Rwi+]
Rwn , [Rwi]
mem , reg
reg , #data16
reg , mem
Format
38 n:0###
30 nm
38 n:11ii
38 n:10ii
34 RR MM MM
36 RR ## ##
32 RR MM MM
6-94
Bytes
2
2
2
2
4
4
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
SUBCB
SUBCB
Integer Subtraction with Carry
Group
Arithmetic Instructions
Syntax
SUBCB op1, op2
Source Operand(s)
op1, op2 → BYTE
Destination Operand(s)
op1 → BYTE
Operation
(op1) ← (op1) - (op2) - (C)
Description
Performs a 2’s complement binary subtraction of the source operand specified by op2
and the previously generated carry bit from the destination operand specified by op1.
The result is then stored in op1. This instruction can be used to perform multiple
precision arithmetic.
CPU Flags
E
*
E
Z
V
C
N
Z
S
V
*
C
S
N
*
Set if the value of op2 represents the lowest possible negative number.
Cleared otherwise. Used to signal the end of a table.
Set if result equals zero and the previous Z flag was set. Cleared
otherwise.
Set if an arithmetic underflow occurred, i.e. the result cannot be
represented in the word data type. Cleared otherwise.
Set if a borrow is generated. Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
Encoding
Mnemonic
SUBCB
SUBCB
SUBCB
SUBCB
SUBCB
SUBCB
SUBCB
User’s Manual
Rbn , #data3
Rbn , Rbm
Rbn , [Rwi+]
Rbn , [Rwi]
mem , reg
reg , #data8
reg , mem
Format
39 n:0###
31 nm
39 n:11ii
39 n:10ii
35 RR MM MM
37 RR ## xx
33 RR MM MM
6-95
Bytes
2
2
2
2
4
4
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
TRAP
TRAP
Software Trap
Group
Call Instructions
Syntax
TRAP op1
Source Operand(s)
op1 → 7-bit trap number
Destination Operand(s)
none
Operation
(SP) ← (SP) - 2
((SP) ← (PSW)
IF (SYSCON.SGTDIS = 0) THEN
(SP) ← (SP) - 2
((SP)) ← (CSP)
(CSP) ← (0)
END IF
(SP) ← (SP) - 2
((SP)) ← (IP)
(IP) ← zero_extended((op1) * 4)
Description
Invokes a trap or interrupt routine based on the specified operand op1. The invoked
routine is determined by branching to the specified vector table entry point. This routine
has no indication of whether it was called by software or hardware. System state is
preserved identically to hardware interrupt entry except that the CPU priority level is not
affected. The RETI, Return from Interrupt instruction is used to resume execution after
the completion of the trap or interrupt routine. The CSP is pushed if the segmentation is
enabled. This is indicated by the SGTDIS bit of the SYSCON register.
CPU Flags
E
E
Z
V
C
N
User’s Manual
Z
-
V
-
C
-
N
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
6-96
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
Encoding
Mnemonic
TRAP
User’s Manual
#trap7
Format
9B t:ttt0
6-97
Bytes
2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
XOR
XOR
Logical Exclusive OR
Group
Logical Instructions
Syntax
XOR op1, op2
Source Operand(s)
op1, op2 → WORD
Destination Operand(s)
op1 → WORD
Operation
(op1) ← (op1) ⊕ (op2)
Description
Performs a bitwise logical EXCLUSIVE OR of the source operand specified by op2 and
the destination operand specified by op1. The result is then stored in op1.
CPU Flags
E
*
E
Z
V
C
N
Z
*
V
0
C
0
N
*
Set if the value of op2 represents the lowest possible negative number.
Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Always cleared.
Always cleared.
Set if the most significant bit of the result is set. Cleared otherwise.
Encoding
Mnemonic
XOR
XOR
XOR
XOR
XOR
XOR
XOR
User’s Manual
Rwn , #data3
Rwn , Rwm
Rwn , [Rwi+]
Rwn , [Rwi]
mem , reg
reg , #data16
reg , mem
Format
58 n:0###
50 nm
58 n:11ii
58 n:10ii
54 RR MM MM
56 RR ## ##
52 RR MM MM
6-98
Bytes
2
2
2
2
4
4
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
XORB
XORB
Logical Exclusive OR
Group
Logical Instructions
Syntax
XORB op1, op2
Source Operand(s)
op1, op2 → BYTE
Destination Operand(s)
op1 → BYTE
Operation
(op1) ← (op1) ⊕ (op2)
Description
Performs a bitwise logical EXCLUSIVE OR of the source operand specified by op2 and
the destination operand specified by op1. The result is then stored in op1.
CPU Flags
E
*
E
Z
V
C
N
Z
*
V
0
C
0
N
*
Set if the value of op2 represents the lowest possible negative number.
Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Always cleared.
Always cleared.
Set if the most significant bit of the result is set. Cleared otherwise.
Encoding
Mnemonic
XORB
XORB
XORB
XORB
XORB
XORB
XORB
User’s Manual
Rbn , #data3
Rbn , Rbm
Rbn , [Rwi+]
Rbn , [Rwi]
mem , reg
reg , #data8
reg , mem
Format
59 n:0###
51 nm
59 n:11ii
59 n:10ii
55 RR MM MM
57 RR ## xx
53 RR MM MM
6-99
Bytes
2
2
2
2
4
4
4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Detailed Instruction Set
User’s Manual
6-100
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Parallel Ports
7
Parallel Ports
In order to accept or generate single external control signals or parallel data, the C166S
s provides up to 48 parallel IO lines organized into six 8-bit IO ports (PORT0 made of
P0H and P0L, PORT1 made of P1H and P1L, Port 4, Port 6).
These port lines may be used for general purpose Input/Output controlled via software
or may be used implicitly by the C166S V1 SubS R1’s integrated peripherals or the
External Bus Controller.
All port lines are bit addressable, and all input/output lines are individually (bit-wise)
programmable as inputs or outputs via direction registers. The IO ports are true
bidirectional ports which are switched to high impedance state when configured as
inputs.
The logic level of a pin is clocked into the input latch once per state time, regardless
whether the port is configured for input or output.
Data Input / Output
Registers
Data Input / Output
Registers
Direction Control
Registers
Direction Control
Registers
P0L
DP0L
E
P1L
DP1L
E
P0H
DP0H
E
P1H
DP1H
E
P4
DP4
P6
DP6
Figure 7-1
SFRs associated with the Parallel Ports
A write operation to a port pin configured as an input causes the value to be written into
the port output register, while a read operation returns the registered state of the pin
itself. A read-modify-write operation reads the value of the pin, modifies it, and writes it
back to the output register.
Writing to a pin configured as an output (DPx.y=‘1’) causes the output register and the
pin to have the written value, since the output buffer is enabled. Reading this pin returns
the value of the output register. A read-modify-write operation reads the value of the
output register, modifies it, and writes it back to the output register, thus also modifying
the level at the pin.
User’s Manual
7-1
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Parallel Ports
7.1
Alternate Port Functions
In order to provide a maximum of flexibility for different applications and their specific IO
requirements port lines have programmable alternate input or output functions
associated with them.
Table 7-1
Port
Summary of Alternate Port Functions
Alternate Function(s)
Alternate Signal(s)
PORT0 Address and data lines when accessing
external resources (e.g. memory)
AD15 ... AD0
PORT1 Address lines when accessing ext. resources
A15 ... A0,
Port 4
Selected segment address lines in systems
A23 ... A16
with more than 64 KBytes of external resources
Port 6
Chip select output signals
CS4 ... CS0
If an alternate output function of a pin is to be used, the direction of this pin must be
programmed for output (DPx.y=‘1’), except for some signals that are used directly after
reset and are configured automatically. Otherwise the pin remains in the high-impedance
state and is not effected by the alternate output function. The respective port register
should hold a ‘1’, because its output is combined with the alternate output data.
If an alternate input function of a pin is used, the direction of the pin must be
programmed for input (DPx.y=‘0’) if an external device is driving the pin. The input
direction is the default after reset. If no external device is connected to the pin, however,
one can also set the direction for this pin to output. In this case, the pin reflects the state
of the port output register. Thus, the alternate input function reads the value stored in the
port output register. This can be used for testing purposes to allow a software trigger of
an alternate input function by writing to the port output register.
On most of the port lines, the user software is responsible for setting the proper direction
when using an alternate input or output function of a pin. This is done by setting or
clearing the direction control bit DPx.y of the pin before enabling the alternate function.
There are port lines, however, where the direction of the port line is switched
automatically. For instance, in the multiplexed external bus modes of PORT0, the
direction must be switched several times for an instruction fetch in order to output the
addresses and to input the data. Obviously, this cannot be done through instructions. In
these cases, the direction of the port line is switched automatically by hardware if the
alternate function of such a pin is enabled.
To determine the appropriate level of the port output registers check how the alternate
data output is combined with the respective port register output.
There is one basic structure for all port lines with only an alternate input function. Port
lines with only an alternate output function, however, have different structures due to the
User’s Manual
7-2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Parallel Ports
way the direction of the pin is switched and depending on whether the pin is accessible
by the user software or not in the alternate function mode.
All port lines that are not used for these alternate functions may be used as general
purpose IO lines. When using port pins for general purpose output, the initial output
value should be written to the port register prior to enabling the output drivers, in order
to avoid undesired transitions on the output pins. This applies to single pins as well as
to pin groups (see examples below).
OUTPUT_ENABLE_SINGLE_PIN:
BSET
P4.0
BSET
DP4.0
;Initial output level is ’high’
;Switch on the output driver
OUTPUT_ENABLE_PIN_GROUP:
BFLDL
P4, #05H, #05H
BFLDL
DP4, #05H, #05H
;Initial output level is ’high’
;Switch on the output drivers
Note: When using several BSET pairs to control more pins of one port, these pairs must
be separated by instructions, which do not reference the respective port (see
Section 3.8.1 “Particular Pipeline Effects” in chapter “The Central Processing
Unit”).
Each of these ports and the alternate input and output functions are described in detail
in the following subsections.
7.2
PORT0
The two 8-bit ports P0H and P0L represent the higher and lower part of PORT0,
respectively. Both halfs of PORT0 can be written (e.g. via a PEC transfer) without
effecting the other half.
If this port is used for general purpose IO, the direction of each line can be configured
via the corresponding direction registers DP0H and DP0L.
P0L
PORT0 Low Register
15
14
13
12
SFR (FF00H/80H
11
10
9
8
7
6
Reset value: - - 00H
5
4
3
2
1
0
P0L P0L P0L P0L P0L P0L P0L P0L
.7
.6
.5
.4
.3
.2
.1
.0
-
-
User’s Manual
-
-
-
-
-
-
rw
7-3
rw
rw
rw
rw
rw
rw
rw
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Parallel Ports
P0H
PORT0 High Register
15
14
13
12
SFR (FF02H/81H)
11
10
9
8
7
6
Reset value: - - 00H
5
4
3
2
1
0
P0H P0H P0H P0H P0H P0H P0H P0H
.7
.6
.5
.4
.3
.2
.1
.0
-
-
-
-
-
-
-
-
rw
rw
Bit
Function
P0X.y
Port data register P0H or P0L bit y
DP0L
P0L Direction Ctrl. Register
15
14
13
12
11
rw
rw
ESFR (F100H/80H)
10
9
8
7
6
rw
rw
rw
rw
Reset value: - - 00H
5
4
3
2
1
0
DP0L DP0L DP0L DP0L DP0L DP0L DP0L DP0L
.7
.6
.5
.4
.3
.2
.1
.0
-
-
-
-
-
-
DP0H
P0H Direction Ctrl. Register
15
14
13
12
11
10
-
-
rw
rw
rw
rw
ESFR (F102H/81H)
9
8
7
6
rw
rw
rw
rw
Reset Value: - - 00H
5
4
3
2
1
0
DP0H DP0H DP0H DP0H DP0H DP0H DP0H DP0H
.7
.6
.5
.4
.3
.2
.1
.0
-
-
-
-
-
-
-
-
rw
rw
rw
rw
rw
Bit
Function
DP0X.y
Port direction register DP0H or DP0L bit y
DP0X.y = 0: Port line P0X.y is an input (high-impedance)
DP0X.y = 1: Port line P0X.y is an output
rw
rw
rw
Alternate Functions of PORT0
When an external bus is enabled, PORT0 is used as data bus or address/data bus.
Note that an external 8-bit demultiplexed bus only uses P0L, while P0H is free for IO
(provided that no other bus mode is enabled).
During external accesses in multiplexed bus modes PORT0 first outputs the 16-bit intrasegment address as an alternate output function. PORT0 is then switched to highimpedance input mode to read the incoming instruction or data. In 8-bit data bus mode,
two memory cycles are required for word accesses, the first for the low byte and the
second for the high byte of the word. During write cycles PORT0 outputs the data byte
or word after outputting the address.
User’s Manual
7-4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Parallel Ports
During external accesses in demultiplexed bus modes PORT0 reads the incoming
instruction or data word or outputs the data byte or word.
Alternate Function
a)
b)
P0H.7
P0H.6
P0H.5
P0H.4
P0H.3
P0H.2
P0H.1
P0H.0
P0L.7
P0L.6
P0L.5
P0L.4
P0L.3
P0L.2
P0L.1
P0L.0
D7
D6
D5
D4
D3
D2
D1
D0
General Purpose
Input/Output
8-bit
Demux Bus
P0H
PORT0
P0L
Figure 7-2
c)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit
Demux Bus
d)
A15
A14
A13
A12
A11
A10
A9
A8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
8-bit
MUX Bus
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
16-bit
MUX Bus
PORT0 IO and Alternate Functions
When an external bus mode is enabled, the direction of the port pin and the loading of
data into the port output latch are controlled by the bus controller hardware. The input of
the port output latch is disconnected from the internal bus and is switched to the line
labeled “Alternate Data Output” via a multiplexer. The alternate data can be the 16-bit
intrasegment address or the 8/16-bit data information. The incoming data on PORT0 is
read on the line “Alternate Data Input”. While an external bus mode is enabled, the user
software should not write to the port output latch, otherwise unpredictable results may
occur. When the external bus modes are disabled, the contents of the direction register
last written by the user becomes active.
User’s Manual
7-5
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Parallel Ports
The figure below shows the structure of a PORT0 pin.
Port Output
Register
Read
Write
Read
Write
Internal Bus
Direction
Register
0
1
0
AltDir
1
AltEN
0
AltDataOut
1
Driver
Pin
Clock
Input
Register
Port0_1.vsd
AltDataIn
P0H.7-0, P0L.7-0
Figure 7-3
User’s Manual
Block Diagram of a PORT0 Pin
7-6
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Parallel Ports
7.3
PORT1
The two 8-bit ports P1H and P1L represent the higher and lower part of PORT1,
respectively. Both halfs of PORT1 can be written (e.g. via a PEC transfer) without
effecting the other half.
If this port is used for general purpose IO, the direction of each line can be configured
via the corresponding direction registers DP1H and DP1L.
P1L
PORT1 Low Register
15
14
13
12
SFR (FF04H/82H)
11
10
9
8
7
6
Reset Value: - - 00H
5
4
3
2
1
0
P1L P1L P1L P1L P1L P1L P1L P1L
.7
6
.5
.4
.3
.2
.1
.0
-
-
-
-
-
-
P1H
PORT1 High Register
15
14
13
12
-
-
rw
rw
rw
rw
SFR (FF06H/83H)
11
10
9
8
7
6
rw
rw
rw
rw
Reset Value: - - 00H
5
4
3
2
1
0
P1H P1H P1H P1H P1H P1H P1H P1H
.7
.6
.5
.4
.3
.2
.1
.0
-
-
-
-
-
-
-
-
rw
rw
Bit
Function
P1X.y
Port data register P1H or P1L bit y
DP1L
P1L Direction Ctrl. Register
15
14
13
12
11
rw
rw
ESFR (F104H/82H)
10
9
8
7
6
rw
rw
rw
rw
Reset Value: - - 00H
5
4
3
2
1
0
DP1 DP1 DP1 DP1 DP1 DP1 DP1 DP1
L.7 L.6 L.5 L.4 L.3 L.2 L.1 L.0
-
-
-
-
-
-
DP1H
P1H Direction Ctrl. Register
15
14
13
12
11
10
-
-
rw
rw
rw
rw
ESFR (F106H/83H)
9
8
7
6
rw
rw
rw
rw
Reset Value: - - 00H
5
4
3
2
1
0
DP1 DP1 DP1 DP1 DP1 DP1 DP1 DP1
H.7 H.6 H.5 H.4 H.3 H.2 H.1 H.0
-
-
User’s Manual
-
-
-
-
-
-
rw
7-7
rw
rw
rw
rw
rw
rw
rw
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Parallel Ports
Bit
Function
DP1X.y
Port direction register DP1H or DP1L bit y
DP1X.y = 0: Port line P1X.y is an input (high-impedance)
DP1X.y = 1: Port line P1X.y is an output
Alternate Functions of PORT1
When a demultiplexed external bus is enabled, PORT1 is used as address bus.
Note that demultiplexed bus modes use PORT1 as a 16-bit port. Otherwise all 16 port
lines can be used for general purpose IO.
Alternate Function
P1H
PORT1
P1L
P1H.7
P1H.6
P1H.5
P1H.4
P1H.3
P1H.2
P1H.1
P1H.0
P1L.7
P1L.6
P1L.5
P1L.4
P1L.3
P1L.2
P1L.1
P1L.0
General Purpose
Input/Output
Figure 7-4
a)
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
8/16-bit
Demux Bus
PORT1 IO and Alternate Functions
During external accesses in demultiplexed bus modes PORT1 outputs the 16-bit intrasegment address as an alternate output function.
During external accesses in multiplexed bus modes, when no BUSCON register selects
a demultiplexed bus mode, PORT1 is not used and is available for general purpose IO.
When an external bus mode is enabled, the direction of the port pin and the loading of
data into the port output register are controlled by the bus controller hardware. The input
of the port output register is disconnected from the internal bus and is switched to the
line labeled “Alternate Data Output” via a multiplexer. The alternate data is the 16-bit
intrasegment address. While an external bus mode is enabled, the user software should
not write to the port output register, otherwise unpredictable results may occur. When the
external bus modes are disabled, the contents of the direction register last written by the
user becomes active.
User’s Manual
7-8
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Parallel Ports
The figures below show the structure of PORT1 pins. The upper 4 pins of PORT1
combine internal bus data and alternate data output before the port register input.
Port Output
Register
Read
Write
Read
Write
Internal Bus
Direction
Register
0
1
0
AltDir = ’1’
1
AltEN
0
AltDataOut
1
Driver
Pin
Input
Register
Figure 7-5
User’s Manual
Port1_1.vsd
Clock
Block Diagram of a PORT1 Pin with Address Function
7-9
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Parallel Ports
7.4
Port 4
If this 8-bit port is used for general purpose IO, the direction of each line can be
configured via the corresponding direction register DP4.
P4
3RUW'DWD5HJLVWHU
15
14
13
12
SFR (FFC8H/E4H)
11
10
9
8
7
6
Reset Value: - - 00H
5
4
3
2
1
0
P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0
-
-
-
-
-
-
-
-
rw
Bit
Function
P4.y
Port data register P4 bit y
DP4
P4 Direction Ctrl. Register
15
14
13
12
11
rw
rw
rw
SFR (FFCAH/E5H)
10
9
8
7
6
rw
rw
rw
rw
Reset Value: - - 00H
5
4
3
2
1
0
DP4 DP4 DP4 DP4 DP4 DP4 DP4 DP4
.7
.6
.5
.4
.3
.2
.1
.0
-
-
-
-
-
-
-
-
rw
rw
rw
rw
rw
Bit
Function
DP4.y
Port direction register DP4 bit y
DP4.y = 0: Port line P4.y is an input (high-impedance)
DP4.y = 1: Port line P4.y is an output
rw
rw
rw
Alternate Functions of Port 4
During external bus cycles that use segmentation (i.e. an address space above
64 KByte) a number of Port 4 pins may output the segment address lines. The number
of pins that is used for segment address output determines the external address space
which is directly accessible. The other pins of Port 4 (if any) may be used for general
purpose IO.
If segment address lines are selected, the alternate function of Port 4 may be necessary
to access e.g. external memory directly after reset. For this reason Port 4 will be
switched to this alternate function automatically.
The number of segment address lines is selected via conf_rst_salsel_i[1:0] (SALSEL)
during reset.
User’s Manual
7-10
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Parallel Ports
The table below summarizes the alternate functions of Port 4 depending on the number
of selected segment address lines.
Table 7-2
Alternate Functions of Port 4
Port 4 Std. Function
Pin
SALSEL=01
64 KB
Altern. Function
SALSEL=11
256KB
Altern. Function
SALSEL=00
1 MB
Altern. Function
SALSEL=10
16 MB
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
Seg. Address A16
Seg. Address A17
Gen. purpose IO
Gen. purpose IO
Gen. purpose IO
Gen. purpose IO
Gen. purpose IO
Gen. purpose IO
Seg. Address A16
Seg. Address A17
Seg. Address A18
Seg. Address A19
Gen. purpose IO
Gen. purpose IO
Gen. purpose IO
Gen. purpose IO
Seg. Address A16
Seg. Address A17
Seg. Address A18
Seg. Address A19
Seg. Address A20
Seg. Address A21
Seg. Address A22
Seg. Address A23
Gen. purpose IO
Gen. purpose IO
Gen. purpose IO
Gen. purpose IO
Gen. purpose IO
Gen. purpose IO
Gen. purpose IO
Gen. purpose IO
Note: Port 4 pins that are not used for segment address output may be used for general
purpose IO.
Alternate Function
Port 4
P4.7
P4.6
P4.5
P4.4
P4.3
P4.2
P4.1
P4.0
General Purpose
Input/Output
Figure 7-6
User’s Manual
a)
A23
A22
A21
A20
A19
A18
A17
A16
Full Segment
Address (16 MB)
Port 4 IO and Alternate Functions
7-11
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Parallel Ports
Port Output
Register
Read
Write
Read
Write
Internal Bus
Direction
Register
0
1
0
AltDir = ’1’
1
AltEN
0
AltDataOut
1
Driver
Pin
Clock
Input
Register
Port4_1.vsd
AltDataIn
P4.7-0
Figure 7-7
User’s Manual
Block Diagram of a Port 4 Pin
7-12
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Parallel Ports
7.5
Port 6
If this 8-bit port is used for general purpose IO, the direction of each line can be
configured via the corresponding direction register DP6.
P6
3RUW'DWD5HJLVWHU
15
14
13
12
SFR (FFCCH/E6H)
11
10
9
8
7
6
Reset Value: - - 00H
5
4
3
2
1
0
P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0
-
-
-
-
-
-
-
-
rw
Bit
Function
P6.y
Port data register P6 bit y
DP6
P6 Direction Ctrl. Register
15
14
13
12
11
rw
rw
rw
SFR (FFCEH/E7H)
10
9
8
7
6
rw
rw
rw
rw
Reset Value: - - 00H
5
4
3
2
1
0
DP6 DP6 DP6 DP6 DP6 DP6 DP6 DP6
.7
.6
.5
.4
.3
.2
.1
.0
-
-
-
-
-
-
-
-
rw
rw
rw
rw
rw
Bit
Function
DP6.y
Port direction register DP6 bit y
DP6.y = 0: Port line P6.y is an input (high-impedance)
DP6.y = 1: Port line P6.y is an output
rw
rw
rw
Alternate Functions of Port 6
A programmable number of chip select signals (CS4...CS0) derived from the bus control
registers (BUSCON4...BUSCON0) can be output on 5 pins of Port 6. The number of chip
select signals is selected via conf_rst_cssel_i[1:0] (CSSEL) during reset.
User’s Manual
7-13
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Parallel Ports
The table below summarizes the alternate functions of Port 6 depending on the number
of selected chip select lines (coded via bitfield CSSEL).
Table 7-3
Alternate Functions of Port 6
Port 6 Pin Altern. Function Altern. Function Altern. Function Altern. Function
CSSEL = 10
CSSEL = 01
CSSEL = 00
CSSEL = 11
Gen. purpose IO
Gen. purpose IO
Gen. purpose IO
Gen. purpose IO
Gen. purpose IO
Gen. purpose IO
Gen. purpose IO
Gen. purpose IO
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
Alternate Function
Port 6
Chip select CS0
Chip select CS1
Gen. purpose IO
Gen. purpose IO
Gen. purpose IO
Gen. purpose IO
Gen. purpose IO
Gen. purpose IO
Chip select CS0
Chip select CS1
Chip select CS2
Gen. purpose IO
Gen. purpose IO
Gen. purpose IO
Gen. purpose IO
Gen. purpose IO
Chip select CS0
Chip select CS1
Chip select CS2
Chip select CS3
Chip select CS4
Gen. purpose IO
Gen. purpose IO
Gen. purpose IO
a)
P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
P6.0
P6.7
P6.6
P6.5
CS4
CS3
CS2
CS1
CS0
General Purpose
Input/Output
Figure 7-8
Port 6 IO and Alternate Functions
Note: The chip select lines of Port 6 should have (product specific) an internal weak pullup device.This device should be switched on during reset for all potential CS
output pins. This feature should be implemented to drive the chip select lines high
during reset in order to avoid multiple chip selection.
After reset the CS function must be used, if selected so. In this case there is no possibility
to program any port registers before. Thus the alternate function (CS) is selected
automatically in this case.
User’s Manual
7-14
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Parallel Ports
Port Output
Register
Read
Write
Read
Write
Internal Bus
Direction
Register
0
1
0
AltDir = ’1’
1
AltEN
0
AltDataOut
1
Pin
Driver
Clock
Port6_1.vsd
AltDataIn
Input
Register
P6.4-0
Figure 7-9
User’s Manual
Block Diagram of Port 6 Pins with an alternate output function
7-15
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Parallel Ports
Port Output
Register
Read
Write
Read
Write
Internal Bus
Direction
Register
0
1
Driver
Pin
Input
Register
Port6_2.vsd
Clock
P6.7-5
Figure 7-10 Block Diagram of Port 6 Pins without an alternate output function
User’s Manual
7-16
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
8
The External Bus Interface
Although the C166S subsystem supports a powerful set of on-chip peripherals and onchip RAM and ROM/OTP/Flash areas, these internal units cover only a small fraction of
the chip’s address space (up to 16 MBytes). The external bus interface allows access to
external peripherals and additional volatile and non-volatile memory. The external bus
interface has a number of possible configurations, so it can be tailored to fit perfectly into
a given application system.
Ports & Direction Control
Alternate Functions
Address Registers
Mode Registers
P0L / P0H
BUSCON0
SYSCON
RP0H
P1L / P1H
ADDRSEL1
BUSCON1
DP3
ADDRSEL2
BUSCON2
P3
ADDRSEL3
BUSCON3
ODP4E
ADDRSEL4
BUSCON4
P4
ODP6E
DP6
P6
P0L/P0H
P1L/P1H
DP3
P3
ODP4
P4
A[23:0]
D[15:0]
ALE
RD
WR/WRL
BHE/WRH
PORT0 Data Registers
PORT1 Data Registers
Port 3 Direction Control Register
Port 3 Data Register
Port 4 Open Drain Control Register
Port 4 Data Register
Figure 8-1
EA
RSTIN
READY
Control Registers
BREQ
HLDA
HOLD
CS[4:0]
ODP6
Port 6 Open Drain Control Register
DP6
Port 6 Direction Control Register
P6
Port 6 Data Register
ADDRSELx Address Range Select Register 1...4
BUSCONx Bus Mode Control Register 0...4
SYSCON
System Control Register
RP0H
Port P0H Reset Configuration Register
SFRs and Port Pins Associated with the External Bus Interface
Accesses to external memory or peripherals are executed by the integrated External Bus
Controller (EBC). The function of the EBC is controlled via the SYSCON, BUSCONx,
and ADDRSELx registers. The BUSCONx registers specify the external bus cycles in
terms of address (mux / demux), data width (16-bit / 8-bit), chip selects, and length
(waitstates / READY control / ALE / RW delay). These parameters are used for accesses
within a specific address area that is defined via the corresponding register ADDRSELx.
The four pairs BUSCON1/ADDRSEL1...BUSCON4/ADDRSEL4 make it possible to
define four independent “address windows”, while all external accesses outside these
windows are controlled via BUSCON0.
User’s Manual
8-1
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
8.1
Single-chip Mode
Single-chip mode is entered when the signal conf_start_external_n_i is high during
reset. In this case, BUSCON0 is initialized with 0000H, which also resets bit BUSACT0,
so no external bus is enabled.
In single-chip mode, the C166S operates only with and out of internal resources. No
external bus is configured and no external peripherals and/or memory can be accessed.
No port lines are used for the bus interface. When running in single-chip mode, however,
external access may be enabled by configuring an external bus under software control.
Single-chip mode allows the C166S to start execution out of the internal program
memory (Mask-ROM, OTP, DRAM, SRAM or flash memory).
Note: Any attempt to access a location in the external memory space in single-chip
mode results in the hardware trap ILLBUS if no external bus has been enabled
explicitly by software.
8.2
External Bus Modes
When the external bus interface is enabled (bit BUSACTx=1) and configured (bitfield
BTYP), the C166S uses a subset of its port lines together with some control lines to build
the external bus.
Table 8-1
Summary of External Bus Modes
BTYP
Encoding
External Data Bus Width
External Address Bus Mode
00
8-bit Data
Demultiplexed Addresses
01
8-bit Data
Multiplexed Addresses
10
16-bit Data
Demultiplexed Addresses
11
16-bit Data
Multiplexed Addresses
The bus configuration (BTYP) for the address windows (BUSCON4... BUSCON1) is
selected via software, typically during the initialization of the system.
The bus configuration (BTYP) for the default address range (BUSCON0) is selected via
conf_rst_bustyp_i[1:0] during reset, provided that the signal conf_start_external_n_i is
low during reset. Otherwise, BUSCON0 may be programmed via software just like the
other BUSCON registers.
The 16-MByte address space of the C166S is divided into 256 segments of 64 KBytes
each. The 16-bit intra-segment address is output on PORT0. When segmentation is
disabled, only one 64-KByte segment can be used and accessed. Otherwise, additional
address lines may be output on Port 4 (addressing up to 16 MByte), and/or several chip
select lines may be used to select different memory banks or peripherals. These
User’s Manual
8-2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
functions are selected during reset via bitfields SALSEL and CSSEL of register RP0H,
respectively.
8.2.1
Multiplexed Bus Modes
In the multiplexed bus modes, the 16-bit intra-segment address and the data both use
PORT0. The address is time-multiplexed with the data, and has to be latched externally.
The width of the required latch depends on the selected data bus width. For example,
an 8-bit data bus requires a byte latch (the address bits A15...A8 on P0H do not change,
while P0L multiplexes address and data); a 16-bit data bus requires a word latch (the
least significant address line A0 is not relevant for word accesses). The upper segment
address lines (An...A16) are permanently output on Port 4 if segmentation is enabled,
and do not require latches.
The EBC initiates an external access by generating the Address Latch Enable (ALE)
signal and then placing an address on the bus. The falling edge of ALE triggers an
external latch to capture the address. After a period of time during which the address
must have been latched externally, the address is removed from the bus. The EBC now
activates the appropriate command signal (RD, WR, WRL, WRH). Data is driven onto
the bus either by the EBC (for write cycles) or by the external memory/peripheral (for
read cycles). After a period of time that is determined by the access time of the memory/
peripheral, data become valid.
Read cycles: Input data is latched and the command signal is now deactivated. This
causes the accessed device to remove its data from the bus, which is then tri-stated
again.
Write cycles: The command signal is now deactivated. The data remain valid on the bus
until the next external bus cycle is started.
User’s Manual
8-3
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
CLKOUT
Normal ALE Cycle 5)
Normal ALE
Extended ALE Cycle 5)
Extend. ALE
CSxL6)
A23-A0,
BHE, CSxE6)
Valid
WRL, WRH,
WR, WRCS
1)
D15-D0
(Norm. ALE)
D15-D0
(Extd. ALE)
Low Address
Low Address
2)
Data Out
Data Out
1)
Section 8.3.4 Read/Write Delay
Section 8.3.5 Early Write
3)
Section 8.3.2 Memory Cycle Time
4)
Section 8.3.3 Memory Tri-State Time
5)
Section 8.3.1 ALE Length Control
6)
Section 8.2.3 CS Signal Generation
2)
Figure 8-2
User’s Manual
3)
4)
MCTC
MTTC
Multiplexed Bus, Write Access
8-4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
CLKOUT
Normal ALE Cycle 5)
Normal ALE
Extended ALE Cycle 5)
Extend. ALE
CSxL6)
A23-A0,
BHE, CSxE6)
Valid
RD,
RDCS
D15-D0
(Norm. ALE)
D15-D0
(Extd. ALE)
1)
Low Address
Low Address
Data In
1)
Section 8.3.4 Read/Write Delay
3)
Section 8.3.2 Memory Cycle Time
4)
Section 8.3.3 Memory Tri-State Time
5)
Section 8.3.1 ALE Length Control
6)
Section 8.2.3 CS Signal Generation
Figure 8-3
User’s Manual
Data In
3)
4)
MCTC
MTTC
Multiplexed Bus, Read Access
8-5
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
8.2.2
Demultiplexed Bus Modes
In the demultiplexed bus modes, the 16-bit intra-segment address is permanently output
on PORT1, while the data uses PORT0 (16-bit data) or P0L (8-bit data). The upper
address lines are permanently output on Port 4 (if selected via SALSEL during reset). No
address latches are required.
The EBC initiates an external access by placing an address on the address bus. After a
programmable period of time, the EBC activates the appropriate command signal (RD,
WR, WRL, WRH). Data is driven onto the data bus either by the EBC (for write cycles)
or by the external memory/peripheral (for read cycles). After a period of time determined
by the access time of the memory/peripheral, data becomes valid.
Read cycles: Input data is latched and the command signal is now deactivated. This
causes the accessed device to remove its data from the data bus which is then tri-stated
again.
Write cycles: The command signal is now deactivated. If a subsequent external bus
cycle is required, the EBC places the relevant address on the address bus. The data
remain valid on the bus until the next external bus cycle is started.
User’s Manual
8-6
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
CLKOUT
Normal ALE Cycle 5)
Normal ALE
Extended ALE Cycle 5)
Extend. ALE
CSxL6)
A23-A0,
BHE, CSxE6)
Valid
WRL, WRH,
WR, WRCS
2)
1)
D15-D0
(Normal Wr.)
Data Out
D15-D0
(Early Write)
Data Out
1)
Section 8.3.4 Read/Write Delay
Section 8.3.5 Early Write
3)
Section 8.3.2 Memory Cycle Time
4)
Section 8.3.3 Memory Tri-State Time
5)
Section 8.3.1 ALE Length Control
6)
Section 8.2.3 CS Signal Generation
2)
Figure 8-4
User’s Manual
3)
4)
MCTC
MTTC
Demultiplexed Bus, Write Access
8-7
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
CLKOUT
Normal ALE Cycle 5)
Normal ALE
Extended ALE Cycle
5)
Extend. ALE
CSxL6)
A23-A0,
BHE, CSxE6)
Valid
RD,
RDCS
1)
D15-D0
Data In
1)
3)
4)
3)
MCTC
MTTC
Section 8.3.4 Read/Write Delay
Section 8.3.2 Memory Cycle Time
4)
Section 8.3.3 Memory Tri-State Time
5)
Section 8.3.1 ALE Length Control
6)
Section 8.2.3 CS Signal Generation
Figure 8-5
User’s Manual
Demultiplexed Bus, Read Access
8-8
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
8.2.3
Switching Among the Bus Modes
The EBC allows dynamic switching among different bus modes, i.e., subsequent
external bus cycles may be executed in different ways. Certain address areas may use
an 8-bit or 16-bit data bus, or predefined waitstates.
A change of the external bus characteristics can be initiated in two different ways:
Reprogramming the BUSCON and/or ADDRSEL registers allows the bus mode to be
changed for a given address window, or changing the size of an address window that
uses a certain bus mode. Reprogramming makes it possible to use a great number of
different address windows (more than BUSCONs are available), although there is some
overhead for changing the registers and keeping appropriate tables.
Switching between predefined address windows automatically selects the bus mode
that is associated with the respective window. Predefined address windows allow the
use of different bus modes without any overhead, but restrict the number of windows to
the number of BUSCONs. However, as BUSCON0 controls all address areas that are
not covered by the other BUSCONs, there may be gaps between windows that use the
bus mode of BUSCON0.
PORT1 will output the intra-segment address when any of the BUSCON registers
selects a demultiplexed bus mode, even if the current bus cycle uses a multiplexed bus
mode. This allows an external address decoder to be connected to PORT1 only, while
using it for all kinds of bus cycles.
Note: Never change the configuration for an address area that currently supplies the
instruction stream. Due to internal pipelining, it is very difficult to determine the first
instruction fetch that will use the new configuration. Only change the configuration
for address areas that are not currently accessed. This applies to BUSCON
registers as well as to ADDRSEL registers.
The usage of the BUSCON/ADDRSEL registers is controlled via the addresses issued.
When an access (code fetch or data) is initiated, the generated physical address
determines whether the access is made internally, uses one of the address windows
defined by ADDRSEL4...1, or uses the default configuration in BUSCON0. After
initializing the active registers, they are selected and evaluated automatically by
interpreting the physical address. No additional switching or selecting is necessary
during run time, except when more than four address windows plus the default
(BUSCON0) are to be used.
Switching from demultiplexed to multiplexed bus mode represents a special case.
The bus cycle is started by activating ALE and driving the address to Port 4 and PORT1
as usual, if another BUSCON register selects a demultiplexed bus. However, in the
multiplexed bus modes, the address is also required on PORT0. In this special case. the
address on PORT0 is delayed by one CPU clock cycle, which delays the complete
(multiplexed) bus cycle and extends the corresponding ALE signal (see Figure 8-6).
User’s Manual
8-9
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
This extra time is required to allow the previously-selected device (via demultiplexed
bus) to release the data bus, which would be available in a demultiplexed bus cycle.
GHPX[HG
LGOH
PX[HG
ALE
A23-A0
A7-A0,(A15-A8)
D15-D0
valid
valid
Data In
low address
RD
A7-A0,(A15-A8)
D15-D0 write data
low address write data
WR
Figure 8-6
Switching from Demultiplexed to Multiplexed Bus Mode
Switching between external resources (e.g., different peripherals) may create a
problem if the previously-accessed resource needs some time to switch off its output
drivers (after a read), and if the resource to be accessed next switches on its output
drivers very fast. In systems running on higher frequencies, this may lead to a bus
conflict (switch-off delays normally are independent from the clock frequency).
In such a case, an additional waitstate can automatically be inserted when leaving a
certain address window, i.e. when the next cycle accesses a different window. This
waitstate is controlled in the same way as the waitstate when switching from
demultiplexed to multiplexed bus mode (see Figure 8-6).
BUSCON switch waitstates are enabled via bits BSWCx in the BUSCON registers. By
enabling the automatic BUSCON switch waitstate (BSWCx = 1), there is no impact on
the system performance as long as the external bus cycles access the same address
window. If the following cycle accesses a different window, a waitstate is inserted
between the last access to the previous window and the first access to the new window.
After reset, no BUSCON switch waitstates are selected.
User’s Manual
8-10
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
External Data Bus Width
The EBC can operate on 8-bit- or 16-bit-wide external memory/peripherals. A 16-bit data
bus uses PORT0, while an 8-bit data bus only uses P0L, the lower byte of PORT0. This
saves on address latches, bus transceivers, bus routing, and memory-related increases
in transfer time. The EBC can control word accesses on an 8-bit data bus as well as byte
accesses on a 16-bit data bus.
Word accesses on an 8-bit data bus are automatically split into two subsequent byte
accesses in which the low byte is accessed first, then the high byte. The assembly of
bytes to words and the disassembly of words into bytes is handled by the EBC, and is
transparent to the CPU and the programmer.
Byte accesses on a 16-bit data bus require that the upper and lower half of the memory
can be accessed individually. In this case, the upper byte is selected with the Byte High
Enable BHE signal, while the lower byte is selected with the A0 signal. The two bytes of
the memory can be enabled independently of each other, or together when accessing
words.
When writing bytes to an external 16-bit device that has a single CS input and two WR
enable inputs (for the two bytes), the EBC can generate these two write control signals
directly. This saves the external combination of the WR signal with A0 or BHE. In this
case, pin WR serves as WRL (WRite Low byte) and pin BHE serves as WRH (WRite
High byte). Bit WRCFG in register SYSCON selects the operating mode for pins WR and
BHE. The respective byte will be written on both data bus halves.
When reading bytes from an external 16-bit device, whole words may be read and the
C166S automatically selects the byte to be input and discards the other. However, care
must be taken when reading devices that change state when being read such as FIFOs,
interrupt status registers, etc. In this case, individual bytes should be selected using BHE
and A0.
Table 8-2
Bus Mode Versus Performance
Bus Mode
Transfer Rate
System Requirements
(Speed factor for
byte/word/dword access)
8-bit Multiplexed Very low
8-bit Demultipl.
( 1.5 / 3 / 6 )
Low
(1/2/4)
16-bit Multiplexed High
( 1.5 / 1.5 / 3 )
16-bit Demultipl. Very high
(1/1/2)
Low (8-bit latch, byte bus)
Free IO
Lines
P1H, P1L
Very low (no latch, byte bus) P0H
High (16-bit latch, word bus) P1H, P1L
Low (no latch, word bus)
---
Note: PORT1 becomes available for general-purpose IO when none of the BUSCON
registers selects a demultiplexed bus mode. PORT0H becomes available for
general-purpose IO when only the 8-bit demultiplexed bus mode is selected.
User’s Manual
8-11
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
Disable/Enable Control for Pin BHE (BYTDIS)
Bit BYTDIS is provided for controlling the active low Byte High Enable (BHE) pin. The
function of the BHE pin is enabled if the BYTDIS bit contains a 0. Otherwise, it is disabled
and the pin can be used as a standard I/O pin. The BHE pin is used implicitly by the EBC
to select one of two byte-organized memory chips, which are connected to the C166S
via a word-wide external data bus. After reset, the BHE function is automatically enabled
(BYTDIS = 0) if a 16-bit data bus is selected during reset; otherwise it is disabled
(BYTDIS=1). It may be disabled if byte access to 16-bit memory is not required, and if
the BHE signal is not used.
Segment Address Generation
During external accesses, the EBC generates a (programmable) number of address
lines on Port 4, which extend the 16-bit address output on PORT0 and thus increase the
accessible address space. The number of segment address lines is selected via
conf_rst_salsel_i[1:0] during reset, and coded in bit field SALSEL in register RP0H (see
table below).
Table 8-3
Decoding of Segment Address Lines
SALSEL
Segment Address Lines
Directly accessible Address Space
11
Two:
A17...A16
256
KByte (Default without pull-downs)
10
Eight:
A23...A16
16
MByte (Maximum)
01
None
64
KByte (Minimum)
00
Four:
1
MByte
A19...A16
Note: The total accessible address space may be increased by accessing several banks
that are distinguished by individual chip select lines.
If Port 4 is used to output segment address lines, in most cases the drivers must
operate in push/pull mode. Make sure that OPD4 does not select open-drain mode
in this case.
User’s Manual
8-12
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
CS Signal Generation
During external accesses, the EBC can generate a (programmable) number of CS lines
on Port 4, which make it possible to select external peripherals or memory banks directly
without requiring an external decoder. The number of CS lines is selected via
conf_rst_cssel_i[1:0] during reset, and coded in bit field CSSEL in register RP0H (see
Table 8-4).
Table 8-4
Decoding of Chip Select Lines
CSSEL
Chip Select Lines
11
Five:
10
None
01
Two:
CS1...CS0
00
Three:
CS2...CS0
Note
CS4...CS0 Default without pull-downs
The CSx outputs are associated with the BUSCONx registers, and are driven active low
for any access within the address area defined for the respective BUSCON register. For
any access outside this defined address area, the respective CSx signal will go inactive
high. At the beginning of each external bus cycle, the corresponding valid CS signal is
determined and activated. All other CS lines are deactivated (driven high) at the same
time.
Note: The CSx signals will not be updated for an access to any internal address area
(i.e. when no external bus cycle is started), even if this area is covered by the
respective ADDRSELx register. An internal bus interface access deactivates all
external CS signals.
Upon accesses to address windows without a selected CS line, all selected CS
lines are deactivated.
The chip-select signals may be operated in four different modes (see Table 8-5) that are
selected via bits CSWENx and CSRENx in the respective BUSCONx register.
Table 8-5
Chip-Select Generation Modes
CSWENx CSRENx Chip-Select Mode
0
0
Address chip select (default after reset)
0
1
Read chip select
1
0
Write chip select
1
1
Read/write chip select
User’s Manual
8-13
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
Read or Write Chip-Select (CS is renamed WRCS or RDCS in the protocol diagrams)
signals remain active only as long as the associated control signal (RD or WR) is active.
This also includes the programmable read/write delay. Read chip select is activated only
for read cycles; write chip select is activated only for write cycles; and read/write chip
select is activated for both read and write cycles (write cycles are assumed if either of
the signals WRH or WRL goes active). These modes save external glue logic when
accessing external devices such as latches or drivers that have only a single enable
input.
Address Chip-Select signals remain active during the complete bus cycle. For address
chip select signals, two generation modes can be selected via bit CSCFG in register
SYSCON:
• A latched address chip-select signal (CS is renamed in CSxL in the protocol
diagrams) (CSCFG=0) becomes active with the falling edge of ALE and becomes
inactive at the beginning of an external bus cycle that accesses a different address
window. No spikes will be generated on the chip-select lines, and no changes occur
as long as locations within the same address window or within internal memory
(excluding internal bus interface) are accessed.
• An early address chip-select signal (CS is renamed in CSxE in the protocol diagrams)
(CSCFG=1) becomes active together with the address and BHE (if enabled) and
remains active until the end of the current bus cycle. Early address chip-select signals
are not latched internally and may toggle intermediately while the address is changing.
Note: CS0 provides a latched address chip select directly after reset (except for singlechip mode) when the first instruction is fetched.
Internal pull-up devices hold all CS lines high during reset. After the end of a reset
sequence, the pull-up devices are switched off and the pin drivers control the pin levels
on the selected CS lines. Unselected CS lines will enter the high-impedance state, and
be available for general purpose I/O.
User’s Manual
8-14
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
CLKOUT
Normal ALE Cycle 5)
Normal ALE
Extended ALE Cycle 5)
Extend. ALE
CSxL
CSxE
5)
Valid
Section 8.3.1 ALE Length Control
Figure 8-7
Latched and Early Chip Select
Segment Address versus Chip Select
The external bus interface of the C166S supports many configurations for the external
memory. By increasing the number of segment address lines, the C166S can address a
linear address space of 256 KByte, 1 MByte, 4 MByte, 8 MByte or 16 MByte. This allows
implementation of a large sequential memory area, and access to a great number of
external devices, using an external decoder. By increasing the number of CS lines, the
C166S can access memory banks or peripherals without external glue logic. These two
features may be combined to optimize the overall system performance.
Note: If the number of segment address lines and CS lines configured at reset cause
overlap (e.g. A18...A16 and CS4...CS0), the segment address line function will
take precedence.
User’s Manual
8-15
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
8.3
Programmable Bus Characteristics
Important timing characteristics of the external bus interface have been made userprogrammable to adapt it to a wide range of external bus and memory configurations
with different types of memories and/or peripherals.
The following parameters of an external bus cycle are programmable:
• ALE Control defines the ALE signal length and the address hold time after its falling
edge
• Memory Cycle Time (extendable with 1-15 waitstates) defines the allowable access time
• Memory Tri-State Time (extendable with 1 waitstate) defines the time for a data driver to
float
• Read/Write Delay Time defines when a command is activated after the falling edge of
ALE
Note: External accesses use the slowest possible bus cycle after reset. The bus cycle
timing may then be optimized by the initialization software.
ALECTL
Figure 8-8
8.3.1
MCTC
MTTC
Programmable External Bus Cycle
ALE Length Control
The length of the ALE signal and the address hold time after its falling edge are
controlled by the ALECTLx bits in the BUSCON registers. When bit ALECTL is set to 1,
User’s Manual
8-16
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
external bus cycles accessing the appropriate address window will have their ALE signal
prolonged by half a CPU clock (1 TCL). Also the address hold time after the falling edge
of ALE (on a multiplexed bus) will be prolonged by half a CPU clock, so the data transfer
within a bus cycle refers to the same CLKOUT edges as usual (i.e., the data transfer is
delayed by one CPU clock). This allows more time for the address to be latched.
Note: ALECTL0 is 1 after reset to select the slowest possible bus cycle, the other
ALECTLx bits are 0 after reset.
8.3.2
Programmable Memory Cycle Time
The C166S allows the user to adjust the controller’s external bus cycles to the access
time of the respective memory or peripheral. This access time is the total time required
to move the data to the destination. It represents the period of time during which the
controller’s signals do not change.
The external bus cycles of the C166S can be extended by introducing waitstates during
access (see Figure 8-8) to compensate for a memory or peripheral that cannot keep
pace with the controller’s maximum speed . During these memory cycle time waitstates,
the CPU is idle if this access is required for the execution of the current instruction.
The memory cycle time waitstates can be programmed in increments of one CPU clock
(2 TCL) within a range from 0 to 15 (default after reset) via the Memory Cycle Time
Control (MCTC) fields of the BUSCON registers. 15-<MCTC> waitstates will be
inserted.
8.3.3
Programmable Memory Tri-State Time
The C166S allows the user to adjust the time between two subsequent external
accesses in order to account for the tri-state time of the external device. The tristate time
defines when the external device has released the bus after deactivation of the read
command (RD).
The output of the next address on the external bus can be delayed by introducing a
waitstate after the previous bus cycle in order to compensate for a memory or peripheral
that needs more time to switch off its bus drivers, (see Figure 8-8). During this memory
tri-state time waitstate, the CPU is not idle, so CPU operations will be slowed down only
if a subsequent external instruction or data fetch operation is required during the next
instruction cycle.
The memory tristate time waitstate requires one CPU clock (2 TCL) and is controlled via
the Memory Tristate Time Control (MTTCx) bits of the BUSCON registers. A waitstate
will be inserted if bit MTTCx is 0 (default after reset).
Note: External bus cycles in multiplexed bus modes implicitly add one tristate time
waitstate in addition to the programmable MTTC waitstate.
User’s Manual
8-17
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
8.3.4
Read/Write Signal Delay
The C166S allows the user to adjust the timing of the read and write commands to
account for timing requirements of external peripherals. The read/write delay controls the
time between the falling edge of ALE and the falling edge of the command. Without read/
write delay, the falling edges of ALE and command(s) are concurrent (except for
propagation delays). With the delay enabled, the command(s) become active half a CPU
clock (1 TCL) after the falling edge of ALE. The read/write delay does not extend the
memory cycle time, and does not slow down the controller. In multiplexed bus modes,
however, the data drivers of an external device may conflict with the C166S’s address
when the early RD signal is used. Therefore, multiplexed bus cycles should always be
programmed with read/write delay.
The read/write delay is controlled via the Read Write Delay Control (RWDCx) bits in the
BUSCON registers. The command(s) will be delayed if bit RWDCx is 0 (default after
reset).
8.3.5
Early WR
The duration of an external write access can be shortened by one TCL. The WR signal
is activated (driven low) in the standard way, but can be deactivated (driven high) one
TCL earlier than defined in the standard timing. In this case, the data output drivers will
also be deactivated one TCL earlier.
This is especially useful in systems that operate on higher CPU clock frequencies and
employ external modules (memories, peripherals, etc.) that switch on their own data
drivers very rapidly in response to e.g. a chip select signal.
Conflicts between the C166S’s and the external peripheral’s output drivers can be
avoided by selecting early WR for the C166S.
Note: Make sure that the reduced WR low time still meets the requirements of the
external peripheral/memory.
Early WR deactivation is controlled via the Early Write EnNable (EWENx) bits in the
BUSCON registers. The WR signal will be shortened if bit EWENx is 1 (default after reset
is a standard WR signal, i.e. EWENx = 0).
8.3.6
READY Controlled Bus Cycles
For situations in which the programmable waitstates are not enough, or the response
(access) time of a peripheral is not constant, the C166S has external bus cycles that are
terminated via an asynchronous READY input signal. In this case, the C166S first inserts
a programmable number of waitstates (0-7) and then monitors the READY line to
determine the actual end of the current bus cycle. The external device drives READY low
in order to indicate that data have been latched (write cycle) or are available (read cycle).
User’s Manual
8-18
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
Running Cycle 4)
6)
CLKOUT
Command
(RD, WR)
Asynch.
READY
Figure 8-9
1)
5)
2)
5)
7)
The next external bus
cycle my start here.
READY-WS MUX/MTTC
READY Controlled Bus Cycles
1)
Section 8.3.4 Read/Write Delay
2) Section 8.3.5 Early Write
4)
Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).
5)
READY sampled HIGH at this sampling point generates a READY controlled waitstate,
READY sampled LOW at this sampling point terminates the currently running bus cycle.
6)
Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may
be inserted here. For a multiplexed bus with MTTC waitstate, this delay is 2 CLKOUT cycles; for a
demultiplexed bus without MTTC waitstate this delay is zero.
7)
If the next following bus cycle is READY controlled, an active READY signal must be disabled before the first
valid sample point for the next bus cycle. This sample point depends on the MTTC waitstate of the current
cycle, and on the MCTC waitstates and the ALE mode of the next cycle. If the current cycle uses a multiplexed
bus, the intrinsic MUX waitstate adds another CLKOUT cycle to the READY deactivation time.
The READY function is enabled via the ReaDY ENable (RDYENx) bits in the BUSCON
registers. When this function is selected (RDYENx = 1), only the lower 3 bits of the
respective MCTC bit field define the number of inserted waitstates (0-7), while the MSB
of bit field MCTC is unused:
As shown in Figure 8-9, the asychronous READY requires additional waitstates caused
by the internal synchronization. The asynchronous READY is synchronized internally,
and programmed waitstates may be necessary to provide proper bus cycles (see also
notes on “normally-ready” peripherals below).
An asynchronous READY signal that has been activated by an external device may be
deactivated in response to the trailing (rising) edge of the respective command (RD or
WR).
Note: When the READY function is enabled for a specific address window, each bus
cycle within this window must be terminated with an active READY signal.
Otherwise, the controller hangs until the next reset. A time-out function is provided
by the watchdog timer.
User’s Manual
8-19
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
Combining the READY function with predefined waitstates is advantageous in two
cases:
Memory components with a fixed access time and peripherals operating with READY
may be grouped into the same address window. The (external) waitstate control logic in
this case would activate READY either upon the memory’s chip select or with the
peripheral’s READY output. After the predefined number of waitstates, the C166S will
check its READY line to determine the end of the bus cycle. For a memory access, it will
already be low; for a peripheral access, it may be delayed. As memories tend to be faster
than peripherals, there should be no impact on system performance.
When using the READY function with so-called “normally-ready” peripherals, erroneous
bus cycles may occur if the READY line is sampled too early. These peripherals pull their
READY output low while they are idle. When they are accessed, they deactivate READY
until the bus cycle is complete, then drive it low again. If, however, the peripheral
deactivates READY after the first sample point of the C166S, the controller samples an
active READY and terminates the current bus cycle too early. By inserting predefined
waitstates, the first READY sample point can be shifted to an interval in which the
peripheral has safely controlled the READY line.
User’s Manual
8-20
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
8.4
Controlling the External Bus Controller
A set of registers controls the functions of the EBC. General features such as the usage
of interface pins (WR, BHE), segmentation, and internal memory mapping are controlled
via register SYSCON. The properties of a bus cycle such as chip-select mode, length of
ALE, external bus mode, read/write delay, and waitstates are controlled via registers
BUSCON4-BUSCON0. Four of these registers (BUSCON4-BUSCON1) have an
address select register (ADDRSEL4-ADDRSEL1) associated with them, which makes it
possible to specify up to four address areas and the individual bus characteristics within
these areas. All accesses that are not covered by these four areas are then controlled
via BUSCON0. This allows the use of memory components or peripherals with different
interfaces within the same system, while optimizing accesses to each of them.
SYSCON
System Control Register
15
14
13
12
11
SFR (FF12H/89H)
10
9
8
7
6
Reset value: 0XX0H
5
4
3
2
1
0
SYS SYS SYS
SYS
ROM SGT ROM BYT CLK WR CS CON
CON XPEN VISICON
S1 DIS EN DIS EN CFG CFG 5 CON
BLE
4
3
0
rw
rw rwh rwh rw rwh rw rwh rwh rwh rw
rw rwh
STKSZ
rw
Field
Bits
Type Description
SYSCON0
0
rwh
System Configuration Bit
VISIBLE
1
rw
Visible Mode Control
0:
Accesses to XBUS peripherals are done internally
1:
XBUS peripheral accesses are made visible on the
external pins
XPEN
2
rw
XBUS Peripheral Enable Bit
0:
Accesses to the on-chip X-Peripherals and their
functions are disabled
1:
The on-chip X-Peripherals are enabled and can be
accessed
SYSCON3
.....
SYSCON5
3
....
5
rwh
System Configuration Bit
User’s Manual
8-21
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
Field
Bits
Type Description
CSCFG
6
rw
Chip Select Configuration Control
0:
Latched CS mode. The CS signals are latched
internally and driven to the (enabled) port pins
synchronously.
1:
Unlatched CS mode. The CS signals are directly
derived from the address and driven to the
(enabled) port pins.
WRCFG
7
rwh
Write Configuration Control (Set according to pin
P0H.0 during reset)
0:
Pins WR and BHE retain their normal function
1:
Pin WR acts as WRL, pin BHE acts as WRH
CLKEN
8
rw
System Clock Enable (CLKOUT, cleard after reset)
0:
CLKOUT disabled: pin may be used for general
purpose IO
1:
CLKOUT enabled: pin outputs the system clock
signal
BYTDIS
9
rwh
Disable/Enable Control for Pin BHE (Set according to
data bus width)
0:
Pin BHE enabled
1:
Pin BHE disabled, pin may be used for general
purpose IO
ROMEN
10
rwh
CPU Configuration Bit
Internal ROM Enable (Set according to pin EA during
reset)
0 Internal Local Memory disabled: accesses to the
Local Memory area use the external bus
1 Internal Local Memory enabled
SGTDIS
11
rw
CPU Configuration Bit
Segmentation Disable/Enable Control
0 Segmentation enabled (CSP is saved/restored
during interrupt entry/exit)
1 Segmentation disabled (Only IP is saved/restored)
User’s Manual
8-22
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
Field
Bits
Type Description
ROMS1
12
rw
STKSZ
[15:13] rw
CPU Configuration Bit
Internal Local Memory Mapping
0 Internal Local Memory area mapped to segment 0
(00’0000H...00’7FFFH)
1 Internal Local Memory area mapped to segment 1
(01’0000H...01’7FFFH)
CPU Configuration Bit
System Stack Size
Selects the size of the system stack (in the internal
DPRAM) from 32 to 1024 words
Note: Register SYSCON cannot be changed after execution of the EINIT instruction.
The layout of the BUSCON registers and ADDRSEL registers is identical.
Registers BUSCON4...BUSCON1, which control the selected address windows, are
completely under software control. Register BUSCON0, which is also used for the very
first code access after reset, is partly controlled by hardware, i.e., it is initialized via
dedicated configuration signals during the reset sequence. This hardware control allows
an appropriate external bus to be defined for systems in which no internal program
memory is provided.
User’s Manual
8-23
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
BUSCON0
Bus Control Register 0
15
14
13
CSW CSR
EN0 EN0
rw
0
rw
r
12
11
SFR (FF0CH/86H)
10
14
13
CSW CSR
EN1 EN1
rw
0
rw
r
14
13
CSW CSR
EN2 EN2
rw
0
rw
r
12
11
10
14
13
CSW CSR
EN3 EN3
rw
0
rw
r
12
11
14
13
CSW CSR
EN4 EN4
rw
rw
0
r
8
11
10
9
8
11
rwh
5
4
BTYP
rw
BTYP
rw
9
8
7
5
BTYP
rw
4
9
8
7
ALE EW
RDY BSW BUS
ACT
CTL EN4
EN4 C4
4
4
rw
rw
rw
rw
rw
BTYP
rw
2
1
0
MCTC
rw
Reset value: 0000H
5
4
3
MTT RWD
C2 C2
2
1
0
MCTC
rw
rw
Reset value: 0000H
5
4
3
MTT RWD
C3 C3
rw
6
3
rw
2
1
0
MCTC
rw
SFR (FF1AH/8DH)
10
0
rw
MTT RWD
C1 C1
rw
6
1
MCTC
rw
SFR (FF18H/8CH)
10
2
Reset value: 0000H
rw
6
3
MTT RWD
C0 C0
rw
6
7
ALE EW
RDY BSW BUS
CTL EN3
EN3 C3 ACT
3
3
rw
rw
rw
rw
rw
12
BTYP
7
ALE EW
RDY BSW BUS
ACT
CTL EN2
EN2 C2
2
2
rw
rw
rw
rw
rw
12
6
SFR (FF16H/8BH)
BUSCON4
Bus Control Register 4
15
9
ALE EW
RDY BSW BUS
CTL EN1
EN1 C1 ACT
1
1
rw
rw
rw
rw
rw
BUSCON3
Bus Control Register 3
15
7
SFR (FF14H/8AH)
BUSCON2
Bus Control Register 2
15
8
ALE EW
RDY BSW BUS
ACT
CTL EN0
EN0 C0
0
0
rw
rw rwh rwh rw
BUSCON1
Bus Control Register 1
15
9
Reset value: 0XX0H
rw
Reset value: 0000H
5
4
MTT RWD
C4 C4
rw
rw
3
2
1
0
MCTC
rw
Note: BUSCON0 is initialized with 00C0H if conf_start_external_i is high during reset. If
conf_start_external_i is low during reset, bits BUSACT0 and ALECTL0 are set (1)
User’s Manual
8-24
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
and bit field BTYP is loaded with the bus configuration selected via
conf_rst_bustyp_i[1:0].
Field
Bits Type Description
MCTC
[3:0] rw
Memory Cycle Time Control 1)(Number of memory cycle
time waitstates)
0000: 15 waitstates
. . . (Number = 15 - <MCTC>)
1111: No waitstates
RWDCx
4
rw
Read/Write Delay Control for BUSCONx
0:
With rd/wr delay: activate command 1 TCL after falling
edge of ALE
1:
No rd/wr delay: activate command with falling edge of
ALE
MTTCx
5
rw
Memory Tristate Time Control
0:
1 waitstate
1:
No waitstate
BTYP
[7:6] rw
External Bus Configuration
00: 8-bit Demultiplexed Bus
01: 8-bit Multiplexed Bus
10: 16-bit Demultiplexed Bus
11: 16-bit Multiplexed Bus
Note: For
BUSCON0,
BTYP
is
conf_rst_bustyp_i[1:0] during reset.
defined
via
EWENx
8
rw
Early Write Enable
0:
Normal WR signal
1:
Early write: The WR signal is deactivated and write
data is tristated
one TCL earlier
ALECTLx
9
rw
ALE Lengthening Control
0:
Normal ALE signal
1:
Lengthened ALE signal
rw
Bus Active Control
0:
External bus disabled
1:
External bus enabled within respective address window
(ADDRSEL)
BUSACTx 10
User’s Manual
8-25
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
Field
Bits Type Description
BSWCx
11
rw
BUSCON Switch Control
0:
Address windows are switched immediately
1:
A tristate waitstate is inserted if the next bus cycle
accesses a different window than the one controlled by
this BUSCON register2)
RDYENx
12
rw
READY Input Enable
0:
External bus cycle is controlled by bit field MCTC only
1:
External bus cycle is controlled by the READY input
signal
CSRENx
14
rw
Read Chip Select Enable
0:
The CS signal is independent of the read command
(RD)
1:
The CS signal is generated for the duration of the read
command
CSWENx
15
rw
Write Chip Select Enable
0:
The CS signal is independent of the write cmd.
(WR,WRL,WRH)
1:
The CS signal is generated for the duration of the write
command
1)
When the READY function is selected (RDYENx = 1), only the lower 3 bits of the respective MCTC bit field
define the number of inserted waitstates (0-7), while the MSB of bit field MCTC is unused
2)
A BUSCON switch waitstate is enabled by bit BUSCONx.BSWCx of the address window that is left.
ADDRSEL1
Address Select Register 1
15
14
13
12
11
SFR (FE18H/0CH)
10
9
14
13
User’s Manual
12
11
7
6
5
4
3
2
1
RGSAD
RGSZ
rw
rw
ADDRSEL2
Address Select Register 2
15
8
Reset value: 0000H
SFR (FE1AH/0DH)
10
9
8
7
6
Reset value: 0000H
5
4
3
2
1
RGSAD
RGSZ
rw
rw
8-26
0
0
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
ADDRSEL3
Address Select Register 3
15
14
13
12
11
SFR (FE1CH/0EH)
10
9
14
13
12
11
7
6
5
4
3
2
1
RGSAD
RGSZ
rw
rw
ADDRSEL4
Address Select Register 4
15
8
Reset value: 0000H
SFR (FE1EH/0FH)
10
9
8
7
6
0
Reset value: 0000H
5
4
3
2
1
RGSAD
RGSZ
rw
rw
0
Field
Bits
Type Description
RGSZ
[0:3]
rw
Range Size Selection
Defines the size of the address area controlled by the
respective BUSCONx/ADDRSELx register pair. See
Table 8-6 below.
RGSAD
[15:4]
rw
Range Start Address
Defines the upper bits of the start address of the respective
address area. See Table 8-6 below.
Note: There is no register ADDRSEL0, as register BUSCON0 controls all external
accesses outside the four address windows of BUSCON4-BUSCON1 within the
complete address space.
User’s Manual
8-27
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
Definition of Address Areas
The four register pairs BUSCON4/ADDRSEL4-BUSCON1/ADDRSEL1 allow 4 address
areas to be defined within the address space of the C166S. Within each of these address
areas, external accesses can be controlled by one of the four different bus modes,
independent of each other and of the bus mode specified in register BUSCON0. Each
ADDRSELx register cuts out an address window, within which the parameters in register
BUSCONx are used to control external accesses. The range start address of such a
window defines the upper address bits, which are not used within the address window of
the specified size (see table below). For a given window size, only those upper address
bits of the start address (marked “R”) that are not implicitly used for addresses inside the
window are used. The lower bits of the start address (marked “x”) are disregarded.
Table 8-6
Address Window Definition
Bit field RGSZ Resulting Window Size
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
11xx
4 KByte
8 KByte
16 KByte
32 KByte
64 KByte
128 KByte
256 KByte
512 KByte
1 MByte
2 MByte
4 MByte
8 MByte
Reserved.
Relevant Bits (R) of Start Addr. (A12...)
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
x
R
R
R
R
R
R
R
R
R
R
x
x
R
R
R
R
R
R
R
R
R
x
x
x
R
R
R
R
R
R
R
R
x
x
x
x
R
R
R
R
R
R
R
x
x
x
x
x
R
R
R
R
R
R
x
x
x
x
x
x
R
R
R
R
R
x
x
x
x
x
x
x
R
R
R
R
x
x
x
x
x
x
x
x
R
R
R
x
x
x
x
x
x
x
x
x
R
R
x
x
x
x
x
x
x
x
x
x
R
x
x
x
x
x
x
x
x
x
x
x
Address Window Arbitration
The address windows that can be defined within the C166S’s address space may partly
overlap each other. Thus small areas may be cut out of bigger windows, for example, in
order to utilize external resources effectively, especially within segment 0.
For each access, the EBC compares the current address with all address-select
registers (programmable ADDRSELx and hardwired/programmable XADRSx1)). This
comparison is done in three levels. The XADRSx registers have the highest priority
(priority I). The ADDRSEL registers have the second highest priority (priority II). If there
is no match with any XADRSx or ADDRSELx register, the access to the external bus
uses register BUSCON0 (priority III).
1)
The XADR registers are the control registers of the internal XBUS interface (see Section 8.7).
User’s Manual
8-28
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
Priority 1: The XADRSx registers are evaluated first. A match with one of these
registers directs the access to the respective X-Peripheral using the corresponding
XBCONx register and ignoring all other ADDRSELx registers. Priority of the XADRSx
registers: XADR1 (priority I.1) , XADRS2 (I.2), XADRS3 (I.3), XADR4 (I.4) , XADRS5
(I.5), XADRS6 (I.6)
Priority 2: A match with one of the registers ADDRSELx directs the access to the
respective external area using the corresponding BUSCONx register.
Priority of the ADDRSELx registers: ADDRSEL2 (priority II.1), ADDRSEL4 (II.2),
ADDRSEL1 (II.3), ADDRSEL3 (II.4)
Priority 3: If there is no match with any XADRSx or ADDRSELx register, the access to
the external bus uses BUSCON0.
XBCON1
XBCON...
XBCON6
BUSCON2
BUSCON4
BUSCON1
BUSCON3
BUSCON0
Active Window
Inactive Window
Figure 8-10 Address Window Arbitration Example
RP0H
Reset Value of P0H
15
14
13
12
SFR (F108H/84H)
11
10
9
8
7
6
Reset value: - - XXH
5
4
3
2
1
0
CLKCFG
SALSEL
CSSEL
WRC
rh
rh
rh
rh
Note: RP0H cannot be changed directly via software, but rather allows the current
configuration to be checked.
Bitfields CLKCFG, SALSEL, and CSSEL may be reconfigured via register
RSTCON.
User’s Manual
8-29
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
Bit
WRC
Function
Write Configuration
0:
Pins WR and BHE operate as WRL and WRH signals
1:
Pins WR and BHE operate as WR and BHE signals
CSSEL
Chip Select Line Selection (Number of active CS outputs)
00: 3 CS lines: CS2...CS0
01: 2 CS lines: CS1...CS0
10: No CS lines at all
11: 4 CS lines: CS3...CS0 (Default without put-downs)
SALSEL
Segment Address Line Selection (Nr. of active segment addr. outputs)
00: 4-bit segment address: A19...A16
01: No segment address lines at all
10: 6-bit segment address: A21...A16
11: 2-bit segment address: A17...A16 (Default without put-downs)
CLKCFG
Clock Generation Mode Configuration
These pins define the clock generation mode, i.e. the mechanism how
the internal CPU clock is generated from the externally applied (XTAL1)
input clock.
Precautions and Hints
• The external bus interface is enabled as long as at least one of the BUSCON registers
has its BUSACT bit set.
• PORT1 will output the intra-segment address as long as at least one of the BUSCON
registers selects a demultiplexed external bus, even for multiplexed bus cycles.
• The address windows defined via registers ADDRSELx may overlap internal address
areas. Internal accesses will be executed in this case.
• For any access to an internal address area, the EBC will remain inactive (see
Section 8.5 EBC Idle State).
8.5
EBC Idle State
When the external bus interface is enabled, but no external access is currently being
executed, the EBC is idle. As long as only internal resources (from an architecture point
of view) such as DPRAM, GPRs, or SFRs, etc. are used, the external bus interface does
not change (seeTable 8-7 below).
Accesses to on-chip X-Peripherals are also controlled by the EBC. However, even
though an X-Peripheral appears to the controller as if it were an external peripheral, the
accesses do not generate valid external bus cycles.
User’s Manual
8-30
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
Due to timing constraints, address and write data of an XBUS cycle are reflected on the
external bus interface (see Table 8-7 below). The “address” mentioned above includes
Port 4, BHE, and ALE (which also pulses for an XBUS cycle). The external CS signals
are driven inactive (high) because the EBC switches to an internal XCS signal.
The external control signals (RD and WR or WRL/WRH if enabled) remain inactive
(high).
Table 8-7
Status Of The External Bus Interface During EBC Idle State
Pins
Internal accesses only
XBUS accesses
PORT0
Tristated (floating)
Tristated (floating) for read
accesses
XBUS write data for write accesses
PORT1
Last used external address
(if used for the bus interface)
Last used XBUS address
(if used for the bus interface)
Port 4
Last used external segment address Last used XBUS segment address
(on selected pins)
(on selected pins)
Inactive (high) for selected CS
Active external CS signal
corresponding to last used address signals
BHE
Level corresponding to last external Level corresponding to last XBUS
access
access
ALE
Inactive (low)
Pulses as defined for X-Peripheral
RD
Inactive (high)
Inactive (high)
WR/WRL
Inactive (high)
Inactive (high)
WRH
Inactive (high)
Inactive (high)
8.6
External Bus Arbitration
In high-performance systems, it may be efficient to share external resources such as
memory banks or peripheral devices among more than one controller. The C166S
supports this approach with the possibility to arbitrate the access to its external bus, i.e.,
to the external devices.
This bus arbitration allows an external master to request the C166S’s bus via the HOLD
input. The C166S acknowledges this request via the HLDA output and will float its bus
lines in this case. The CS outputs provide internal pull-up devices. The new master may
now access the peripheral devices or memory banks via the same interface lines as the
C166S. During this time, the C166S can keep on executing, as long as it does not need
User’s Manual
8-31
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
access to the external bus. All actions that just require internal resources such as
instruction, data memory, or on-chip peripherals may be executed in parallel.
When the C166S needs access to its external bus while it is occupied by another bus
master, it demands it via the BREQ output.
The external bus arbitration is enabled by setting bit HLDEN in register PSW to 1. The
three bus arbitration pins HOLD, HLDA, and BREQ will be controlled automatically by
the EBC independent of their I/O configuration. Bit HLDEN may be cleared during the
execution of program sequences in which the external resources are required but cannot
be shared with other bus masters. In this case, the C166S will not answer to HOLD
requests from other external masters. If HLDEN is cleared while the C166S is in hold
state (code execution from internal RAM/ROM), this hold state is left only after HOLD
has been deactivated again. The current hold state will continue and only the next HOLD
request is not answered.
PSW
Processor Status Word
15
14
13
12
SFR(FF10H,88H)
Reset value: 0000H
11
10
9
8
7
6
5
4
3
2
1
0
ILVL
IEN
HLD
EN
0
0
0
USR0
MUL
IP
E
Z
V
C
N
rwh
rw
rw
r
r
r
rw
rwh
rwh
rwh
rwh
rwh
rwh
Field
Bits
Type Description
HLDEN
[10]
rw
External Bus Arbitration Control
0H
External arbitration disabled
1H
External arbitration enabled
Connecting two C166Ss in this way would require additional logic to combine the
respective output signals HLDA and BREQ. This can be avoided by switching one of the
controllers into Slave Mode, in which pin HLDA is switched to input. This allows the slave
controller to be connected directly to another master controller without glue logic. The
Slave Mode is selected by setting bit DP6.7 to ’1’. DP6.7=’0’ (default after reset) selects
the Master Mode.
Note: The pins HOLD, HLDA and BREQ keep their alternate function (bus arbitration)
even after the arbitration mechanism has been switched off by clearing HLDEN.
All three pins are used for bus arbitration after bit HLDEN has been set once.
Connecting Bus Masters
When multiple C166Ss or a C166S and another bus master share external resources,
some glue logic is required to define the currently active bus master, and to enable a
User’s Manual
8-32
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
C166S that has surrendered its bus interface to regain control of it in case it must access
the shared external resources. This glue logic is required if the other bus master does
not automatically remove its hold request after having used the shared resources.
When two C166Ss are to be connected in this way, the external glue logic can be left
out. One of the controllers must be operated in its Master Mode (default after reset,
DP6.7=0) while the other one must be operated in its Slave Mode (selected with
DP6.7=1).
HOLD
HOLD
HLDA
HLDA
BREQ
BREQ
C166S in
Slave Mode
C166S in
Master Mode
In Slave Mode, the C166S inverts the direction of its HLDA pin and uses it as an input,
while the master’s HLDA pin remains an output. This approach does not require any
additional glue logic for the bus arbitration (see Figure 8-11 below).
Figure 8-11 Sharing External Resources Using Slave Mode
When the bus arbitration is enabled (HLDEN=1), the three corresponding pins are
controlled automatically by the EBC. Normally, the respective port direction register bits
retain their reset value, which is 0. This selects Master Mode. Slave Mode is enabled by
intentionally switching pin BREQ to output (DP6.7=1).
Entering the Hold State
Access to the C166S’s external bus is requested by driving its HOLD input low. After
synchronizing this signal, the C166S will complete a current external bus cycle (if any is
active), release the external bus, and grant access to it by driving the HLDA output low.
During hold state, the C166S treats the external bus interface as follows:
•
•
•
•
Address and data bus(es) float to tristate
ALE is pulled low by an internal pull-down device
Command lines are pulled high by internal pull-up devices (RD, WR/WRL, BHE/WRH)
CSx outputs are pulled high (push/pull mode) or float to tri-state (open-drain mode)
User’s Manual
8-33
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
Should the C166S require access to its external bus during hold mode, it activates its
bus request output BREQ to notify the arbitration circuitry. BREQ is activated only during
hold mode. It will be inactive during normal operation.
Figure 8-12 External Bus Arbitration, Releasing the Bus
Note: The C166S will complete the bus cycle that is currently running before granting
bus access, as indicated by the broken lines in Figure 8-12. This may delay hold
acknowledge compared to this figure. The Figure 8-12 shows the first possibility
for BREQ to go active.
During bus hold pin, P3.12 is switched back to its standard function and is then
controlled by DP3.12 and P3.12. DP3.12 should be cleared and held at 0 to ensure
floating in hold mode.
Exiting the Hold State
The external bus master returns the access rights to the C166S by driving the HOLD
input high. After synchronizing this signal, the C166S will drive the HLDA output high,
actively drive the control signals, and resume executing external bus cycles if required.
Depending on the arbitration logic, the external bus can be returned to the C166S under
two circumstances:
• The external master no longer requires access to the shared resources and gives up
its own access rights, or
User’s Manual
8-34
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
• the C166S needs access to the shared resources and demands this by activating its
BREQ output. The arbitration logic may then deactivate the other master’s HLDA and
so free the external bus for the C166S, depending on the priority of the different
masters.
Note: The Hold State is not terminated by clearing bit HLDEN.
Figure 8-13 External Bus Arbitration, Regaining the Bus
Note: The falling BREQ edge indicates the last chance for BREQ to trigger the regain
sequence. Even if BREQ is activated earlier, the regain sequence is initiated by
HOLD going high. BREQ and HOLD are connected via an external arbitration
circuitry. HOLD may also be deactivated without the C166S requesting the bus.
8.7
The XBUS Interface
The C166S provides an on-chip interface (the XBUS interface) by which integrated
customer/application-specific peripherals can be connected to the standard controller
core. The XBUS is an internal representation of the external bus interface, i.e., it is
operated in the same way.
For each peripheral on the XBUS (X-Peripheral) there is a separate address window
controlled by a register pair XBCONx/XADRSx (similar to registers BUSCONx and
ADDRSELx). Because an interface to a peripheral is represented in many cases by just
a few registers, most of the XADDRSEL registers select smaller address windows than
User’s Manual
8-35
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
the standard ADDRSEL registers. As the register pairs control integrated peripherals
rather than externally connected ones, most of the registers are fixed by mask
programming rather than being user-programmable.
The XBUS provides byte-wide or word-wide X-Peripheral accesses. Because the onchip connection can be very efficient, and for performance reasons, X-Peripherals are
implemented only with a separate address bus, i.e., in demultiplexed bus mode. Interrupt
nodes are provided for X-Peripherals to be integrated.
Enabling XBUS Peripherals
After reset, all on-chip XBUS peripherals are disabled. An XBUS peripheral cannot be
used unless it has been enabled via the global enable bit XPEN in register SYSCON.
Additional to the XPEN bit, the XPERCON register define which on-chip peripherals are
enabled or disabled (xpercon_o[15:0]). If a peripheral is disabled all it’s addresses are
no more visible.
The XPERCON register is accessible until execution of the EINIT instruction.
XPER selection with the XPERCON register has to be performed before the selected Xperipherals are globally enabled via XPEREN-bit in SYSCON Register.
XPERCON
XPeripheral Control Register
15
14
13
12
11
10
SFR (F024H/12H)
9
8
7
6
Reset value: 0000H
5
4
3
2
1
0
PER PER PER PER PER PER PER PER PER PER PER PER PER PER PER PER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
PER0
[0]
rw
XPeripheral Enable Control for XCS1
0
XPeripheral disabled
1
XPeripheral enabled
PER1
[1]
rw
XPeripheral Enable Control for XCS2
0
XPeripheral disabled
1
XPeripheral enabled
PER2
[2]
rw
XPeripheral Enable Control for XCS3
0
XPeripheral disabled
1
XPeripheral enabled
PER3
[3]
rw
XPeripheral Enable Control for XCS4
0
XPeripheral disabled
1
XPeripheral enabled
User’s Manual
8-36
rw
rw
rw
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
Field
Bits
Type Description
PER4
[4]
rw
XPeripheral Enable Control for XCS5
0
XPeripheral disabled
1
XPeripheral enabled
PER5
[5]
rw
XPeripheral Enable Control for XCS6
0
XPeripheral disabled
1
XPeripheral enabled
PERx
[15:6]
rw
XPeripheral Enable Control for XCSx, x=7..16
0
XPeripheral disabled
1
XPeripheral enabled
8.7.1
XBUS Access Control
In C166S up to six (configurable) address ranges with according bus definitions can be
programmed for XBUS peripherals (including memories).
Address ranges and thus address mapping of memories or peripherals on XBUS are
controlled with the address selection registers XADRSx. The respective bus type
definitions are controlled with registers XBCONx.
The XADRS registers are defined as follows:
XADRS1(/2/3/4/5/6)
XBUS Address Selection Reg.
15
14
13
12
11
10
9
8
(Reset value: XXXXH)
7
6
5
4
3
2
1
RGSADx
RGSZx
rw
rw
Field
Bits
Type Description
RGSADx
[15:4]
rw
Address Range Start Address Selection
RGSZx
[3:0]
rw
Address Range Size Selection
0
The respective SFR addresses of XADRSx registers can be found in list of SFRs.
Due to the different range size options, address mapping of XPERs is possible only
within the first MByte of the total address range if XADRS1 to XADRS4 is used. The
upper four address lines (A23:A20) are set to zero. Note that the range start address can
be located only on boundaries specified by the selected range size.
The following table shows the definitions of range size selections and range start
addresses for the address selection registers XADRS1/2/3/4.
User’s Manual
8-37
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
The address range and address range start definition of XADRS5 and XADRS6
registers is identical to the address selection definition for external devices (see
Address Window Definition). It is thus possible to use the whole address range also
for internal memories or peripherals.
Range
Size
RGSZ
Selected
Address
Range
Relevant(R) bits
of RGSAD
Selected Range Start Address
(Relevant(R) bits of RGSAD)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
11xx
256 Byte
512 Bytes
1 KBytes
2 KBytes
4 KBytes
8 KBytes
16 KBytes
32 KBytes
64 KBytes
128 KBytes
256 KBytes
512 KBytes
- reserved
RRRR
RRRR
RRRR
RRRR
RRRR
RRRR
RRRR
RRRR
RRRR
RRR0
RR00
R000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
RRRR
RRRR
RRRR
RRRR
RRRR
RRR0
RR00
R000
0000
0000
0000
0000
RRRR
RRR0
RR00
R000
0000
0000
0000
0000
0000
0000
0000
0000
RRRR
RRRR
RRRR
RRRR
RRRR
RRRR
RRRR
RRRR
RRRR
RRR0
RR00
R000
RRRR
RRRR
RRRR
RRRR
RRRR
RRR0
RR00
R000
0000
0000
0000
0000
RRRR
RRR0
RR00
R000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
Figure 8-14 Address Range and Address Range Start Definition of XADRS1/2/3/
4 register
The XBCONx registers are defined as follows:
XBCON1 (/2/3/4/5/6)
XBUS Control Register
15
14
13
0
0
0
r
r
r
12
11
(Reset value: XXXXH)
10
RDY BS BUS
ENx WCx ACT
x
rw
rw
rw
9
8
0
0
r
r
7
B
TYP
x
rw
6
5
4
3
2
1
0
1
1
MCTCx
r
r
r
rw
0
All XBCONx registers are located in the bitaddressable ESFR memory space. The
respective SFR addresses of XBCON registers can be found in list of SFRs.
User’s Manual
8-38
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
Field
Bits
Type Description
MCTCx
[3:0]
rw
Memory Cycle Time Control 1)
(number of wait states). See BUSCON
BTYPx
[7]
rw
XBUS Type Definition
0
8-bit Demultiplexed Bus
1
16-bit Demultiplexed Bus
BUSACTx
10
rw
XBUS Active Control
0
XBUS (peripheral) disabled
1
XBUS (peripheral) enabled
Enables the XBUS and the according chip select XCSx
for the respective address window (respective XBUS
peripheral), selected with XADRSx window.
Note: Enable/Disable also is controlled with XPERCON
and SYSCON registers.
BSWCx
11
rw
BUSCON Switch Control
0:
Address windows are switched immediately
1:
A tristate waitstate is inserted if the next bus cycle
accesses a different window than the one
controlled by this BUSCON register2)
RDYENx
12
rw
READY Enable
0
The bus cycle length is controlled by bit field
MCTC only
1
The bus cycle length is controlled by the
peripheral using READY signal
1)
When the READY function is selected (RDYENx = 1), only the lower 3 bits of the respective MCTC bit field
define the number of inserted waitstates (0-7), while the MSB of bit field MCTC is unused
2)
A BUSCON switch waitstate is enabled by bit BUSCONx.BSWCx of the address window that is left.
User’s Manual
8-39
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
The External Bus Interface
User’s Manual
8-40
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Watchdog Timer
9
Watchdog Timer
To allow recovery from software or hardware failure, the User’s Manual provides a
Watchdog Timer 1). If the software fails to service this timer before an overflow occurs,
a watchdog timer reset can be initiated and a watchdog timer overflow can be signaled
by wdtint_n_o.
When the watchdog timer reset is enabled (default) and the software has been designed
to service it regularly before it overflows, the watchdog timer will supervise the program
execution as it only will overflow if the program does not progress properly. The
watchdog timer will also time out if a software error was due to hardware related failures.
This prevents the controller from malfunctioning for longer than a user-specified time.
The watchdog timer reset resets the CPU, Interruptcontroller, the External Bus
Controller, the Control Block and the WDT itself.
The wdtint_n_o always shows the occurrence of a watchdog timer overflow. If the
watchdog timer reset is disabled, the WDTINT signal can be used to trigger an interrupt.
The wdtint_n_o signals can be directly connected to one interrupt control node. The
watchdog timer can be used as a running timer and generates a periodical interrupt
request with the occurrence of a timer overflow. In case of an overflow the WDT counter
is automatically reloaded. Nevertheless the automatic reload is overruled in case of a
WDT reset (wdt reset not disabled). The WDT can still be serviced with the execution of
the srvwdt instruction.
Note: The WDT is automatically reloaded in case of a WDT overflow. In case of an
enabled WDT reset, the generated reset resets the WDT and overrules the reload
mechanism.
The watchdog timer provides two 16-bit registers and two subsystem signals:
•
•
•
•
a read-only timer register that contains the current count,
a control register for initialization and reset source detection,
a conf_wdt_en_i subsystem signal to disable globally the WDT and
a wdtint_o subsystem signal to signal a watchdog timer overflow.
The 16-bit watchdog timer is realized as two concatenated 8-bit timers. The upper 8 bits
of the watchdog timer can be preset to a user-programmable value via a watchdog
service access in order to vary the watchdog expire time. The lower 8 bits are reset upon
each service access.
The watchdog timer is a 16-bit up counter which is clocked with the prescaled PDBus+
clock (fPD). The prescaler divides the PDBus+ clock
• by 2 (WDTIN = ’0’, WDTPRE = ’0’), or
• by 4 (WDTIN = ’0’, WDTPRE = ’1’), or
1)
The WDT can be globally disabled by the conf_wdt_en subsystem signal.
User’s Manual
9-1
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Watchdog Timer
• by 128 (WDTIN = ’1’, WDTPRE = ’0’), or
• by 256 (WDTIN = ’1’, WDTPRE = ’1’).
9.1
Operation of the Watchdog Timer
The current count value of the Watchdog Timer is contained in the Watchdog Timer
Register WDT which is a non-bitaddressable read-only register. The operation of the
Watchdog Timer is controlled by its bitaddressable Watchdog Timer Control Register
WDTCON. This register specifies the reload value for the high byte of the timer, selects
the input clock prescaling factor and also provides flags that indicate the source of a
reset.
After any reset a globally enable watchdog timer (conf_wdt_en active) starts counting up
from 0000H with the default frequency fWDT = fPD/256. The default input frequency may
be changed to another frequency (fWDT = fPD/128) by programming the prescaler (bit
WDTIN).
The watchdog timer supports different modes:
• WDT Reset mode: When the watchdog timer is not disabled via instruction DISWDT
it will continue counting up, even during Idle Mode. If it is not serviced via the
instruction SRVWDT by the time the count reaches FFFFH the watchdog timer will
overflow and cause a watchdog timer reset and a wdt overflow will be signaled (wdtint)
as well. But nevertheless the whole subsystem including the WDT itself will be
reseted.
• WDT Interrupt mode: If the TIMEN bit is set, only the generation of watchdog timer
resets is surpressed after the execution of the DISWDT instruction. A watchdog timer
overflow event will still be signaled.
• WDT Disable mode: This mode is enable if the TIMer ENable TIMEN bit in the
WDTCON register is not set, and the watchdog timer reset generation was stopped
with the execution of the DISWDT instruction. In this case the whole WDT counter is
stopped. Neither a watchdog timer reset will be generated nor a watchdog timer
overflow (wdtint_o) event will be signaled.
Instruction DISWDT is a protected 32-bit instruction which will ONLY be executed during
the time between a reset and execution of either the EINIT (End of Initialization) or the
SRVWDT (Service Watchdog Timer) instruction. Either one of these instructions
disables the execution of DISWDT.
Note: The above described protection using the execution of EINIT or SRVWDT must
be implemented inside the WDT block.
A watchdog reset will not complete a running external bus cycle before starting the
internal reset sequence.
To prevent the watchdog timer from overflowing it must be serviced periodically by the
user software. The watchdog timer is serviced with the instruction SRVWDT which is a
protected 32-bit instruction. Servicing the watchdog timer clears the low byte and reloads
User’s Manual
9-2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Watchdog Timer
the high byte of the watchdog timer register WDT with the preset value from bitfield
WDTREL which is the high byte of register WDTCON. After being serviced the watchdog
timer continues counting up from the value (<WDTREL> * 28).
Note: SRVWDT always triggers a timer reload independent of the execution of the EINIT
and DISWDT instruction.
Instruction SRVWDT has been encoded in such a way that the chance of unintentionally
servicing the watchdog timer (e.g. by fetching and executing a bit pattern from a wrong
location) is minimized. When instruction SRVWDT does not match the format for
protected instructions the Protection Fault Trap will be entered, rather than the
instruction be executed.
WDTCON
WDT Control Register
15
14
13
12
11
WDTREL
10
9
8
7
6
WDT TIM
PRE EN
1)
Reset value: 008X1)H
SFR (FFAEH/D7H)
rw
rw
5
4
3
-
-
-
-
-
-
2
1
0
SW WDT WDT
R
R
IN
rh
rh
rw
X=0xx1b
Bit
Function
WDTIN
Watchdog Timer Input Frequency Select (combined with WDTPRE)
Controls the input clock prescaler.
WDTR
Watchdog Timer Reset Indication Flag
SWR
Software Reset Indication Flag
TIMEN
TIMer ENable TIMEN
If the TIMEN bit is set, only the generation of watchdog timer resets is
surpressed after the execution of the DISWDT instruction. A watchdog
timer overflow event will still be signaled.
WDTPRE
Watchdog Timer Input Prescaler Control (combined with WDTIN)
Controls the input clock prescaler.
WDTREL
Watchdog Timer Reload Value (for the high byte of WDT)
The time period for an overflow of the watchdog timer is programmable in two ways:
• the input frequency to the watchdog timer can be selected via a prescaler controlled
by bits WDTPRE and WDTIN in register WDTCON to be
fPD/2, fPD/4, fPD/128, or fPD/256.
• the reload value WDTREL for the high byte of WDT can be programmed in register
WDTCON.
User’s Manual
9-3
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Watchdog Timer
The period PWDT between servicing the watchdog timer and the next overflow can
therefore be determined by the following formula:
PWDT =
2(1 + <WDTPRE> + <WDTIN>*6) * (216 - <WDTREL>*28)
fPD
Note: For safety reasons, the user is advised to rewrite WDTCON each time before the
watchdog timer is serviced.
Table 9-1
Reset Indication Flag Combinations
Reset Indication Flags1)
Event
SWR
WDTR
Hardware Reset (HWRST)
0
0
Software Reset (SRST)
1
0
Watchdog Timer Reset (WDTRST)
0
1
HWRST and SRST
0
0
HWRST and WDTRST
0
0
HWRST, SRST and WDTRST
0
0
SRST and WDTRST
1
1
1)
Description of table entries:
’1’ = flag is set, ’0’ = flag is cleared.
Hardware Reset is indicated after a reset was triggered by a hardware event. In this
case neither the SWR nor the WDTR bit is set. In case of a hardware reset, the software
and watchdog timer reset are surpressed and not visible.
Software Reset is indicated after a reset was triggered by the execution of instruction
SRST.
Watchdog Timer Reset is indicated after a reset triggered by an overflow of the
watchdog timer.
User’s Manual
9-4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Asynchronous/Synchronous Serial Interface (ASC)
10
Asynchronous/Synchronous Serial Interface (ASC)
10.1
Introduction
This document describes the Asynchronous/Synchronous Serial Interface (ASC). The
ASC supports a certain protocol to transfer data via a serial interconnection. It is also
connected to a parallel bus of a microcontroller. The implementation is similar to the
implementation in the C166 microcontrollers, however its parameters are changeable to
work with parallel busses of different width and with different protocols.
Features
• Full duplex asynchronous operating modes
– 8- or 9-bit data frames, LSB first
– Parity bit generation/checking
– One or two stop bits
– Baudrate from 3.75 MBaud to 0.888 Baud (@ 60 MHz module clock fclk)
• Multiprocessor Mode for automatic address/data byte detection
• Loop-back capability
• Half-duplex 8-bit synchronous operating mode
– Baudrate from 7.5 MBaud to 764.4 Baud (@ 60 MHz module clock fclk)
• Double buffered transmitter/receiver
• Interrupt generation
• on a transmitter buffer empty condition
• on a transmit last bit of a frame condition
• on a receiver buffer full condition
• on an error condition (frame, parity, overrun error)
User’s Manual
10-1
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Asynchronous/Synchronous Serial Interface (ASC)
Figure 10-1 shows all funtional relevant interfaces associated with the ASC Kernel.
fclk
Clock
Control
TXD
ASC
Module
Address
Decoder
(Kernel)
Port
RXD
Control
TIR
Interrupt
TBIR
Control
RIR
EIR
BPI
Interface
Product
Interface
Module
Figure 10-1 ASC Interface Diagram
Figure 10-2 shows all of the registers associated with the ASC Kernel.
Control Registers
Data Registers
CON
TBUF
FDV
RBUF
BG
PISEL
CON
FDV
BG
PISEL
Control Register
Fractional Divider Register
Baudrate Timer/Reload Register
Port Input Select Register
TBUF Transmit Buffer Register
RBUF Receive Buffer Register
Figure 10-2 ASC Kernel Registers
All ASC registers are located in the SFR/ESFR memory space. The respective SFR
addresses can be found in list of SFRs.
User’s Manual
10-2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Asynchronous/Synchronous Serial Interface (ASC)
Port Input Select Register
The PISEL register controls the receiver input selection of the ASC module.
PISEL
Port Input Select Register
15
14
13
12
11
(Reset value: 0000H)
10
9
8
7
6
5
4
3
2
0
0
RIS
r
rw
Field
Bits
Typ Description
RIS
[0]
rw
Receiver Input Select
0
Receiver input RXDY0 selected
1
Receiver input RXDY1 selected
0
[15:1]
r
Reserved for future use; reading returns 0;
writing to these bit positions has no effect.
User’s Manual
1
10-3
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Asynchronous/Synchronous Serial Interface (ASC)
10.2
Operational Overview
Figure 10-3 shows a block diagram of the ASC with its operating modes (asynchronous
and synchronous mode).
fclk
Prescaler /
Divider
Baudrate
Timer
$V\QFKURQRXV
0RGH
Serial Port
Control
Receive / Transmit
buffers and
Shift Registers
RXD
fclk
÷2
or
÷3
Baudrate
Timer
TXD
6\QFKURQRXV
0RGH
Serial Port
Control
TXD
Shift Clock
Receive / Transmit
buffers and
Shift Registers
RXD
Figure 10-3 Block Diagram of the ASC
User’s Manual
10-4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Asynchronous/Synchronous Serial Interface (ASC)
10.3
General Operation
The ASC supports full-duplex asynchronous communication up to 3.75 MBaud and
half-duplex synchronous communication up to 7.5 MBaud (@ 60 MHz module clock). In
Synchronous Mode, data are transmitted or received synchronous to a shift clock that is
generated by the microcontroller. In Asynchronous Mode, either 8- or 9-bit data transfer,
parity generation, and the number of stop bits can be selected. Parity, framing, and
overrun error detection is provided to increase the reliability of data transfers.
Transmission and reception of data is double-buffered. For multiprocessor
communication, a mechanism is provided to distinguish address bytes from data bytes.
Testing is supported by a loop-back option. A 13-bit baudrate timer with a versatile input
clock divider circuitry provides the serial clock signal.
A transmission is started by writing to the Transmit Buffer register TBUF. The selected
operating mode determines the number of data bits that will actually be transmitted, so
that, bits written to positions 9 through 15 of register TBUF are always insignificant. Data
transmission is double-buffered, so a new character may be written to the transmit buffer
register before the transmission of the previous character is complete. This allows the
transmission of characters back-to-back without gaps.
Data reception is enabled by the Receiver Enable Bit CON_REN. After reception of a
character has been completed, the received data can be read from the (read-only)
Receive Buffer register RBUF; the received parity bit can also be read if provided by the
selected operating mode. Bits in the upper half of RBUF that are not valid in the selected
operating mode will be read as zeros.
Data reception is double-buffered, so that reception of a second character may already
begin before the previously received character has been read out of the receive buffer
register. In all modes, receive overrun error detection can be selected through bit
CON_OEN. When enabled, the overrun error status flag CON_OE and the error interrupt
request line EIR will be activated when the receive buffer register has not been read by
the time reception of a ninth character is complete. The previously received character in
the receive buffer is overwritten.
The Loop-Back option (selected by bit CON_LB) allows the data currently being
transmitted to be received simultaneously in the receive buffer. This may be used to test
serial communication routines at an early stage without having to provide an external
network. In Loop-back Mode, the alternate input/output functions of the asosiacted Port
pins are not necessary.
Note: Serial data transmission or reception is only possible when the Baudrate
Generator Run Bit CON_R is set to 1. Otherwise, the serial interface is idle.
Do not program the mode control field COM_M to one of the reserved
combinations to avoid unpredictable behavior of the serial interface.
User’s Manual
10-5
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Asynchronous/Synchronous Serial Interface (ASC)
The operating mode of the serial channel ASC is controlled by its control register CON.
This register contains control bits for mode and error check selection, and status flags
for error identification.
CON
Control Register
13
(Reset value: 0000H)
15
14
R
LB BRS ODD FDE OE
FE
FEN/ PEN REN STP
PE OEN RXDI
M
rw
rw
rwh
rwh
rw
rw
12
rw
11
rw
10
rwh
9
8
7
rw
6
rw
5
rw
4
rwh
3
rw
2
1
0
Field
Bits
Typ Description
M
[2:0]
rw
Mode Control
000 8-bit-data for synchronous operation
001 8-bit-data for asynchronous operation
010 Reserved. Do not use this combination
011 7-bit-data and parity for asynchronous
operation
100 9-bit-data for asynchronous operation
101 8-bit-data and wake up bit for asynchronous
operation
110 Reserved. Do not use this combination
111 8-bit-data and parity for asynchronous
operation
STP
[3]
rw
Number of Stop Bits Selection
0
One stop bit
1
Two stop bits
REN
[4]
rwh Receiver Enable Bit
0
Receiver disabled
1
Receiver enabled
Note: bit is cleared by hardware after reception of a
byte in Synchronous Mode
PEN
User’s Manual
[5]
rw
Parity Check Enable
All Asynchronous Modes without IrDA Mode:
0
Ignore parity
1
Check parity
10-6
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Asynchronous/Synchronous Serial Interface (ASC)
Field
Bits
Typ Description
FEN
[6]
rw
Framing Check Enable
(Asynchronous Mode only)
0
Ignore framing errors
1
Check framing errors
OEN
[7]
rw
Overrun Check Enable
0
Ignore overrun errors
1
Check overrun errors
PE
[8]
rwh Parity Error Flag
Set by hardware on a parity error (PEN=1).
Must be cleared by software.
FE
[9]
rwh Framing Error Flag
Set by hardware on a framing error (FEN=1).
Must be cleared by software.
OE
[10]
rwh Overrun Error Flag
Set by hardware on an overrun error (OEN=1).
Must be cleared by software.
FDE
[11]
rw
Fractional Divider Enable
0
Fractional divider disabled
1
Fractional divider enabled and used as
perscaler for baudrate generator
(bit BRS is don’t care)
ODD
[12]
rw
Parity Selection
0
Even parity selected (parity bit of 1 is included
in data stream on odd number of 1 and parity
bit of 0 is included in data stream on even
number of 1)
1
Odd parity selected (parity bit of 1 is included
in data stream on even number of 1 and parity
bit of 0 is included in data stream on odd
number of 1)
BRS
[13]
rw
Baudrate Selection
0
Divide clock by reload-value+constant
(depending on mode)
1
Additionally reduce serial clock to 2/3
Note: BRS is don’t care if FDE=1
(fractional divider selected)
User’s Manual
10-7
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Asynchronous/Synchronous Serial Interface (ASC)
Field
Bits
Typ Description
LB
[14]
rw
Loopback Mode Enabled
0
Loopback Mode disabled.
Standard transmit/receive Mode
1
Loopback Mode enabled
R
[15]
rw
Baudrate Generator Run Control Bit
0
Baudrate generator disabled (ASC inactive)
1
Baudrate generator enabled
Note: BR_VALUE should only be written if R=0.
User’s Manual
10-8
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Asynchronous/Synchronous Serial Interface (ASC)
10.3.1
Asynchronous Operation
Asynchronous Mode supports full-duplex communication in which both transmitter and
receiver use the same data frame format and the same baudrate. Data is transmitted on
line TXD and received on line RXD. Figure 10-4 shows the block diagram of the ASC
when operating in Asynchronous Mode.
FDE
13-Bit Reload Register
Fractional
Divider
fclk
MUX
÷2
fDIV
13-Bit Baudrate Timer
fBR
fBRT
÷3
R
÷16
BRS
M
REN
FEN
PEN
OEN
LB
RXD
Sampling
ODD
PE
STP
FE
OE
RIR
Shift Clock
TIR
Serial Port Control
Shift
Clock
TBIR
EIR
Receive Shift
Register
Transmit Shift
Register
Receive Buffer Reg.
RBUF
Transmit Buffer Reg.
TBUF
Receive Int.
Request
Transmit Int.
Request
Transmit Buffer
Int. Request
Error Int.
Request
TXD
Internal Bus
Figure 10-4 Asynchronous Mode of Serial Channel ASC
User’s Manual
10-9
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Asynchronous/Synchronous Serial Interface (ASC)
10.3.1.1 Asynchronous Data Frames
8-Bit Data Frames
8-bit data frames consist of either eight data bits D7...D0 (CON_M=’001B’), or seven data
bits D6...D0 plus an automatically generated parity bit (CON_M=’011B’). Parity may be
odd or even, depending on bit CON_ODD. An even parity bit will be set if the modulo-2sum of the 7 data bits is 1. An odd parity bit will be cleared in this case. Parity checking
is enabled via bit CON_PEN (always OFF in 8-bit data mode). The parity error flag
CON_PE will be set, along with the error interrupt request flag, if a wrong parity bit is
received. The parity bit itself will be stored in bit RBUF.7.
10-/11-Bit UART Frame
8 Data Bits
&21B0 %
Start
D0
Bit
LSB
0
D1
D2
D3
D4
1
D5
D6
1
D7 (1st) (2nd)
MSB Stop Stop
Bit
Bit
1
1
10-/11-Bit UART Frame
7 Data Bits
&21B0 %
Start
D0
Bit
LSB
0
D1
D2
D3
D4
D5
D6 Parity (1st) (2nd)
MSB Bit Stop Stop
Bit
Bit
Figure 10-5 Asynchronous 8-Bit Frames
9-Bit Data Frames
9-bit data frames consist of either nine data bits D8...D0 (CON_M=’100B’), eight data bits
D7...D0 plus an automatically generated parity bit (CON_M=’111B’), or eight data bits
D7...D0 plus wake-up bit (CON_M=’101B’). Parity may be odd or even, depending on bit
CON_ODD. An even parity bit will be set if the modulo-2-sum of the 8 data bits is 1. An
odd parity bit will be cleared in this case. Parity checking is enabled via bit CON_PEN
(always OFF in 9-bit data and wake-up mode). The parity error flag CON_PE will be set,
along with the error interrupt request flag, if a wrong parity bit is received. The parity bit
itself will be stored in bit RBUF.8.
User’s Manual
10-10
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Asynchronous/Synchronous Serial Interface (ASC)
11-/12-Bit UART Frame
9 Data Bits
Start
D0
Bit
LSB
0
D1
D2
D3
D4
1
D5
D6
D7
1
(1st) (2nd)
Bit 9 Stop Stop
Bit
Bit
&21B0 % Bit 9 = Data Bit D8
&21B0 % Bit 9 = Wake-up Bit
&21B0 % Bit 9 = Parity Bit
Figure 10-6 Asynchronous 9-Bit Frames
In wake-up mode, received frames are transferred to the receive buffer register only if
the 9th bit (the wake-up bit) is 1. If this bit is 0, no receive interrupt request will be
activated and no data will be transferred.
This feature may be used to control communication in a multi-processor system:
When the master processor wants to transmit a block of data to one of several slaves, it
first sends out an address byte to identify the target slave. An address byte differs from
a data byte in that the additional 9th bit is a 1 for an address byte, but is a 0 for a data
byte; so, no slave will be interrupted by a data ’byte’. An address ’byte’ will interrupt all
slaves (operating in 8-bit data + wake-up bit mode), so each slave can examine the eight
LSBs of the received character (the address). The addressed slave will switch to 9-bit
data mode (such as by clearing bit CON_M.0), to enable it to also receive the data bytes
that will be coming (having the wake-up bit cleared). The slaves not being addressed
remain in 8-bit data + wake-up bit mode, ignoring the following data bytes.
10.3.1.2 Asynchronous Transmission
Asynchronous transmission begins at the next overflow of the divide-by-16 baudrate
timer (transition of the baudrate clock fBR), if bit CON_R is set and data has been loaded
into TBUF. The transmitted data frame consists of three basic elements:
– Start bit
– Data field (eight or nine bits, LSB first, including a parity bit, if selected)
– Delimiter (one or two stop bits)
Data transmission is double-buffered. When the transmitter is idle, the transmit data
loaded in the transmit buffer register TBUF is immediately moved to the transmit shift
register, thus freeing the transmit buffer for the next data to be sent. This is indicated by
the transmit Buffer interrupt request line TBIR being activated. TBUF may now be loaded
with the next data, while transmission of the previous data continues.
User’s Manual
10-11
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Asynchronous/Synchronous Serial Interface (ASC)
The transmit interrupt request line TIR will be activated before the last bit of a frame is
transmitted, that is, before the first or the second stop bit is shifted out of the transmit
shift register.
TBUF
Transmit Buffer Register
15
14
13
12
11
(Reset value: 0000H)
10
9
8
7
6
5
4
3
0
TD_VALUE
r
rw
2
1
0
Field
Bits
Typ Description
TD_VALUE
[8:0]
rw
Transmit Data Register Value
TBUF contains the data to be transmitted in either
asynchronous or synchronous operating mode of
the ASC. Data transmission is double buffered.
Therefore, a new value can be written to TBUF
before transmission of the previous value is
completed.
0
[15:9]
r
Reserved for future use; reading returns 0;
writing to these bit positions has no effect.
Note: The transmitter output pin TXD must be configured for alternate data output’.
10.3.1.3 Asynchronous Reception
Asynchronous reception is initiated by a falling edge (1-to-0 transition) on line RXD,
provided that bits CON_R and CON_REN are set. The receive data input line RXD is
sampled at 16 times the rate of the selected baudrate. A majority decision of the 7th, 8th,
and 9th sample determines the effective bit value. This avoids erroneous results that
may be caused by noise.
If the detected value is not a 0 when the start bit is sampled, the receive circuit is reset
and waits for the next 1-to-0 transition at line RXD. If the start bit proves valid, the receive
circuit continues sampling and shifts the incoming data frame into the receive shift
register.
When the last stop bit has been received, the content of the receive shift register are
transferred to the receive data Buffer register RBUF. Simultaneously, the receive
interrupt request line RIR is activated after the 9th sample in the last stop bit time slot (as
programmed), regardless of whether valid stop bits have been received or not. The
User’s Manual
10-12
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Asynchronous/Synchronous Serial Interface (ASC)
receive circuit then waits for the next start bit (1-to-0 transition) at the receive data input
line.
RBUF
Receive Buffer Register
15
14
13
12
11
Reset value: 0000H
10
9
8
7
6
5
4
3
0
RD_VALUE
r
rw
2
1
0
Field
Bits
Typ Description
RD_VALUE
[8:0]
rw
Receive Data Register Value
RBUF contains the received data bits and,
depending on the selected mode, the parity bit in
asynchronous and synchronous operating mode of
the ASC.
In asynchronous operating mode with M=011 (7-bit
data + parity) the received parity bit is written into
RD7.
In asynchronous operating mode with M=111 (8-bit
data + parity) the received parity bit is written into
RD8.
0
[15:9]
r
Reserved for future use; reading returns 0;
writing to these bit positions has no effect.
Note: The receiver input pin RXD must be configured for input.
Asynchronous reception is stopped by clearing bit CON_REN. A currently received
frame is completed including the generation of the receive interrupt request and an error
interrupt request, if appropriate. Start bits that follow this frame will not be recognized.
Note: In wake-up mode, received frames are transferred to the receive FIFO register
only if the 9th bit (the wake-up bit) is 1. If this bit is 0, no receive interrupt request
will be activated and no data will be transferred.
User’s Manual
10-13
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Asynchronous/Synchronous Serial Interface (ASC)
10.3.2
Synchronous Operation
Synchronous Mode supports half-duplex communication, basically for simple I/O
expansion via shift registers. Data is transmitted and received via line RXD while line
TXD outputs the shift clock.
Note: These signals are alternate functions of port pins.
Synchronous Mode is selected with CON_M=’000B’.
Eight data bits are transmitted or received synchronous to a shift clock generated by the
internal baudrate generator. The shift clock is active only as long as data bits are
transmitted or received.
13-Bit Reload Register
fclk
÷2
Mux
fDIV
13-Bit Baudrate Timer
fBR
fBRT
÷3
R
÷4
BRS
M=000B
OE
RIR
Shift Clock
REN
OEN
LB
TXD
RXD
TIR
Serial Port Control
Shift
Clock
0
MUX
1
TBIR
EIR
Receive Shift
Register
Transmit Shift
Register
Receive Buffer Reg.
RBUF
Transmit Buffer Reg.
TBUF
Receive Int.
Request
Transmit Int.
Request
Transmit Buffer
Int. Request
Error Int.
Request
Internal Bus
Figure 10-7 Synchronous Mode of Serial Channel ASC
User’s Manual
10-14
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Asynchronous/Synchronous Serial Interface (ASC)
10.3.2.1 Synchronous Transmission
Synchronous transmission begins within four state times after data has been loaded into
TBUF, provided that CON_R is set and CON_REN is cleared (half-duplex, no reception).
Exception: in loopback mode (bit CON_LB set), CON_REN must be set for reception of
the transmitted byte. Data transmission is double-buffered. When the transmitter is idle,
the transmit data loaded into TBUF is immediately moved to the transmit shift register,
thus freeing TBUF for more data. This is indicated by the transmit Buffer interrupt request
line TBIR being activated. TBUF may now be loaded with the next data, while
transmission of the previous continoues. The data bits are transmitted synchronous with
the shift clock. After the bit time for the eighth data bit, both the TXD and RXD lines will
go high, the transmit interrupt request line TIR is activated, and serial data transmission
stops.
Note: Pin TXD must be configured for alternate data output in order to provide the shift
clock. Pin RXD must also be configured for output during transmission.
10.3.2.2 Synchronous Reception
Synchronous reception is initiated by setting bit CON_REN. If bit CON_R is set, the data
applied at RXD is clocked into the receive shift register synchronous to the clock that is
output at TXD. After the eighth bit has been shifted in, the contents of the receive shift
register are transferred to the receive data buffer RBUF, the receive interrupt request line
RIR is activated, the receiver enable bit CON_REN is reset, and serial data reception
stops.
Note: Pin TXD must be configured for alternate data output in order to provide the shift
clock. Pin RXD must be configured as alternate data input.
Synchronous reception is stopped by clearing bit CON_REN. A currently received byte
is completed, including the generation of the receive interrupt request and an error
interrupt request, if appropriate. Writing to the transmit buffer register while a reception
is in progress has no effect on reception and will not start a transmission.
If a previously received byte has not been read out of a full receive buffer at the time the
reception of the next byte is complete, both the error interrupt request line EIR and the
overrun error status flag CON_OE will be activated/set, provided the overrun check has
been enabled by bit CON_OEN.
10.3.2.3 Synchronous Timing
Figure 10-8 shows timing diagrams of the ASC Synchronous Mode data reception and
data transmission. In idle state, the shift clock level is high. With the beginning of a
synchronous transmission of a data byte, the data is shifted out at RXD with the falling
edge of the shift clock. If a data byte is received through RXD, data is latched with the
rising edge of the shift clock.
User’s Manual
10-15
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Asynchronous/Synchronous Serial Interface (ASC)
Between two consecutive receive or transmit data bytes, one shift clock cycle (fBR) delay
is inserted.
Shift
Receive/Transmit Timing
Shift
Shift
Latch
Latch
Shift Clock
(TXD)
Transmit Data
(RXD)
Data
Bit n
Data
Bit n+1
Data
Bit n+2
Receive Data
(RXD)
Valid
Data n
Valid
Data n+1
Valid
Data n+2
Continuous Transmit Timing
Shift Clock
(TXD)
Transmit Data
(RXD)
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
1. Byte
Receive Data
(RXD)
D0
D1
D2
D3
D4
D2
D3
2. Byte
D5
1. Byte
D6
D7
D0
D1
D2
D3
2. Byte
Figure 10-8 ASC Synchronous Mode Waveforms
User’s Manual
10-16
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Asynchronous/Synchronous Serial Interface (ASC)
10.3.3
Baudrate Generation
The serial channel ASC has its own dedicated 13-bit baudrate generator with reload
capability, allowing baudrate generation independent of other timers.
The baudrate generator is clocked with a clock (fDIV) derived via a prescaler from the
ASC input clock fclk. The baudrate timer counts downwards and can be started or
stopped through the baudrate generator run bit CON_R. Each underflow of the timer
provides one clock pulse to the serial channel. The timer is reloaded with the value
stored in its 13-bit reload register each time it underflows. The resulting clock fBRT is
again divided by a factor for the baudrate clock (±16 in asynchronous modes and ±4 in
synchronous mode). The prescaler is selected by the bits CON_BRS and CON_FDE. In
addition to the two fixed dividers, a fractional divider prescaler unit is available in the
asynchronous operating modes that allows selection of prescaler divider ratios of n/512
with n=0...511. Therefore, the baudrate of ASC is determined by the module clock, the
content of FDV, the reload value of BG, and the operating mode (asynchronous or
synchronous).
Register BG is the dual-function Baudrate Generator/Reload register. Reading BG
returns the contents of the timer BR_VALUE (bits 15...13 return zero), while writing to
BG always updates the reload register (bits 15...13 are insignificant).
An auto-reload of the timer with the contents of the reload register is performed each time
CON_BG is written to. However, if CON_R is cleared at the time a write operation to
CON_BG is performed, the timer will not be reloaded until the first instruction cycle after
CON_R was set. For a clean baudrate initialization, CON_BG should be written only if
CON_R is reset. If CON_BG is written while CON_R is set, unpredictable behavior of the
ASC may occur during running transmit or receive operations.
The ASC baudrate timer reload register BG contains the 13-bit reload value for the
baudrate timer in Asynchronous and Synchronous modes.
BG
Baudrate Timer/Reload Register
15
14
13
12
11
10
Reset value: 0000H
9
8
7
6
5
0
BR_VALUE
r
rw
4
3
2
1
0
10.3.3.1 Baudrate in Asynchronous Mode
For asynchronous operation, the baudrate generator provides a clock fBRT with sixteen
times the rate of the established baudrate. Every received bit is sampled at the 7th, 8th,
and 9th cycle of this clock. The clock divider circuitry, which generates the input clock for
the 13-bit baudrate timer, is extended by a fractional divider circuitry that allows
adjustment for more accurate baudrate and the extension of the baudrate range.
User’s Manual
10-17
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Asynchronous/Synchronous Serial Interface (ASC)
Field
Bits
Typ Description
BR_VALUE
[12:0]
rw
Baudrate Timer/Reload Value
Reading returns the 13-bit contents of the baudrate
timer; writing loads the baudrate timer/reload value.
Note: BG should only be written if R=’0’.
0
[15:13] r
Reserved for future use; reading returns 0;
writing to these bit positions has no effect.
The baudrate of the baudrate generator depends on the following bits and register
values:
–
–
–
–
Input clock fclk
Selection of the baudrate timer input clock fDIV by bits CON_FDE and CON_BRS
If bit CON_FDE=1 (fractional divider): value of register CON_FDV
Value of the 13-bit reload register BG
The output clock of the baudrate timer with the reload register is the sample clock in the
asynchronous modes of the ASC. For baudrate calculations, this baudrate clock fBR is
derived from the sample clock fDIV by a division by 16.
The ASC fractional divider register FDV contains the 9-bit divider value for the fractional
divider (asynchronous mode only). It is also used for reference clock generation of the
autobaud detection unit.
FDV
Fractional Divider Register
15
14
13
12
11
Reset value: 0000H
10
9
8
7
6
5
4
3
0
FD_VALUE
r
rw
2
1
0
Field
Bits
Typ Description
FD_VALUE
[8:0]
rw
Fractional divider register value
FD_VALUE contains the 9-bit value of the fractional
divider which defines the fractional divider ratio n/
512 (n=0...511). With n=0, the fractional divider is
switched off (input=output frequency,
fDIV = fclk, see Figure 10-9).
0
[15:9]
r
Reserved for future use; reading returns 0;
writing to these bit positions has no effect.
User’s Manual
10-18
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Asynchronous/Synchronous Serial Interface (ASC)
13-Bit Reload Register
FDE
Fractional
Divider
fclk
Mux
÷2
R
÷16
fDIV
13-Bit Baudrate Timer
fBR Baud
Rate
Clock
Sample
Clock
fBRT
÷3
BRS
)'(
BRS
Selected Divider
0
0
÷2
0
1
÷3
1
X
Fractional Divider
Figure 10-9 ASC Baudrate Generator Circuitry in Asynchronous Modes
Using the fixed Input Clock Divider
The baudrate for asynchronous operation of serial channel ASC when using the fixed
input clock divider ratios (CON_FDE=0) and the required reload value for a given
baudrate can be determined by the following formulas:
Table 10-1
Asynchronous Baudrate Formulas using the Fixed Input Clock
Dividers
FDE
BRS
BG
0
0
0 ... 8191
Formula
Baudrate =
BG =
1
Baudrate =
BG =
User’s Manual
10-19
fclk
32 x (BG+1)
fclk
32 x Baudrate
-1
fclk
48 x (BG+1)
fkw_clk
-1
48 x Baudrate
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Asynchronous/Synchronous Serial Interface (ASC)
BG represents the contents of the reload register BG (BR_VALUE), taken as unsigned
13-bit integer.
The maximum baudrate that can be achieved for the asynchronous modes when using
the two fixed clock dividers and a module clock of 60 MHz is 1.875 MBaud. Table 10-2
lists various commonly used baudrates together with the required reload values and the
deviation errors compared to the intended baudrate.
Table 10-2
Baudrate
Typical Asynchronous Baudrates using the Fixed Input Clock
Dividers
BRS = ‘0’, fclk = 60 MHz
BRS = ‘1’, fclk = 60 MHz
Deviation
Error
Reload Value Deviation
Error
Reload Value
1.875 MBaud
---
0000H
---
---
1.25 MBaud
---
---
---
0000H
19.2 KBaud
+0.7 % / -0.4 % 0060H / 0061H +0.2 % / -1.4 % 0040H / 0041H
9600 Baud
+0.2 % / -0.4 % 00C2H /
00C3H
4800 Baud
+0.2 % / -0.1 % 0185H / 0186H +0.2 % / -0.2 % 0104H / 0105H
2400 Baud
+0.0 % / -0.1 % 030CH /
030DH
+0.2 % / -0.0 % 0207H / 0208H
1200 Baud
+0.0 % / -0.0 % 0619H /
061AH
+0.1 % / -0.0 % 0410H / 0411H
+0.2 % / -0.6 % 0081H / 0082H
Note: CON_FDE must be 0 to achieve the baudrates in the table above. The deviation
errors given in the table above are rounded. Using a baudrate crystal will provide
correct baudrates without deviation errors.
Using the Fractional Divider
When the fractional divider is selected, the input clock fDIV for the baudrate timer is
derived from the module clock fclk by a programmable divider. If CON_FDE is set, the
fractional divider is activated. It divides fclk by a fraction of n/512 for any value of n from
0 to 511. If n=0, the divider ratio is 1, which means that fDIV=fclk. In general, the fractional
divider allows the baudrate to be programmed with much more accuracy than with the
two fixed prescaler divider stages.
BG represents the contents of the reload register BG (BR_VALUE), taken as an
unsigned 13-bit integer.
FDV represents the contents of the fractional divider register (FD_VALUE) taken as an
unsigned 9-bit integer.
User’s Manual
10-20
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Asynchronous/Synchronous Serial Interface (ASC)
Table 10-3
Asynchronous Baudrate Formulas using the Fractional Input Clock
Divider
FDE
BRS
BG
FDV
Formula
1
-
1 ... 8191 1 ... 511
0
Table 10-4
Baudrate =
Baudrate =
FDV
512
x
fclk
16 x (BG+1)
fclk
16 x (BG+1)
Typical Asynchronous Baudrates using the Fractional Input Clock
Divider
fclk
Desired
Baudrate
BG
FDV
Resulting
Baudrate
40 MHz
115.2 kBaud
15H
1F7H
115.214 kBaud
0.01 %
57.6 kBaud
26H
1F7H
57.607 kBaud
0.01 %
38.4 kBaud
41H
1F7H
38.404 kBaud
0.01 %
19.2 kBaud
83H
1F7H
19.202 kBaud
0.01 %
115.2 kBaud
20H
1F7H
115.214 kBaud
0.01 %
57.6 kBaud
41H
1F7H
57.607 kBaud
0.01 %
38.4 kBaud
61H
1FDH
38.415 kBaud
0.04 %
19.2 kBaud
C5H
1FDH
19.207 kBaud
0.04 %
60 MHz
Deviation
Note: ApNote AP2423 provides a program ’ASC.EXE’ which allows calculation of
values for the FDV and BG registers depending on fclk, the requested baudrate,
and the maximum deviation.
10.3.3.2 Baudrate in Synchronous Mode
For synchronous operation, the baudrate generator provides a clock with four times the
rate of the established baudrate.(see Figure 10-10).
User’s Manual
10-21
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Asynchronous/Synchronous Serial Interface (ASC)
13-Bit Reload Register
÷2
fclk
fDIV
Mux
13-Bit Baudrate Timer
fBRT
Shift /
Sample
Clock
÷4
÷3
R
BRS
BRS
Selected Divider
0
÷2
1
÷3
Figure 10-10 ASC Baudrate Generator Circuitry in Synchronous Mode
The baudrate for synchronous operation of serial channel ASC can be determined by the
formulas as shown in Table 10-5.
Table 10-5
Synchronous Baudrate Formulas
SBRS
BG
0
0 ... 8191
1
Formula
Baudrate =
fclk
8 x (BG+1)
BG =
fclk
8 x Baudrate
-1
Baudrate =
fclk
12 x (BG+1)
BG =
fclk
12 x Baudrate
-1
BG represents the contents of the reload register (BR_VALUE), taken as an unsigned
13-bit integers.
The maximum baudrate that can be achieved in synchronous mode when using a
module clock of 60 MHz is 7.5 MBaud.
User’s Manual
10-22
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Asynchronous/Synchronous Serial Interface (ASC)
10.3.4
Hardware Error Detection Capabilities
To improve the safety of serial data exchange, the serial channel ASC provides an error
interrupt request flag to indicate the presence of an error, and three (selectable) error
status flags in register CON to indicate which error has been detected during reception.
Upon completion of a reception, the error interrupt request line EIR will be activated
simultaneously with the receive interrupt request line RIR, if one or more of the following
conditions are met:
– If the framing error detection enable bit CON_FEN is set and any of the expected
stop bits is not high, the framing error flag CON_FE is set, indicating that the error
interrupt request is due to a framing error (Asynchronous Mode only).
– If the parity error detection enable bit CON_PEN is set in the modes where a parity
bit is received, and the parity check on the received data bits proves false, the parity
error flag CON_PE is set, indicating that the error interrupt request is due to a parity
error (Asynchronous Mode only).
– If the overrun error detection enable bit CON_OEN is set and the last character
received was not read out of the receive buffer by software or by a DMA transfer at
the time the reception of a new frame is complete, the overrun error flag CON_OE
is set indicating that the error interrupt request is due to an overrun error
(Asynchronous and Synchronous Mode).
10.3.5
Interrupts
Four interrupt sources are provided for serial channel ASC. Line TIC indicates a transmit
interrupt, TBIC indicates a transmit FIFO interrupt, RIC indicates a receive interrupt, and
SEIC indicates an error interrupt of the serial channel. The interrupt output lines TBIR,
TIR, RIR, and EIR are activated (active state) for two periods of the module clock fclk.
The cause of an error interrupt request (framing, parity, overrun error) can be identified
by the error status flags FE, PE, and OE located in control register CON.
Note: In contrast to the error interrupt request line EIR, the error status flags FE/PE/OE
are not reset automatically but must be cleared by software.
For normal operation (other than error interrupt) the ASC provides three interrupt
requests to control data exchange via this serial channel:
– TBIR is activated when data is moved from TBUF to the transmit shift register.
– TIR is activated before the last bit of an asynchronous frame is transmitted, or after
the last bit of a synchronous frame has been transmitted.
– RIR is activated when the received frame is moved to RBUF.
While the task of the receive interrupt handler is quite clear, the transmitter is serviced
by two interrupt handlers. This provides advantages for the servicing software.
For single transfers, it is sufficient to use the transmitter interrupt (TIR), which indicates
that all the previously loaded data has been transmitted except for the last bit of an
asynchronous frame.
User’s Manual
10-23
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Asynchronous/Synchronous Serial Interface (ASC)
For multiple back-to-back transfers, it is necessary to load the following piece of data
until the time the last bit of the previous frame has been transmitted. In Asynchronous
Mode, this leaves just one bit-time for the handler to respond to the transmitter interrupt
request; in Synchronous Mode it is completly impossible at all if no FIFO is present.
Using the transmit buffer interrupt (TBIR) to reload transmit data provides the time to
transmit a complete frame for the service routine, as TBUF may be reloaded while the
previous data is still being transmitted.
Asynchronous Mode
TIR
TBIR
RIR
Stop
Stop
RIR
Start
TBIR
Start
Stop
Idle
Start
TBIR
TIR
TIR
Idle
RIR
Synchronous Mode
TIR
TBIR
TIR
TBIR
TIR
TBIR
Idle
Idle
RIR
RIR
RIR
Figure 10-11 ASC Interrupt Generation
As shown in Figure 10-11, TBIR is an early trigger for the reload routine, while TIR
indicates the completed transmission. Therefore, software using handshake should rely
on TIR at the end of a data block to ensure that all data has actually been transmitted.
Note: Refer to the general Interrupt Control Register description for an explanation of the
control fields
User’s Manual
10-24
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
High-Speed Synchronous Serial Interface (SSC)
11
High-Speed Synchronous Serial Interface (SSC)
11.1
Introduction
The High-Speed Synchronous Serial Interface (SSC) supports both full-duplex and halfduplex serial synchronous communication up to 30 MBaud (@ 60 MHz module clock).
The serial clock signal can be generated by the SSC itself (Master Mode) or can be
received from an external master (Slave Mode). Data width, shift direction, clock polarity,
and phase are programmable. This allows communication with SPI-compatible devices.
Transmission and reception of data is double-buffered. A 16-bit baudrate generator
provides the SSC with a separate serial clock signal.
Features:
• Master and Slave Mode operation
– Full-duplex or half-duplex operation
• Flexible data format
– Programmable number of data bits: 2 to 16 bits
– Programmable shift direction: LSB or MSB shift first
– Programmable clock polarity: idle low or high state for the shift clock
– Programmable clock/data phase: data shift with leading or trailing edge of the shift
clock
• Baudrate generation from 30 MBaud to 457.76 Baud (@ 60 MHz module clock)
• Interrupt generation
– On a transmitter empty condition
– On a receiver full condition
– On an error condition (receive, phase, baudrate, transmit error)
User’s Manual
11-1
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
High-Speed Synchronous Serial Interface (SSC)
Figure 11-1 shows all funtional relevant interfaces associated with the SSC Kernel.
fclk
TXD
Master
Control
RXD
SSC
Module
Address
Decoder
(Kernel)
TXD
Slave
Clock
RXD
Port
Control
EIRQ
Control
MS_CLK
SCLK
Interrupt
RIRQ
SS_CLK
TIRQ
BPI
Interface
Product
Interface
Module
Figure 11-1 SSC Interface Diagram
Figure 11-2 shows all of the registers associated with the SSC Kernel.
Control Registers
Data Registers
CON
TB
BR
RB
CON
BR
TB
RB
Control Register
Baudrate Timer Reload Register
Transmit Buffer Register
Receive Buffer Register
Figure 11-2 SSC Kernel Registers
All SSC registers are located in the SFR/ESFR memory space. The respective SFR
addresses can be found in list of SFRs.
User’s Manual
11-2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
High-Speed Synchronous Serial Interface (SSC)
11.2
General Operation
The SSC supports full-duplex and half-duplex synchronous communication up to
30 MBaud (@ 60 MHz module clock). The serial clock signal can be generated by the
SSC itself (Master Mode) or can be received from an external master (Slave Mode). Data
width, shift direction, clock polarity, and phase are programmable. This allows
communication with SPI-compatible devices. Transmission and reception of data is
double-buffered. A 16-bit baudrate generator provides the SSC with a separate serial
clock signal.
The high-speed synchronous serial interface can be configured in a very flexible way, so
it can be used with other synchronous serial interfaces, can serve for master/slave or
multimaster interconnections or can operate compatible with the popular SPI interface.
Thus, the SSC can be used to communicate with shift registers (IO expansion),
peripherals (e.g. EEPROMs etc.) or other controllers (networking). The SSC supports
half-duplex and full-duplex communication. Data is transmitted or received on lines TXD
and RXD, normally connected with pins MTSR (Master Transmit / Slave Receive) and
MRST (Master Receive / Slave Transmit). The clock signal is output via line MS_CLK
(Master Serial Shift Clock) or input via line SS_CLK (Slave Serial Shift Clock). Both lines
are normally connoted to pin SCLK. These pins are alternate functions of port pins.
User’s Manual
11-3
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
High-Speed Synchronous Serial Interface (SSC)
fclk
Baudrate
Generator
SS_CLK
MS_CLK
Clock
Control
Shift
Clock
RIR
Receive Int. Request
SSC Control Block TIR
Register CON
EIR
Status
Transmit Int. Request
Error Int. Request
Control
TXD(Master)
16-Bit Shift Register
Pin
Control
RXD(Slave)
TXD(Slave)
RXD(Master)
Transmit Buffer
Register TB
Receive Buffer
Register RB
Internal Bus
Figure 11-3 Synchronous Serial Channel SSC Block Diagram
User’s Manual
11-4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
High-Speed Synchronous Serial Interface (SSC)
11.2.1
Operating Mode Selection
The operating mode of the serial channel SSC is controlled by its control register CON.
This register serves two purposes:
– During programming (SSC disabled by CON.EN=0), it provides access to a set of
control bits
– During operation (SSC enabled by CON.EN=1), it provides access to a set of status
flags.
Configuration Register
This register contains control bits for mode and error check selection, and status flags
for error identification. Depending on bit EN, either control functions or status flags and
master/slave control is enabled.
CON.EN = 0: Programming Mode
CON
Control Register
15
14
13
EN
MS
0
rw
rw
r
(Reset value: 0000H)
12
11
10
9
8
A
REN BEN PEN REN TEN
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
LB
PO
PH
HB
BM
rw
rw
rw
rw
rw
0
Field
Bits
Type
Description
BM
[3:0]
rw
Data Width Selection
0000 Reserved. Do not use this combination.
0001 1111 Transfer Data Width is 2...16 bit (<BM>+1)
HB
4
rw
Heading Control
0
Transmit/Receive LSB First
1
Transmit/Receive MSB First
PH
5
rw
Clock Phase Control
0
Shift transmit data on the leading clock edge,
latch on trailing edge
1
Latch receive data on leading clock edge, shift
on trailing edge
PO
6
rw
Clock Polarity Control
0
Idle clock line is low, leading clock edge is lowto-high transition
1
Idle clock line is high, leading clock edge is highto-low transition
User’s Manual
11-5
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
High-Speed Synchronous Serial Interface (SSC)
Field
Bits
Type
Description
LB
7
rw
Loop Back Control
0
Normal output
1
Receive input is connected with transmit output
(half-duplex mode)
TEN
8
rw
Transmit Error Enable
0
Ignore transmit errors
1
Check transmit errors
REN
9
rw
Receive Error Enable
0
Ignore receive errors
1
Check receive errors
PEN
10
rw
Phase Error Enable
0
Ignore phase errors
1
Check phase errors
BEN
11
rw
Baudrate Error Enable
0
Ignore baudrate errors
1
Check baudrate errors
AREN
12
rw
Automatic Reset Enable
0
No additional action upon a baudrate error
1
The SSC is automatically reset upon a baudrate
error
MS
14
rw
Master Select
0
Slave Mode. Operate on shift clock received via
SCLK.
1
Master Mode. Generate shift clock and output it
via SCLK.
EN
15
rw
Enable Bit = ‘0’
Transmission and reception disabled. Access to
control bits.
0
13
r
Reserved; returns ‘0’ if read; should be written with ‘0’;
CON.EN = 1: Operating Mode
CON
Control Register
15
14
13
EN
MS
0
rw
rw
r
User’s Manual
(Reset value: 0000H)
12
11
10
9
8
7
6
5
4
BSY BE
PE
RE
TE
–
–
–
–
rwh
rwh
rwh
rh
rwh
11-6
r
3
2
1
0
BC
rw
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
High-Speed Synchronous Serial Interface (SSC)
Field
Bits
Type Description
BC
[3:0]
rh
Bit Count Field
0001 1111 Shift counter is updated with every shifted bit.
Do not write to !!!
TE
8
rwh
Transmit Error Flag
0
No error
1
Transfer starts with the slave’s transmit buffer not
being updated
RE
9
rwh
Receive Error Flag
0
No error
1
Reception completed before the receive buffer
was read
PE
19
rwh
Phase Error Flag
0
No error
1
Received data changes around sampling clock
edge
BE
11
rwh
Baudrate Error Flag
0
No error
1
More than factor 2 or 0.5 between slave’s actual
and expected baudrate
BSY
12
rh
Busy Flag
Set while a transfer is in progress. Do not write to!!!
MS
14
rw
Master Select Bit
0
Slave Mode. Operate on shift clock received via
SCLK.
1
Master Mode. Generate shift clock and output it
via SCLK.
EN
15
rw
Enable Bit = ‘1’
Transmission and reception enabled. Access to status
flags and M/S control
–
[7:4]
-
Reserved:
0
13
r
Reserved; returns ‘0’ if read; should be written with ‘0’;
Note: The target of an access to CON (control bits or flags) is determined by the state of
CON.EN prior to the access; that is, writing C057H to CON in programming mode
(CON.EN=0) will initialize the SSC (CON.EN was 0) and then turn it on
(CON.EN=1). When writing to CON, ensure that reserved locations receive zeros.
User’s Manual
11-7
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
High-Speed Synchronous Serial Interface (SSC)
The shift register of the SSC is connected to both the transmit lines and the receive lines
via the pin control logic (see block diagram in Figure 11-3). Transmission and reception
of serial data are synchronized and take place at the same time, i.e. the same number
of transmitted bits is also received. Transmit data is written into the Transmit Buffer (TB).
It is moved to the shift register as soon as this is empty. An SSC master (CON.MS=1)
immediately begins transmitting, while an SSC slave (CON.MS=0) will wait for an active
shift clock. When the transfer starts, the busy flag CON.BSY is set and the Transmit
Interrupt Request line TIR will be activated to indicate that register TB may be reloaded
again. When the programmed number of bits (2...16) has been transferred, the contents
of the shift register are moved to the Receive Buffer RB and the Receive Interrupt
Request line RIR will be activated. If no further transfer is to take place (TB is empty),
CON.BSY will be cleared at the same time. Software should not modify CON.BSY, as
this flag is hardware controlled.
Transmitter Buffer Register
The SSC transmitter buffer register TB contains the transmit data value.
TB
Transmitter Buffer Register
15
14
13
12
11
10
(Reset value: 0000H)
9
8
7
6
5
4
3
2
1
0
TB_VALUE
rw
Field
Bits
Type Description
TB_VALUE
[15:0]
rw
Transmit Data Register Value
TB_VALUE is the data value to be transmitted.
Unselected bits of TB are ignored during
transmission.
Receiver Buffer Register
The SSC receiver buffer register RB contains the receive data value.
RB
Receiver Buffer Register
15
14
13
12
11
(Reset value: 0000H)
10
9
8
7
6
5
4
3
2
1
0
RB_VALUE
rH
User’s Manual
11-8
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
High-Speed Synchronous Serial Interface (SSC)
Field
Bits
Type Description
RB_VALUE
[15:0]
rh
Receive Data Register Value
RB contains the received data value RB_VALUE.
Unselected bits of RB will be not valid and should be
ignored.
Note: Only one SSC (etc.) can be master at a given time.
The transfer of serial data bits can be programmed in many respects:
–
–
–
–
The data width can be specified from 2 bits to 16 bits
A transfer may start with either the LSB or the MSB
The shift clock may be idle low or idle high
The data bits may be shifted with the leading edge or the trailing edge of the shift
clock signal
– The baudrate may be set from 457.76 Baud up to 30 MBaud (@ 60 MHz module
clock)
– The shift clock can be generated (MS_CLK) or can be received (SS_CLK)
These features allow the adaptation of the SSC to a wide range of applications in which
serial data transfer is required.
The Data Width Selection supports the transfer of frames of any data length, from 2-bit
“characters” up to 16-bit “characters”. Starting with the LSB (CON.HB=0) allows
communication with SSC devices in Synchronous Mode or with 8051 like serial
interfaces for example. Starting with the MSB (CON.HB=1) allows operation compatible
with the SPI interface.
Regardless of the data width selected and whether the MSB or the LSB is transmitted
first, the transfer data is always right-aligned in registers TB and RB, with the LSB of the
transfer data in bit 0 of these registers. The data bits are rearranged for transfer by the
internal shift register logic. The unselected bits of TB are ignored; the unselected bits of
RB will not be valid and should be ignored by the receiver service routine.
The Clock Control allows the adaptation of transmit and receive behavior of the SSC to
a variety of serial interfaces. A specific shift clock edge (rising or falling) is used to shift
out transmit data, while the other shift clock edge is used to latch in receive data. Bit
CON.PH selects the leading edge or the trailing edge for each function. Bit CON.PO
selects the level of the shift clock line in the idle state. Thus, for an idle-high clock, the
leading edge is a falling one, a 1-to-0 transition (see Figure 11-4).
User’s Manual
11-9
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
High-Speed Synchronous Serial Interface (SSC)
CON. CON.
PO
PH
0
0
0
1
1
0
1
1
Shift Clock
MS_CLK/SS_CLK
Pins
MTSR/MRST
First
Bit
Transmit Data
Last
Bit
Latch Data
Shift Data
Figure 11-4 Serial Clock Phase and Polarity Options
11.2.2
Full-Duplex Operation
The various devices are connected through three lines. The definition of these lines is
always determined by the master: The line connected to the master’s data output line
TXD is the transmit line; the receive line is connected to its data input line RXD; the shift
clock line is either MS_CLK or SS_CLK. Only the device selected for master operation
generates and outputs the shift clock on line MS_CLK. All slaves receive this clock; so,
their pin SCLK must be switched to input mode. The output of the master’s shift register
is connected to the external transmit line, which in turn is connected to the slaves’ shift
register input. The output of the slaves’ shift register is connected to the external receive
line in order to enable the master to receive the data shifted out of the slave. The external
connections are hard-wired, the function and direction of these pins is determined by the
master or slave operation of the individual device.
Note: The shift direction shown in the figure applies for MSB-first operation as well as for
LSB-first operation.
When initializing the devices in this configuration, one device must be selected for
master operation while all other devices must be programmed for slave operation.
Initialization includes the operating mode of the device's SSC and also the function of
the respective port lines.
User’s Manual
11-10
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
High-Speed Synchronous Serial Interface (SSC)
Master
Device #1
Device #2
Shift Register
Clock
Slave
Shift Register
MTSR
Transmit
MTSR
MRST
Receive
MRST
CLK
Clock
CLK
Clock
Device #3
Slave
Shift Register
MTSR
MRST
CLK
Clock
Figure 11-5 SSC Full-Duplex Configuration
The data output pins MRST of all slave devices are connected together onto the one
receive line in the configuration shown in Figure 11-5. During a transfer each slave shifts
out data from its shift register. There are two ways to avoid collisions on the receive line
due to different slave data:
– Only one slave drives the line, i.e. enables the driver of its MRST pin. All the other
slaves must have their MRST pins programmed as input so only one slave can put
its data onto the master's receive line. Only receiving data from the master is
possible. The master selects the slave device from which it expects data either by
separate select lines, or by sending a special command to this slave. The selected
slave then switches its MRST line to output until it gets a de-selection signal or
command.
– The slaves use open drain output on MRST. This forms a wired-AND connection.
The receive line needs an external pull-up in this case. Corruption of the data on
the receive line sent by the selected slave is avoided when all slaves not selected
for transmission to the master only send ones (1s). Because this high level is not
actively driven onto the line, but only held through the pull-up device, the selected
slave can pull this line actively to a low level when transmitting a zero bit. The
User’s Manual
11-11
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
High-Speed Synchronous Serial Interface (SSC)
master selects the slave device from which it expects data either by separate select
lines or by sending a special command to this slave.
After performing the necessary initialization of the SSC, the serial interfaces can be
enabled. For a master device, the alternate clock line will now go to its programmed
polarity. The alternate data line will go to either 0 or 1 until the first transfer will start. After
a transfer, the alternate data line will always remain at the logic level of the last
transmitted data bit.
When the serial interfaces are enabled, the master device can initiate the first data
transfer by writing the transmit data into register TB. This value is copied into the shift
register (assumed to be empty at this time), and the selected first bit of the transmit data
will be placed onto the TXD line on the next clock from the baudrate generator
(transmission starts only if CON.EN=1). Depending on the selected clock phase, a clock
pulse will also be generated on the MS_CLK line. At the same time, with the opposite
clock edge, the master latches and shifts in the data detected at its input line RXD. This
“exchanges” the transmit data with the receive data. Because the clock line is connected
to all slaves, their shift registers will be shifted synchronously with the master's shift
register—shifting out the data contained in the registers, and shifting in the data detected
at the input line. After the preprogrammed number of clock pulses (via the data width
selection), the data transmitted by the master is contained in all the slaves’ shift
registers, while the master's shift register holds the data of the selected slave. In the
master and all slaves, the content of the shift register are copied into the receive buffer
RB and the receive interrupt line RIR is activated.
A slave device will immediately output the selected first bit (MSB or LSB of the transfer
data) at line RXD when the contents of the transmit buffer are copied into the slave's shift
register. Bit CON.BSY is not set until the first clock edge at SS_CLK appears. The slave
device will not wait for the next clock from the baudrate generator, as the master does.
The reason for this is that, depending on the selected clock phase, the first clock edge
generated by the master may already be used to clock in the first data bit. Thus, the
slave's first data bit must already be valid at this time.
Note: On the SSC, a transmission and a reception takes place at the same time,
regardless of whether valid data has been transmitted or received.
User’s Manual
11-12
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
High-Speed Synchronous Serial Interface (SSC)
11.2.3
Half-Duplex Operation
In a Half-Duplex Mode, only one data line is necessary for both receiving and
transmitting of data. The data exchange line is connected to both the MTSR and MRST
pins of each device, the shift clock line is connected to the SCLK pin.
The master device controls the data transfer by generating the shift clock, while the slave
devices receive it. Due to the fact that all transmit and receive pins are connected to the
one data exchange line, serial data may be moved between arbitrary stations.
Similar to Full-Duplex Mode, there are two ways to avoid collisions on the data exchange
line:
– only the transmitting device may enable its transmit pin driver
– the non-transmitting devices use open drain output and send only ones.
Because the data inputs and outputs are connected together, a transmitting device will
clock in its own data at the input pin (MRST for a master device, MTSR for a slave). By
this method, any corruptions on the common data exchange line are detected if the
received data is not equal to the transmitted data.
Master
Device #1
Transmit
Device #2
Shift Register
Shift Register
Clock
Slave
MTSR
MTSR
MRST
MRST
CLK
Clock
CLK
Common
Transmit/
Receive Device #3
Line
Clock
Slave
Shift Register
MTSR
MRST
CLK
Clock
Figure 11-6 SSC Half-Duplex Configuration
User’s Manual
11-13
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
High-Speed Synchronous Serial Interface (SSC)
11.2.4
Continuous Transfers
When the transmit interrupt request flag is set, it indicates that the transmit buffer TB is
empty and ready to be loaded with the next transmit data. If TB has been reloaded by
the time the current transmission is finished, the data is immediately transferred to the
shift register and the next transmission will start without any additional delay. On the data
line, there is no gap between the two successive frames. For example, two byte transfers
would look the same as one word transfer. This feature can be used to interface with
devices that can operate with or require more than 16 data bits per transfer. It is just a
matter of software, how long a total data frame length can be. This option can also be
used to interface to byte-wide and word-wide devices on the same serial bus, for
instance.
Note: Of course, this can happen only in multiples of the selected basic data width,
because it would require disabling/enabling of the SSC to reprogram the basic
data width on-the-fly.
User’s Manual
11-14
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
High-Speed Synchronous Serial Interface (SSC)
11.2.5
Baudrate Generation
The serial channel SSC has its own dedicated 16-bit baudrate generator with 16-bit
reload capability, allowing baudrate generation independent of the timers. Figure 11-3
shows the baudrate generator. Figure 11-7 shows the baudrate generator of the SSC in
more detail.
16-Bit Reload Register
fclk
.. 2
fMS_CLK/SS_CLK
16-Bit Counter
fMS_CLK max in Master Mode
fclk / 2
fSS_CLK
fclk / 4
max
in Slave Mode
Figure 11-7 SSC Baudrate Generator
The baudrate generator is clocked with the module clock fclk. The timer counts
downwards. Register BR is the dual-function Baudrate Generator/Reload register.
Reading BR, while the SSC is enabled, returns the content of the timer. Reading BR,
while the SSC is disabled, returns the programmed reload value. In this mode the
desired reload value can be written to BR.
Baudrate Timer Reload Register
The SSC baudrate timer reload register BR contains the 16-bit reload value for the
baudrate timer.
BR
Baudrate Timer Reload Register
15
14
13
12
11
10
(Reset value: 0000H)
9
8
7
6
5
4
3
2
1
0
BR_VALUE
rw
Note: Never write to BR while the SSC is enabled.
The formulas below calculate either the resulting baudrate for a given reload value, or
the required reload value for a given baudrate:
User’s Manual
11-15
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
High-Speed Synchronous Serial Interface (SSC)
Baudrate =
fclk
BR =
2 * (<BR> + 1)
Field
Bits
Type Description
BR_VALUE
[15:0]
rw
fclk
2 * Baudrate
-1
Baudrate Timer/Reload Register Value
Reading BR returns the 16-bit content of the baudrate
timer. Writing BR loads the baudrate timer reload
register with BR_VALUE.
<BR> represents the contents of the reload register, taken as unsigned 16-bit integer;
while Baudrate is equal to fMS_CLK/SS_CLK as shown in Figure 11-7.
The maximum baudrate that can be achieved when using a module clock of 60 MHz is
30 MBaud in Master Mode (with <BR> = 0000H) or 15 MBaud in Slave Mode (with <BR>
= 0001H).
Table 11-1 lists some possible baudrates together with the required reload values and
the resulting bit times, assuming a module clock of 60 MHz.
Table 11-1
Typical Baudrates of the SSC (fclk = 60 MHz)
Reload Value
Baudrate (= fMS_CLK/SS_CLK)
Deviation
0000H
30 MBaud (only in Master Mode)
0.0%
0001H
15 MBaud
0.0%
001DH
1 MBaud
0.0%
0027H
750 kBaud
0.0%
003BH
500 kBaud
0.0%
0095H
200 kBaud
0.0%
012BH
100 kBaud
0.0%
FFFFH
457.76 Baud
0.0%
User’s Manual
11-16
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
High-Speed Synchronous Serial Interface (SSC)
11.2.6
Error Detection Mechanisms
The SSC is able to detect four different error conditions. Receive Error and Phase Error
are detected in all modes; Transmit Error and Baudrate Error only apply to Slave Mode.
When an error is detected, the respective error flag is set and an error interrupt request
will be generated by activating the EIR line (see Figure 11-8). The error interrupt handler
may then check the error flags to determine the cause of the error interrupt. The error
flags are not reset automatically but rather must be cleared by software after servicing.
This allows servicing of some error conditions via interrupt, while the others may be
polled by software.
Note: The error interrupt handler must clear the associated (enabled) error flag(s) to
prevent repeated interrupt requests.
Bits in Register
CON
TEN
Transmit
Error
TE
REN
Receive
Error
1
Error Interrupt
EIR
&
PE
BEN
Baudrate
Error
&
RE
PEN
Phase
Error
&
&
BE
Figure 11-8 SSC Error Interrupt Control
A Receive Error (Master or Slave Mode) is detected when a new data frame is
completely received but the previous data was not read out of the receive buffer register
RB. This condition sets the error flag CON.RE and, when enabled via CON.REN, the
error interrupt request line EIR. The old data in the receive buffer RB will be overwritten
with the new value and is irretrievably lost.
User’s Manual
11-17
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
High-Speed Synchronous Serial Interface (SSC)
A Phase Error (Master or Slave Mode) is detected when the incoming data at pin MRST
(Master Mode) or MTSR (Slave Mode), sampled with the same frequency as the module
clock, changes between one cycle before and two cycles after the latching edge of the
shift clock signal SCLK. This condition sets the error flag CON.PE and, when enabled
via CON.PEN, the error interrupt request line EIR.
A Baudrate Error (Slave Mode) is detected when the incoming clock signal deviates
from the programmed baudrate by more than 100%, i.e. it either is more than double or
less than half the expected baudrate. This condition sets the error flag CON.BE and,
when enabled via CON.BEN, the error interrupt request line EIR. Using this error
detection capability requires that the slave’s baudrate generator is programmed to the
same baudrate as the master device. This feature detects false additional, or missing
pulses on the clock line (within a certain frame).
Note: If this error condition occurs and bit CON.REN=1, an automatic reset of the SSC
will be performed in case of this error. This is done to re-initialize the SSC if too
few or too many clock pulses have been detected.
A Transmit Error (Slave Mode) is detected when a transfer was initiated by the master
(SS_CLK gets active) but the transmit buffer TB of the slave was not updated since the
last transfer. This condition sets the error flag CON.TE and, when enabled via
CON.TEN, the error interrupt request line EIR. If a transfer starts while the transmit buffer
is not updated, the slave will shift out the ’old’ contents of the shift register, which
normally is the data received during the last transfer. This may lead to corruption of the
data on the transmit/receive line in half-duplex mode (open drain configuration) if this
slave is not selected for transmission. This mode requires that slaves not selected for
transmission only shift out ones; that is, their transmit buffers must be loaded with
’FFFFH’ prior to any transfer.
Note: A slave with push/pull output drivers not selected for transmission, will normally
have its output drivers switched. However, in order to avoid possible conflicts or
misinterpretations, it is recommended to always load the slave’s transmit buffer
prior to any transfer.
The cause of an error interrupt request (receive, phase, baudrate, transmit error) can be
identified by the error status flags in control register CON.
Note: In contrast to the error interrupt request line EIR, the error status flags CON.TE,
CON.RE, CON.PE, and CON.BE, are not reset automatically upon entry into the
error interrupt service routine, but must be cleared by software.
User’s Manual
11-18
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
12
General Purpose Timer Unit
12.1
Introduction
The General Purpose Timer Unit (GPT12E) provides very flexible multifunctional timer
structures that may be used for timing, event counting, pulse width measurement, pulse
generation, frequency multiplication, and other purposes. The GPT12E incorporates five
16-bit timers grouped into two timer blocks: Block 1 (GPT1) and Block 2 (GPT2). Each
timer in each block can operate independently in a number of different modes, such as
Gated Timer Mode or Counter Mode; or, each timer can be concatenated with another
timer of the same block.
Block 1 contains three timers/counters with a maximum resolution of fclk/4. The auxiliary
timers of GPT1 may optionally be configured as reload or capture registers for the core
timer.
Block 2 contains two timers/counters with a maximum resolution of fclk/2. An additional
CAPREL register supports capture and reload operation with extended functionality.
Note: Core Timer T6 may be concatenated with timers of other on chip peripherals.
The following summary identifies all features to be supported by the GPT12E:
• Timer Block 1:
– Maximum resolution of fclk/4
– Three independent timers/counters
– Concatenation of timers/counters can be done
– Four operating modes (Timer Mode, Gated Timer Mode, Counter Mode,
Incremental Interface Mode)
– Separate interrupt lines for each timer/counter
• Timer Block 2:
– Maximum resolution of fclk/2
– Two independent timers/counters
– Concatenation of Timers/counters can be done
– Three operating modes (Timer Mode, Gated Timer Mode, Counter Mode)
– Extended capture/reload functions via 16-bit capture/reload register CAPREL
– Separate interrupt lines for each timer/counter
User’s Manual
12-1
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
Clock
T6OFL
fclk
T3OUT
T6OUT
Control
GPT12E
Module
Address
Decoder
(Kernel)
Interrupt
Control
BPI
Interface
T2IN
T3IN
T4IN
T5IN
T6IN
CAPIN
Port
Control
T2EUD
T3EUD
T4EUD
T5EUD
T6EUD
T2IRQ
T3IRQ
T4IRQ
T5IRQ
T6IRQ
CRIRQ
Module
Product
Interface
Figure 12-1 GPT12E Interface Diagram
Note: Bus Peripheral Interface (BPI) is the connection to the on-chip bus system.
User’s Manual
12-2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
12.2
Functional Description of Timer Block 1
All three timers of Block 1 (T2, T3, T4) can run in four basic modes: Timer Mode, Gated
Timer Mode, Counter Mode, and Incremental Interface Mode. All timers can count up or
down. Each timer of Block 1 is controlled by a separate control register TxCON.
Each timer has an input line, TxIN, associated with it which serves as the gate control in
Gated Timer Mode, or as the count input in Counter Mode. The count direction (up/down)
may be programmed via software or may be dynamically altered by a signal at an
external control line, External Up/Down Control Input TxEUD. An overflow/underflow of
core Timer T3 is indicated by the Output Toggle Latch T3OTL whose state may be output
on related signal line T3OUT. Additionally, the auxiliary timers T2 and T4 may be
concatenated with core Timer T3 or may be used as capture or reload registers for core
Timer T3. Concatenation of T3 with other timers is provided through line T3OTL.
The current contents of each timer can be read or modified by the CPU by accessing the
corresponding timer registers, T2, T3, or T4, located in the non-bitaddressable Special
Function Register (SFR) space. When any of the timer registers is written by the CPU in
the state immediately before a timer increment, decrement, reload, or capture is to be
performed, the CPU write operation has priority in order to guarantee correct results.
From a programmer’s point of view, the GPT1 block is composed of a set of SFRs as
summarized below. Those registers which are not part of the GPT1 block are shaded.
Data Registers
Control Registers
Interrupt Control
T2
T2CON
T2IC
T3
T3CON
T3IC
T4
T4CON
T4IC
T2CONTimer 2 Control Register
T3CONTimer 3 Control Register
T4CONTimer 4 Control Register
T2 Timer 2 Register
T3 Timer 3 Register
T4 Timer 4 Register
T2ICTimer 2 Interrupt Control Register
T3ICTimer 3 Interrupt Control Register
T4ICTimer 4 Interrupt Control Register
Figure 12-2 SFRs associated with Timer Block GPT1
All GPT1 registers are located in the SFR/ESFR memory space. The respective SFR
addresses can be found in list of SFRs.
User’s Manual
12-3
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
U/D
T2EUD
fclk
Prescaler
T2IN
T2
Mode
Control
GPT1 Timer T2
T2IRQ
Reload
Capture
T3OTL
fclk
T3IRQ
Prescaler
1
T3
Mode
Control
T3IN
GPT1 Timer T3
U/D
T3EUD
T3OTL
T3OTL
0
MUX
1
T3OUT
T3OE
Capture
Reload
T4IN
fclk
Prescaler
T4
Mode
Control
GPT1 Timer T4
T4IRQ
U/D
T4EUD
MCT02141_b
Figure 12-3 Structure of Timer Block 1
User’s Manual
12-4
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
12.2.1
Core Timer T3
The operation of core Timer T3 is controlled by its bitaddressable control register
T3CON.
T3
Timer 3
15
14
(Reset value: 0000H)
13
12
11
10
9
8
7
6
5
4
3
2
1
0
T3
rwh
Field
Bits
Typ Description
T3
[15:0]
rwh Timer 3
Contains the current value of Timer 3.
User’s Manual
12-5
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
T3CON
Timer 3 Control Register
15
14
13
T3
T3
T3 CH
EDG
RDIR DIR
E
rh rwh rwh
12
11
BPS1
(Reset value: 0000H)
10
9
8
7
T3
T3
T3
T3
OTL OE UDE UD
rw
rw
5
4
3
2
1
T3R
T3M
T3I
rw
rw
rw
0
rw
rwh
Field
Bits
Typ Description
T3I
[2:0]
rw
Timer 3 Input Parameter Selection
Timer Mode: see Table 12-2 for encoding
Gated Timer Mode: see Table 12-2 for encoding
Counter Mode: see Table 12-4 for encoding
Incremental Interface Mode: see Table 12-5 for
encoding
T3M
[5:3]
rw
Timer 3 Mode Control
000 Timer Mode
001 Counter Mode
010 Gated Timer Mode with gate active low
011 Gated Timer Mode with gate active high
100 Reserved. Do not use this combination!
101 Reserved. Do not use this combination!
110 Incremental Interface Mode
(Rotation Detection Mode)
111 Incremental Interface Mode
(Edge Detection Mode)
T3R
[6]
rw
Timer 3 Run Bit
0
Stops Timer/counter 3
1
Runs Timer/counter 3
T3UD
[7]
rw
Timer 3 Up/Down Control
(when T3UDE = 0)
0
Counts up
1
Counts down
T3UDE
[8]
rw
Timer 3 External Up/Down Enable
0
Counting direction is internally controlled by
software
1
Counting direction is externally controlled by
line T3EUD
User’s Manual
rw
6
12-6
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
Field
Bits
Typ Description
T3OE
[9]
rw
T3OTL
[10]
rwh Timer 3 Overflow Toggle Latch
Toggles on each overflow/underflow of T3.
Can be set or reset by software.
BPS1
[12:11] rw
T3EDGE
[13]
rwh Timer 3 Edge Detection
The bit is set on each successful edge detection.
The bit has to be reset by SW.
0
No count edge was detected
1
A count edge was detected
T3CHDIR
[14]
rwh Timer 3 Count Direction Change
The bit is set on a change of the count direction of
Timer 3. The bit has to be reset by SW.
0
No change in count direction was detected
1
A change in count direction was detected
T3RDIR
[15]
rh
1)
Overflow/Underflow Output Enable
0
T3 overflow/underflow cannot be externally
monitored via T3IN
1
T3 overflow/underflow may be externally
monitored via T3IN
Timer Block Prescaler 1
The maximum input frequency1)
00
Timer Block 1 is fclk / 8
01
Timer Block 1 is fclk / 4
10
Timer Block 1 is fclk / 32
11
Timer Block 1 is fclk / 16
Timer 3 Rotation Direction
0
Timer 3 counts up
1
Timer 3 counts down
Additionally, the timer input frequency can be modified by T3I for Timer Mode, Gated Timer Mode and Counter
Mode.
Run Control
The timer can be started or stopped by software through bit T3R. Setting bit T3R will start
the timer; clearing T3R stops the timer.
In Gated Timer Mode, the timer will run only if T3R is set and the gate is active (high or
low, as programmed).
Note: When bit T2RC/T4RC in timer control register T2CON/T4CON is set, T3R will also
control (start and stop) auxiliary Timer T2/T4.
User’s Manual
12-7
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
Count Direction Control
The count direction of the core timer can be controlled either by software or by the
external input line, T3EUD. These options are selected by bits T3UD and T3UDE in
control register, T3CON. When the up/down control is set by software (bit T3UDE is
cleared), the count direction can be altered by setting or clearing bit T3UD. When T3UDE
is set, line T3EUD is selected to be the controlling source of the count direction.
However, bit T3UD can still be used to reverse the actual count direction, as shown in
Table 12-1. If T3UD is cleared and line T3EUD shows a low level, the timer is counting
up. With a high level at T3EUD, the timer is counting down. If T3UD is set, a high level
at line T3EUD specifies counting up, and a low level specifies counting down. The count
direction can be changed whether or not the timer is running or not.
Note: When line T3EUD is used as external count direction control input, its associated
port pin must be configured as input.
Table 12-1
Core Timer T3 Count Direction Control
Line T3EUD
Bit T3UDE
Bit T3UD
Count Direction
X
0
0
Count Up
X
0
1
Count Down
0
1
0
Count Up
1
1
0
Count Down
0
1
1
Count Down
1
1
1
Count Up
Note: The direction control works the same way for core Timer T3 and for auxiliary
Timers T2 and T4.
Timer 3 Overflow/Underflow Monitoring
An overflow or underflow of Timer T3 will set clock bit T3OTL in control register T3CON.
T3OTL can also be set or reset by software. Bit T3OE (overflow/underflow output
enable) in register T3CON enables the state of T3OTL to be monitored via an external
line, T3OUT. If this line is linked to an external port pin (configured as output), T3OUT
can be used to control external hardware.
Additionally, T3OTL can be used in conjunction with auxiliary Timers T2 and T4. In this
case, T3OTL serves as input for the counter function or as trigger source for the reload
function of T2 and T4. T3OTL is internally connected for this functionality and it is not
necessary to enable overflow/underflow output on T3OUT for this purpose.
User’s Manual
12-8
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
Timer 3 in Timer Mode
Timer Mode for core Timer T3 is selected by setting bitfield T3M in register T3CON to
‘000B’.
A block diagram of T3 in Timer Mode is shown in Figure 12-4.
In this mode, T3 is clocked with the module clock fclk divided by a programmable
prescaler block, controlled by bitfield T3I and BPS1. The input frequency fT3 for Timer
T3 and its resolution rT3 are scaled linearly with lower module clock frequencies, as can
be seen from the following formula:
fclk
<BPS1> * 2<T3I>
fT3 =
r
[ms]
=
T3
<BPS1> * 2<T3I>
fclk [MHz]
Note: <BPS1> represents the prescaler value of the prescaler part controlled by bitfield
BPS1. For the values, see the bit description in register T3CON.
Table 12-2
Timer 3 Input Parameter Selection: Timer and Gated Timer Modes
T3I
Prescaler for fclk Prescaler for fclk Prescaler for fclk Prescaler for fclk
(BPS1 = 00)
(BPS1 = 01)
(BPS1 = 11)
(BPS1 = 10)
000
8
4
32
16
001
16
8
64
32
010
32
16
128
64
011
64
32
256
128
100
128
64
512
256
101
256
128
1024
512
110
512
256
2048
1024
111
1024
512
4096
2048
Table 12-3
Example for Timer 3 Frequencies and Resolutions
fclk [MHz]
T3I
BPS1
fT3 [KHz]
rT3 [µs]
40
7
10
9.77
102.4
40
0
01
10000
0.1
50
0
00
6250
0.16
50
4
11
195.31
5.12
50
7
10
12.20
81.97
User’s Manual
12-9
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
This formula also applies to T3 in Gated Timer Mode and to the auxiliary timers T2 and
T4 in Timer Mode and Gated Timer Mode.
BPS1 T3l
Prescaler
fclk
T3IRQ
Core Timer T3
T3R
T3UD
Up/
Down
0
1
T3OTL
0
MUX
1
T3OUT
MUX
T3EUD
EXOR
T3OE
1
T3UDE
MCB02028_d
Figure 12-4 Block Diagram of Core Timer T3 in Timer Mode
Timer 3 in Gated Timer Mode
Gated Timer Mode for core Timer T3 is selected by setting bitfield T3M in register
T3CON to ‘010B’ or ‘011B’.
Bit T3M.0 (T3CON.3) selects the active level of the gate input. The same options for the
input frequency are available in Gated Timer Mode as for the Timer Mode. However, the
input clock to the timer in this mode is gated by the external input line T3IN (Timer T3
External Input); an associated port pin should be configured as input.
User’s Manual
12-10
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
BPS1 T3l
Prescaler
fclk
1
MUX
T3IN
Core Timer T3
T3M
T3R
Up/
Down
T3UD
T3OTL
0
MUX
1
T3OUT
T3OE
0
T3IRQ
MUX
T3EUD
XOR
1
T3UDE
MCB02029_d
Figure 12-5 Block Diagram of Core Timer T3 in Gated Timer Mode
If T3M = ‘010B’, the timer is enabled when T3IN shows a low level. A high level at this
line stops the timer. If T3M = ‘011B’, line T3IN must have a high level to enable the timer.
Additionally, the timer can be turned on or off by software using bit T3R. The timer will
run only if T3R is set and the gate is active. It will stop if either T3R is cleared or the gate
is inactive.
Note: A transition of the gate signal at line T3IN does not cause an interrupt request.
Timer 3 in Counter Mode
Counter Mode for core Timer T3 is selected by setting bitfield T3M in register T3CON to
‘001B’. In Counter Mode, Timer T3 is clocked by a transition at the external input line
T3IN. The event causing an increment or decrement of the timer can be a positive, a
negative, or both a positive and a negative transition at this line. Bitfield T3I in control
register T3CON selects the triggering transition (see Table 12-4).
User’s Manual
12-11
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
Edge
Select
1
T3IN
Core Timer T3
T3R
T3UD
T3OTL
Up/
Down
0
MUX
1
T3OUT
T3OE
T3l
0
T3IRQ
MUX
T3EUD
XOR
1
T3UDE
MCB02030_b
Figure 12-6 Block Diagram of Core Timer T3 in Counter Mode
Table 12-4
Core Timer T3 (Counter Mode) Input Edge Selection
T3I
Triggering Edge for Counter Increment/Decrement
000
None. Counter T3 is disabled
001
Positive transition (rising edge) on T3IN
010
Negative transition (falling edge) on T3IN
011
Any transition (rising or falling edge) on T3IN
1XX
Reserved. Do not use this combination
For Counter Mode operation, a port pin associated with line T3IN must be configured as
input. The maximum input frequency allowed in Counter Mode is fclk/8 (BPS1 =’01B’). To
ensure that a transition of the count input signal applied to T3IN is correctly recognized,
its level should be held high or low for at least 4 fclk cycles (BPS1 =’01B’) before it
changes.
Timer 3 in Incremental Interface Mode
Incremental Interface Mode for core Timer T3 is selected by setting bitfield T3M in
register T3CON to ‘110B’ or ‘111B’. In Incremental Interface Mode, the two inputs
associated with Timer T3 (T3IN, T3EUD) are used to interface to an external incremental
encoder. T3 is clocked by each transition on one or both of the external input lines which
gives 2-fold or 4-fold resolution of the encoder input.
User’s Manual
12-12
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
T3OE
1
T3IN
Edge
Select
Timer T3
T3l
T3R
T3OTL
0
MUX
1
T3OUT
Up/
Down
T3
Edge
T3
RDIR
T3IRQ
T3IRQ
T3UD
T3M
Change
Detection
T3EUD
Phase
Detect
XOR
T3
CHDIR
0
MUX
1
T3IRQ
T3M
T3UDE
MCB03998_b
Figure 12-7 Block Diagram of Core Timer T3 in Incremental Interface Mode
Bitfield T3I in control register T3CON selects the triggering transitions (see Table 12-5).
The sequence of the transitions of the two input signals is evaluated and generates count
pulses as well as the direction signal. Depending on whether Rotation Detection Mode
(T3M=’110B’) or Edge Detection Mode (T3M=’111B’) is chosen, an interrupt request on
T3IRQ is generated. For Rotation Detection Mode, an interrupt is generated each time
the count direction of Timer T3 changes. For Edge Detection Mode, an interrupt is
generated each time a count action for Timer T3 occurs. Count direction, changes in the
count direction, and count requests are monitored by status bits T3RDIR, T3CHDIR, and
T3EDGE in register T3CON. T3 is modified automatically according to the speed and
direction of the incremental encoder. Therefore, the contents of Timer T3 always
represents the encoder’s current position.
Table 12-5
Core Timer T3 (Incremental Interface Mode) Input Edge Selection
T3I
Triggering Edge for Counter Increment/Decrement
000
None. Counter T3 stops.
001
Any transition (rising or falling edge) on T3IN.
010
Any transition (rising or falling edge) on T3EUD.
011
Any transition (rising or falling edge) on any T3 input (T3IN or T3EUD).
1XX
Reserved. Do not use this combination
User’s Manual
12-13
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
The incremental encoder can be connected directly to the microcontroller without
external interface logic. In a standard system, however, comparators will be employed
to convert the encoder’s differential outputs (such as A, A) to digital signals (such as A
in Figure 12-8). This greatly increases noise immunity.
Note: The third encoder output T0, which indicates the mechanical zero position, may
be connected to an external interrupt input to trigger a reset of Timer T3.
([WHUQDO
(QFRGHU
$
$
$
%
%
%
7LQSXW
7
7
7
,QWHUUXSt
7LQSXW
0LFURFRQWUROOHU
6LJQDO&RQGLWLRQLQJ
Figure 12-8 Interfacing the Encoder to the Microcontroller
The following conditions must be met for Incremental Interface Mode operation:
• Bitfield T3M must be ’110B’ or ‘111B’
• Pins associated with lines T3IN and T3EUD must be configured as inputs
• Bit T3UDE must be set to enable external direction control
The maximum input frequency allowed in Incremental Interface Mode is fclk/8 (T3BPS =
’01B’). To ensure that a transition of any input signal is correctly recognized, its level
should be held high or low for at least 4 fclk cycles (T3BPS = ’01B’) before it changes.
In Incremental Interface Mode, the count direction is automatically derived from the
sequence in which the input signals change, corresponding to the rotation direction of
the connected sensor. Table 12-6 summarizes the possible combinations.
Table 12-6
Core Timer T3 (Incremental Interface Mode) Count Direction
Level on
respective other
input
T3IN Input
T3EUD Input
Rising
Falling
Rising
Falling
High
Down
Up
Up
Down
Low
Up
Down
Down
Up
Figure 12-9 and Figure 12-10 give examples of the operation of T3 to illustrate count
signal generation and direction control. Each example also shows how input jitter, which
might occur if the sensor rests near one of its switching points, is compensated.
User’s Manual
12-14
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
Forward
Jitter
Backward
Jitter
Forward
T3IN
p
U
U
ow
D
Contents
of T3
p
T3EUD
n
Note: This example shows the timer behavior assuming that T3 counts upon any
transition on any input, i.e. T3I = ’011B’.
Figure 12-9 Evaluation of the Incremental Encoder Signals
Forward
Jitter
Backward
Jitter
Forward
T3IN
T3EUD
p
U
ow
D
U
p
&RQWHQWV
RI7
n
Note: This example shows the timer behavior assuming that T3 counts upon any
transition on input T3IN, i.e. T3I = ’001B’.
Figure 12-10 Evaluation of the Incremental Encoder Signals
Note: Timer T3 operating in Incremental Interface Mode automatically provides
information about the sensor’s current position. Dynamic information (speed,
acceleration, deceleration) may be obtained by measuring the incoming signal
periods.
User’s Manual
12-15
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
12.2.2
Auxiliary Timers T2 and T4
T2
Timer 2
15
14
(Reset value: 0000H)
13
12
11
10
9
8
7
6
5
4
3
2
1
0
T2
rwh
T4
Timer 4
15
14
(Reset value: 0000H)
13
12
11
10
9
8
7
6
5
4
3
2
1
0
T4
rwh
T2CON
Timer 2 Control Register
15
14
13
12
(Reset value: 0000H)
11
T2
T2
T2
T2 CH
EDG
IR
RDIR DIR
E
DIS
rh rwh rwh rw
10
9
8
7
0
T2
T2
T2
RC UDE UD
r
rw
rw
rw
6
5
4
14
13
12
T2M
T2I
rw
rw
rw
10
9
8
7
0
T4
T4
T4
RC UDE UD
r
rw
rw
rw
6
5
4
3
1
T4M
T4I
rw
rw
rw
Bits
Typ Description
Tx
[15:0]
rwh Timer x
Contains the current value of Timer x.
12-16
2
T4R
Field
User’s Manual
1
0
(Reset value: 0000H)
11
T4
T4
T4
T4 CH
EDG
IR
RDIR DIR
E
DIS
rh rwh rwh rw
2
T2R
T4CON
Timer 4 Control Register
15
3
0
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
Field
Bits
Typ Description
TxI
[2:0]
rw
Timer x Input Parameter Selection
Timer Mode: see Table 12-7 for encoding
Gated Timer Mode: see Table 12-7 for encoding
Counter Mode: see Table 12-8 for encoding
Incremental Interface Mode: see Table 12-9 for
encoding
TxM
[5:3]
rw
Timer x Mode Control (Basic Operating Mode)
000 Timer Mode
001 Counter Mode
010 Gated Timer Mode with gate active low
011 Gated Timer Mode with gate active high
100 Reload Mode
101 Capture Mode
110 Incremental Interface Mode
(Rotation Detection Mode)
111 Incremental Interface Mode
(Edge Detection Mode)
TxR
[6]
rw
Timer x Run Bit
0
Timer/Counter x stops
1
Timer/Counter x runs
TxUD
[7]
rw
Timer x Up/Down Control
(when TxUDE = ’0’)
0
Counts Up
1
Counts Down
TxUDE
[8]
rw
Timer x External Up/Down Enable
0
Counting direction is internally controlled by
software
1
Counting direction is externally controlled by
line TxEUD
TxRC
[9]
rw
Timer x Remote Control
0
Timer/Counter x is controlled by its own run bit
TxR
1
Timer/Counter x is controlled by the run bit of
core Timer 3
User’s Manual
12-17
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
Field
Bits
Typ Description
TxIRDIS
[12]
rw
TxEDGE
[13]
rwh Timer x Edge Detection
The bit is set on each successful edge detection.
The bit has to be reset by software.
0
No count edge was detected
1
A count edge was detected
TxCHDIR
[14]
rwh Timer x Count Direction Change
The bit is set on a change of the count direction of
timer x. The bit has to be reset by software.
0
No change in count direction was detected
1
A change in count direction was detected
TxRDIR
[15]
rh
0
[11:10] r
Timer x Interrupt Disable
0
Interrupt generation for TxCHDIR and
TxEDGE interrupts in Incremental Interface
Mode is enabled
1
Interrupt generation for TxCHDIR and
TxEDGE interrupts in Incremental Interface
Mode is disabled
Timer x Rotation Direction
0
Timer x counts up
1
Timer x counts down
Reserved for future use; reading returns 0;
writing to these bit positions has no effect.
Both auxiliary timers T2 and T4 have exactly the same functionality. They can be
configured for Timer Mode, Gated Timer Mode, Counter Mode, or Incremental Interface
Mode with the same options for the timer frequencies and the count signal as the core
Timer T3. In addition to these 4 counting modes, the auxiliary timers can be
concatenated with the core timer, or they may be used as reload or capture registers in
conjunction with the core timer.
The individual configurations for Timers T2 and T4 are determined by their
bitaddressable control registers T2CON and T4CON, which are organized identically.
Note that functions which are present in all 3 timers of Timer Block 1 are controlled in the
same bit positions and manner in each of the specific control registers.
Run control for auxiliary timers T2 and T4 can be handled by the associated run control
bit T2R/T4R in register T2CON/T4CON. Alternatively, a remote control option (T2RC,
T4RC set) may be enabled to start and stop T2/T4 via the run bit T3R of core Timer T3.
User’s Manual
12-18
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
Timers T2 and T4 in Timer Mode or Gated Timer Mode
When the auxiliary Timers T2 and T4 are programmed to Timer Mode or Gated Timer
Mode, their operation is the same as described for the core Timer T3. The descriptions,
figures, and tables apply accordingly with two exceptions:
• There is no TxOUT output line for T2 and T4.
• Overflow/underflow monitoring is not supported (no bit TxOTL in registers TxCON).
Table 12-7
Timer x Input Parameter Selection: Timer and Gated Timer Modes
TxI
Prescaler for fclk Prescaler for fclk Prescaler for fclk Prescaler for fclk
(BPS1 = 00)
(BPS1 = 01)
(BPS1 = 10)
(BPS1 = 11)
000
8
4
32
16
001
16
8
64
32
010
32
16
128
64
011
64
32
256
128
100
128
64
512
256
101
256
128
1024
512
110
512
256
2048
1024
111
1024
512
4096
2048
User’s Manual
12-19
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
Timers T2 and T4 in Counter Mode
In Counter Mode, Timers T2 and T4 can be clocked either by a transition at the
respective external input line TxIN, or by a transition of T3OTL.
Edge
Select
TxIN
Auxiliary Timer Tx
T3OTL
TxIRQ
Up/
Down
TxR
Txl
TxUD
0
MUX
TxEUD
XOR
1
x = 2,4
TxUDE
MCB02221_b
Figure 12-11 Block Diagram of an Auxiliary Timer in Counter Mode
The event causing an increment or decrement of a timer can be a positive, a negative,
or both a positive and a negative transition at either the respective input line or at the
output toggle latch T3OTL. Bitfield TxI in the respective control register TxCON selects
the triggering transition (see Table 12-8).
Table 12-8
Auxiliary Timer (Counter Mode) Input Edge Selection
T2I / T4I
Triggering Edge for Counter Increment / Decrement
X00
None. Counter Tx is disabled
001
Positive transition (rising edge) on TxIN
010
Negative transition (falling edge) on TxIN
011
Any transition (rising or falling edge) on TxIN
101
Positive transition (rising edge) of T3OTL
110
Negative transition (falling edge) of T3OTL
111
Any transition (rising or falling edge) of T3OTL
Note: Only state transitions of T3OTL caused by the overflow/underflow of T3 will trigger
the counter function of T2/T4. Modifications of T3OTL via software will NOT trigger
the counter function of T2/T4.
User’s Manual
12-20
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
For counter operation, an external pin associated with line TxIN must be configured as
input. The maximum input frequency allowed in Counter Mode is fclk/8 (BPS1 = ’01’). To
ensure that a transition of the count input signal applied to TxIN is correctly recognized,
its level should be held for at least 4 fclk cycles (BPS1 = ’01’) before it changes.
12.2.3
Timer Concatenation
Using T3OTL as a clock source for an auxiliary timer of Block 1 in Counter Mode
concatenates core Timer T3 with the respective auxiliary timer. Depending on which
transition of T3OTL is selected to clock the auxiliary timer, this concatenation forms a
32-bit or a 33-bit timer/counter.
• 32-bit Timer/Counter: If both a positive and a negative transition of T3OTL are used
to clock the auxiliary timer, this timer is clocked on every overflow/underflow of core
Timer T3. Thus, the two timers form a 32-bit timer.
• 33-bit Timer/Counter: If either a positive or a negative transition of T3OTL is selected
to clock the auxiliary timer, this timer is clocked on every second overflow/underflow
of core Timer T3. This configuration forms a 33-bit timer (16-bit core
timer+T3OTL+16-bit auxiliary timer).
The count directions is not required to be the same in the two concatenated timers. This
offers a wide variety of different configurations. T3 can operate in Timer Mode, Gated
Timer Mode or Counter Mode in this case.
BPS1
T3l
1
Prescaler
fclk
Core Timer T3
T3R
*)
T3OTL
Up/Down
0
MUX
1
T3OUT
T3OE
T3IRQ
Edge
Select
Auxiliary Timer Tx
TxIR
TxIN
TxIRQ
x = 2,4
TxR
Txl
MCB02034_d
Up/Down
Figure 12-12 Concatenation of Core Timer T3 and an Auxiliary Timer
Note: Line ’*)’ is affected by over/underflow of T3 only, but NOT by software
modifications of T3OTL
User’s Manual
12-21
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
Auxiliary Timer in Reload Mode
Reload Mode for the auxiliary timers T2 and T4 is selected by setting bitfield TxM in the
respective register TxCON to ‘100B’. In Reload Mode, core Timer T3 is reloaded with the
contents of an auxiliary timer register, triggered by one of two different signals. The
trigger signal is selected the same way as the clock source for Counter Mode (see
Table 12-8). That is, a transition of the auxiliary timer’s input or the output toggle latch
T3OTL may trigger the reload.
Note: When programmed for Reload Mode, the respective auxiliary Timer (T2 or T4)
stops independently of its run flag T2R or T4R.
Source/Edge
Select
Auxiliary Timer Tx
TxIRQ
TxIN
*)
TxI
BPS1
fclk
T3IRQ
Core Timer T3
T3l
Prescaler
Up/Down
T3OTL
1
1
MUX
0
T3R
T3OUT
x = 2,4
MCB02035_b
T3OE
Figure 12-13 GPT1 Auxiliary Timer in Reload Mode
Note: Line ’*)’ is affected by over/underflow of T3 only, but NOT by software
modifications of T3OTL
Upon a trigger signal, T3 is loaded with the contents of the respective timer register (T2
or T4) and T2IRQ or T4IRQ is driven high.
Note: When a T3OTL transition is selected for the trigger signal, the interrupt request
flag T3IR will be set upon a trigger, indicating T3’s overflow or underflow.
Modifications of T3OTL via software will NOT trigger the counter function of T2/T4.
User’s Manual
12-22
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
The Reload Mode triggered by T3OTL can be used in a number of different
configurations. Depending on the selected active transition, the following functions can
be performed:
• If both a positive and a negative transition of T3OTL are selected to trigger a reload,
the core timer will be reloaded with the contents of the auxiliary timer each time it
overflows or underflows. This is the standard Reload Mode (reload on overflow/
underflow).
• If either a positive or a negative transition of T3OTL is selected to trigger a reload, the
core timer will be reloaded with the contents of the auxiliary timer on every second
overflow or underflow.
• Using this “single-transition” mode for both auxiliary timers allows very flexible Pulse
Width Modulation (PWM). One of the auxiliary timers is programmed to reload the
core timer on a positive transition of T3OTL; the other is programmed for a reload on
a negative transition of T3OTL. With this combination, the core timer is alternately
reloaded from the two auxiliary timers.
The Figure 12-14 shows an example for the generation of a PWM signal using the
alternate reload mechanism. T2 defines the high time of the PWM signal (reloaded on
positive transitions) and T4 defines the low time of the PWM signal (reloaded on negative
transitions). The PWM signal can be output on line T3OUT if the enable bit T3OE is set.
Using this method, the high and low time of the PWM signal can be varied over a wide
range.
Note: T3OTL is accessible via software and may be changed, if required, to modify the
PWM signal. However, this will NOT trigger the reloading of T3.
Note: An associated port pin linked to line T3OUT should be configured as output.
User’s Manual
12-23
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
Auxiliary Timer T2
T2IRQ
*)
BPS1 T3l
T2I
1
fclk
Prescaler
Core Timer T3
T3R
Up/Down
T3OTL
0
MUX
1
T3OUT
T3OE
T3IRQ
*)
T4IRQ
Auxiliary Timer T4
T4I
MCB02037_b
Figure 12-14 GPT1 Timer Reload Configuration for PWM Generation
Note: Line ’*)’ is affected by over/underflow of T3 only, NOT by software modifications
of T3OTL
Note: It should be avoided to select the same reload trigger event for both auxiliary
timers. In this case both reload registers would try to load the core timer at the
same time. If this combination is selected, T2 is disregarded and the contents of
T4 is reloaded.
Auxiliary Timer in Capture Mode
Capture Mode for the auxiliary Timers T2 and T4 is selected by setting bitfield TxM in the
respective register TxCON to ‘101B’. In Capture Mode, the contents of the core timer are
latched into an auxiliary timer register in response to a signal transition at the respective
auxiliary timer's external input line TxIN. The capture trigger signal can be a positive, a
negative, or both a positive and a negative transition.
The two Least Significant Bits of bitfield TxI are used to select the active transition (see
Table 12-8), while the most significant bit TxI.2 is irrelevant for Capture Mode. It is
recommended to keep this bit cleared (TxI.2 = ‘0’).
Note: When programmed for Capture Mode, the respective auxiliary Timer (T2 or T4)
stops independently of its run flag T2R or T4R.
User’s Manual
12-24
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
Edge
Select
Auxiliary Timer Tx
TxIN
TxIRQ
TxI
T3IRQ
Core Timer T3
BPS1 T3l
1
fclk
Prescaler
Up/Down
T3OTL
0
MUX
1
T3OUT
x = 2,4
T3R
T3OE
MCB02038_b
Figure 12-15 Auxiliary Timer of Timer Block 1 in Capture Mode
Upon a trigger (selected transition) at the corresponding input line TxIN, the contents of
the core timer are loaded into the auxiliary timer register and the associated interrupt
request line TxIRQ will be driven high.
Note: Port pins associated with T2IN and T4IN must be configured to Input, and the level
of the capture trigger signal should be held high or low for at least 4 fclk (BPS1 =
’01’) cycles before it changes to ensure correct edge detection.
Auxiliary in Incremental Interface Mode
When auxiliary Timers T2 and T4 are programmed to Incremental Interface Mode, their
operation is the same as described for core Timer T3. The descriptions, figures, and
tables apply accordingly with two exceptions:
• There is no TxOUT output line for T2 and T4.
• Overflow/underflow monitoring is not supported (no bit TxOTL).
Table 12-9
Timer x Input Parameter Selection for Incremental Interface Mode
TxI
Triggering Edge for Counter Update
000
None. Counter Tx stops
001
Any transition (rising or falling edge) on TxIN
010
Any transition (rising or falling edge) on TxEUD
011
Any transition (rising or falling edge) on TxIN or TxEUD
1XX
Reserved. Do not use this combination!
User’s Manual
12-25
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
12.3
Functional Description of Timer Block 2
Timer Block 2 includes the two Timers T5 (referred to as the auxiliary timer) and T6
(referred to as the core timer), and the 16-bit capture/reload register CAPREL. Each
timer of Block 2 is controlled by a separate control register, TxCON.
Each timer has an input line (TxIN) associated with it which serves as the gate control in
Gated Timer Mode or as the count input in Counter Mode. The count direction (up/down)
may be programmed via software or may be dynamically altered by a signal at an
external control input line. An overflow/underflow of core Timer T6 is indicated by bit
T6OTL whose state may be output on related line T6OUT and on line T6OFL. Core
Timer T6 may be reloaded with the contents of CAPREL.
The toggle bit also supports the concatenation of T6 with auxiliary Timer T5, while
concatenation of T6 with other timers is provided through line T6OUT. Triggered by an
external signal, the contents of T5 can be captured into register CAPREL, and T5 may
optionally be cleared. Both timer (T6 and T5) can count up or down, and the current timer
value can be read or modified by the CPU in the non-bitaddressable SFRs T6 and T5.
From a programmer’s point of view, the GPT2 block is composed of a set of SFRs as
summarized below. Those registers which are not part of the GPT2 block are shaded.
Data Registers
Control Registers
Interrupt Control
T5
T5CON
T5IC
T6
T6CON
T6IC
CAPREL
T5CON Timer 5 Control Register
T6CON Timer 6 Control Register
CRIC
T5
T6
CAPREL
T5IC
T6IC
CRIC
Timer 5 Register
Timer 6 Register
Capture/Reload Register
Timer 5 Interrupt Control Register
Timer 6 Interrupt Control Register
Caprel Interrupt Control Register
Figure 12-16 SFRs associated with Timer Block GPT2
All GPT2 registers are located in the SFR/ESFR memory space. The respective SFR
addresses can be found in list of SFRs.
User’s Manual
12-26
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
T5EUD
fclk
Prescaler
T5IN
T5
Mode
Control
U/D
GPT2 Timer T5
T5IRQ
Clear
Capture
CAPIN
CRIRQ
MUX
T3IN/
T3EUD
GPT2 CAPREL
CT3
T6IRQ
Clear
1
GPT2 Timer T6
T6IN
fclk
Prescaler
U/D
T6
Mode
Control
T6OTL
0
MUX
1
T3OUT
T3OE
T6OFL
T6EUD
MCB03999_b
Figure 12-17 Structure of Timer Block 2
User’s Manual
12-27
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
12.3.1
Core Timer T6
The operation of the core Timer T6 is controlled by its bitaddressable control register
T6CON.
T6
Timer 6
15
14
(Reset value: 0000H)
13
12
11
10
9
8
7
6
5
4
3
2
1
0
T6
rwh
T6CON
Timer 6 Control Register
15
14
13
12
11
(Reset value: 0000H)
10
9
8
7
5
4
3
2
1
0
T6
T6
SR CLR
0
BPS2
rw
r
rw
rwh
Field
Bits
Typ Description
T6
[15:0]
rwh Timer 6
Contains the current value of Timer 6.
Field
Bits
Typ Description
T6I
[2:0]
rw
Timer 6 Input Parameter Selection
Timer Mode: see Table 12-11 for encoding
Gated Timer Mode: see Table 12-11 for encoding
Counter Mode: see Table 12-12 for encoding
T6M
[5:3]
rw
Timer 6 Mode Control (Basic Operating Mode)
000 Timer Mode
001 Counter Mode
010 Gated Timer Mode with gate active low
011 Gated Timer with gate active high
1XX Reserved. Do not use this combination!
T6R
[6]
rw
Timer 6 Run Bit
0
Timer/Counter 6 stops
1
Timer/Counter 6 runs
rw
User’s Manual
T6
T6
T6
T6
OTL OE UDE UD
6
rw
rw
rw
12-28
T6R
T6M
T6I
rw
rw
rw
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
Field
Bits
Typ Description
T6UD
[7]
rw
Timer 6 Up / Down Control
(when T6UDE = ’0’)
0
Counts Up
1
Counts Down
T6UDE
[8]
rw
Timer 6 External Up/Down Enable
0
Counting direction is internally controlled by
software
1
Counting direction is externally controlled by
line T6EUD
T6OE
[9]
rw
Overflow/Underflow Output Enable
0
T6 overflow/underflow can not be externally
monitored
1
T6 overflow/underflow may be externally
monitored via T6OUT
T6OTL
[10]
rwh Timer 6 Output Toggle Latch
Toggles on each overflow/underflow of T6. Can be
set or reset by software.
BPS2
[12:11] rw
Timer Block Prescaler 2
The maximum input frequency1)
00
Timer Block 2 is fclk / 4
01
Timer Block 2 is fclk / 2
10
Timer Block 2 is fclk / 16
11
Timer Block 2 is fclk / 8
T6CLR
[14]
rw
Timer 6 Clear Bit
0
Timer 6 is not cleared on a capture event
1
Timer 6 is cleared on a capture event
T6SR
[15]
rw
Timer 6 Reload Mode Enable
0
Reload from register CAPREL disabled
1
Reload from register CAPREL enabled
0
[13]
r
Reserved for future use; reading returns 0;
writing to these bit positions has no effect.
1)
Additionally, the timer input frequency can be modified by T6I for Timer Mode, Gated Timer Mode and Counter
Mode.
Timer 6 Run Bit
The timer can be started or stopped by software through bit T6R (Timer T6 Run Bit).
Setting bit T6R will start the timer; clearing T6R stops the timer.
User’s Manual
12-29
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
In Gated Timer Mode, the timer will run only if T6R is set and the gate is active (high or
low, as programmed).
Note: When bit T5RC is set, bit T6R will also control (start and stop) auxiliary Timer T5.
Count Direction Control
The count direction of the core timer can be controlled either by software or by the
External Up/Down control input line (T6EUD). These options are selected by bits T6UD
and T6UDE in control register T6CON. When the up/down control is done by software
(bit T6UDE is cleared), the count direction can be altered by setting or clearing bit T6UD.
When T6UDE is set, line T6EUD is selected to be the controlling source of the count
direction. However, bit T6UD can still be used to reverse the actual count direction, as
shown in the table below. If T6UD is cleared and line T6EUD shows a low level, the timer
is counting up. With a high level at T6EUD the timer is counting down. If T6UD is set, a
high level at line T6EUD specifies counting up, and a low level specifies counting down.
The count direction can be changed whether the timer is running or not.
Table 12-10 Core Timer T6 Count Direction Control
Line T6EUD
Bit T6UDE
Bit T6UD
Count Direction
X
0
0
Count Up
X
0
1
Count Down
0
1
0
Count Up
1
1
0
Count Down
0
1
1
Count Down
1
1
1
Count Up
Note: The direction control works the same for core Timer T6 and for auxiliary Timer T5.
Timer 6 Overflow/Underflow Monitoring
An overflow or underflow of Timer T6 will toggle T6OTL in control register T6CON.
T6OTL can also be set or reset by software. Bit T6OE in register T6CON enables the
state of T6OTL to be monitored via the external output line T6OUT. An associated port
pin must be configured as output.
Additionally, T6OTL can be used in conjunction with the timer over/underflow as an input
for the counter function of auxiliary Timer T5. For this purpose, the state of T6OTL does
not have to be available at line T6OUT, because an internal connection is provided for
this option.
An overflow or underflow of Timer T6 can also be used to clock other timers. For this
purpose, there is the special output line T6OFL.
User’s Manual
12-30
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
Timer 6 in Timer Mode
Timer Mode for core Timer T6 is selected by setting bitfield T6M in register T6CON to
‘000B’. In this mode, T6 is clocked with the module clock divided by a programmable
prescaler, as selected by bitfield T6I. The input frequency fT6 for Timer T6 and its
resolution rT6 are scaled linearly with lower clock frequencies fclk, as can be seen from
the following formula:
fT6 =
fclk [MHz]
<BPS2> * 2<T6I>
rT6 [ms] =
fclk [MHz]
<BPS2> * 2<T6I>
Note: <BPS2> represents the prescaler value of the prescaler part controlled by bitfield
BPS2. For the values, see the bit description in register T6CON.
BPS2
T6l
T6OFL
Prescaler
fclk
T6IRQ
Core Timer T6
T6R
T6UD
1
Up/
Down
T6OTL
0
MUX
1
T3OUT
0
T3OE
MUX
T6EUD
EXOR
1
T6UDE
MCB02028_e
Figure 12-18 Block Diagram of Core Timer T6 in Timer Mode
Table 12-11 Timer 6 Input Parameter Selection: Timer and Gated Timer Modes
T6I
Prescaler for fclk Prescaler for fclk Prescaler for fclk Prescaler for fclk
(BPS2 = 00)
(BPS2 = 01)
(BPS2 = 10)
(BPS2 = 11)
000
4
2
16
8
001
8
4
32
16
010
16
8
64
32
011
32
16
128
64
User’s Manual
12-31
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
Table 12-11 Timer 6 Input Parameter Selection: Timer and Gated Timer Modes
T6I
Prescaler for fclk Prescaler for fclk Prescaler for fclk Prescaler for fclk
(BPS2 = 00)
(BPS2 = 01)
(BPS2 = 10)
(BPS2 = 11)
100
64
32
256
128
101
128
64
512
256
110
256
128
1024
512
111
512
256
2048
1024
Timer 6 in Gated Timer Mode
Gated Timer Mode for core Timer T6 is selected by setting bitfield T6M in register
T6CON to ‘010B’ or ‘011B’. Bit T6M.0 (T6CON.3) selects the active level of the gate
input. In Gated Timer Mode, the same options for the input frequency as for the Timer
Mode are available. However, in this mode, the input clock to the timer is gated by the
external input line T6IN.
BPS2 T6I
T6OFL
fclk
Prescaler
1
MUX
T6IN
Core Timer T6
T6M
T6R
Up/
Down
T6OTL
0
MUX
1
T6OUT
T6OE
T6UD
0
T6IRQ
MUX
T6EUD
XOR
1
T6UDE
MCB02029_e
Figure 12-19 Block Diagram of Core Timer T6 in Gated Timer Mode
If T6M.0 = ‘0’, the timer is enabled when T6IN shows a low level. A high level at this line
stops the timer. If T6M.0 = ‘1’, line T6IN must have a high level to enable the timer.
Additionally, the timer can be turned on or off by software using bit T6R. The timer will
run only if T6R is set and the gate is active. It will stop if either T6R is cleared or the gate
is inactive.
Note: A transition of the gate signal at line T6IN does not cause an interrupt request.
User’s Manual
12-32
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
Timer 6 in Counter Mode
Counter Mode for core Timer T6 is selected by setting bitfield T6M in register T6CON to
‘001B’. In Counter Mode, Timer T6 is clocked by a transition at the external input line
T6IN. The event causing an increment or decrement of the timer can be a positive, a
negative, or both a positive and a negative transition at this line. Bitfield T6I in control
register T6CON selects the triggering transition (see Table 12-12).
Edge
Select
T6OFL
1
T6IN
Core Timer T6
T6R
T6UD
T6OTL
Up/
Down
0
MUX
1
T6OUT
T6OE
T6l
0
T6IRQ
MUX
T6EUD
XOR
1
MCB02030_c
T6UDE
Figure 12-20 Block Diagram of Core Timer T6 in Counter Mode
Table 12-12 Core Timer T6 (Counter Mode) Input Edge Selection
T6I
Triggering Edge for Counter Increment/Decrement
000
None. Counter T6 is disabled
001
Positive transition (rising edge) on T6IN
010
Negative transition (falling edge) on T6IN
011
Any transition (rising or falling edge) on T6IN
1XX
Reserved. Do not use this combination
User’s Manual
12-33
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
The maximum input frequency allowed in Counter Mode is fclk/4 (BPS2 = ’01’). To ensure
that a transition of the count input signal applied to T6IN is correctly recognized, its level
should be held high or low for at least 2 fclk cycles (BPS2 = ’01’) before it changes.
12.3.2
Auxiliary Timer T5
The auxiliary Timer T5 can be configured for Timer Mode, Gated Timer Mode, or Counter
Mode with the same options for the timer frequencies and the count signal as core Timer
T6. In addition to these three counting modes, the auxiliary timer can be concatenated
with the core timer.
The individual configuration for Timer T5 is determined by its bitaddressable control
register T5CON. Note that functions present in both timers of Timer Block 2 are
controlled in the same bit positions and in the same manner in each of the specific control
registers.
Run control for auxiliary Timer T5 can be handled by the associated Run Control Bit T5R
in register T5CON. Alternatively, a remote control option (T5RC is set) may be enabled
to start and stop T5 via the run bit T6R of core Timer T6.
Note: The auxiliary timer has no bit T5OTL. Therefore, an output line for overflow/
underflow monitoring is not provided.
T5
Timer 5
15
14
(Reset value: 0000H)
13
12
11
10
9
8
7
6
5
4
3
2
1
0
T5
rwh
T5CON
Timer 5 Control Register
15
14
13
12
(Reset value: 0000H)
11
10
T5
T5
SC CLR
CI
T5
CC
CT3
rw
rw
rw
rw
rw
9
8
7
T5
T5
T5
RC UDE UD
rw
rw
rw
6
5
4
3
T5M
T5I
rw
rw
rw
Bits
Typ Description
T5
[15:0]
rwh Timer 5
Contains the current value of Timer 5.
12-34
1
T5R
Field
User’s Manual
2
0
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
Field
Bits
Typ Description
T5I
[2:0]
rw
Timer 5 Input Parameter Selection
Timer Mode: see Table 12-13 for encoding
Gated Timer Mode: see Table 12-13 for encoding
Counter Mode: see Table 12-14 for encoding
T5M
[5:3]
rw
Timer 5 Mode Control (Basic Operating Mode)
000 Timer Mode
001 Counter Mode
010 Gated Timer Mode with gate active low
011 Gated Timer Mode with gate active high
1XX Reserved. Do not use this combination!
T5R
[6]
rw
Timer 5 Run Bit
0
Timer/Counter 5 stops
1
Timer/Counter 5 runs
T5UD
[7]
rw
Timer 5 Up/Down Control
(when T5UDE = ’0’)
0
Counts Up
1
Counts Down
T5UDE
[8]
rw
Timer 5 External Up/Down Enable
0
Counting direction is internally controlled by
software
1
Counting direction is externally controlled by
line T5EUD
T5RC
[9]
rw
Timer 5 Remote Control
0
Timer/counter 5 is controlled by its own run bit
T5R
1
Timer/counter 5 is controlled by the run bit of
core Timer 6
CT3
[10]
rw
Timer 3 Capture Trigger Enable
0
Capture trigger from input line CAPIN
1
Capture trigger from T3 input lines T3IN and/
or T3EUD
T5CC
[11]
rw
Timer 5 Capture Correction
0
T5 is just captured, without any correction
1
T5 is decremented by 1 before being captured
User’s Manual
12-35
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
Field
Bits
Typ Description
CI
[13:12] rw
Register CAPREL Capture Trigger Selection
(depending on bit CT3)
00
Capture disabled
01
Positive transition (rising edge) on CAPIN or
any transition on T3IN
10
Negative transition (falling edge) on CAPIN or
any transition on T3EUD
11
Any transition (rising or falling edge) on CAPIN
or any transition on T3IN or T3EUD
T5CLR
[14]
rw
Timer 5 Clear Bit
0
Timer 5 is not cleared on a capture event
1
Timer 5 is cleared on a capture event
T5SC
[15]
rw
Timer 5 Capture Mode Enable
0
Capture into register CAPREL disabled
1
Capture into register CAPREL enabled
Count Direction Control for Auxiliary Timer
The count direction of the auxiliary timer can be controlled in the same way as for core
Timer T6. The description and the table apply accordingly.
Timer T5 in Timer Mode or Gated Timer Mode
When auxiliary Timer T5 is programmed to Timer or Gated Timer Mode, its operation is
the same as described for core Timer T6. The descriptions, figures, and tables apply
accordingly with three exceptions:
• There is no T5OUT line for T5
• There is no T5OFL line for T5
• Overflow/underflow monitoring is not supported (no bit T5OTL).
User’s Manual
12-36
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
Table 12-13 Timer 5 Input Parameter Selection: Timer and Gated Timer Modes
T5I
Prescaler for fclk Prescaler for fclk Prescaler for fclk Prescaler for fclk
(BPS2 = 00)
(BPS2 = 01)
(BPS2 = 10)
(BPS2 = 11)
000
4
2
16
8
001
8
4
32
16
010
16
8
64
32
011
32
16
128
64
100
64
32
256
128
101
128
64
512
256
110
256
128
1024
512
111
512
256
2048
1024
Timer T5 in Counter Mode
Counter Mode for auxiliary Timer T5 is selected by setting bitfield T5M in register T5CON
to ‘001B’. In Counter Mode, Timer T5 can be clocked either by a transition at the external
input line T5IN or by a transition of the output toggle latch T6OTL on Timer 6.
Edge
Select
T5IN
Auxiliary Timer T5
T6OTL
T5IRQ
Up/
Down
T5R
T5l
TxUD
0
MUX
TxEUD
XOR
1
TxUDE
MCB02221_c
Figure 12-21 Block Diagram of Auxiliary Timer T5 in Counter Mode
User’s Manual
12-37
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
The event causing an increment or decrement of the timer can be a positive, a negative,
or both a positive and a negative transition at either the input line T5IN or at the toggle
latch T6OTL.
Bitfield T5P in control register T5CON selects the triggering transition (see Table 12-14).
Table 12-14 Auxiliary Timer (Counter Mode) Input Edge Selection
T5P
Triggering Edge for Counter Increment/Decrement
X00
None. Counter T5 is disabled
001
Positive transition (rising edge) on T5IN
010
Negative transition (falling edge) on T5IN
011
Any transition (rising or falling edge) on T5IN
101
Positive transition (rising edge) on T6OTL
110
Negative transition (falling edge) on T6OTL
111
Any transition (rising or falling edge) on T6OTL
Note: Only state transitions of T6OTL caused by the overflow/underflow of T6 will trigger
the counter function of T5. Modifications of T6OTL via software will NOT trigger
the counter function of T5.
The maximum input frequency allowed in Counter Mode is fclk/4 (BPS2 = ’01’). To ensure
that a transition of the count input signal applied to T5IN is correctly recognized, its level
should be held high or low for at least 2 fclk cycles (BPS2 = ’01’) before it changes.
12.3.3
Timer Concatenation
Using the toggle bit T6OTL as a clock source for the auxiliary Timer of Block 2 in Counter
Mode concatenates core Timer T6 with auxiliary Timer T5. Depending on which
transition of T6OTL is selected to clock auxiliary Timer T5, this concatenation forms a
32-bit or a 33-bit timer/counter.
• 32-bit Timer/Counter: If both a positive and a negative transition of T6OTL is used to
clock auxiliary Timer T5, this timer is clocked on every overflow/underflow of core
Timer T6. Thus, the two timers form a 32-bit timer.
• 33-bit Timer/Counter: If either a positive or a negative transition of T6OTL is selected
to clock auxiliary Timer T5, this timer is clocked on every second overflow/underflow
of core Timer T6. This configuration forms a 33-bit timer (16-bit core
timer+T6OTL+16-bit auxiliary timer).The count directions of the two concatenated
timers are not required to be the same. This offers a wide variety configurations.T6
can operate in Timer Mode, Gated Timer Mode or Counter Mode in this case.
User’s Manual
12-38
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
BPS2
T6l
1
Prescaler
fclk
Core Timer T6
T6R
*)
0
MUX
1
T6OTL
T6OUT
T6OE
Up/Down
T6IRQ
Edge
Select
Auxiliary Timer T5
T5IRQ
T5IR
T5IN
T5R
MCB02034_e
Up/Down
T5l
Figure 12-22 Concatenation of Core Timer T6 and Auxiliary Timer T5
Note: Line ’*)’ is affected by over/underflow of T6 only, NOT by software modifications
of T6OTL
Capture/Reload Register CAPREL in Capture Mode
CAPREL
Capture/Reload Register
15
14
13
12
11
(Reset value: 0000H)
10
9
8
7
6
5
4
3
2
1
0
CAPREL
rwh
Field
Bits
Typ Description
CAPREL
[15:0]
rwh Capture Reload Register Value
Contains the current value of the CAPREL register.
This 16-bit register can be used as a capture register for auxiliary Timer T5. This mode
is selected by setting bit T5SC in control register T5CON. Bit CT3 selects the external
input line (CAPIN) or the input lines (T3IN and/or T3EUD) of Timer T3 as the source for
a capture trigger. Either a positive, a negative, or both a positive and a negative transition
at line CAPIN can be selected to trigger the capture function, or transitions on input T3IN
User’s Manual
12-39
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
or input T3EUD or both inputs T3IN and T3EUD. The active edge is controlled by bitfield
CI in register T5CON.
The maximum input frequency for the capture trigger signal at CAPIN is fclk/2 (BPS2 =
’01’). To ensure that a transition of the capture trigger signal is correctly recognized, its
level should be held for at least one fclk cycle (BPS2 = ’01’) before it changes.
When Timer T3 capture trigger is enabled (CT3 is set) register CAPREL captures the
contents of T5 upon transitions of the selected input(s). These values can be used to
measure input signals of T3. This is useful, for example, when T3 operates in
Incremental Interface Mode, to derive dynamic information (speed or acceleration) from
the input signals.
When a selected transition at the external input line CAPIN is detected, the contents of
auxiliary Timer T5 are latched into register CAPREL, and interrupt request line CRIRQ
is driven at high level. With the same event, Timer T5 can be cleared to 0000H. This
option is controlled by bit T5CLR in register T5CON. If T5CLR is cleared, the contents of
Timer T5 are not affected by a capture. If T5CLR is set, Timer T5 is cleared after the
current timer value has been latched into register CAPREL.
Note: Bit T5SC only controls whether a capture is performed or not. If T5SC is cleared,
the input line CAPIN can still be used to clear Timer T5 or as an external interrupt
input. This interrupt is controlled by the CAPREL interrupt control register CRIC.
fclk
BPS2 T5l
Up/Down
Prescaler
Auxiliary Timer T5
T5IRQ
T5R
Edge
Select
CAPIN
T3IN/
T3EUD
T5CLR
T5CC
MUX
CT3
CI
T5SC
CRIRQ
CAPREL Register
MCB02044_c
Figure 12-23 Timer Block 2 Register CAPREL in Capture Mode
User’s Manual
12-40
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
Timer Block 2 Capture/Reload Register CAPREL in Reload Mode
This 16-bit register can be used as a reload register for core Timer T6. This mode is
selected by setting bit T6SR in register T6CON. The event causing a reload in this mode
is an overflow or underflow of core Timer T6.
When Timer T6 overflows from FFFFH to 0000H (when counting up) or underflows from
0000H to FFFFH (when counting down), the value stored in register CAPREL is loaded
into Timer T6. This will not drive the interrupt request line CRIRQ associated with the
CAPREL register. However, interrupt request line T6IRQ will be driven at high level to
indicate the overflow/underflow of T6.
CAPREL Register
1
T6OTL
BPS2 T6l
T6SR
fclk
Prescaler
Core Timer T6
T6R
0
MUX
1
T6OUT
T6OE
T6IRQ
T6OFL
Up/Down
MCB02045_b
Figure 12-24 Timer Block 2 Register CAPREL in Reload Mode
User’s Manual
12-41
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
Timer Block 2 Capture/Reload Register CAPREL in Capture-And-Reload Mode
Because the reload and capture functions of register CAPREL can be enabled
individually by bits T5SC and T6SR, the two functions can be enabled simultaneously by
setting both bits. This feature can be used to generate an output frequency that is a
multiple of the input frequency.
BPS2 T5l
Prescaler
fclk
Up/Down
T5R
T5IRQ
Auxiliary Timer T5
Edge
Select
CAPIN
T5CLR
T5CC
MUX
T3IN/
T3EUD
T5SC
CT3
CI
CRIRQ
CAPREL Register
1
T6CLR
T6OTL
0
MUX
1
T6OUT
BPS2 T6l
T6SR
fclk
Prescaler
T6R
T6OE
Core Timer T6
T6IRQ
Up/Down
T6OFL
MCB02046_c
Figure 12-25 Timer Block 2 Register CAPREL in Capture-And-Reload Mode
This combined mode can be used to detect consecutive external events which may
occur aperiodically, but which require a finer resolution (more ’ticks’ within the time
between two external events). For this purpose, the time between the external events is
measured using Timer T5 and the CAPREL register. Timer T5 runs in Timer Mode
counting up with a frequency of fclk/32, for example. The external events are applied to
line CAPIN. When an external event occurs, the contents of Timer T5 are latched into
User’s Manual
12-42
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
register CAPREL, and Timer T5 is cleared (T5CLR cleared). Thus, register CAPREL
always contains the correct time between two events, measured in Timer T5 increments.
Timer T6, which runs in Timer Mode counting down with a frequency of fclk/4, for
example, uses the value in register CAPREL to perform a reload on underflow. This
means that the value in register CAPREL represents the time between two underflows
of Timer T6, now measured in Timer T6 increments. Because Timer T6 runs eight times
faster than Timer T5, it will underflow eight times within the time between two external
events. Thus, the underflow signal of Timer T6 generates eight ’ticks’. Upon each
underflow, the interrupt request flag T6IR will be set and bit T6OTL will be toggled. The
state of T6OTL may be output on line T6OUT. This signal has eight times more
transitions than the signal applied to line CAPIN.
A certain deviation of the output frequency is generated by the fact that Timer T5 will
count actual time units (for example: T5 running at 1 MHz will capture the value 64H/
100D for a 10 KHz input signal) while T6OTL will only toggle upon an underflow of T6
(that is, the transition from 0000H to FFFFH). In the above mentioned example T6 would
count down from 64H so the underflow would occur after 101 T6 timing ticks. The actual
output frequency then is 79.2 KHz instead of the expected 80 KHz.
This can be solved by activating the Capture Correction (T5CC is set). If capture
correction is active, the content of T5 is decremented by 1 before being captured. The
described deviation is eliminated (in the example, T5 would now capture 63H/99D and
the output frequency would be 80 KHz).
Note: The underflow signal of Timer T6 can furthermore be used to clock one ore more
timers of other timer units. This makes it possible to set compare events based on
a finer resolution than that of the external events. This connection is accomplished
via signal T6OFL.
User’s Manual
12-43
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
User’s Manual
12-44
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Instruction Index
13
Instruction Index
This section lists alphabetically all C166S instructions together with references to
respective pages holding the detailed descriptions. This helps to quickly find the
explanation of any specific core instruction.
ADD . . . . . . . . . . 6-2
ADDB . . . . . . . . . 6-3
ADDC . . . . . . . . . 6-4
ADDCB . . . . . . . 6-5
AND . . . . . . . . . . 6-6
ANDB . . . . . . . . . 6-7
ASHR . . . . . . . . . 6-8
ATOMIC . . . . . . 6-10
BAND . . . . . . . . 6-11
BCLR . . . . . . . . 6-12
BCMP . . . . . . . 6-13
BFLDH . . . . . . . 6-14
BFLDL . . . . . . . 6-15
BMOV . . . . . . . 6-16
BMOVN . . . . . . 6-17
BOR . . . . . . . . . 6-18
BSET . . . . . . . . 6-19
BXOR . . . . . . . . 6-20
CALLA . . . . . . . 6-21
CALLI . . . . . . . . 6-22
CALLR . . . . . . . 6-23
CALLS . . . . . . . 6-24
CMP . . . . . . . . . 6-25
CMPB . . . . . . . 6-26
CMPD1 . . . . . . 6-27
CMPD2 . . . . . . 6-28
CMPI1 . . . . . . . 6-29
CMPI2 . . . . . . . 6-30
CPL . . . . . . . . . 6-31
CPLB . . . . . . . . 6-32
DISWDT . . . . . . 6-33
DIV . . . . . . . . . . 6-34
User’s Manual
DIVL . . . . . . . . .6-35
DIVLU . . . . . . . .6-36
DIVU . . . . . . . . .6-37
EINIT . . . . . . . .6-38
EXTP . . . . . . . .6-39
EXTPR . . . . . . .6-41
EXTR . . . . . . . .6-43
EXTS . . . . . . . .6-44
EXTSR . . . . . . .6-46
IDLE . . . . . . . . .6-48
JB . . . . . . . . . . .6-49
JBC . . . . . . . . .6-50
JMPA . . . . . . . .6-52
JMPI . . . . . . . . .6-53
JMPR . . . . . . . .6-54
JMPS . . . . . . . .6-55
JNB . . . . . . . . .6-56
JNBS . . . . . . . .6-57
MOV . . . . . . . . .6-58
MOVB . . . . . . . .6-60
MOVBS . . . . . .6-62
MOVBZ . . . . . .6-63
MUL . . . . . . . . .6-64
MULU . . . . . . . .6-65
NEG . . . . . . . . .6-66
NEGB . . . . . . . .6-67
NOP . . . . . . . . .6-68
OR . . . . . . . . . .6-69
ORB . . . . . . . . .6-70
PCALL . . . . . . .6-71
POP . . . . . . . . .6-73
PRIOR . . . . . . .6-74
13-1
PUSH . . . . . . .
PWRDN . . . . .
RET . . . . . . . . .
RETI . . . . . . . .
RETP . . . . . . .
RETS . . . . . . .
ROL . . . . . . . .
ROR . . . . . . . .
SCXT . . . . . . .
SHL . . . . . . . . .
SHR . . . . . . . .
SRST . . . . . . .
SRVWDT . . . .
SUB . . . . . . . .
SUBB . . . . . . .
SUBC . . . . . . .
SUBCB . . . . . .
TRAP . . . . . . .
XOR . . . . . . . .
XORB . . . . . . .
6-75
6-76
6-77
6-78
6-79
6-80
6-81
6-83
6-85
6-86
6-88
6-90
6-91
6-92
6-93
6-94
6-95
6-96
6-98
6-99
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Instruction Index
User’s Manual
13-2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Keyword Index
14
Keyword Index
This section lists a number of keywords which refer to specific details of the C166S V1
SubS R1 in terms of its architecture, its functional units or functions. This helps to quickly
find the answer to specific questions about the C166S V1 SubS R1.
A
Address
Arbitration 8-28
Area Definition 8-28
Boundaries 4-9
Segment 8-12
Addressing Modes
Indirect Addressing Mode 3-59
Long Adressing Mode 3-58
Long and Indirect Addressing Modes 354
Short Addressing Modes 3-52
ADDRSELx 8-25, 8-28
ALE length 8-16
Alternate signals 7-2
Arbitration
Address 8-28
External Bus 8-31
ASC0
Error Detection 10-23
Auxiliary Timer 5 12-34
B
Baudrate
ASC0 10-17
BHE 8-12
Bit
protected 3-71
Boundaries 4-9
Bus
Arbitration 8-31
Demultiplexed 8-6
Idle State 8-30
Mode Configuration 8-2
Multiplexed 8-3
User’s Manual
BUSCONx 8-23, 8-29
BWT 3-37
C
CAPREL 12-39
Capture Mode (GPT2) 12-39
Capture/Reload Register 12-39
Central System Control 2-13
CGU 2-14
Chip Select
Configuration 8-13
Latched/Early 8-14
Clock Generation Unit 2-14
Concatenation of Timers 12-21, 12-38
Configuration
Address 8-12
Bus Mode 8-2
Chip Select 8-13
Context Pointer 3-50
Context Switch 3-50
Continuous PEC Transfers 3-38
Core Timer T3 12-5
COUNT 3-37, 3-38, 3-39
Count direction 12-8, 12-30
CP Register 3-50
CPU 2-2
CPUID Register 3-90
CSP Register 3-15
D
Data Page
boundaries 4-9
Data Page Pointer 3-55
Data Types 3-68
Delay
14-1
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Keyword Index
Read/Write 8-18
Demultiplexed Bus 8-6
Development Support 1-5
Direction
count 12-8, 12-30
DP0L, DP0H 7-3
DP1L, DP1H 7-7
DP4 7-10, 7-13
DPPx Register 3-56
DSTPx Register 3-34
Internal
Bus 2-8
Interrrupt Control Register 3-21, 3-44
Interrupt
System 2-6, 3-19
Interrupt Sources 4-43, 4-48
IP Register 3-15
E
L
Early chip select 8-14
Early WR control 8-18
Enable
XBUS peripherals 8-36
Error Detection
ASC0 10-23
ESFR Table (ordered by address) 4-12
ESFR Table (ordered by name) 4-32
External
Bus 2-8
Bus Characteristics 8-16–8-20
Bus Idle State 8-30
Bus Modes 8-2–8-11
Latched chip select 8-14
G
J
JTAG 2-12
M
Master mode
External bus 8-32
MDC Register 3-73
MDH Register 3-72
MDL Register 3-72
Memory
External 4-8
ROM 4-4
Tristate time 8-17
Memory Cycle Time 8-17
Multiplexed Bus 8-3
GPR 4-10
GPT1 12-3
GPT2 12-26
N
H
Hold State 8-33
OCDS 2-12
ONES Register 3-89
I
P
ID Control 2-13
Idle
State (Bus) 8-30
INC 3-36, 3-37
Instruction
Timing 3-87
Interface
External Bus 8-1
P0L, P0H 7-3
P1L, P1H 7-7
P4 7-10, 7-13
PEC 3-32
PEC Control Register 3-36
PEC Pointer Address Handling 3-33
PEC Transfer Count 3-37
PECCx Register 3-36
User’s Manual
NMI 3-18, 3-29
O
14-2
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Keyword Index
PECSNx Register 3-35
Peripheral
Summary 2-8
Peripheral Event Controller 3-32
Pipeline
Effects 3-80
PLEV 3-36
Power Saving Control 2-13
Protected
Bits 3-71
PSW 3-22
PSW Register 3-76
R
Read/Write Delay 8-18
READY 8-18
Register
CP 3-50
CPUID 3-90
CSP 3-15
DPPx 3-56
DSTPx 3-34
IP 3-15
MDC 3-73
MDH 3-72
MDL 3-72
ONES 3-89
PECCx 3-36
PECSNx 3-35
PSW 3-76
SP 3-61
SRCPx 3-34
STKOV 3-62
STKUN 3-63
SYSCON 3-17
TFR 3-27
xxIC 3-21, 3-44
ZEROS 3-89
Reset Control 2-12
S
S0BG 10-17
S0EIC, S0RIC, S0TIC, S0TBIC 10-23
User’s Manual
S0RBUF 10-13, 10-15
S0TBUF 10-11, 10-15
SCU 2-12
Segment
Address 8-12
boundaries 4-9
Serial Interface
Asynchronous 10-9
Synchronous 10-14
SFR 4-5
SFR Table (ordered by address) 4-12
SFR Table (ordered by name) 4-32
Single Chip Mode 8-2
Slave mode
External bus 8-32
SP Register 3-61
SRCPx Register 3-34
SSC
Baudrate generation 11-15
Block diagram 11-4
Error detection 11-17
Full duplex operation 11-10
Half duplex operation 11-13
Interrupts 11-17
Registers ??–11-8
BR 11-15
CON 11-5, 11-6
Overview 10-2, 11-2
RB 11-8
TB 11-8
SSC0_BR 11-15
SSC0_CON 11-5, 11-6
SSC0_RB 11-8
SSC0_TB 11-8
SSC1_BR 11-15
SSC1_CON 11-5, 11-6
SSC1_RB 11-8
SSC1_TB 11-8
STKOV Register 3-62
STKUN Register 3-63
SYSCON 3-16, 3-17, 8-21, 8-36
SYSCON Register 3-17
System Control Unit 2-12
14-3
V 1.6, 2001-08
User’s Manual
C166S V1 SubSystem
Keyword Index
T
T2 12-16
T2CON 12-16
T3CON 12-6
T4 12-16
T4CON 12-16
T5 12-34
T5CON 12-34
T6 12-28
T6CON 12-28
TFR Register 3-27
Timer
Auxiliary Timer 2/4 12-16
Concatenation 12-21, 12-38
Timer 2 12-16
Timer 2 Capture Mode 12-24
Timer 2 Control Register 12-16
Timer 2 Counter Mode 12-20
Timer 2 Gated Mode 12-19
Timer 2 Incremental Interface 12-25
Timer 2 Reload Mode 12-22
Timer 2 Timer Mode 12-19
Timer 3 Control Register 12-6
Timer 3 Counter Mode 12-11
Timer 3 Gated Timer Mode 12-10
Timer 3 Incremental Interface 12-12
Timer 3 Timer Mode 12-9
Timer 4 Capture Mode 12-24
Timer 4 Control Register 12-16
Timer 4 Counter Mode 12-20
Timer 4 Gated Mode 12-19
Timer 4 Incremental Interface 12-25
Timer 4 Reload Mode 12-22
Timer 4 Timer Mode 12-19
Timer 5 12-34
Timer 5 Control Register 12-34
Timer 5 Counter Mode 12-37
Timer 5 Gated Mode 12-36
Timer 5 Timer Mode 12-36
Timer 6
Core Timer 6 12-28
Timer 6 Control Register 12-28
User’s Manual
Timer 6 Counter Mode 12-33
Timer 6 Gated Mode 12-32
Timer 6 Timer Mode 12-31
Timer Block 1 12-3
Timer Block 2 12-26
Timer T3 12-5
Timer4 12-16
Tools 1-5
Trap Number 4-43, 4-48
Traps 3-28
Tristate Time 8-17
V
Vector Location 4-43, 4-48
W
Waitstate
Memory Cycle 8-17
Tristate 8-17
Watchdog Timer 2-13
WDT 2-13
WDTCON 9-3
WDTREL 2-14
X
XADRS 8-37
XBCON 8-38
XBUS 8-35
enable peripherals 8-36
Z
ZEROS Register 3-89
14-4
V 1.6, 2001-08
Infineon goes for Business Excellence
“Business excellence means intelligent approaches and clearly
defined processes, which are both constantly under review and
ultimately lead to good operating results.
Better operating results and business excellence mean less
idleness and wastefulness for all of us, more professional
success, more accurate information, a better overview and,
thereby, less frustration and more satisfaction.”
Dr. Ulrich Schumacher
http://www.infineon.com
Published by Infineon Technologies AG