C167CS-L16M Low Power V1.0

D at a S heet , V 1. 0, O c t . 20 0 1
C167CS-L16M3V
Low Power
1 6 -B it S in g l e -C h i p M i c r o c o n t ro l l e r
M i c r o c o n t ro l le r s
N e v e r
s t o p
t h i n k i n g .
Edition 2001-10
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 2001.
All Rights Reserved.
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characteristics.
Terms of delivery and rights to technical change reserved.
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circuits, descriptions and charts stated herein.
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Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
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list).
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Due to technical requirements components may contain dangerous substances. For information on the types in
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Infineon Technologies Components may only be used in life-support devices or systems with the express written
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D at a S heet , V 1. 0, O c t . 20 0 1
C167CS-L16M3V
Low Power
1 6 -B i t S i n g l e - C h i p M ic r o co n t ro l l e r
M i c r o c o n t ro l le r s
N e v e r
s t o p
t h i n k i n g .
C167CS-3V
Revision History:
2001-10
Previous Version:
---
Page
V1.0
Subjects (major changes)
Controller Area Network (CAN): License of Robert Bosch GmbH
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16-Bit Single-Chip Microcontroller
C166 Family
C167CS-3V
C167CS-3V
• High Performance 16-bit CPU with 4-Stage Pipeline
– 125 ns Instruction Cycle Time at 16 MHz CPU Clock
– 625 ns Multiplication (16 × 16 bit), 1250 ns Division (32/16 bit)
– Enhanced Boolean Bit Manipulation Facilities
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Single-Cycle Context Switching Support
– 16 MBytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area
• 16-Priority-Level Interrupt System with 56 Sources, Sample-Rate down to 62 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC)
• Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5),
via prescaler or via direct clock input
• On-Chip Memory Modules
– 3 KBytes On-Chip Internal RAM (IRAM)
– 8 KBytes On-Chip Extension RAM (XRAM)
• On-Chip Peripheral Modules
– 24-Channel 10-bit A/D Converter with Programmable Conversion Time
down to 7.8 µs
– Two 16-Channel Capture/Compare Units
– 4-Channel PWM Unit
– Two Multi-Functional General Purpose Timer Units with 5 Timers
– Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)
– Two On-Chip CAN Interfaces (Rev. 2.0B active) with 2 × 15 Message Objects
(Full CAN/Basic CAN), can work on one bus with 30 objects
– On-Chip Real Time Clock
• Up to 16 MBytes External Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit
Data Bus Width
– Five Programmable Chip-Select Signals
– Hold- and Hold-Acknowledge Bus Arbitration Support
• Idle, Sleep, and Power Down Modes with Flexible Power Management
• Programmable Watchdog Timer and Oscillator Watchdog
• Up to 111 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis
Data Sheet
1
V1.0, 2001-10
C167CS-L16M3V
Low Power
• Supported by a Large Range of Development Tools like C-Compilers,
Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers, Programming Boards
• On-Chip Bootstrap Loader
• 144-Pin MQFP Package
This document describes several derivatives of the C167 group. Table 1 enumerates
these derivatives and summarizes the differences. As this document refers to all of these
derivatives, some descriptions may not apply to a specific product.
Table 1
C167CS-3V Derivative Synopsis
Derivative1)
Program Memory
Operating Frequency
SAB-C167CS-L16M3V
---
16 MHz
SAF-C167CS-L16M3V
---
16 MHz
1)
This Data Sheet is valid for devices starting with and including design step BA.
For simplicity all versions are referred to by the term C167CS-3V throughout this
document.
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:
• the derivative itself, i.e. its function set, the temperature range, and the supply voltage
• the package and the type of delivery.
For the available ordering codes for the C167CS-3V please refer to the “Product
Catalog Microcontrollers”, which summarizes all available microcontroller variants.
Note: The ordering codes for Mask-ROM versions are defined for each product after
verification of the respective ROM code.
Data Sheet
2
V1.0, 2001-10
C167CS-L16M3V
Low Power
Introduction
The C167CS-3V derivatives are high performance derivatives of the Infineon
C166 Family of full featured single-chip CMOS microcontrollers. They combine high
CPU performance (up to 8 million instructions per second) with high peripheral
functionality and enhanced IO-capabilities. They also provide clock generation via PLL
and various on-chip memory modules such as program ROM, internal RAM, and
extension RAM.
VAREF VAGND VDD
VSS
Port 0
16 Bit
XTAL1
XTAL2
Port 1
16 Bit
RSTIN
RSTOUT
Port 2
16 Bit
NMI
EA
Port 3
15 Bit
C167CS
READY
Port 4
8 Bit
ALE
RD
WR/WRL
Port 6
8 Bit
Port 5
16 Bit
Port 8
8 Bit
Port 7
8 Bit
MCL04411
Figure 1
Logic Symbol
Pin Configuration
(top view)
Data Sheet
3
V1.0, 2001-10
P6.0/CS0
P6.1/CS1
P6.2/CS2
P6.3/CS3
P6.4/CS4
P6.5/HOLD
P6.6/HLDA
P6.7/BREQ
*P8.0/CC16IO
*P8.1/CC17IO
*P8.2/CC18IO
*P8.3/CC19IO
P8.4/CC20IO
P8.5/CC21IO
P8.6/CC22IO
P8.7/CC23IO
VDD
VSS
V SS
V DD
P1L.7/A7/AN23
P1L.6/A6/AN22
P1L.5/A5/AN21
P1L.4/A4/AN20
P1L.3/A3/AN19
P1L.2/A2/AN18
P1L.1/A1/AN17
P1L.0/A0/AN16
P0H.7/AD15
P0H.6/AD14
P0H.5/AD13
P0H.4/AD12
P0H.3/AD11
P0H.2/AD10
P0H.1/AD9
V SS
V DD
P1H.7/A15/CC27IO
P1H.6/A14/CC26IO
P1H.5/A13/CC25IO
P1H.4/A12/CC24IO
P1H.3/A11
P1H.2/A10
P1H.1/A9
P1H.0/A8
V DD
XTAL1
XTAL2
V SS
NMI
RSTOUT
RSTIN
C167CS
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
P0H.0/AD8
P0L.7/AD7
P0L.6/AD6
P0L.5/AD5
P0L.4/AD4
P0L.3/AD3
P0L.2/AD2
P0L.1/AD1
P0L.0/AD0
EA
ALE
READY
WR/WRL
RD
VSS
VDD
P4.7/A23/*
P4.6/A22/*
P4.5/A21/*
P4.4/A20/*
P4.3/A19
P4.2/A18
P4.1/A17
P4.0/A16
N.C.
VSS
VDD
P3.15/CLKOUT/
FOUT
P3.13/SCLK
P3.12/BHE/WRH
P3.111/RxD0
P3.10/TxD0
P3.9/MTSR
P3.8/MRST
P3.7/T2IN
P3.6/T3IN
VSS
VDD
P2.8/CC8IO/EX0IN
P2.9/CC9IO/EX1IN
P2.10/CC10IO/EX2IN
P2.11/CC11IO/EX3IN
P2.12/CC12IO/EX4IN
P2.13/CC13IO/EX5IN
P2.14/CC14IO/EX6IN
P2.15/CC15IO/EX7IN/T7IN
P3.0/T0IN
P3.1/T6OUT
P3.2/CAPIN
P3.3/T3OUT
P3.4/T3EUD
P3.5/T4IN
VSS
VDD
P2.0/CC0IO
P2.1/CC1IO
P2.2/CC2IO
P2.3/CC3IO
P2.4/CC4IO
P2.5/CC5IO
P2.6/CC6IO
P2.7/CC7IO
VSS
VDD
P5.10/AN10/T6EUD
P5.11/AN11/T5EUD
P5.12/AN12/T6IN
P5.13/AN13/T5IN
P5.14/AN14/T4EUD
P5.15/AN15/T2EUD
VAREF
VAGND
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
P7.0/POUT0
P7.1/POUT1
P7.2/POUT2
P7.3/POUT3
P7.4/CC28IO
P7.5/CC29IO
P7.6/CC30IO
P7.7/CC31IO
P5.0/AN0
P5.1/AN1
P5.2/AN2
P5.3/AN3
P5.4/AN4
P5.5/AN5
P5.6/AN6
P5.7/AN7
P5.8/AN8
P5.9/AN9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
V DD
V SS
C167CS-L16M3V
Low Power
MCP04431
Figure 2
*) The marked pins of Port 4 and Port 8 can have CAN interface lines assigned to them.
Table 2 on the pages below lists the possible assignments.
Data Sheet
4
V1.0, 2001-10
C167CS-L16M3V
Low Power
Table 2
Pin Definitions and Functions
Symbol Pin
Num.
Input
Outp.
Function
P6
IO
Port 6 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into highimpedance state. Port 6 outputs can be configured as push/
pull or open drain drivers.
The Port 6 pins also serve for alternate functions:
Chip Select 0 Output
CS0
CS1
Chip Select 1 Output
Chip Select 2 Output
CS2
CS3
Chip Select 3 Output
CS4
Chip Select 4 Output
HOLD
External Master Hold Request Input
Hold Acknowledge Output (master mode)
HLDA
or Input (slave mode)
BREQ
Bus Request Output
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
1
2
3
4
5
6
7
O
O
O
O
O
I
I/O
P6.7
8
O
P8
IO
P8.0
9
P8.1
10
P8.2
11
P8.3
12
P8.4
P8.5
P8.6
P8.7
13
14
15
16
Data Sheet
I/O
I
I
I/O
O
O
I/O
I
I
I/O
I
I
I/O
I/O
I/O
I/O
Port 8 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into highimpedance state. Port 8 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 8 is
selectable (TTL or special). Port 8 pins provide inputs/
outputs for CAPCOM2 and serial interface lines. 1)
CC16IO
CAPCOM2: CC16 Capture Inp./Compare Outp.,
CAN1_RxD CAN 1 Receive Data Input,
CAN2_RxD CAN 2 Receive Data Input
CC17IO
CAPCOM2: CC17 Capture Inp./Compare Outp.,
CAN1_TxD CAN 1 Transmit Data Output,
CAN2_TxD CAN 2 Transmit Data Output
CC18IO
CAPCOM2: CC18 Capture Inp./Compare Outp.,
CAN1_RxD CAN 1 Receive Data Input,
CAN2_RxD CAN 2 Receive Data Input
CC19IO
CAPCOM2: CC19 Capture Inp./Compare Outp.,
CAN1_TxD CAN 1 Transmit Data Output,
CAN2_TxD CAN 2 Transmit Data Output
CC20IO
CAPCOM2: CC20 Capture Inp./Compare Outp.
CC21IO
CAPCOM2: CC21 Capture Inp./Compare Outp.
CC22IO
CAPCOM2: CC22 Capture Inp./Compare Outp.
CC23IO
CAPCOM2: CC23 Capture Inp./Compare Outp.
5
V1.0, 2001-10
C167CS-L16M3V
Low Power
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
Num.
Input
Outp.
Function
P7
IO
Port 7 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into highimpedance state. Port 7 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 7 is
selectable (TTL or special).
The following Port 7 pins also serve for alternate functions:
POUT0
PWM Channel 0 Output
POUT1
PWM Channel 1 Output
POUT2
PWM Channel 2 Output
POUT3
PWM Channel 3 Output
CC28IO
CAPCOM2: CC28 Capture Inp./Compare Outp.
CC29IO
CAPCOM2: CC29 Capture Inp./Compare Outp.
CC30IO
CAPCOM2: CC30 Capture Inp./Compare Outp.
CC31IO
CAPCOM2: CC31 Capture Inp./Compare Outp.
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
19
20
21
22
23
24
25
26
I
P5
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P5.8
P5.9
P5.10
P5.11
P5.12
P5.13
P5.14
P5.15
O
O
O
O
I/O
I/O
I/O
I/O
27
28
29
30
31
32
33
34
35
36
39
40
41
42
43
44
Data Sheet
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Port 5 is a 16-bit input-only port with Schmitt-Trigger char.
The pins of Port 5 also serve as analog input channels for the
A/D converter, or they serve as timer inputs:
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10,
T6EUD GPT2 Timer T6 Ext. Up/Down Ctrl. Inp.
AN11,
T5EUD GPT2 Timer T5 Ext. Up/Down Ctrl. Inp.
AN12,
T6IN
GPT2 Timer T6 Count Inp.
AN13,
T5IN
GPT2 Timer T5 Count Inp.
AN14,
T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp.
AN15,
T2EUD GPT1 Timer T2 Ext. Up/Down Ctrl. Inp.
6
V1.0, 2001-10
C167CS-L16M3V
Low Power
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
Num.
Input
Outp.
Function
P2
IO
Port 2 is a 16-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into highimpedance state. Port 2 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 2 is
selectable (TTL or special).
The following Port 2 pins also serve for alternate functions:
CC0IO
CAPCOM1: CC0 Capture Inp./Compare Output
CC1IO
CAPCOM1: CC1 Capture Inp./Compare Output
CC2IO
CAPCOM1: CC2 Capture Inp./Compare Output
CC3IO
CAPCOM1: CC3 Capture Inp./Compare Output
CC4IO
CAPCOM1: CC4 Capture Inp./Compare Output
CC5IO
CAPCOM1: CC5 Capture Inp./Compare Output
CC6IO
CAPCOM1: CC6 Capture Inp./Compare Output
CC7IO
CAPCOM1: CC7 Capture Inp./Compare Output
CC8IO
CAPCOM1: CC8 Capture Inp./Compare Output,
EX0IN
Fast External Interrupt 0 Input
CC9IO
CAPCOM1: CC9 Capture Inp./Compare Output,
EX1IN
Fast External Interrupt 1 Input
CC10IO
CAPCOM1: CC10 Capture Inp./Compare Outp.,
EX2IN
Fast External Interrupt 2 Input
CC11IO
CAPCOM1: CC11 Capture Inp./Compare Outp.,
EX3IN
Fast External Interrupt 3 Input
CC12IO
CAPCOM1: CC12 Capture Inp./Compare Outp.,
EX4IN
Fast External Interrupt 4 Input
CC13IO
CAPCOM1: CC13 Capture Inp./Compare Outp.,
EX5IN
Fast External Interrupt 5 Input
CC14IO
CAPCOM1: CC14 Capture Inp./Compare Outp.,
EX6IN
Fast External Interrupt 6 Input
CC15IO
CAPCOM1: CC15 Capture Inp./Compare Outp.,
EX7IN
Fast External Interrupt 7 Input,
T7IN
CAPCOM2: Timer T7 Count Input
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P2.8
47
48
49
50
51
52
53
54
57
P2.9
58
P2.10
59
P2.11
60
P2.12
61
P2.13
62
P2.14
63
P2.15
64
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I
Note: During Sleep Mode a spike filter on the EXnIN
interrupt inputs suppresses input pulses <10 ns.
Input pulses >100 ns safely pass the filter.
Data Sheet
7
V1.0, 2001-10
C167CS-L16M3V
Low Power
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
Num.
Input
Outp.
Function
P3
IO
Port 3 is a 15-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into highimpedance state. Port 3 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 3 is
selectable (TTL or special).
The following Port 3 pins also serve for alternate functions:
T0IN
CAPCOM1 Timer T0 Count Input
T6OUT
GPT2 Timer T6 Toggle Latch Output
CAPIN
GPT2 Register CAPREL Capture Input
T3OUT
GPT1 Timer T3 Toggle Latch Output
T3EUD
GPT1 Timer T3 External Up/Down Control Input
T4IN
GPT1 Timer T4 Count/Gate/Reload/Capture Inp
T3IN
GPT1 Timer T3 Count/Gate Input
T2IN
GPT1 Timer T2 Count/Gate/Reload/Capture Inp
MRST
SSC Master-Receive/Slave-Transmit Inp./Outp.
MTSR
SSC Master-Transmit/Slave-Receive Outp./Inp.
T×D0
ASC0 Clock/Data Output (Async./Sync.)
R×D0
ASC0 Data Input (Async.) or Inp./Outp. (Sync.)
External Memory High Byte Enable Signal,
BHE
External Memory High Byte Write Strobe
WRH
SCLK
SSC Master Clock Output / Slave Clock Input.
CLKOUT System Clock Output (= CPU Clock)
FOUT
Programmable Frequency Output
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12
65
66
67
68
69
70
73
74
75
76
77
78
79
P3.13
P3.15
80
81
NC
84
Data Sheet
I
O
I
O
I
I
I
I
I/O
I/O
O
I/O
O
O
I/O
O
O
–
This pin is not connected in the C167CS-3V.
No connection to the PCB is required.
8
V1.0, 2001-10
C167CS-L16M3V
Low Power
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
Num.
Input
Outp.
Function
P4
IO
Port 4 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into highimpedance state. The Port 4 outputs can be configured as
push/pull or open drain drivers. The input threshold of Port 4
is selectable (TTL or special).
Port 4 can be used to output the segment address lines and
for serial interface lines:1)
A16
Least Significant Segment Address Line
A17
Segment Address Line
A18
Segment Address Line
A19
Segment Address Line
A20
Segment Address Line,
CAN2_RxD CAN 2 Receive Data Input
A21
Segment Address Line,
CAN1_RxD CAN 1 Receive Data Input
A22
Segment Address Line,
CAN1_TxD CAN 1 Transmit Data Output,
CAN2_TxD CAN 2 Transmit Data Output
A23
Most Significant Segment Address Line,
CAN1_RxD CAN 1 Receive Data Input,
CAN2_TxD CAN 2 Transmit Data Output,
CAN2_RxD CAN 2 Receive Data Input
P4.0
P4.1
P4.2
P4.3
P4.4
85
86
87
88
89
P4.5
90
P4.6
91
P4.7
92
RD
95
O
External Memory Read Strobe. RD is activated for every
external instruction or data read access.
WR/
WRL
96
O
External Memory Write Strobe. In WR-mode this pin is
activated for every external data write access. In WRL-mode
this pin is activated for low byte data write accesses on a 16bit bus, and for every data write access on an 8-bit bus. See
WRCFG in register SYSCON for mode selection.
I
Ready Input. When the Ready function is enabled, a high
level at this pin during an external memory access will force
the insertion of memory cycle time waitstates until the pin
returns to a low level.
An internal pullup device will hold this pin high when nothing
is driving it.
READY 97
Data Sheet
O
O
O
O
O
I
O
I
O
O
O
O
I
O
I
9
V1.0, 2001-10
C167CS-L16M3V
Low Power
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
Num.
Input
Outp.
Function
ALE
98
O
Address Latch Enable Output. Can be used for latching the
address into external memory or an address latch in the
multiplexed bus modes.
EA
99
I
External Access Enable pin. A low level at this pin during and
after Reset forces the C167CS-3V to begin instruction
execution out of external memory. A high level forces
execution out of the internal program memory.
“ROMless” versions must have this pin tied to ‘0’.
IO
PORT0 consists of the two 8-bit bidirectional I/O ports P0L
and P0H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state.
In case of an external bus configuration, PORT0 serves as
the address (A) and address/data (AD) bus in multiplexed
bus modes and as the data (D) bus in demultiplexed bus
modes.
Demultiplexed bus modes:
Data Path Width:
8-bit
16-bit
P0L.0 – P0L.7:
D0 – D7
D0 - D7
P0H.0 – P0H.7:
I/O
D8 - D15
Multiplexed bus modes:
Data Path Width:
8-bit
16-bit
P0L.0 – P0L.7:
AD0 – AD7 AD0 - AD7
P0H.0 – P0H.7:
A8 - A15
AD8 - AD15
PORT0
P0L.0-7 100107
P0H.0-7 108,
111117
Data Sheet
10
V1.0, 2001-10
C167CS-L16M3V
Low Power
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
Num.
Input
Outp.
Function
PORT1
P1L.0-7 118125
P1H.0-7 128135
IO
P1L.0
P1L.1
P1L.2
P1L.3
P1L.4
P1L.5
P1L.6
P1L.7
P1H.4
P1H.5
P1H.6
P1H.7
118
119
120
121
122
123
124
125
132
133
134
135
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
PORT1 consists of the two 8-bit bidirectional I/O ports P1L
and P1H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state. PORT1 is used as the 16bit address bus (A) in demultiplexed bus modes and also
after switching from a demultiplexed bus mode to a
multiplexed bus mode.
The following PORT1 pins also serve for alternate functions:
AN16
Analog Input Channel 16
AN17
Analog Input Channel 17
AN18
Analog Input Channel 18
AN19
Analog Input Channel 19
AN20
Analog Input Channel 20
AN21
Analog Input Channel 21
AN22
Analog Input Channel 22
AN23
Analog Input Channel 23
CC24IO
CAPCOM2: CC24 Capture Inp./Compare Outp.
CC25IO
CAPCOM2: CC25 Capture Inp./Compare Outp.
CC26IO
CAPCOM2: CC26 Capture Inp./Compare Outp.
CC27IO
CAPCOM2: CC27 Capture Inp./Compare Outp.
XTAL2
XTAL1
137
138
O
I
XTAL2:
XTAL1:
Data Sheet
Output of the oscillator amplifier circuit.
Input to the oscillator amplifier and input to
the internal clock generator
To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC
Characteristics must be observed.
11
V1.0, 2001-10
C167CS-L16M3V
Low Power
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
Num.
Input
Outp.
Function
RSTIN
I/O
Reset Input with Schmitt-Trigger characteristics. A low level
at this pin while the oscillator is running resets the C167CS3V. An internal pullup resistor permits power-on reset using
only a capacitor connected to VSS.
A spike filter suppresses input pulses < 10 ns. Input pulses
> 100 ns safely pass the filter. The minimum duration for a
safe recognition should be 100 ns + 2 CPU clock cycles.
In bidirectional reset mode (enabled by setting bit BDRSTEN
in register SYSCON) the RSTIN line is internally pulled low
for the duration of the internal reset sequence upon any reset
(HW, SW, WDT). See note below this table.
140
Note: To let the reset configuration of PORT0 settle and to
let the PLL lock a reset duration of ca. 1 ms is
recommended.
RST
OUT
141
O
Internal Reset Indication Output. This pin is set to a low level
when the part is executing either a hardware-, a software- or
a watchdog timer reset. RSTOUT remains low until the EINIT
(end of initialization) instruction is executed.
NMI
142
I
Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the C167CS-3V to go into
power down mode. If NMI is high, when PWRDN is
executed, the part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
VAREF
VAGND
37
–
Reference voltage for the A/D converter.
38
–
Reference ground for the A/D converter.
Data Sheet
12
V1.0, 2001-10
C167CS-L16M3V
Low Power
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
Num.
Input
Outp.
Function
VDD
17, 46, –
56, 72,
82, 93,
109,
126,
136,
144
Digital Supply Voltage:
+3.3 V during normal operation and idle mode.
≥2.5 V during power down mode.
VSS
18, 45, –
55, 71,
83, 94,
110,
127,
139,
143
Digital Ground.
1)
The CAN interface lines are assigned to ports P4 and P8 under software control. Within the CAN module
several assignments can be selected.
Note: The following behaviour differences must be observed when the bidirectional reset
is active:
• Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared
automatically after a reset.
• The reset indication flags always indicate a long hardware reset.
• The PORT0 configuration is treated like on a hardware reset. Especially the bootstrap
loader may be activated when P0L.4 is low.
• Pin RSTIN may only be connected to external reset devices with an open drain output
driver.
• A short hardware reset is extended to the duration of the internal reset sequence.
Data Sheet
13
V1.0, 2001-10
C167CS-L16M3V
Low Power
Functional Description
The architecture of the C167CS-3V combines advantages of both RISC and CISC
processors and of advanced peripheral subsystems in a very well-balanced way. In
addition the on-chip memory blocks allow the design of compact systems with maximum
performance.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the C167CS-3V.
Note: All time specifications refer to a CPU clock of 16 MHz
(see definition in the AC Characteristics section).
C166-Core
16
Data
ROM
32 KByte
32
16
CPU
Instr. / Data
Data
16
IRAM
Dual Port
ProgMem
Internal
RAM
3 KByte
Osc / PLL
XRAM
PEC
XTAL
External Instr. / Data
6+2 KByte
Interrupt Controller 16-Level
Priority
RTC
WDT
16
CAN1
8
Port 6
8
Port 4
Rev 2.0B active
Peripheral Data Bus
16
EBC
ADC
ASC0
SSC
10-Bit
16+8
Channels
(USART)
(SPI)
16
PWM CCOM2 CCOM1
T2
T7
T0
T3
T8
T1
T4
XBUS Control
External Bus
Control
Port 0
GPT
Port 2
Rev 2.0B active
Interrupt Bus
On-Chip XBUS (16-Bit Demux)
CAN2
T5
BRGen
Port 1
16
Port 5
T6
BRGen
Port 3
16
15
Port 7
8
16
Port 8
8
MCB04323_7CS
Figure 3
Block Diagram
The program memory, the internal RAM (IRAM) and the set of generic peripherals are
connected to the CPU via separate buses. A fourth bus, the XBUS, connects external
resources as well as additional on-chip resoures, the X-Peripherals (see Figure 3).
The XBUS resources (XRAM, CAN) of the C167CS-3V can be individually enabled or
disabled during initialization. Register XPERCON selects the required modules which
are then enabled by setting the general X-Peripheral enable bit XPEN (SYSCON.2).
Modules that are disabled consume neither address space nor port pins.
Note: The default value of register XPERCON after reset selects 2 KByte XRAM and
module CAN1, so the default XBUS resources are compatible with the C167CR.
Data Sheet
14
V1.0, 2001-10
C167CS-L16M3V
Low Power
Memory Organization
The memory space of the C167CS-3V is configured in a Von Neumann architecture
which means that code memory, data memory, registers and I/O ports are organized
within the same linear address space which includes 16 MBytes. The entire memory
space can be accessed bytewise or wordwise. Particular portions of the on-chip memory
have additionally been made directly bitaddressable.
3 KBytes of on-chip Internal RAM (IRAM) are provided as a storage for user defined
variables, for the system stack, general purpose register banks and even for code. A
register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0,
…, RL7, RH7) so-called General Purpose Registers (GPRs).
1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the C166 Family.
8 KBytes of on-chip Extension RAM (XRAM), organized as two blocks of 2 KByte and
6 KByte, respectively, are provided to store user data, user stacks, or code. The XRAM
is accessed like external memory and therefore cannot be used for the system stack or
for register banks and is not bitaddressable. The XRAM permits 16-bit accesses with
maximum speed.
In order to meet the needs of designs where more memory is required than is provided
on chip, up to 16 MBytes of external RAM and/or ROM can be connected to the
microcontroller.
Data Sheet
15
V1.0, 2001-10
C167CS-L16M3V
Low Power
External Bus Controller
All of the external memory accesses are performed by a particular on-chip External Bus
Controller (EBC). It can be programmed either to Single Chip Mode when no external
memory is required, or to one of four different external memory access modes, which are
as follows:
–
–
–
–
16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed
16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed
16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed
16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed
In the demultiplexed bus modes, addresses are output on PORT1 and data is input/
output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses
and data use PORT0 for input/output.
Important timing characteristics of the external bus interface (Memory Cycle Time,
Memory Tri-State Time, Length of ALE and Read Write Delay) have been made
programmable to allow the user the adaption of a wide range of different types of
memories and external peripherals.
In addition, up to 4 independent address windows may be defined (via register pairs
ADDRSELx / BUSCONx) which control the access to different resources with different
bus characteristics. These address windows are arranged hierarchically where
BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to
locations not covered by these 4 address windows are controlled by BUSCON0.
Up to 5 external CS signals (4 windows plus default) can be generated in order to save
external glue logic. The C167CS-3V offers the possibility to switch the CS outputs to an
unlatched mode. In this mode the internal filter logic is switched off and the CS signals
are directly generated from the address. The unlatched CS mode is enabled by setting
CSCFG (SYSCON.6).
Access to very slow memories or memories with varying access times is supported via
a particular ‘Ready’ function.
A HOLD/HLDA protocol is available for bus arbitration and allows to share external
resources with other bus masters. The bus arbitration is enabled by setting bit HLDEN
in register PSW. After setting HLDEN once, pins P6.7 … P6.5 (BREQ, HLDA, HOLD)
are automatically controlled by the EBC. In Master Mode (default after reset) the HLDA
pin is an output. By setting bit DP6.7 to ‘1’ the Slave Mode is selected where pin HLDA
is switched to input. This allows to directly connect the slave controller to another master
controller without glue logic.
For applications which require less than 16 MBytes of external memory space, this
address space can be restricted to 1 MByte, 256 KByte, or to 64 KByte. In this case
Port 4 outputs four, two, or no address lines at all. It outputs all 8 address lines, if an
address space of 16 MBytes is used.
Data Sheet
16
V1.0, 2001-10
C167CS-L16M3V
Low Power
Note: When one or both of the on-chip CAN Modules are used with the interface lines
assigned to Port 4, the CAN lines override the segment address lines and the
segment address output on Port 4 is therefore limited to 6/4 bits i.e. address lines
A21/A19 … A16. CS lines can be used to increase the total amount of
addressable external memory.
Central Processing Unit (CPU)
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic
and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a
separate multiply and divide unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the C167CS-3V’s instructions can be
executed in just one machine cycle which requires 50 ns at 40 MHz CPU clock. For
example, shift and rotate instructions are always processed during one machine cycle
independent of the number of bits to be shifted. All multiple-cycle instructions have been
optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 × 16
bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline
optimization, the so-called ‘Jump Cache’, allows reducing the execution time of
repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
CPU
Internal
RAM
SP
STKOV
STKUN
MDH
MDL
R15
Exec. Unit
Instr. Ptr.
Instr. Reg.
Mul/Div-HW
Bit-Mask Gen
General
4-Stage
Pipeline
R15
Purpose
ALU
32
ROM
16
(16-bit)
Barrel - Shifter
Registers
R0
PSW
SYSCON
Context Ptr.
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3
ADDRSEL 4
Data Page Ptr.
Code Seg. Ptr.
R0
16
MCB02147
Figure 4
Data Sheet
CPU Block Diagram
17
V1.0, 2001-10
C167CS-L16M3V
Low Power
The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal.
These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer
(CP) register determines the base address of the active register bank to be accessed by
the CPU at any time. The number of register banks is only restricted by the available
internal RAM space. For easy parameter passing, a register bank may overlap others.
A system stack of up to 1024 words is provided as a storage for temporary data. The
system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the
stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly
compared against the stack pointer value upon each stack access for the detection of a
stack overflow or underflow.
The high performance offered by the hardware implementation of the CPU can efficiently
be utilized by a programmer via the highly efficient C167CS-3V instruction set which
includes the following instruction classes:
–
–
–
–
–
–
–
–
–
–
–
–
Arithmetic Instructions
Logical Instructions
Boolean Bit Manipulation Instructions
Compare and Loop Control Instructions
Shift and Rotate Instructions
Prioritize Instruction
Data Movement Instructions
System Stack Instructions
Jump and Call Instructions
Return Instructions
System Control Instructions
Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes
and words. A variety of direct, indirect or immediate addressing modes are provided to
specify the required operands.
Data Sheet
18
V1.0, 2001-10
C167CS-L16M3V
Low Power
Interrupt System
With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of
internal program execution), the C167CS-3V is capable of reacting very fast to the
occurrence of non-deterministic events.
The architecture of the C167CS-3V supports several mechanisms for fast and flexible
response to service requests that can be generated from various sources internal or
external to the microcontroller. Any of these interrupt requests can be programmed to
being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is
suspended and a branch to the interrupt vector table is performed, just one cycle is
‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a
single byte or word data transfer between any two memory locations with an additional
increment of either the PEC source or the destination pointer. An individual PEC transfer
counter is implicity decremented for each PEC service except when performing in the
continuous transfer mode. When this counter reaches zero, a standard interrupt is
performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data.
The C167CS-3V has 8 PEC channels each of which offers such fast interrupt-driven data
transfer capabilities.
A separate control register which contains an interrupt request flag, an interrupt enable
flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via
its related register, each source can be programmed to one of sixteen interrupt priority
levels. Once having been accepted by the CPU, an interrupt service can only be
interrupted by a higher prioritized service request. For the standard interrupt processing,
each of the possible interrupt sources has a dedicated vector location.
Fast external interrupt inputs are provided to service external interrupts with high
precision requirements. These fast interrupt inputs feature programmable edge
detection (rising edge, falling edge or both edges).
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with
an individual trap (interrupt) number.
Table 3 shows all of the possible C167CS-3V interrupt sources and the corresponding
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.
Note: Interrupt nodes which are not used by associated peripherals, may be used to
generate software controlled interrupt requests by setting the respective interrupt
request bit (xIR).
Data Sheet
19
V1.0, 2001-10
C167CS-L16M3V
Low Power
Table 3
C167CS-3V Interrupt Nodes
Source of Interrupt or Request
PEC Service Request Flag
Enable
Flag
Interrupt
Vector
Vector
Location
Trap
Number
CAPCOM Register 0
CC0IR
CC0IE
CC0INT
00’0040H
10H
CAPCOM Register 1
CC1IR
CC1IE
CC1INT
00’0044H
11H
CAPCOM Register 2
CC2IR
CC2IE
CC2INT
00’0048H
12H
CAPCOM Register 3
CC3IR
CC3IE
CC3INT
00’004CH
13H
CAPCOM Register 4
CC4IR
CC4IE
CC4INT
00’0050H
14H
CAPCOM Register 5
CC5IR
CC5IE
CC5INT
00’0054H
15H
CAPCOM Register 6
CC6IR
CC6IE
CC6INT
00’0058H
16H
CAPCOM Register 7
CC7IR
CC7IE
CC7INT
00’005CH
17H
CAPCOM Register 8
CC8IR
CC8IE
CC8INT
00’0060H
18H
CAPCOM Register 9
CC9IR
CC9IE
CC9INT
00’0064H
19H
CAPCOM Register 10
CC10IR
CC10IE
CC10INT
00’0068H
1AH
CAPCOM Register 11
CC11IR
CC11IE
CC11INT
00’006CH
1BH
CAPCOM Register 12
CC12IR
CC12IE
CC12INT
00’0070H
1CH
CAPCOM Register 13
CC13IR
CC13IE
CC13INT
00’0074H
1DH
CAPCOM Register 14
CC14IR
CC14IE
CC14INT
00’0078H
1EH
CAPCOM Register 15
CC15IR
CC15IE
CC15INT
00’007CH
1FH
CAPCOM Register 16
CC16IR
CC16IE
CC16INT
00’00C0H
30H
CAPCOM Register 17
CC17IR
CC17IE
CC17INT
00’00C4H
31H
CAPCOM Register 18
CC18IR
CC18IE
CC18INT
00’00C8H
32H
CAPCOM Register 19
CC19IR
CC19IE
CC19INT
00’00CCH
33H
CAPCOM Register 20
CC20IR
CC20IE
CC20INT
00’00D0H
34H
CAPCOM Register 21
CC21IR
CC21IE
CC21INT
00’00D4H
35H
CAPCOM Register 22
CC22IR
CC22IE
CC22INT
00’00D8H
36H
CAPCOM Register 23
CC23IR
CC23IE
CC23INT
00’00DCH
37H
CAPCOM Register 24
CC24IR
CC24IE
CC24INT
00’00E0H
38H
CAPCOM Register 25
CC25IR
CC25IE
CC25INT
00’00E4H
39H
CAPCOM Register 26
CC26IR
CC26IE
CC26INT
00’00E8H
3AH
CAPCOM Register 27
CC27IR
CC27IE
CC27INT
00’00ECH
3BH
CAPCOM Register 28
CC28IR
CC28IE
CC28INT
00’00E0H
3CH
CAPCOM Register 29
CC29IR
CC29IE
CC29INT
00’0110H
44H
Data Sheet
20
V1.0, 2001-10
C167CS-L16M3V
Low Power
Table 3
C167CS-3V Interrupt Nodes (cont’d)
Source of Interrupt or Request
PEC Service Request Flag
Enable
Flag
Interrupt
Vector
Vector
Location
Trap
Number
CAPCOM Register 30
CC30IR
CC30IE
CC30INT
00’0114H
45H
CAPCOM Register 31
CC31IR
CC31IE
CC31INT
00’0118H
46H
CAPCOM Timer 0
T0IR
T0IE
T0INT
00’0080H
20H
CAPCOM Timer 1
T1IR
T1IE
T1INT
00’0084H
21H
CAPCOM Timer 7
T7IR
T7IE
T7INT
00’00F4H
3DH
CAPCOM Timer 8
T8IR
T8IE
T8INT
00’00F8H
3EH
GPT1 Timer 2
T2IR
T2IE
T2INT
00’0088H
22H
GPT1 Timer 3
T3IR
T3IE
T3INT
00’008CH
23H
GPT1 Timer 4
T4IR
T4IE
T4INT
00’0090H
24H
GPT2 Timer 5
T5IR
T5IE
T5INT
00’0094H
25H
GPT2 Timer 6
T6IR
T6IE
T6INT
00’0098H
26H
GPT2 CAPREL Reg.
CRIR
CRIE
CRINT
00’009CH
27H
A/D Conversion
Complete
ADCIR
ADCIE
ADCINT
00’00A0H
28H
A/D Overrun Error
ADEIR
ADEIE
ADEINT
00’00A4H
29H
ASC0 Transmit
S0TIR
S0TIE
S0TINT
00’00A8H
2AH
ASC0 Transmit Buffer
S0TBIR
S0TBIE
S0TBINT
00’011CH
47H
ASC0 Receive
S0RIR
S0RIE
S0RINT
00’00ACH
2BH
ASC0 Error
S0EIR
S0EIE
S0EINT
00’00B0H
2CH
SSC Transmit
SCTIR
SCTIE
SCTINT
00’00B4H
2DH
SSC Receive
SCRIR
SCRIE
SCRINT
00’00B8H
2EH
SSC Error
SCEIR
SCEIE
SCEINT
00’00BCH
2FH
PWM Channel 0...3
PWMIR
PWMIE
PWMINT
00’00FCH
3FH
CAN Interface 1
XP0IR
XP0IE
XP0INT
00’0100H
40H
CAN Interface 2
XP1IR
XP1IE
XP1INT
00’0104H
41H
Unassigned node
XP2IR
XP2IE
XP2INT
00’0108H
42H
PLL/OWD and RTC
XP3IR
XP3IE
XP3INT
00’010CH
43H
Data Sheet
21
V1.0, 2001-10
C167CS-L16M3V
Low Power
The C167CS-3V also provides an excellent mechanism to identify and to process
exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’.
Hardware traps cause immediate non-maskable system reaction which is similar to a
standard interrupt service (branching to a dedicated vector table location). The
occurence of a hardware trap is additionally signified by an individual bit in the trap flag
register (TFR). Except when another higher prioritized trap service is in progress, a
hardware trap will interrupt any actual program execution. In turn, hardware trap services
can normally not be interrupted by standard or PEC interrupts.
Table 4 shows all of the possible exceptions or error conditions that can arise during runtime:
Table 4
Hardware Trap Summary
Exception Condition
Trap
Flag
Reset Functions:
– Hardware Reset
– Software Reset
– W-dog Timer Overflow
–
Class A Hardware Traps:
– Non-Maskable Interrupt NMI
– Stack Overflow
STKOF
– Stack Underflow
STKUF
Class B Hardware Traps:
– Undefined Opcode
– Protected Instruction
Fault
– Illegal Word Operand
Access
– Illegal Instruction
Access
– Illegal External Bus
Access
Trap
Vector
Vector
Location
Trap
Number
Trap
Priority
RESET
RESET
RESET
00’0000H
00’0000H
00’0000H
00H
00H
00H
III
III
III
NMITRAP 00’0008H
STOTRAP 00’0010H
STUTRAP 00’0018H
02H
04H
06H
II
II
II
UNDOPC BTRAP
PRTFLT BTRAP
00’0028H
00’0028H
0AH
0AH
I
I
ILLOPA
BTRAP
00’0028H
0AH
I
ILLINA
BTRAP
00’0028H
0AH
I
ILLBUS
BTRAP
00’0028H
0AH
I
Reserved
–
–
[2CH –
3CH]
[0BH –
0FH]
–
Software Traps
– TRAP Instruction
–
–
Any
Any
[00’0000H – [00H –
00’01FCH] 7FH]
in steps
of 4H
Data Sheet
22
Current
CPU
Priority
V1.0, 2001-10
C167CS-L16M3V
Low Power
Capture/Compare (CAPCOM) Units
The CAPCOM units support generation and control of timing sequences on up to
32 channels with a maximum resolution of 16 TCL. The CAPCOM units are typically
used to handle high speed I/O tasks such as pulse and waveform generation, pulse
width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time
recording relative to external events.
Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time
bases for the capture/compare register array.
The input clock for the timers is programmable to several prescaled values of the internal
system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.
This provides a wide range of variation for the timer period and resolution and allows
precise adjustments to the application specific requirements. In addition, external count
inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/compare
registers relative to external events.
Both of the two capture/compare register arrays contain 16 dual purpose capture/
compare registers, each of which may be individually allocated to either CAPCOM timer
T0 or T1 (T7 or T8, respectively), and programmed for capture or compare function.
Each register has one port pin associated with it which serves as an input pin for
triggering the capture function, or as an output pin to indicate the occurrence of a
compare event.
When a capture/compare register has been selected for capture mode, the current
contents of the allocated timer will be latched (‘capture’d) into the capture/compare
register in response to an external event at the port pin which is associated with this
register. In addition, a specific interrupt request for this capture/compare register is
generated. Either a positive, a negative, or both a positive and a negative external signal
transition at the pin can be selected as the triggering event. The contents of all registers
which have been selected for one of the five compare modes are continuously compared
with the contents of the allocated timers. When a match occurs between the timer value
and the value in a capture/compare register, specific actions will be taken based on the
selected compare mode.
Data Sheet
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Table 5
Compare Modes (CAPCOM)
Compare Modes
Function
Mode 0
Interrupt-only compare mode;
several compare interrupts per timer period are possible
Mode 1
Pin toggles on each compare match;
several compare events per timer period are possible
Mode 2
Interrupt-only compare mode;
only one compare interrupt per timer period is generated
Mode 3
Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow;
only one compare event per timer period is generated
Double
Register Mode
Two registers operate on one pin;
pin toggles on each compare match;
several compare events per timer period are possible.
Data Sheet
24
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Reload Reg. TxREL
fCPU
2n : 1
TxIN
Tx
Input
Control
CAPCOM Timer Tx
Mode
Control
(Capture
or
Compare)
16-Bit
Capture/
Compare
Registers
Ty
Input
Control
CAPCOM Timer Ty
Interrupt
Request
(TxIR)
GPT2 Timer T6
Over/Underflow
CCxIO
16 Capture Inputs
16 Compare Outputs
16 Capture/Compare
Interrupt Request
CCxIO
fCPU
GPT2 Timer T6
Over/Underflow
2n : 1
x = 0, 7
y = 1, 8
n = 3 … 10
Figure 5
Interrupt
Request
(TyIR)
Reload Reg. TyREL
MCB02143B
CAPCOM Unit Block Diagram
PWM Module
The Pulse Width Modulation Module can generate up to four PWM output signals using
edge-aligned or center-aligned PWM. In addition the PWM module can generate PWM
burst signals and single shot outputs. The frequency range of the PWM signals covers
2 Hz to 8 MHz (referred to a CPU clock of 16 MHz), depending on the resolution of the
PWM output signal. The level of the output signals is selectable and the PWM module
can generate interrupt requests.
Data Sheet
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Low Power
General Purpose Timer (GPT) Unit
The GPT unit represents a very flexible multifunctional timer/counter structure which
may be used for many different time related tasks such as event timing and counting,
pulse width and duty cycle measurements, pulse generation, or pulse multiplication.
The GPT unit incorporates five 16-bit timers which are organized in two separate
modules, GPT1 and GPT2. Each timer in each module may operate independently in a
number of different modes, or may be concatenated with another timer of the same
module.
Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for
one of four basic modes of operation, which are Timer, Gated Timer, Counter, and
Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from
the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer
to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the
operation of a timer is controlled by the ‘gate’ level on an external input pin. For these
purposes, each timer has one associated port pin (TxIN) which serves as gate or clock
input. The maximum resolution of the timers in module GPT1 is 16 TCL.
The count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal on a port pin (TxEUD) to
facilitate e.g. position tracking.
In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected
to the incremental position sensor signals A and B via their respective inputs TxIN and
TxEUD. Direction and count signals are internally derived from these two input signals,
so the contents of the respective timer Tx corresponds to the sensor position. The third
position sensor signal TOP0 can be connected to an interrupt input.
Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer overflow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out
monitoring of external hardware components, or may be used internally to clock timers
T2 and T4 for measuring long time periods with high resolution.
In addition to their basic operating modes, timers T2 and T4 may be configured as reload
or capture registers for timer T3. When used as capture or reload registers, timers T2
and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a
signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2
or T4 triggered either by an external signal or by a selectable state transition of its toggle
latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite
state transitions of T3OTL with the low and high times of a PWM signal, this signal can
be constantly generated without software intervention.
Data Sheet
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Low Power
T2EUD
fCPU
U/D
2n : 1
T2IN
Interrupt
Request
(T2IR)
GPT1 Timer T2
T2
Mode
Control
Reload
Capture
fCPU
Interrupt
Request
(T3IR)
2n : 1
Toggle FF
T3
Mode
Control
T3IN
GPT1 Timer T3
T3OTL
T3OUT
U/D
T3EUD
Capture
Reload
T4IN
fCPU
2n : 1
T4
Mode
Control
GPT1 Timer T4
Interrupt
Request
(T4IR)
U/D
T4EUD
MCT04825
n = 3 … 10
Figure 6
Block Diagram of GPT1
With its maximum resolution of 8 TCL, the GPT2 module provides precise event control
and time measurement. It includes two timers (T5, T6) and a capture/reload register
(CAPREL). Both timers can be clocked with an input clock which is derived from the CPU
clock via a programmable prescaler or with external signals. The count direction (up/
down) for each timer is programmable by software or may additionally be altered
dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is
supported via the output toggle latch (T6OTL) of timer T6, which changes its state on
each timer overflow/underflow.
The state of this latch may be used to clock timer T5, and/or it may be output on pin
T6OUT. The overflows/underflows of timer T6 can additionally be used to clock the
CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The
CAPREL register may capture the contents of timer T5 based on an external signal
transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared
Data Sheet
27
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after the capture procedure. This allows the C167CS-3V to measure absolute time
differences or to perform pulse multiplication without software overhead.
The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of
GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3
operates in Incremental Interface Mode.
T5EUD
fCPU
2n : 1
T5IN
T5
Mode
Control
U/D
Interrupt
Request
GPT2 Timer T5
Clear
Capture
Interrupt
Request
T3
MUX
GPT2 CAPREL
CAPIN
Interrupt
Request
CT3
GPT2 Timer T6
T6IN
fCPU
2n :
1
T6OTL
T6OUT
U/D
T6
Mode
Control
Other
Timers
T6EUD
MCB03999
n=2…9
Figure 7
Data Sheet
Block Diagram of GPT2
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Real Time Clock
The Real Time Clock (RTC) module of the C167CS-3V consists of a chain of 3 divider
blocks, a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer
(accessible via registers RTCH and RTCL). The RTC module is directly clocked with the
on-chip oscillator frequency divided by 32 via a separate clock driver (fRTC = fOSC/32)
and is therefore independent from the selected clock generation mode of the C167CS3V. All timers count up.
The RTC module can be used for different purposes:
• System clock to determine the current time and date
• Cyclic time based interrupt
• 48-bit timer for long term measurements
T14REL
Reload
T14
8:1
f RTC
Interrupt
Request
RTCH
RTCL
MCD04432
Figure 8
RTC Block Diagram
Note: The registers associated with the RTC are not affected by a reset in order to
maintain the correct system time even when intermediate resets are executed.
Data Sheet
29
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A/D Converter
For analog signal measurement, a 10-bit A/D converter with 24 multiplexed input
channels (16 standard channels and 8 extension channels) and a sample and hold
circuit has been integrated on-chip. It uses the method of successive approximation. The
sample time (for loading the capacitors) and the conversion time is programmable and
can so be adjusted to the external circuitry.
Overrun error detection/protection is provided for the conversion result register
(ADDAT): either an interrupt request will be generated when the result of a previous
conversion has not been read from the result register at the time the next conversion is
complete, or the next conversion is suspended in such a case until the previous result
has been read.
For applications which require less than 24 analog input channels, the remaining
channel inputs can be used as digital input port pins.
The A/D converter of the C167CS-3V supports four different conversion modes. In the
standard Single Channel conversion mode, the analog level on a specified channel is
sampled once and converted to a digital result. In the Single Channel Continuous mode,
the analog level on a specified channel is repeatedly sampled and converted without
software intervention. In the Auto Scan mode, the analog levels on a prespecified
number of channels (standard or extension) are sequentially sampled and converted. In
the Auto Scan Continuous mode, the number of prespecified channels is repeatedly
sampled and converted. In addition, the conversion of a specific channel can be inserted
(injected) into a running sequence without disturbing this sequence. This is called
Channel Injection Mode.
The Peripheral Event Controller (PEC) may be used to automatically store the
conversion results into a table in memory for later evaluation, without requiring the
overhead of entering and exiting interrupt routines for each data transfer.
After each reset and also during normal operation the ADC automatically performs
calibration cycles. This automatic self-calibration constantly adjusts the converter to
changing operating conditions (e.g. temperature) and compensates process variations.
These calibration cycles are part of the conversion cycle, so they do not affect the normal
operation of the A/D converter.
In order to decouple analog inputs from digital noise and to avoid input trigger noise
those pins used for analog input can be disconnected from the digital IO or input stages
under software control. This can be selected for each pin separately via registers
P5DIDIS (Port 5 Digital Input Disable) and P1DIDIS (PORT1 Digital Input Disable).
Data Sheet
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Serial Channels
Serial communication with other microcontrollers, processors, terminals or external
peripheral components is provided by two serial interfaces with different functionality, an
Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous
Serial Channel (SSC).
The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller
families and supports full-duplex asynchronous communication at up to 500 KBaud and
half-duplex synchronous communication at up to 2.0 MBaud (@ 16 MHz CPU clock).
A dedicated baud rate generator allows to set up all standard baud rates without
oscillator tuning. For transmission, reception and error handling 4 separate interrupt
vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or
received, preceded by a start bit and terminated by one or two stop bits. For
multiprocessor communication, a mechanism to distinguish address from data bytes has
been included (8-bit data plus wake up bit mode).
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a
shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop
back option is available for testing purposes.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. A parity bit can automatically be generated on
transmission or be checked on reception. Framing error detection allows to recognize
data frames with missing stop bits. An overrun error will be generated, if the last
character received has not been read out of the receive buffer register at the time the
reception of a new character is complete.
The SSC supports full-duplex synchronous communication at up to 4.0 MBaud
(@ 16 MHz CPU clock). It may be configured so it interfaces with serially linked
peripheral components. A dedicated baud rate generator allows to set up all standard
baud rates without oscillator tuning. For transmission, reception and error handling 3
separate interrupt vectors are provided.
The SSC transmits or receives characters of 2 … 16 bits length synchronously to a shift
clock which can be generated by the SSC (master mode) or by an external master (slave
mode). The SSC can start shifting with the LSB or with the MSB and allows the selection
of shifting and latching clock edges as well as the clock polarity.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. Transmit and receive error supervise the correct handling
of the data buffer. Phase and baudrate error detect incorrect serial data.
Data Sheet
31
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CAN-Modules
The integrated CAN-Modules handle the completely autonomous transmission and
reception of CAN frames in accordance with the CAN specification V2.0 part B (active),
i.e. the on-chip CAN-Modules can receive and transmit standard frames with 11-bit
identifiers as well as extended frames with 29-bit identifiers.
The modules provide Full CAN functionality on up to 15 message objects each. Message
object 15 may be configured for Basic CAN functionality. Both modes provide separate
masks for acceptance filtering which allows to accept a number of identifiers in Full CAN
mode and also allows to disregard a number of identifiers in Basic CAN mode. All
message objects can be updated independent from the other objects and are equipped
for the maximum message length of 8 bytes.
The bit timing is derived from the XCLK and is programmable up to a data rate of
1 MBaud. Each CAN-Module uses two pins of Port 4 or Port 8 to interface to an external
bus transceiver. The interface pins are assigned via software.
Module CAN2 is identical with the first one, except that it uses a separate address area
and a separate interrupt node.
The two CAN modules can be internally coupled by assigning their interface pins to the
same two port pins, or they can interface to separate CAN buses.
Note: When any CAN interface is assigned to Port 4, the respective segment address
lines on Port 4 cannot be used. This will limit the external address space.
Watchdog Timer
The Watchdog Timer represents one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can only be
disabled in the time interval until the EINIT (end of initialization) instruction has been
executed. Thus, the chip’s start-up procedure is always monitored. The software has to
be designed to service the Watchdog Timer before it overflows. If, due to hardware or
software related failures, the software fails to do so, the Watchdog Timer overflows and
generates an internal hardware reset and pulls the RSTOUT pin low in order to allow
external hardware components to be reset.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by 2/4/128/
256. The high byte of the Watchdog Timer register can be set to a prespecified reload
value (stored in WDTREL) in order to allow further variation of the monitored time
interval. Each time it is serviced by the application software, the high byte of the
Watchdog Timer is reloaded. Thus, time intervals between 32 µs and 1049 ms can be
monitored (@ 16 MHz).
The default Watchdog Timer interval after reset is 8.2 ms (@ 16 MHz).
Data Sheet
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Parallel Ports
The C167CS-3V provides up to 111 I/O lines which are organized into eight input/output
ports and one input port. All port lines are bit-addressable, and all input/output lines are
individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O
ports are true bidirectional ports which are switched to high impedance state when
configured as inputs. The output drivers of five I/O ports can be configured (pin by pin)
for push/pull operation or open-drain operation via control registers. During the internal
reset, all port pins are configured as inputs.
The input threshold of Port 2, Port 3, Port 7, and Port 8 is selectable (TTL or CMOS like),
where the special CMOS like input threshold reduces noise sensitivity due to the input
hysteresis. The input threshold may be selected individually for each byte of the
respective ports.
All port lines have programmable alternate input or output functions associated with
them. All port lines that are not used for these alternate functions may be used as general
purpose IO lines.
PORT0 and PORT1 may be used as address and data lines when accessing external
memory, while Port 4 outputs the additional segment address bits A23/19/17 … A16 in
systems where segmentation is enabled to access more than 64 KBytes of memory.
Port 2, Port 8 and Port 7 (and parts of PORT1) are associated with the capture inputs or
compare outputs of the CAPCOM units and/or with the outputs of the PWM module.
Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select
signals.
Port 3 includes alternate functions of timers, serial interfaces, the optional bus control
signal BHE/WRH, and the system clock output CLKOUT (or the programmable
frequency output FOUT).
Port 5 (and parts of PORT1) is used for the analog input channels to the A/D converter
or timer control signals.
The edge characteristics (transition time) and driver characteristics (output current) of
the C167CS-3V’s port drivers can be selected via the Port Output Control registers
(POCONx).
Data Sheet
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Oscillator Watchdog
The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip
oscillator (either with a crystal or via external clock drive). For this operation the PLL
provides a clock signal which is used to supervise transitions on the oscillator clock. This
PLL clock is independent from the XTAL1 clock. When the expected oscillator clock
transitions are missing the OWD activates the PLL Unlock/OWD interrupt node and
supplies the CPU with the PLL clock signal. Under these circumstances the PLL will
oscillate with its basic frequency.
In direct drive mode the PLL base frequency is used directly (fCPU = 2 … 5 MHz).
In prescaler mode the PLL base frequency is divided by 2 (fCPU = 1 … 2.5 MHz).
Note: The CPU clock source is only switched back to the oscillator clock after a
hardware reset.
The oscillator watchdog can be disabled by setting bit OWDDIS in register SYSCON.
In this case (OWDDIS = ‘1’) the PLL remains idle and provides no clock signal, while the
CPU clock signal is derived directly from the oscillator clock or via prescaler or SDD. Also
no interrupt request will be generated in case of a missing oscillator clock.
Note: At the end of a reset bit OWDDIS reflects the inverted level of pin RD at that time.
Thus the oscillator watchdog may also be disabled via hardware by (externally)
pulling the RD line low upon a reset, similar to the standard reset configuration via
PORT0.
Data Sheet
34
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Power Management
The C167CS-3V provides several means to control the power it consumes either at a
given time or averaged over a certain timespan. Three mechanisms can be used (partly
in parallel):
• Power Saving Modes switch the C167CS-3V into a special operating mode (control
via instructions).
Idle Mode stops the CPU while the peripherals can continue to operate.
Sleep Mode and Power Down Mode stop all clock signals and all operation (RTC may
optionally continue running). Sleep Mode can be terminated by external interrupt
signals.
• Clock Generation Management controls the distribution and the frequency of
internal and external clock signals (control via register SYSCON2).
Slow Down Mode lets the C167CS-3V run at a CPU clock frequency of fOSC/1 … 32
(half for prescaler operation) which drastically reduces the consumed power. The PLL
can be optionally disabled while operating in Slow Down Mode.
External circuitry can be controlled via the programmable frequency output FOUT.
• Peripheral Management permits temporary disabling of peripheral modules (control
via register SYSCON3).
Each peripheral can separately be disabled/enabled. A group control option disables
a major part of the peripheral set by setting one single bit.
The on-chip RTC supports intermittend operation of the C167CS-3V by generating cyclic
wakeup signals. This offers full performance to quickly react on action requests while the
intermittend sleep phases greatly reduce the average power consumption of the system.
Data Sheet
35
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Instruction Set Summary
Table 6 lists the instructions of the C167CS-3V in a condensed way.
The various addressing modes that can be used with a specific instruction, the operation
of the instructions, parameters for conditional execution of instructions, and the opcodes
for each instruction can be found in the “C166 Family Instruction Set Manual”.
This document also provides a detailled description of each instruction.
Table 6
Mnemonic
ADD(B)
ADDC(B)
SUB(B)
SUBC(B)
MUL(U)
DIV(U)
DIVL(U)
CPL(B)
NEG(B)
AND(B)
OR(B)
XOR(B)
BCLR
BSET
BMOV(N)
BAND, BOR,
BXOR
BCMP
BFLDH/L
CMP(B)
CMPD1/2
CMPI1/2
PRIOR
SHL / SHR
ROL / ROR
ASHR
Data Sheet
Instruction Set Summary
Description
Add word (byte) operands
Add word (byte) operands with Carry
Subtract word (byte) operands
Subtract word (byte) operands with Carry
(Un)Signed multiply direct GPR by direct GPR (16-16-bit)
(Un)Signed divide register MDL by direct GPR (16-/16-bit)
(Un)Signed long divide reg. MD by direct GPR (32-/16-bit)
Complement direct word (byte) GPR
Negate direct word (byte) GPR
Bitwise AND, (word/byte operands)
Bitwise OR, (word/byte operands)
Bitwise XOR, (word/byte operands)
Clear direct bit
Set direct bit
Move (negated) direct bit to direct bit
AND/OR/XOR direct bit with direct bit
Bytes
2/4
2/4
2/4
2/4
2
2
2
2
2
2/4
2/4
2/4
2
2
4
4
Compare direct bit to direct bit
Bitwise modify masked high/low byte of bit-addressable
direct word memory with immediate data
Compare word (byte) operands
Compare word data to GPR and decrement GPR by 1/2
Compare word data to GPR and increment GPR by 1/2
Determine number of shift cycles to normalize direct
word GPR and store result in direct word GPR
Shift left/right direct word GPR
Rotate left/right direct word GPR
Arithmetic (sign bit) shift right direct word GPR
4
4
36
2/4
2/4
2/4
2
2
2
2
V1.0, 2001-10
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Table 6
Instruction Set Summary (cont’d)
Mnemonic
MOV(B)
MOVBS
MOVBZ
JMPA, JMPI,
JMPR
JMPS
J(N)B
JBC
JNBS
CALLA, CALLI,
CALLR
CALLS
PCALL
TRAP
PUSH, POP
SCXT
RET
RETS
RETP
RETI
SRST
IDLE
PWRDN
SRVWDT
DISWDT
EINIT
ATOMIC
EXTR
EXTP(R)
EXTS(R)
NOP
Data Sheet
Description
Move word (byte) data
Move byte operand to word operand with sign extension
Move byte operand to word operand. with zero extension
Jump absolute/indirect/relative if condition is met
Bytes
2/4
2/4
2/4
4
Jump absolute to a code segment
Jump relative if direct bit is (not) set
Jump relative and clear bit if direct bit is set
Jump relative and set bit if direct bit is not set
Call absolute/indirect/relative subroutine if condition is met
4
4
4
4
4
Call absolute subroutine in any code segment
Push direct word register onto system stack and call
absolute subroutine
Call interrupt service routine via immediate trap number
Push/pop direct word register onto/from system stack
Push direct word register onto system stack und update
register with word operand
Return from intra-segment subroutine
Return from inter-segment subroutine
Return from intra-segment subroutine and pop direct
word register from system stack
Return from interrupt service subroutine
Software Reset
Enter Idle Mode
Enter Power Down Mode (supposes NMI-pin being low)
Service Watchdog Timer
Disable Watchdog Timer
Signify End-of-Initialization on RSTOUT-pin
Begin ATOMIC sequence
Begin EXTended Register sequence
Begin EXTended Page (and Register) sequence
Begin EXTended Segment (and Register) sequence
Null operation
4
4
37
2
2
4
2
2
2
2
4
4
4
4
4
4
2
2
2/4
2/4
2
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Special Function Registers Overview
Table 7 lists all SFRs which are implemented in the C167CS-3V in alphabetical order.
Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the
Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical
Address”. Registers within on-chip X-peripherals are marked with the letter “X” in column
“Physical Address”.
An SFR can be specified via its individual mnemonic name. Depending on the selected
addressing mode, an SFR can be accessed via its physical address (using the Data
Page Pointers), or via its short 8-bit address (without using the Data Page Pointers).
Table 7
Name
C167CS-3V Registers, Ordered by Name
Physical
Address
8-Bit Description
Addr.
Reset
Value
ADCIC
b FF98H
CCH
A/D Converter End of Conversion
Interrupt Control Register
0000H
ADCON
b FFA0H
D0H
A/D Converter Control Register
0000H
ADDAT
FEA0H
50H
A/D Converter Result Register
0000H
ADDAT2
F0A0H
E 50H
A/D Converter 2 Result Register
0000H
ADDRSEL1
FE18H
0CH
Address Select Register 1
0000H
ADDRSEL2
FE1AH
0DH
Address Select Register 2
0000H
ADDRSEL3
FE1CH
0EH
Address Select Register 3
0000H
ADDRSEL4
FE1EH
0FH
Address Select Register 4
0000H
b FF9AH
CDH
A/D Converter Overrun Error Interrupt
Control Register
0000H
BUSCON0 b FF0CH
86H
Bus Configuration Register 0
0XX0H
BUSCON1 b FF14H
8AH
Bus Configuration Register 1
0000H
BUSCON2 b FF16H
8BH
Bus Configuration Register 2
0000H
BUSCON3 b FF18H
8CH
Bus Configuration Register 3
0000H
BUSCON4 b FF1AH
8DH
Bus Configuration Register 4
0000H
ADEIC
C1BTR
EF04H
X ---
CAN1 Bit Timing Register
C1CSR
EF00H
X ---
CAN1 Control/Status Register
C1GMS
EF06H
X ---
CAN1 Global Mask Short
UFUUH
C1PCIR
EF02H
X ---
CAN1 Port Control/Interrupt Register
XXXXH
C1LGML
EF0AH X ---
CAN1 Lower Global Mask Long
UUUUH
C1LMLM
EF0EH X ---
CAN1 Lower Mask of Last Message
UUUUH
Data Sheet
38
UUUUH
XX01H
V1.0, 2001-10
C167CS-L16M3V
Low Power
Table 7
C167CS-3V Registers, Ordered by Name (cont’d)
Name
Physical
Address
C1UAR
EFn2H
X ---
CAN1 Upper Arbitration Reg. (msg. n)
UUUUH
C1UGML
EF08H
X ---
CAN1 Upper Global Mask Long
UUUUH
C1UMLM
EF0CH X ---
CAN1 Upper Mask of Last Message
UUUUH
C2BTR
EE04H
X ---
CAN2 Bit Timing Register
UUUUH
C2CSR
EE00H
X ---
CAN2 Control/Status Register
C2GMS
EE06H
X ---
CAN2 Global Mask Short
UFUUH
C2PCIR
EE02H
X ---
CAN2 Port Control/Interrupt Register
XXXXH
C2LGML
EE0AH X ---
CAN2 Lower Global Mask Long
UUUUH
C2LMLM
EE0EH X ---
CAN2 Lower Mask of Last Message
UUUUH
C2UAR
EEn2H
X ---
CAN2 Upper Arbitration Reg. (msg. n)
UUUUH
C2UGML
EE08H
X ---
CAN2 Upper Global Mask Long
UUUUH
C2UMLM
EE0CH X ---
CAN2 Upper Mask of Last Message
UUUUH
CAPREL
FE4AH
25H
GPT2 Capture/Reload Register
0000H
CC0
FE80H
40H
CAPCOM Register 0
0000H
b FF78H
BCH
CAPCOM Reg. 0 Interrupt Ctrl. Reg.
0000H
CC1
FE82H
41H
CAPCOM Register 1
0000H
CC10
FE94H
4AH
CAPCOM Register 10
0000H
b FF8CH
C6H
CAPCOM Reg. 10 Interrupt Ctrl. Reg.
0000H
FE96H
4BH
CAPCOM Register 11
0000H
b FF8EH
C7H
CAPCOM Reg. 11 Interrupt Ctrl. Reg.
0000H
FE98H
4CH
CAPCOM Register 12
0000H
b FF90H
C8H
CAPCOM Reg. 12 Interrupt Ctrl. Reg.
0000H
FE9AH
4DH
CAPCOM Register 13
0000H
b FF92H
C9H
CAPCOM Reg. 13 Interrupt Ctrl. Reg.
0000H
FE9CH
4EH
CAPCOM Register 14
0000H
b FF94H
CAH
CAPCOM Reg. 14 Interrupt Ctrl. Reg.
0000H
FE9EH
4FH
CAPCOM Register 15
0000H
b FF96H
CBH
CAPCOM Reg. 15 Interrupt Ctrl. Reg.
0000H
FE60H
30H
CAPCOM Register 16
0000H
b F160H
E B0H
CAPCOM Reg. 16 Interrupt Ctrl. Reg.
0000H
CC0IC
CC10IC
CC11
CC11IC
CC12
CC12IC
CC13
CC13IC
CC14
CC14IC
CC15
CC15IC
CC16
CC16IC
Data Sheet
8-Bit Description
Addr.
39
Reset
Value
XX01H
V1.0, 2001-10
C167CS-L16M3V
Low Power
Table 7
C167CS-3V Registers, Ordered by Name (cont’d)
Name
Physical
Address
8-Bit Description
Addr.
Reset
Value
CC17
FE62H
31H
CAPCOM Register 17
0000H
b F162H
E B1H
CAPCOM Reg.17 Interrupt Ctrl. Reg.
0000H
FE64H
32H
CAPCOM Register 18
0000H
b F164H
E B2H
CAPCOM Reg. 18 Interrupt Ctrl. Reg.
0000H
FE66H
33H
CAPCOM Register 19
0000H
CC19IC
b F166H
E B3H
CAPCOM Reg. 19 Interrupt Ctrl. Reg.
0000H
CC1IC
b FF7AH
BDH
CAPCOM Reg.1 Interrupt Ctrl. Reg.
0000H
CC2
FE84H
42H
CAPCOM Register 2
0000H
CC20
FE68H
34H
CAPCOM Register 20
0000H
b F168H
E B4H
CAPCOM Reg. 20 Interrupt Ctrl. Reg.
0000H
FE6AH
35H
CAPCOM Register 21
0000H
b F16AH
E B5H
CAPCOM Reg. 21 Interrupt Ctrl. Reg.
0000H
FE6CH
36H
CAPCOM Register 22
0000H
b F16CH
E B6H
CAPCOM Reg. 22 Interrupt Ctrl. Reg.
0000H
FE6EH
37H
CAPCOM Register 23
0000H
b F16EH
E B7H
CAPCOM Reg. 23 Interrupt Ctrl. Reg.
0000H
FE70H
38H
CAPCOM Register 24
0000H
b F170H
E B8H
CAPCOM Reg. 24 Interrupt Ctrl. Reg.
0000H
FE72H
39H
CAPCOM Register 25
0000H
b F172H
E B9H
CAPCOM Reg. 25 Interrupt Ctrl. Reg.
0000H
FE74H
3AH
CAPCOM Register 26
0000H
b F174H
E BAH
CAPCOM Reg. 26 Interrupt Ctrl. Reg.
0000H
FE76H
3BH
CAPCOM Register 27
0000H
b F176H
E BBH
CAPCOM Reg. 27 Interrupt Ctrl. Reg.
0000H
FE78H
3CH
CAPCOM Register 28
0000H
b F178H
E BCH
CAPCOM Reg. 28 Interrupt Ctrl. Reg.
0000H
FE7AH
3DH
CAPCOM Register 29
0000H
CC29IC
b F184H
E C2H
CAPCOM Reg. 29 Interrupt Ctrl. Reg.
0000H
CC2IC
b FF7CH
BEH
CAPCOM Reg. 2 Interrupt Ctrl. Reg.
0000H
FE86H
43H
CAPCOM Register 3
0000H
CC17IC
CC18
CC18IC
CC19
CC20IC
CC21
CC21IC
CC22
CC22IC
CC23
CC23IC
CC24
CC24IC
CC25
CC25IC
CC26
CC26IC
CC27
CC27IC
CC28
CC28IC
CC29
CC3
Data Sheet
40
V1.0, 2001-10
C167CS-L16M3V
Low Power
Table 7
C167CS-3V Registers, Ordered by Name (cont’d)
Name
Physical
Address
8-Bit Description
Addr.
Reset
Value
CC30
FE7CH
3EH
CAPCOM Register 30
0000H
b F18CH
E C6H
CAPCOM Reg. 30 Interrupt Ctrl. Reg.
0000H
FE7EH
3FH
CAPCOM Register 31
0000H
CC31IC
b F194H
E CAH
CAPCOM Reg. 31 Interrupt Ctrl. Reg.
0000H
CC3IC
b FF7EH
BFH
CAPCOM Reg. 3 Interrupt Ctrl. Reg.
0000H
FE88H
44H
CAPCOM Register 4
0000H
b FF80H
C0H
CAPCOM Reg. 4 Interrupt Ctrl. Reg.
0000H
FE8AH
45H
CAPCOM Register 5
0000H
b FF82H
C1H
CAPCOM Reg. 5 Interrupt Ctrl. Reg.
0000H
FE8CH
46H
CAPCOM Register 6
0000H
b FF84H
C2H
CAPCOM Reg. 6 Interrupt Ctrl. Reg.
0000H
FE8EH
47H
CAPCOM Register 7
0000H
b FF86H
C3H
CAPCOM Reg. 7 Interrupt Ctrl. Reg.
0000H
FE90H
48H
CAPCOM Register 8
0000H
b FF88H
C4H
CAPCOM Reg. 8 Interrupt Ctrl. Reg.
0000H
FE92H
49H
CAPCOM Register 9
0000H
CC9IC
b FF8AH
C5H
CAPCOM Reg. 9 Interrupt Ctrl. Reg.
0000H
CCM0
b FF52H
A9H
CAPCOM Mode Control Register 0
0000H
CCM1
b FF54H
AAH
CAPCOM Mode Control Register 1
0000H
CCM2
b FF56H
ABH
CAPCOM Mode Control Register 2
0000H
CCM3
b FF58H
ACH
CAPCOM Mode Control Register 3
0000H
CCM4
b FF22H
91H
CAPCOM Mode Control Register 4
0000H
CCM5
b FF24H
92H
CAPCOM Mode Control Register 5
0000H
CCM6
b FF26H
93H
CAPCOM Mode Control Register 6
0000H
CCM7
b FF28H
94H
CAPCOM Mode Control Register 7
0000H
FE10H
08H
CPU Context Pointer Register
FC00H
b FF6AH
B5H
GPT2 CAPREL Interrupt Ctrl. Reg.
0000H
FE08H
04H
CPU Code Seg. Pointer Reg. (read only)
0000H
DP0L
b F100H
E 80H
P0L Direction Control Register
00H
DP0H
b F102H
E 81H
P0H Direction Control Register
00H
CC30IC
CC31
CC4
CC4IC
CC5
CC5IC
CC6
CC6IC
CC7
CC7IC
CC8
CC8IC
CC9
CP
CRIC
CSP
Data Sheet
41
V1.0, 2001-10
C167CS-L16M3V
Low Power
Table 7
Name
C167CS-3V Registers, Ordered by Name (cont’d)
Physical
Address
8-Bit Description
Addr.
Reset
Value
DP1L
b F104H
E 82H
P1L Direction Control Register
00H
DP1H
b F106H
E 83H
P1H Direction Control Register
00H
DP2
b FFC2H
E1H
Port 2 Direction Control Register
0000H
DP3
b FFC6H
E3H
Port 3 Direction Control Register
0000H
DP4
b FFCAH
E5H
Port 4 Direction Control Register
00H
DP6
b FFCEH
E7H
Port 6 Direction Control Register
00H
DP7
b FFD2H
E9H
Port 7 Direction Control Register
00H
DP8
b FFD6H
EBH
Port 8 Direction Control Register
00H
DPP0
FE00H
00H
CPU Data Page Pointer 0 Reg. (10 bits)
0000H
DPP1
FE02H
01H
CPU Data Page Pointer 1 Reg. (10 bits)
0001H
DPP2
FE04H
02H
CPU Data Page Pointer 2 Reg. (10 bits)
0002H
DPP3
FE06H
03H
CPU Data Page Pointer 3 Reg. (10 bits)
0003H
EXICON
b F1C0H
E E0H
External Interrupt Control Register
0000H
EXISEL
b F1DAH E EDH
External Interrupt Source Select Reg.
0000H
FOCON
b FFAAH
D5H
Frequency Output Control Register
0000H
IDCHIP
F07CH
E 3EH
Identifier
0CXXH
IDMANUF
F07EH
E 3FH
Identifier
1820H
IDMEM
F07AH
E 3DH
Identifier
X040H
IDMEM2
F076H
E 3BH
Identifier
XXXXH
IDPROG
F078H
E 3CH
Identifier
XXXXH
ISNC
b F1DEH E EFH
Interrupt Subnode Control Register
0000H
MDC
b FF0EH
87H
CPU Multiply Divide Control Register
0000H
MDH
FE0CH
06H
CPU Multiply Divide Reg. – High Word
0000H
MDL
FE0EH
07H
CPU Multiply Divide Reg. – Low Word
0000H
ODP2
b F1C2H
E E1H
Port 2 Open Drain Control Register
0000H
ODP3
b F1C6H
E E3H
Port 3 Open Drain Control Register
0000H
ODP4
b F1CAH E E5H
Port 4 Open Drain Control Register
00H
ODP6
b F1CEH E E7H
Port 6 Open Drain Control Register
00H
ODP7
b F1D2H
E E9H
Port 7 Open Drain Control Register
00H
ODP8
b F1D6H
E EBH
Port 8 Open Drain Control Register
00H
Data Sheet
42
V1.0, 2001-10
C167CS-L16M3V
Low Power
Table 7
Name
C167CS-3V Registers, Ordered by Name (cont’d)
Physical
Address
8-Bit Description
Addr.
Reset
Value
ONES
b FF1EH
8FH
Constant Value 1’s Register (read only)
FFFFH
P0H
b FF02H
81H
Port 0 High Reg. (Upper half of PORT0)
00H
P0L
b FF00H
80H
Port 0 Low Reg. (Lower half of PORT0)
00H
FEA4H
52H
Port 1 Digital Input Disable Register
P1H
b FF06H
83H
Port 1 High Reg. (Upper half of PORT1)
00H
P1L
b FF04H
82H
Port 1 Low Reg.(Lower half of PORT1)
00H
P2
b FFC0H
E0H
Port 2 Register
0000H
P3
b FFC4H
E2H
Port 3 Register
0000H
P4
b FFC8H
E4H
Port 4 Register (8 bits)
P5
b FFA2H
D1H
Port 5 Register (read only)
P5DIDIS
b FFA4H
D2H
Port 5 Digital Input Disable Register
P6
b FFCCH
E6H
Port 6 Register (8 bits)
00H
P7
b FFD0H
E8H
Port 7 Register (8 bits)
00H
P8
b FFD4H
EAH
Port 8 Register (8 bits)
00H
PECC0
FEC0H
60H
PEC Channel 0 Control Register
0000H
PECC1
FEC2H
61H
PEC Channel 1 Control Register
0000H
PECC2
FEC4H
62H
PEC Channel 2 Control Register
0000H
PECC3
FEC6H
63H
PEC Channel 3 Control Register
0000H
PECC4
FEC8H
64H
PEC Channel 4 Control Register
0000H
PECC5
FECAH
65H
PEC Channel 5 Control Register
0000H
PECC6
FECCH
66H
PEC Channel 6 Control Register
0000H
PECC7
FECEH
67H
PEC Channel 7 Control Register
0000H
PICON
b F1C4H
E E2H
Port Input Threshold Control Register
0000H
POCON0H
F082H
E 41H
Port P0H Output Control Register
0000H
POCON0L
F080H
E 40H
Port P0L Output Control Register
0000H
POCON1H
F086H
E 43H
Port P1H Output Control Register
0000H
POCON1L
F084H
E 42H
Port P1L Output Control Register
0000H
POCON2
F088H
E 44H
Port P2 Output Control Register
0000H
POCON20
F0AAH E 55H
Dedicated Pin Output Control Register
0000H
POCON3
F08AH
Port P3 Output Control Register
0000H
P1DIDIS
Data Sheet
E 45H
43
0000H
00H
XXXXH
0000H
V1.0, 2001-10
C167CS-L16M3V
Low Power
Table 7
C167CS-3V Registers, Ordered by Name (cont’d)
Name
Physical
Address
POCON4
F08CH
E 46H
Port P4 Output Control Register
0000H
POCON6
F08EH
E 47H
Port P6 Output Control Register
0000H
POCON7
F090H
E 48H
Port P7 Output Control Register
0000H
POCON8
F092H
E 49H
Port P8 Output Control Register
0000H
PP0
F038H
E 1CH
PWM Module Period Register 0
0000H
PP1
F03AH
E 1DH
PWM Module Period Register 1
0000H
PP2
F03CH
E 1EH
PWM Module Period Register 2
0000H
PP3
F03EH
E 1FH
PWM Module Period Register 3
0000H
b FF10H
88H
CPU Program Status Word
0000H
PT0
F030H
E 18H
PWM Module Up/Down Counter 0
0000H
PT1
F032H
E 19H
PWM Module Up/Down Counter 1
0000H
PT2
F034H
E 1AH
PWM Module Up/Down Counter 2
0000H
PT3
F036H
E 1BH
PWM Module Up/Down Counter 3
0000H
PTCR
F0AEH E 57H
Port Temperature Compensation Reg.
0000H
PW0
FE30H
18H
PWM Module Pulse Width Register 0
0000H
PW1
FE32H
19H
PWM Module Pulse Width Register 1
0000H
PW2
FE34H
1AH
PWM Module Pulse Width Register 2
0000H
PW3
FE36H
1BH
PWM Module Pulse Width Register 3
0000H
PWMCON0 b FF30H
98H
PWM Module Control Register 0
0000H
PWMCON1 b FF32H
99H
PWM Module Control Register 1
0000H
PSW
8-Bit Description
Addr.
Reset
Value
PWMIC
b F17EH
E BFH
PWM Module Interrupt Control Register
0000H
RP0H
b F108H
E 84H
System Startup Config. Reg. (Rd. only)
XXH
RSTCON
b F1E0H m ---
Reset Control Register
00XXH
RTCH
F0D6H
E 6BH
RTC High Register
XXXXH
RTCL
F0D4H
E 6AH
RTC Low Register
XXXXH
S0BG
FEB4H
5AH
Serial Channel 0 Baud Rate Generator
Reload Register
0000H
S0CON
b FFB0H
D8H
Serial Channel 0 Control Register
0000H
S0EIC
b FF70H
B8H
Serial Channel 0 Error Interrupt Ctrl. Reg
0000H
Data Sheet
44
V1.0, 2001-10
C167CS-L16M3V
Low Power
Table 7
C167CS-3V Registers, Ordered by Name (cont’d)
Name
Physical
Address
8-Bit Description
Addr.
S0RBUF
FEB2H
59H
Serial Channel 0 Receive Buffer Reg.
(read only)
S0RIC
b FF6EH
B7H
Serial Channel 0 Receive Interrupt
Control Register
0000H
S0TBIC
b F19CH
E CEH
Serial Channel 0 Transmit Buffer
Interrupt Control Register
0000H
FEB0H
58H
Serial Channel 0 Transmit Buffer
Register (write only)
00H
b FF6CH
B6H
Serial Channel 0 Transmit Interrupt
Control Register
0000H
SP
FE12H
09H
CPU System Stack Pointer Register
FC00H
SSCBR
F0B4H
E 5AH
SSC Baudrate Register
0000H
SSCCON
b FFB2H
D9H
SSC Control Register
0000H
SSCEIC
b FF76H
BBH
SSC Error Interrupt Control Register
0000H
SSCRB
F0B2H
E 59H
SSCRIC
b FF74H
BAH
SSCTB
F0B0H
E 58H
SSCTIC
b FF72H
STKOV
STKUN
S0TBUF
S0TIC
SYSCON
Reset
Value
XXH
SSC Receive Buffer
XXXXH
SSC Receive Interrupt Control Register
0000H
SSC Transmit Buffer
0000H
B9H
SSC Transmit Interrupt Control Register
0000H
FE14H
0AH
CPU Stack Overflow Pointer Register
FA00H
FE16H
0BH
CPU Stack Underflow Pointer Register
b FF12H
89H
FC00H
1)
CPU System Configuration Register
0XX0H
SYSCON1 b F1DCH E EEH
CPU System Configuration Register 1
0000H
SYSCON2 b F1D0H
E E8H
CPU System Configuration Register 2
0000H
SYSCON3 b F1D4H
E EAH
CPU System Configuration Register 3
0000H
T0
FE50H
28H
CAPCOM Timer 0 Register
0000H
T01CON
b FF50H
A8H
CAPCOM Timer 0 and Timer 1 Ctrl. Reg.
0000H
T0IC
b FF9CH
CEH
CAPCOM Timer 0 Interrupt Ctrl. Reg.
0000H
T0REL
FE54H
2AH
CAPCOM Timer 0 Reload Register
0000H
T1
FE52H
29H
CAPCOM Timer 1 Register
0000H
b FF9EH
CFH
CAPCOM Timer 1 Interrupt Ctrl. Reg.
0000H
FE56H
2BH
CAPCOM Timer 1 Reload Register
0000H
T1IC
T1REL
Data Sheet
45
V1.0, 2001-10
C167CS-L16M3V
Low Power
Table 7
C167CS-3V Registers, Ordered by Name (cont’d)
Name
Physical
Address
T14
F0D2H
E 69H
RTC Timer 14 Register
XXXXH
T14REL
F0D0H
E 68H
RTC Timer 14 Reload Register
XXXXH
T2
FE40H
20H
GPT1 Timer 2 Register
0000H
T2CON
b FF40H
A0H
GPT1 Timer 2 Control Register
0000H
T2IC
b FF60H
B0H
GPT1 Timer 2 Interrupt Control Register
0000H
FE42H
21H
GPT1 Timer 3 Register
0000H
T3CON
b FF42H
A1H
GPT1 Timer 3 Control Register
0000H
T3IC
b FF62H
B1H
GPT1 Timer 3 Interrupt Control Register
0000H
FE44H
22H
GPT1 Timer 4 Register
0000H
T4CON
b FF44H
A2H
GPT1 Timer 4 Control Register
0000H
T4IC
b FF64H
B2H
GPT1 Timer 4 Interrupt Control Register
0000H
FE46H
23H
GPT2 Timer 5 Register
0000H
T5CON
b FF46H
A3H
GPT2 Timer 5 Control Register
0000H
T5IC
b FF66H
B3H
GPT2 Timer 5 Interrupt Control Register
0000H
FE48H
24H
GPT2 Timer 6 Register
0000H
T6CON
b FF48H
A4H
GPT2 Timer 6 Control Register
0000H
T6IC
b FF68H
B4H
GPT2 Timer 6 Interrupt Control Register
0000H
F050H
E 28H
CAPCOM Timer 7 Register
0000H
T78CON
b FF20H
90H
CAPCOM Timer 7 and 8 Control Reg.
0000H
T7IC
b F17AH
E BEH
CAPCOM Timer 7 Interrupt Ctrl. Reg.
0000H
T7REL
F054H
E 2AH
CAPCOM Timer 7 Reload Register
0000H
T8
F052H
E 29H
CAPCOM Timer 8 Register
0000H
b F17CH
E BFH
CAPCOM Timer 8 Interrupt Ctrl. Reg.
0000H
F056H
E 2BH
CAPCOM Timer 8 Reload Register
0000H
0000H
T3
T4
T5
T6
T7
T8IC
T8REL
TFR
WDT
8-Bit Description
Addr.
b FFACH
D6H
Trap Flag Register
FEAEH
57H
Watchdog Timer Register (read only)
Reset
Value
0000H
2)
WDTCON
b FFAEH
D7H
XP0IC
b F186H
E C3H
CAN1 Module Interrupt Control Register
0000H
XP1IC
b F18EH
E C7H
CAN2 Module Interrupt Control Register
0000H
XP2IC
b F196H
E CBH
Unassigned Interrupt Control Register
0000H
Data Sheet
Watchdog Timer Control Register
46
00XXH
V1.0, 2001-10
C167CS-L16M3V
Low Power
Table 7
Name
XP3IC
XPERCON
ZEROS
C167CS-3V Registers, Ordered by Name (cont’d)
Physical
Address
8-Bit Description
Addr.
b F19EH
E CFH
RTC/PLL Interrupt Control Register
0000H
F024H
E 12H
X-Peripheral Control Register
0401H
b FF1CH
8EH
Constant Value 0’s Register (read only)
0000H
1)
The system configuration is selected during reset.
2)
The reset value depends on the indicated reset source.
Data Sheet
Reset
Value
47
V1.0, 2001-10
C167CS-L16M3V
Low Power
Absolute Maximum Ratings
Table 8
Absolute Maximum Rating Parameters
Parameter
Symbol
Limit Values
min.
Unit
Notes
max.
TST
TJ
VDD
-65
150
°C
–
-40
150
°C
under bias
-0.5
6.5
V
–
Voltage on any pin with
respect to ground (VSS)
VIN
-0.5
VDD + 0.5 V
–
Input current on any pin
during overload condition
–
-10
10
mA
–
Absolute sum of all input
currents during overload
condition
–
–
|100|
mA
–
Power dissipation
PDISS
–
1.5
W
–
Storage temperature
Junction temperature
Voltage on VDD pins with
respect to ground (VSS)
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS) the
voltage on VDD pins with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
Data Sheet
48
V1.0, 2001-10
C167CS-L16M3V
Low Power
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation of the C167CS-3V. All parameters specified in the following sections refer to
these operating conditions, unless otherwise noticed.
Table 9
Operating Condition Parameters
Parameter
Symbol
Limit Values
min.
Digital supply voltage
VDD
VSS
Overload current
IOV
Absolute sum of overload Σ|IOV|
Unit Notes
max.
3.15
3.6
V
Active mode,
fCPUmax = 16 MHz
2.51)
3.6
V
PowerDown mode
V
Reference voltage
Digital ground voltage
0
–
±5
mA
Per pin2)3)
–
50
mA
3)
currents
External Load
Capacitance
CL
–
50
pF
Pin drivers in
fast edge mode4)
Ambient temperature
TA
0
70
°C
SAB-C167CS-3V
…
-40
85
°C
SAF-C167CS-3V
…
-40
125
°C
SAK-C167CS-3V
…
1)
Output voltages and output currents will be reduced when VDD leaves the range defined for active mode.
2)
Overload conditions occur if the standard operatings conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range (i.e. VOV > VDD+0.5 V or VOV < VSS-0.5 V). The absolute sum of input overload
currents on all pins may not exceed 50 mA. The supply voltage must remain within the specified limits.
Proper operation is not guaranteed if overload conditions occur on functional pins line XTAL1, RD, WR, etc.
3)
Not 100% tested, guaranteed by design and characterization.
4)
The timing is valid for pin drivers in high current or dynamic current mode. The reduced static output current in
dynamic current mode must be respected when designing the system.
Data Sheet
49
V1.0, 2001-10
C167CS-L16M3V
Low Power
Parameter Interpretation
The parameters listed in the following partly represent the characteristics of the C167CS3V and partly its demands on the system. To aid in interpreting the parameters right,
when evaluating them for a design, they are marked in column “Symbol”:
CC (Controller Characteristics):
The logic of the C167CS-3V will provide signals with the respective characteristics.
SR (System Requirement):
The external system must provide signals with the respective characteristics to the
C167CS-3V.
DC Characteristics
(Operating Conditions apply)1)
Parameter
Symbol
Limit Values
min.
Input low voltage (TTL,
all except XTAL1)
VIL
Input low voltage XTAL1
max.
V
–
VIL2 SR -0.5
VILS SR -0.5
0.3 VDD V
–
1.3
V
–
Input high voltage (TTL,
all except RSTIN and XTAL1)
VIH
VDD +
V
–
Input high voltage RSTIN
(when operated as input)
VIH1 SR 0.6 VDD VDD +
V
–
Input high voltage XTAL1
VIH2 SR 0.7 VDD VDD +
V
–
V
–
Input low voltage
(Special Threshold)
SR -0.5
Unit Test Condition
SR 1.8
0.8
0.5
0.5
0.5
Input high voltage
(Special Threshold)
VIHS SR 0.8 VDD VDD +
Input Hysteresis
(Special Threshold)
HYS
Output low voltage2)
VOL CC –
VOH CC VDD -
- 0.2
0.5
150
–
mV
Series
resistance = 0 Ω
0.45
V
–
V
IOL ≤ IOLnom3)
IOH ≥ IOHnom3)
IOZ1 CC –
Input leakage current (all other) IOZ2 CC –
±200
nA
0 V < VIN < VDD
±500
nA
0.45 V < VIN
< VDD
RSTIN inactive current5)
-5
µA
VIN = VIH1
Output high voltage4)
0.45
Input leakage current (Port 5)
Data Sheet
IRSTH6)
–
50
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C167CS-L16M3V
Low Power
DC Characteristics (cont’d)
(Operating Conditions apply)1)
Parameter
Symbol
RSTIN active current5)
READY/RD/WR inact. current8)
READY/RD/WR active current8)
8)
ALE inactive current
ALE active current
8)
8)
Port 6 inactive current
Port 6 active current8)
PORT0 configuration current9)
XTAL1 input current
10)
Pin capacitance
(digital inputs/outputs)
Limit Values
IRSTL7)
IRWH6)
IRWL7)
IALEL6)
IALEH7)
IP6H6)
IP6L7)
IP0H6)
IP0L7)
IIL
CC
CIO CC
Unit Test Condition
min.
max.
-100
–
µA
–
-10
µA
-500
–
µA
–
20
µA
500
–
µA
–
-10
µA
-500
–
µA
–
-5
µA
-100
–
µA
–
±20
µA
–
10
pF
VIN = VIL
VOUT = 2.4 V
VOUT = VOLmax
VOUT = VOLmax
VOUT = 2.4 V
VOUT = 2.4 V
VOUT = VOLmax
VIN = VIHmin
VIN = VILmax
0 V < VIN < VDD
f = 1 MHz
TA = 25 °C
1)
Keeping signal levels within the levels specified in this table, ensures operation without overload conditions.
For signal levels outside these specifications also refer to the specification of the overload current IOV.
2)
For pin RSTIN this specification is only valid in bidirectional reset mode.
3)
As a rule, with decreasing output current the output levels approach the respective supply level (VOL→VSS,
VOH→VDD). However, only the levels for nominal output currents are guaranteed.
4)
This specification is not valid for outputs which are switched to open drain mode. In this case the respective
output will float and the voltage results from the external circuitry.
5)
These parameters describe the RSTIN pullup, which equals a resistance of ca. 50 to 250 kΩ.
6)
The maximum current may be drawn while the respective signal line remains inactive.
7)
The minimum current must be drawn in order to drive the respective signal line active.
8)
This specification is valid during Reset and during Hold-mode or Adapt-mode. During Hold-mode Port 6 pins
are only affected, if they are used (configured) for CS output and the open drain function is not enabled. The
READY-pullup is always active, except for Powerdown mode.
9)
This specification is valid during Reset and during Adapt-mode.
10)
Not 100% tested, guaranteed by design and characterization.
Data Sheet
51
V1.0, 2001-10
C167CS-L16M3V
Low Power
Table 10
Current Limits for Port Output Drivers
Port Output Driver
Maximum Output Current
(IOLmax, -IOHmax)1)
Nominal Output Current
(IOLnom, -IOHnom)
(PORT0, PORT1,
Port 2, Port 4, ALE,
RD, WR, BHE,
CLKOUT, RSTOUT,
RSTIN2))
-----
1.6 mA
All other outputs
-----
0.5 mA
1)
An output current above |IOXnom| is not specified for the C167CS-3V.
2)
Valid for VOL in bidirectional reset mode only.
Power Consumption C167CS-3V
(Operating Conditions apply)
Parameter
Symbol
Limit Values
min.
max.
Unit Test Condition
Power supply current (active)
with all peripherals active
IDD3
–
10 +
mA
2.0 × fCPU
RSTIN = VIL
fCPU in [MHz]1)
Idle mode supply current
with all peripherals active
IIDX32)
–
5+
mA
1.1 × fCPU
Idle mode supply current
with all peripherals deactivated,
PLL off, SDD factor = 32
IIDO3)2)
–
500 +
50 × fOSC
µA
RSTIN = VIH1
fCPU in [MHz]1)
RSTIN = VIH1
fOSC in [MHz]1)
Sleep and Power-down mode
IPDR3)2)
supply current with RTC running
–
500 +
30 × fOSC
µA
Sleep and Power-down mode
IPDO
supply current with RTC disabled
–
30
µA
VDD = VDDmax
fOSC in [MHz]4)
VDD = VDDmax4)
1)
The supply current is a function of the operating frequency. This dependency is illustrated in Figure 10.
These parameters are tested at VDDmax and maximum CPU clock with all outputs disconnected and all inputs
at VIL or VIH.
2)
These values are not 100% tested but verified by means of system characterization.
3)
This parameter is determined mainly by the current consumed by the oscillator (see Figure 9). This current,
however, is influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a typical
circuitry and may change in case of a not optimized external oscillator circuitry (see also application notes
AP2420: Crystal Oscillator, AP2424: Ceramic Resonator Oscillator).
4)
This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to
0.1 V or at VDD - 0.1 V to VDD, VREF = 0 V, all outputs (including pins configured as outputs) disconnected.
Data Sheet
52
V1.0, 2001-10
C167CS-L16M3V
Low Power
I [µA]
3000
IIDOmax
IIDOtyp
2000
IPDRmax
1000
IPDOmax
10
Figure 9
Data Sheet
20
30
40
fOSC [MHz]
Idle and Power Down Supply Current as a Function of Oscillator
Frequency
53
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C167CS-L16M3V
Low Power
I [mA]
140
120
100
IDD3max
80
IDD3typ
60
IIDX3max
IIDX3typ
40
20
10
Figure 10
Data Sheet
20
30
40
fCPU [MHz]
Supply/Idle Current as a Function of Operating Frequency
54
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C167CS-L16M3V
Low Power
AC Characteristics
Definition of Internal Timing
The internal operation of the C167CS-3V is controlled by the internal CPU clock fCPU.
Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus
cycles) operations.
The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called “TCL” (see Figure 11).
Phase Locked Loop Operation
fOSC
TCL
fCPU
TCL
Direct Clock Drive
fOSC
TCL
fCPU
TCL
Prescaler Operation
fOSC
TCL
fCPU
TCL
Figure 11
MCT04338
Generation Mechanisms for the CPU Clock
The CPU clock signal fCPU can be generated from the oscillator clock signal fOSC via
different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate fCPU. This influence must
be regarded when calculating the timings for the C167CS-3V.
Note: The example for PLL operation shown in Figure 11 refers to a PLL factor of 4.
The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG
in register RP0H.7-5.
Upon a long hardware reset register RP0H is loaded with the logic levels present on the
upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins
Data Sheet
55
V1.0, 2001-10
C167CS-L16M3V
Low Power
P0.15-13 (P0H.7-5). Register RP0H can be loaded from the upper half of register
RSTCON under software control.
Table 11 associates the combinations of these three bits with the respective clock
generation mode.
Table 11
C167CS-3V Clock Generation Modes
CLKCFG
CPU Frequency
(RP0H.7-5) fCPU = fOSC × F
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
fOSC × 4
fOSC × 3
fOSC × 2
fOSC × 5
fOSC × 1
fOSC × 1.5
fOSC / 2
fOSC × 2.5
External Clock
Input Range1)
Notes
2.5 to 4 MHz
Default configuration
3.33 to 5.33 MHz
–
5 to 8 MHz
–
2 to 3.2 MHz
–
1 to 16 MHz
Direct drive2)
6.66 to 10.66 MHz
–
2 to 32 MHz
CPU clock via prescaler
4 to 6.4 MHz
–
1)
The external clock input range refers to a CPU clock range of 10 … 16 MHz.
2)
The maximum frequency depends on the duty cycle of the external clock signal.
Prescaler Operation
When prescaler operation is configured (CLKCFG=001B) the CPU clock is derived from
the internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of fCPU is half the frequency of fOSC and the high and low time of fCPU (i.e.
the duration of an individual TCL) is defined by the period of the input clock fOSC.
The timings listed in the AC Characteristics that refer to TCLs therefore can be
calculated using the period of fOSC for any TCL.
Phase Locked Loop
When PLL operation is configured (via CLKCFG) the on-chip phase locked loop is
enabled and provides the CPU clock (see table above). The PLL multiplies the input
frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e.
fCPU = fOSC × F). With every F’th transition of fOSC the PLL circuit synchronizes the CPU
clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock
frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so
it is locked to fOSC. The slight variation causes a jitter of fCPU which also effects the
duration of individual TCLs.
Data Sheet
56
V1.0, 2001-10
C167CS-L16M3V
Low Power
The timings listed in the AC Characteristics that refer to TCLs therefore must be
calculated using the minimum TCL that is possible under the respective circumstances.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCL is lower than
for one single TCL (see formula and Figure 12).
For a period of N × TCL the minimum value is computed using the corresponding
deviation DN:
(N × TCL)min = N × TCLNOM - DN; DN [ns] = ±(13.3 + N × 6.3) / fCPU [MHz],
where N = number of consecutive TCLs and 1 ≤ N ≤ 40.
So for a period of 3 TCLs @ 25 MHz (i.e. N = 3): D3 = (13.3 + 3 × 6.3) / 25 = 1.288 ns,
and (3TCL)min = 3TCLNOM - 1.288 ns = 58.7 ns (@ fCPU = 25 MHz).
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is neglectible.
Note: For all periods longer than 40 TCL the N=40 value can be used (see Figure 12).
±30
Max. jitter DN
10 MHz
±26.5
ns
This approximated formula is valid for
1 N 40 and 10 MHz fCPU 40 MHz.
±20
16 MHz
20 MHz
25 MHz
±10
33 MHz
40 MHz
±1
1
5
10
20
40
N
MCD04413B
Figure 12
Data Sheet
Approximated Maximum Accumulated PLL Jitter
57
V1.0, 2001-10
C167CS-L16M3V
Low Power
Direct Drive
When direct drive is configured (CLKCFG = 011B) the on-chip phase locked loop is
disabled and the CPU clock is directly driven from the internal oscillator with the input
clock signal.
The frequency of fCPU directly follows the frequency of fOSC so the high and low time of
fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock
fOSC.
The timings listed below that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective circumstances. This minimum value
can be calculated via the following formula:
TCLmin = 1/fOSC × DCmin
(DC = duty cycle)
For two consecutive TCLs the deviation caused by the duty cycle of fOSC is compensated
so the duration of 2TCL is always 1/fOSC. The minimum value TCLmin therefore has to
be used only once for timings that require an odd number of TCLs (1, 3, …). Timings that
require an even number of TCLs (2, 4, …) may use the formula 2TCL = 1/fOSC.
Data Sheet
58
V1.0, 2001-10
C167CS-L16M3V
Low Power
AC Characteristics
External Clock Drive XTAL1
(Operating Conditions apply)
Table 12
External Clock Drive Characteristics
Parameter
Symbol
Direct Drive
1:1
min.
Oscillator period
High time2)
Low time2)
Rise time2)
2)
Fall time
tOSC
t1
t2
t3
t4
Prescaler
2:1
PLL
1:N
Unit
max.
min.
max.
min.
max.
SR 62
–
31
–
941)
5001)
ns
SR 313)
–
8
–
10
–
ns
SR 313)
–
8
–
10
–
ns
SR –
8
–
6
–
10
ns
SR –
8
–
6
–
10
ns
1)
The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock generation
mode. Please see respective table above.
2)
The clock input signal must reach the defined levels VIL2 and VIH2.
3)
The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (fCPU) in
direct drive mode depends on the duty cycle of the clock input signal.
t1
t3
t4
VIH2
0.5 VDD
VIL
t2
t OSC
MCT02534
Figure 13
External Clock Drive XTAL1
Note: If the on-chip oscillator is used together with a crystal, the oscillator frequency is
limited to a range of 4 MHz to 25 MHz.
It is strongly recommended to measure the oscillation allowance (or margin) in the
final target system (layout) to determine the optimum parameters for the oscillator
operation. Please refer to the limits specified by the crystal supplier.
When driven by an external clock signal it will accept the specified frequency
range. Operation at lower input frequencies is possible but is guaranteed by
design only (not 100% tested).
Data Sheet
59
V1.0, 2001-10
C167CS-L16M3V
Low Power
A/D Converter Characteristics
(Operating Conditions apply)
Table 13
A/D Converter Characteristics
Parameter
Symbol
Limit Values
min.
VAREF SR
Analog reference ground
VAGND SR
Analog input voltage range VAIN SR
Basic clock frequency
fBC
Conversion time
tC
CC
Total unadjusted error
TUE
CC
CC
Internal resistance of
reference voltage source
RAREF SR
Internal resistance of
analog source
RASRC SR
ADC input capacitance
CAIN CC
VDD + 0.1
VSS - 0.1 VSS + 0.2
VAGND
VAREF
V
1)
V
–
V
2)
0.5
6.25
MHz
3)
–
40 tBC + tS –
+ 2tCPU
2.6
Analog reference supply
Calibration time after reset tCAL
max.
1)
Unit Test
Condition
4)
tCPU = 1/fCPU
–
3328 tBC
–
–
±4
LSB Channels
0 … 15
–
±10
LSB Channels
16 … 23
–
tBC/60
kΩ
tBC in [ns]5)6)
kΩ
tS in [ns]6)7)
pF
6)
- 0.25
–
tS/450
- 0.25
–
33
1)
TUE is tested at VAREF = 3.3 V, VAGND = 0 V, VDD = 3.2 V. It is guaranteed by design for all other voltages
within the defined voltage range.
If the analog reference supply voltage exceeds the power supply voltage by up to 0.2 V
(i.e. VAREF = VDD = +0.2 V) the maximum TUE is increased to ±5/11 LSB. This range is not 100% tested.
The specified TUE is guaranteed only if the absolute sum of input overload currents on Port 5 pins and P1H
pins (see IOV specification) does not exceed 10 mA.
During the reset calibration sequence the maximum TUE may be ±8 LSB (±12 LSB for channels 16 … 23).
2)
VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in
these cases will be X000H or X3FFH, respectively.
3)
The limit values for fBC must not be exceeded when selecting the CPU frequency and the ADCTC setting.
4)
This parameter includes the sample time tS, the time for determining the digital result and the time to load the
result register with the conversion result.
Values for the basic clock tBC depend on programming and can be taken from Table 14.
This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum.
5)
During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
resistance of the reference voltage source must allow the capacitance to reach its respective voltage level
within each conversion step. The maximum internal resistance results from the programmed conversion
timing.
Data Sheet
60
V1.0, 2001-10
C167CS-L16M3V
Low Power
6)
Not 100% tested, guaranteed by design and characterization.
7)
During the sample time the input capacitance CAIN can be charged/discharged by the external source. The
internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS.
After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result.
Values for the sample time tS depend on programming and can be taken from Table 14.
Sample time and conversion time of the C167CS-3V’s A/D Converter are programmable.
Table 14 should be used to calculate the above timings.
The limit values for fBC must not be exceeded when selecting ADCTC.
Table 14
A/D Converter Computation Table
ADCON.15|14
(ADCTC)
A/D Converter
Basic Clock fBC
ADCON.13|12 Sample time
(ADSTC)
tS
00
fCPU / 4
fCPU / 2
fCPU / 16
fCPU / 8
00
01
10
11
01
10
11
tBC × 8
tBC × 16
tBC × 32
tBC × 64
Converter Timing Example:
Assumptions:
Basic clock
Sample time
Conversion time
Data Sheet
fCPU
fBC
tS
tC
= 12.5 MHz (i.e. tCPU = 80 ns), ADCTC = ‘01’, ADSTC = ‘00’.
= fCPU / 2 = 6.25 MHz, i.e. tBC = 160 ns.
= tBC × 8 = 1280 ns.
= tS + 40 tBC + 2 tCPU = (1280 + 6400 + 160) ns = 7.8 µs.
61
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Testing Waveforms
2.4 V
1.8 V
1.8 V
Test Points
0.8 V
0.45 V
0.8 V
AC inputs during testing are driven at 2.4 V for a logic ’1’ and 0.45 V for a logic ’0’.
Timing measurements are made at VIH min for a logic ’1’ and VIL max for a logic ’0’.
MCA04414
Figure 14
Input Output Waveforms
VLoad + 0.1 V
VOH - 0.1 V
Timing
Reference
Points
VLoad - 0.1 V
VOL + 0.1 V
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs,
but begins to float when a 100 mV change from the loaded VOH / VOL level occurs (I OH / I OL = 20 mA).
MCA00763
Figure 15
Data Sheet
Float Waveforms
62
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C167CS-L16M3V
Low Power
AC Characteristics
Table 15
CLKOUT Reference Signal
Parameter
Symbol
Limits
min.
tc5
tc6
tc7
tc8
tc9
CLKOUT cycle time
CLKOUT high time
CLKOUT low time
CLKOUT rise time
CLKOUT fall time
1)
Unit
max.
62.51)
CC
ns
CC 8
–
ns
CC 6
–
ns
CC –
6
ns
CC –
6
ns
The CLKOUT cycle time is influenced by the PLL jitter (given value applies to fCPU = 16 MHz).
For a single CLKOUT cycle (2 TCL) the deviation caused by the PLL jitter is below 1.6 ns (for fCPU = 16 MHz).
For longer periods the relative deviation decreases (see PLL deviation formula).
tc7
tc5
tc6
tc9
tc8
CLKOUT
MCT04415
Figure 16
CLKOUT Signal Timing
Variable Memory Cycles
The bus timing shown below is programmable via the BUSCONx registers. The duration
of ALE and two types of waitstates can be selected. This table summarizes the possible
bus cycle durations.
Table 16
Variable Memory Cycles
Bus Cycle Type
Bus Cycle Duration
Demultiplexed bus cycle 4 + 2 × (15 - <MCTC>)
with normal ALE
+ 2 × (1 - <MTTC>)
Unit 16 MHz, 0 Waitstates
TCL 125 ns
Demultiplexed bus cycle 6 + 2 × (15 – <MCTC>) TCL 187.5 ns
with extended ALE
+ 2 × (1 - <MTTC>)
Multiplexed bus cycle
with normal ALE
6 + 2 × (15 - <MCTC>)
+ 2 × (1 - <MTTC>)
TCL 187.5 ns
Multiplexed bus cycle
with extended ALE
8 + 2 × (15 - <MCTC>)
+ 2 × (1 - <MTTC>)
TCL 250 ns
Data Sheet
63
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C167CS-L16M3V
Low Power
Table 17
External Bus Cycle Timing (Operating Conditions apply)
Parameter
Symbol
Limits
min.
Output delay from CLKOUT falling edge
tc10 CC 3
Valid for: address (MUX on PORT0), write data out
Unit
max.
26
ns
Output delay from CLKOUT edge
Valid for: latched CS, ALE (normal)
tc11 CC -3
14
ns
Output delay from CLKOUT edge
Valid for: WR, WRL, WRH, WrCS
tc12 CC -3
13
ns
Output delay from CLKOUT edge
Valid for: RD, RdCS
tc13 CC -2
9
ns
Input setup time to CLKOUT falling edge
Valid for: read data in
tc14 SR 14
–
ns
Input hold time after CLKOUT falling edge
Valid for: read data in1)
tc15 SR 0
–
ns
Output delay from CLKOUT falling edge
Valid for: address (on PORT1 and/or P4), BHE
tc16 CC 2
23
ns
Output hold time after CLKOUT falling edge
Valid for: address, BHE2)
tc17 CC -2
17
ns
Output hold time after CLKOUT edge3)
Valid for: write data out
tc18 CC -1
–
ns
Output delay from CLKOUT falling edge
Valid for: ALE (extended), early CS
tc19 CC -2
14
ns
Turn off delay after CLKOUT edge3)
Valid for: write data out
tc20 CC –
7
ns
Turn on delay after CLKOUT falling edge3)
Valid for: write data out
tc21 CC -5
–
ns
Output hold time after CLKOUT edge
Valid for: early CS
tc22 CC -3
6
ns
1)
Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge
of RD. Therefore address changes before the end of RD have no impact on (demultiplexed) read cycles.
2)
Due to comparable propagation delays the address does not change before WR goes high. The minimum
output delay (tc17min) is therefore the actual value of tc12.
3)
Not 100% tested, guaranteed by design and characterization.
The bandwidth of a parameter (minimum and maximum value) covers the whole
operating range (temperature, voltage) as well as process variations. Within a given
device, however, this bandwidth is smaller than the specified range. This is also due to
Data Sheet
64
V1.0, 2001-10
C167CS-L16M3V
Low Power
interdependencies between certain parameters. Some of these interdependencies are
described as relative timing (see below) or in additional notes (see standard timing).
Table 18
External Bus Relative Timing (Operating Conditions apply) 1)
Parameter
Symbol
Limits
min.
Unit
max.
Output hold time after WR rising edge 2)
Valid for: address, write data out
t50
CC 0
–
ns
Input hold time after RD rising edge
Valid for: read data in
t51
SR –
0
ns
1)
Not 100% tested, guaranteed by design and characterization.
2)
See also note 2) in Table 17.
General Notes For The Following Bus Timing Figures
These standard notes apply to all subsequent timing figures. Additional individual notes
are placed at the respective figure.
1)
2)
3)
4)
The falling edge of signals RD and WR/WRH/WRL/WrCS is controlled by the Read/Write delay feature (bit
BUSCON.RWDCx).
The rising edge of signal WR/WRH/WRL/WrCS is controlled by the early write feature (bit BUSCON.EWENx).
A bus cycle is extended here, if MCTC waitstates are selected or if the READY input is sampled inactive.
A bus cycle is extended here, if an MTTC waitstate is selected.
Data Sheet
65
V1.0, 2001-10
C167CS-L16M3V
Low Power
CLKOUT
Normal ALE Cycle
tc 11
tc 11
Normal ALE
Extended ALE Cycle
tc 19
tc 19
Extended ALE
tc 19
tc 19
tc 11
tc 11
CSxE, CSxL
tc16
tc16
tc17
A23-A0,
BHE
Valid
tc12
tc 12
tc12
WRL, WRH,
WR, WrCS
tc12
1)
2)
tc10
tc20
tc21
D15-D0
Data OUT
3)
MCTC
Note: Write data is deactivated 1 TCL earlier
if early write is enabled (same timing).
Figure 17
Data Sheet
tc18
4)
MTTC
MCT04435
Demultiplexed Bus, Write Access
66
V1.0, 2001-10
C167CS-L16M3V
Low Power
CLKOUT
Normal ALE Cycle
tc 11
tc 11
Normal ALE
Extended ALE Cycle
tc 19
tc 19
Extended ALE
tc 19
tc 19
tc 11
tc 11
CSxE, CSxL
tc16
tc16
tc17
A23-A0,
BHE
Valid
tc13
tc13
RD,
RdCS
tc13
1)
tc15
tc14
D15-D0
Data IN
3)
MCTC
4)
MTTC
MCT04436
Figure 18
Data Sheet
Demultiplexed Bus, Read Access
67
V1.0, 2001-10
C167CS-L16M3V
Low Power
CLKOUT
Normal ALE Cycle
tc 11
tc 11
Normal ALE
Extended ALE Cycle
tc 19
tc 19
Extended ALE
tc 19
tc 19
tc 11
tc 11
CSxE, CSxL
tc16
tc16
tc17
A23-A16,
BHE
Valid
tc12
tc 12
tc12
WRL, WRH,
WR, WrCS
1)
tc 10
AD15-AD0
(Normal ALE)
2)
tc 10
tc 21
tc 20
tc 17
tc 18
Low Address
tc 10
Data OUT
tc 10
tc 20
tc 17
tc 21
AD15-AD0
(Extended ALE)
tc12
Low Address
tc 18
Data OUT
3)
MCTC
Note: Write data is deactivated 2 TCL earlier if early write is enabled (same timing).
Figure 19
Data Sheet
4)
MTTC
MCT04437
Multiplexed Bus, Write Access
68
V1.0, 2001-10
C167CS-L16M3V
Low Power
CLKOUT
Normal ALE Cycle
tc 11
tc 11
Normal ALE
Extended ALE Cycle
tc 19
tc 19
Extended ALE
tc 19
tc 19
tc 11
tc 11
CSxE, CSxL
tc16
tc16
tc17
A23-A16,
BHE
Valid
tc13
tc13
RD,
RdCS
tc13
1)
tc10
tc20
tc21
AD15-AD0
(Normal ALE)
tc17
tc14
Low Address
tc10
Data IN
tc20
tc21
AD15-AD0
(Extended ALE)
tc15
tc15
tc17
tc14
Low Address
Data IN
3)
MCTC
4)
MTTC
MCT04438
Figure 20
Data Sheet
Multiplexed Bus, Read Access
69
V1.0, 2001-10
C167CS-L16M3V
Low Power
Bus Cycle Control via READY Input
The duration of an external bus cycle can be controlled by the external circuitry via the
READY input signal.
Synchronous READY permits the shortest possible bus cycle but requires the input
signal to be synchronous to the reference signal CLKOUT.
Asynchronous READY puts no timing constraints on the input signal but incurs one
waitstate minimum due to the additional synchronization stage.
Table 19
READY Timing (Operating Conditions apply)
Parameter
Symbol
Limits
min
Unit
max
Input setup time to CLKOUT rising edge
Valid for: READY input
tc25 CC
16
–
ns
Input hold time after CLKOUT rising edge
Valid for: READY input
tc26 CC
0
–
ns
Asynchronous READY input low time3)
tc27 CC
tc5 + tc25 –
ns
Notes (Valid for Table 19 and Figure 21)
1)
Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).
2) Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may
be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a
demultiplexed bus without MTTC waitstate this delay is zero.
3)
These timings are given for test purposes only, in order to assure recognition at a specific clock edge.
If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT,
it must fulfill tc27 in order to be safely synchronized.
Proper deactivation of READY is guaranteed if READY is deactivated in response to the trailing (rising) edge
of the corresponding command (RD or WR).
4)
READY sampled HIGH at this sampling point generates a READY controlled waitstate,
READY sampled LOW at this sampling point terminates the currently running bus cycle.
5)
If the next following bus cycle is READY controlled, an active READY signal must be disabled before the first
valid sample point for the next bus cycle. This sample point depends on the MTTC waitstate of the current
cycle, and on the MCTC waitstates and the ALE mode of the next following cycle. If the current cycle uses a
multiplexed bus the intrinsic MUX waitstate adds another CLKOUT cycle to the READY deactivation time.
Data Sheet
70
V1.0, 2001-10
C167CS-L16M3V
Low Power
Running Cycle 1)
READY WS
MUX/MTTC
2)
CLKOUT
tc 15
tc 14
D15-D0
Data IN
tc 10
The next external bus cycle may start here.
tc 20
tc 18
tc 21
D15-D0
Data OUT
tc 13
tc 12
tc 13 / tc 19
Command
(RD, WR)
3)
tc 26
tc 25
Synchronous
READY
tc 25
Asynchronous
READY 3)
Figure 21
Data Sheet
tc 25
4)
tc 26
4)
tc 26
4)
tc 27
tc 26
tc 25
4)
5)
MCT04820
READY Timing
71
V1.0, 2001-10
C167CS-L16M3V
Low Power
External Bus Arbitration
Table 20
Bus Arbitration Timing (Operating Conditions apply)
Parameter
Symbol
HOLD input setup time to CLKOUT falling edge
CLKOUT to BREQ delay
CLKOUT to HLDA delay
CSx release
1)
CSx drive
1)
Other signals release
Other signals drive1)
1)
tc28
tc29
tc30
tc31
tc32
tc33
tc34
Limits
Unit
min.
max.
SR
18
–
ns
CC
-2
9
ns
CC
-2
7
ns
CC
0
10
ns
CC
-4
4
ns
CC
0
10
ns
CC
0
6
ns
Not 100% tested, guaranteed by design and characterization.
Data Sheet
72
V1.0, 2001-10
C167CS-L16M3V
Low Power
CLKOUT
tc 28
HOLD
tc 30
HLDA
1)
tc 29
BREQ
2)
tc 31
CS
3)
tc 33
Other
Signals
MCT04421
Figure 22
External Bus Arbitration, Releasing the Bus
Notes
1)
The C167CS-3V will complete the currently running bus cycle before granting bus access.
2)
This is the first possibility for BREQ to get active.
3)
The CS outputs will be resistive high (pullup) after t33. Latched CS outputs are driven high for 1 TCL before
the output drivers are switched off.
Data Sheet
73
V1.0, 2001-10
C167CS-L16M3V
Low Power
5)
CLKOUT
tc 28
HOLD
tc 30
HLDA
tc 29
tc 29
BREQ
tc 29
4)
tc 32
CS
tc 34
Other
Signals
MCT04422
Figure 23
External Bus Arbitration, (Regaining the Bus)
Notes
4)
This is the last chance for BREQ to trigger the indicated regain-sequence.
Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high.
Please note that HOLD may also be deactivated without the C167CS-3V requesting the bus.
5)
The next C167CS-3V driven bus cycle may start here.
Data Sheet
74
V1.0, 2001-10
C167CS-L16M3V
Low Power
External XRAM Access
If XPER-Share mode is enabled the on-chip XRAM of the C167CS-3V can be accessed
(during hold states) by an external master like an asynchronous SRAM.
Table 21
XRAM Access Timing (Operating Conditions apply)
Parameter
Symbol
Limits
min
Address setup time before RD/WR falling edge
Address hold time after RD/WR rising edge
Read
Data turn on delay after RD falling edge
Data output valid delay after address latched
Data turn off delay after RD rising edge
Write data setup time before WR rising edge
Write
Write data hold time after WR rising edge
WR pulse width
WR signal recovery time
t40
t41
t42
t43
t44
t45
t46
t47
t48
Unit
max
SR 5
–
ns
SR 0
–
ns
CC 2
–
ns
CC –
57
ns
CC 0
10
ns
SR 10
–
ns
SR 4
–
ns
SR 20
–
ns
SR t40
–
ns
t40
t41
Address
t47
t48
Command
(RD, WR)
t46
t45
Write Data
t43
t42
t44
Read Data
MCT04423
Figure 24
Data Sheet
External Access to the XRAM
75
V1.0, 2001-10
C167CS-L16M3V
Low Power
Package Outlines
P-MQFP-144-6
(Plastic Metric Quad Flat Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Data Sheet
76
Dimensions in mm
V1.0, 2001-10
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