A1150, A1152, A1153, A1155, A1156, A1157, and A1158 Datasheet

A1150, A1152, A1153, A1155, A1156, A1157, and A1158
Chopper-Stabilized, Two-Wire Hall-Effect Switches
FEATURES AND BENEFITS
DESCRIPTION
•
•
•
•
•
AEC-Q100 automotive qualified
High-speed, 4-phase chopper stabilization
Low switchpoint drift throughout temperature range
Low sensitivity to thermal and mechanical stresses
On-chip protection
□□ Supply transient protection
□□ Reverse-battery protection
□□ On-board voltage regulator
□□ 3 to 24 V operation
• Solid-state reliability
• Robust EMC and ESD performance
• Industry-leading ISO 7637-2 performance through use of
proprietary, 40 V clamping structures
The A1150, A1152, A1153, A1155, A1156, A1157, and A1158
comprise a family of two-wire, unipolar, Hall-effect switches,
which are factory-trimmed to optimize magnetic switchpoint
accuracy. These devices are produced on the Allegro™ advanced
BiCMOS wafer fabrication process, which implements
a patented high-frequency, 4-phase, chopper-stabilization
technique. This technique achieves magnetic stability over
the full operating temperature range, and eliminates offsets
inherent in devices with a single Hall element that are exposed
to harsh application environments.
The A115x family has a number of automotive applications.
These include sensing seat track position, seat belt buckle
presence, hood/trunk latching, and shift selector position.
Continued on the next page…
Two-wire unipolar switches are particularly advantageous in
cost-sensitive applications because they require one less wire
for operation versus the more traditional open-collector output
switches. Additionally, the system designer inherently gains
diagnostics because there is always output current flowing,
which should be in either of two narrow ranges. Any current
level not within these ranges indicates a fault condition.
Packages
3-pin SOT23-W
2 mm × 3 mm × 1
mm (suffix LH)
3-pin ultramini SIP
1.5 mm × 4 mm × 3
mm (suffix UA)
2-pin ultramini SIP
1.5 mm × 4 mm × 4
mm (suffix UB)
All family members are offered in three package styles. The
LH is a SOT-23W style, miniature, low profile package for
surface-mount applications. The UA is a 3-pin, ultra-mini, single
inline package (SIP) for through-hole mounting. The UB is a
2-pin, ultra-mini, single inline package (SIP) for through-hole
mounting. All three packages are lead (Pb) free, with 100%
matte-tin leadframe plating.
Approximate footprint
UB package only
0.1 µF
V+
VCC
Regulator
To all subcircuits
0.01 µF
Amp
Sample and Hold
Clock/Logic
Dynamic Offset
Cancellation
LH & UA
package
only
Low-Pass
Filter
Schmitt
Trigger
Polarity
GND
UA package only
Functional Block Diagram
A1152-DS, Rev. 10
GND
Chopper-Stabilized, Two-Wire
Hall-Effect Switches
A1150, A1152, A1153, A1155,
A1156, A1157, and A1158
Features and Benefits (continued)
• Extended Operating Ambient temperature range,
–40°C to 150°C
• UB package with integrated 0.1 µF bypass capacitor
Selection Guide
Part Number
Packing
Package
A1150LLHLX-T
13-in. reel, 10 000 pieces/reel
3-pin SOT23W surface mount
A1150LUA-T
Bulk, 500 pieces/bag
3-pin SIP through hole
A1152LLHLX-T
13-in. reel, 10 000 pieces/reel
3-pin SOT23W surface mount
A1152LUA-T
Bulk, 500 pieces/bag
3-pin SIP through hole
A1152LUBTN-T
13-in. reel, 4 000 pieces/reel
2-pin SIP through hole
A1153LLHLX-T
13-in. reel, 10 000 pieces/reel
3-pin SOT23W surface mount
A1153LUA-T
Bulk, 500 pieces/bag
3-pin SIP through hole
A1153LUBTN-T
13-in. reel, 4 000 pieces/reel
2-pin SIP through hole
A1155LLHLX-T
13-in. reel, 10 000 pieces/reel
3-pin SOT23W surface mount
A1155LUA-T
Bulk, 500 pieces/bag
3-pin SIP through hole
A1155LUBTN-T
13-in. reel, 4 000 pieces/reel
2-pin SIP through hole
A1156LLHLX-T
13-in. reel, 10 000 pieces/reel
3-pin SOT23W surface mount
A1156LUA-T
Bulk, 500 pieces/bag
3-pin SIP through hole
A1156LUBTN-T
13-in. reel, 4 000 pieces/reel
2-pin SIP through hole
A1157LLHLX-T
13-in. reel, 10 000 pieces/reel
3-pin SOT23W surface mount
A1157LLHLT-T
7-in. reel, 3000 pieces/reel
3-pin SOT23W surface mount
A1157LUA-T
Bulk, 500 pieces/bag
3-pin SIP through hole
A1158LLHLX-T
13-in. reel, 10 000 pieces/reel
3-pin SOT23W surface mount
A1158LLHLT-T
7-in. reel, 3000 pieces/reel
3-pin SOT23W surface mount
A1158LUA-T
Bulk, 500 pieces/bag
3-pin SIP through hole
Output (ICC) in
South Polarity
Field
Supply Current
at ICC(L)
(mA)
Low
2 to 5
Low
5 to 6.9
High
5 to 6.9
Low
5 to 6.9
Magnetic Operate
Point, BOP
(G)
50 to 110
20 to 60
High
5 to 6.9
Low
2 to 5
20 to 80
High
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
Chopper-Stabilized, Two-Wire
Hall-Effect Switches
A1150, A1152, A1153, A1155,
A1156, A1157, and A1158
SPECIFICATIONS
Absolute Maximum Ratings
Characteristic
Symbol
Notes
Rating
Unit
Forward Supply Voltage
VCC
28
V
Reverse Supply Voltage
VRCC
–18
V
Magnetic Flux Density
B
Operating Ambient Temperature
TA
Unlimited
G
–40 to 150
ºC
Maximum Junction Temperature
TJ(max)
165
ºC
Tstg
–65 to 170
ºC
Storage Temperature
Range L
Pin-Out Diagrams and Terminal List Table
3
LH and UA Terminal List Table
Number
1
NC
1
Name
UA package
VCC
VCC
Input power supply
GND
LH package: no connection,
it is highly recommended that
this pin be tied to GND
2
1
LH Package
2
3
2
Function
LH package
NC
UA package: ground terminal
UA Package
3
GND
GND
Ground terminal
UB Terminal List Table
1
Number
Name
Function
1
VCC
Input power supply
2
GND
Ground terminal
2
UB Package
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
Chopper-Stabilized, Two-Wire
Hall-Effect Switches
A1150, A1152, A1153, A1155,
A1156, A1157, and A1158
ELECTRICAL CHARACTERISTICS: valid at TA = –40°C to 150°C, TJ < TJ(max), CBYP = 0.01 µF, through operating supply
voltage range, unless otherwise noted
Characteristics
Supply
Voltage1,2
Symbol
VCC
ICC(L)
Supply Current
ICC(H)
Supply Zener Clamp Voltage
VZ(sup)
Test Conditions
Operating, TJ ≤ 165 °C
A1150, A1157
B > BOP
A1158
B < BRP
A1152, A1155
B > BOP
A1153, A1156
B < BRP
A1150, A1152,
A1155, A1157
B < BRP
A1153, A1156,
A1158
B > BOP
ICC(L)(max) + 3 mA, TA = 25°C
Min.
Typ.
Max.
Unit
3.0
–
24
V
2.0
–
5.0
mA
5
–
6.9
mA
12
–
17
mA
28
–
–
V
mA
Supply Zener Clamp Current
IZ(sup)
VZ(sup) = 28 V
–
–
ICC(L)(max)
+ 3 mA
Reverse Supply Current
IRCC
VRCC = –18 V
–
–
–1.6
mA
No bypass capacitor, capacitance of
probe CS = 20 pF
–
90
–
mA / µs
di/dt
LH
and
UA
UB
Integrated bypass capacitor,
capacitance of probe CS = 20 pF
–
0.22
–
mA / µs
–
700
–
kHz
–
–
25
µs
–
ICC(H)
–
–
Output Slew Rate3
Chopping Frequency
Power-Up Time4,5
Power-Up State2,4,6,7
fc
ton
POS
A1150, A1152,
A1155, A1157
A1153, A1156,
A1158
B > BOP + 10 G
B < BRP – 10 G
ton < ton(max) , VCC slew rate > 25 mV / µs
1V
CC represents the generated voltage between the VCC pin and the GND pin.
2The V
CC slew rate must exceed 600 mV/ms from 0 to 3 V. A slower slew rate through this range can affect device performance.
3Measured without bypass capacitor between VCC and GND. Use of a bypass capacitor results in slower current change.
4Power-Up Time is measured without and with bypass capacitor of 0.01 µF. Adding a larger bypass capacitor would cause longer Power-Up Time.
5Guaranteed by characterization and design.
6Power-Up State as defined is true only with a V
CC slew rate of 25 mV / µs or greater.
7For t > t
on and BRP < B < BOP , Power-Up State is not defined.
MAGNETIC CHARACTERISTICS1: Valid at TA = –40°C to 150°C, TJ < TJ (max), unless otherwise noted
Characteristics
Magnetic Operating Point
Magnetic Release Point
Hysteresis
Symbol
BOP
BRP
BHYS
Min.
Typ.
Max.
Unit2
A1150, A1152, A1153
50
–
110
G
A1155, A1156
20
–
60
G
A1157, A1158
20
–
80
G
A1150, A1152, A1153
45
–
105
G
A1155, A1156
10
–
55
G
A1157, A1158
10
–
60
G
5
–
30
G
1Relative
values of B use the algebraic convention, where positive values indicate south magnetic polarity, and negative values indicate north magnetic polarity; therefore
greater B values indicate a stronger south polarity field (or a weaker north polarity field, if present).
G (gauss) = 0.1 mT (millitesla).
21
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
Chopper-Stabilized, Two-Wire
Hall-Effect Switches
A1150, A1152, A1153, A1155,
A1156, A1157, and A1158
THERMAL CHARACTERISTICS: may require derating at maximum conditions; see application information
Characteristic
Symbol
Package Thermal Resistance
Test Conditions*
RθJA
Value
Unit
Package LH, on 1-layer PCB with copper limited to solder pads
228
ºC/W
Package LH, on 2-layer PCB with 0.463 in.2 of copper area each side
110
ºC/W
Package UA, on 1-layer PCB with copper limited to solder pads
165
ºC/W
Package UB, on 1-layer PCB with copper limited to solder pads
213
ºC/W
*Additional thermal information available on the Allegro website
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
UB Power Derating Curve
VCC(max)
2-layer PCB, Package LH
(RθJA = 110 ºC/W)
1-layer PCB, Package UA
(RθJA = 165 ºC/W)
1-layer PCB, Package LH
(RθJA = 228 ºC/W)
20
40
60
80
100
VCC(min)
120
140
160
180
Temperature (ºC)
Temperature
LH and UAPower
PowerDissipation
Dissipationversus
versus Ambient
Ambient Temperature
Power Dissipation, PD (m W)
Maximum Allowable VCC (V)
Power
Curve Curve
LH and
UADerating
Power Derating
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
UB Power Dissipation versus Ambient Temperature
2l
(R aye
rP
θJ
C
A =
11 B, P
0 º ac
1-la
C/ ka
y
W
(R er PC
) ge L
θJA =
B
H
165 , Pac
k
ºC/
a
W) ge U
A
1-lay
er P
(R
CB,
θJA =
228 Packag
ºC/W
e LH
)
20
40
60
80
100
120
Temperature (°C)
140
160
180
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
Chopper-Stabilized, Two-Wire
Hall-Effect Switches
A1150, A1152, A1153, A1155,
A1156, A1157, and A1158
CHARACTERISTIC PERFORMANCE
A1152/A1153/A1155/A1156
Average Supply Current (Low) versus Temperature
A1152/A1153/A1155/A1156
Average Supply Current (Low) versus Supply Voltage
7.0
Supply Current, ICC(L) (mA)
Supply Current, ICC(L) (mA)
7.0
6.5
VCC = 24 V
6.0
VCC = 3.0 V
5.5
5.0
-60
-40
-20
0
20
40
60
80
100
120
140
6.5
TA = –40°C
6.0
TA = 25°C
5.5
5.0
160
TA = 150°C
2
6
Ambient Temperature, TA (°C)
A1150/A1157/A1158
Average Supply Current (Low) versus Temperature
18
22
26
A1150/A1157/A1158
5.0
Supply Current, ICC(L) (mA)
Supply Current, ICC(L) (mA)
14
Average Supply Current (Low) versus Supply Voltage
5.0
4.5
4.0
VCC = 24 V
3.5
VCC = 3.0 V
3.0
2.5
2.0
-60
-40
-20
0
20
40
60
80
100
120
140
4.5
4.0
TA = –40°C
3.0
2.5
2.0
160
TA = 150°C
TA = 25°C
3.5
2
6
Ambient Temperature, TA (°C)
A1150/A1152/A1153/A1155/A1156/A1157/A1158
14
18
22
26
A1150/A1152/A1153/A1155/A1156/A1157/A1158
Average Supply Current (High) versus Supply Voltage
17
Supply Current, ICC(H) (mA)
17
16
VCC = 24 V
15
VCC = 3.0 V
14
13
12
-60
10
Supply Voltage, VCC (V)
Average Supply Current (High) versus Temperature
Supply Current, ICC(H) (mA)
10
Supply Voltage, VCC (V)
16
-20
0
20
40
60
80
100
Ambient Temperature, TA (°C)
120
140
160
TA = 150°C
TA = 25°C
14
13
12
-40
TA = –40°C
15
2
6
10
14
18
22
26
Supply Voltage, VCC (V)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
Chopper-Stabilized, Two-Wire
Hall-Effect Switches
A1150, A1152, A1153, A1155,
A1156, A1157, and A1158
A1150/A1152/A1153
A1155/A1156
Average Operate Point versus Temperature
Average Operate Point versus Temperature
60
55
100
Applied Flux Density at
Operate Point, BOP (G)
Applied Flux Density at
Operate Point, BOP (G)
110
90
VCC = 24 V
80
VCC = 3.0 V
70
60
50
-60
-40
-20
0
20
40
60
80
100
120
140
50
45
VCC = 3.0 V
40
VCC = 24 V
35
30
25
20
-60
160
-40
-20
Ambient Temperature, TA (°C)
A1150/A1152/A1153
40
60
80
100
120
140
160
Average Release Point versus Temperature
105
55
50
95
Applied Flux Density at
Release Point, BRP (G)
Applied Flux Density at
Release Point, BRP (G)
20
A1155/A1156
Average Release Point versus Temperature
85
75
VCC = 3.0 V
65
VCC = 24 V
55
45
-60
-40
-20
0
20
40
60
80
100
120
140
45
40
35
30
VCC = 3.0 V
25
VCC = 24 V
20
15
10
-60
160
-40
-20
Ambient Temperature, TA (°C)
A1150/A1152/A1153
A1150/A1152/A1153/A1155/A1156/A1157/A1158
25
20
VCC = 24 V
VCC = 3.0 V
10
5
-60
-40
-20
0
20
40
60
80
100
Ambient Temperature, TA (°C)
20
40
60
80
100
120
140
160
A1155/A1156
A1150/A1152/A1153/A1155/A1156/A1157/A1158
Average Switchpoint Hysteresis versus Temperature
Applied Flux Density at
Switchpoint Hysteresis, BHYS (G)
30
15
0
Ambient Temperature, TA (°C)
Average Switchpoint Hysteresis versus Temperature
Applied Flux Density at
Switchpoint Hysteresis, BHYS (G)
0
Ambient Temperature, TA (°C)
120
140
160
30
25
20
15
VCC = 3.0 V
VCC = 24 V
10
5
-60
-40
-20
0
20
40
60
80
100
120
140
160
Ambient Temperature, TA (°C)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
Chopper-Stabilized, Two-Wire
Hall-Effect Switches
A1150, A1152, A1153, A1155,
A1156, A1157, and A1158
FUNCTIONAL DESCRIPTION
I+
B+
BHYS
(A) Hysteresis curve for A1150, A1152, A1155, and A1157
0
ICC(L)
B–
BRP
BOP
BRP
ICC(H)
ICC
ICC
ICC(L)
B–
I+
Switch to Low
0
Switch to Low
Switch to High
ICC(H)
The difference between the magnetic operate and release points
is called the hysteresis of the device, BHYS . This built-in hysteresis allows clean switching of the output even in the presence of
external mechanical vibration and electrical noise.
Switch to High
In the case of the reverse output polarity, as in the A1153, A1156,
and A1158, the device output switches high after the magnetic
field at the Hall sensor IC exceeds the operate point threshold,
BOP . When the magnetic field is reduced to below the release
point threshold, BRP, the device output goes low (panel B).
BOP
The A1150, A1152, A1155, and A1157 output, ICC, switches low
after the magnetic field at the Hall sensor IC exceeds the operate point threshold, BOP . When the magnetic field is reduced to
below the release point threshold, BRP , the device output goes
high. This is shown in Figure 1, panel A.
B+
BHYS
(B) Hysteresis curve for A1153, A1156, and A1158
Figure 1: Alternative Switching Behaviors Available in the A115x Device Family.
On the horizontal axis, the B+ direction indicates increasing south polarity magnetic field strength, and the B– direction indicates decreasing
south polarity field strength (including the case of increasing north polarity).
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
Chopper-Stabilized, Two-Wire
Hall-Effect Switches
A1150, A1152, A1153, A1155,
A1156, A1157, and A1158
V+
VCC
RSENSE
A115x
V+
CBYP
0.1 µF
VCC
0.01 µF
A115x
C
B
CBYP
GND
0.1 µF
GND
0.01 µF
C
B
A
GND
GND
ECU
A
Package UA Only
B
Package UB Only
C
Package LH & UA Only
RSENSE
A
(A) Low side sensing
(B) High side sensing
Figure 2: Typical Application Circuits
Chopper Stabilization Technique
When using Hall-effect technology, a limiting factor for
switchpoint accuracy is the small signal voltage developed
across the Hall element. This voltage is disproportionally small
relative to the offset that can be produced at the output of the
Hall sensor IC. This makes it difficult to process the signal while
maintaining an accurate, reliable output over the specified operating temperature and voltage ranges. Chopper stabilization is
a unique approach used to minimize Hall offset on the chip. The
patented Allegro technique, namely Dynamic Quadrature Offset
Cancellation, removes key sources of the output drift induced by
thermal and mechanical stresses. This offset reduction technique
is based on a signal modulation-demodulation process. The
undesired offset signal is separated from the magnetic fieldinduced signal in the frequency domain, through modulation.
The subsequent demodulation acts as a modulation process for
the offset, causing the magnetic field-induced signal to recover
its original spectrum at base band, while the DC offset becomes
a high-frequency signal. The magnetic-sourced signal then can
pass through a low-pass filter, while the modulated DC offset is
suppressed. The chopper stabilization technique uses a 350 kHz
high frequency clock. For demodulation process, a sample and
hold technique is used, where the sampling is performed at twice
the chopper frequency. This high-frequency operation allows
a greater sampling rate, which results in higher accuracy and
faster signal-processing capability. This approach desensitizes
the chip to the effects of thermal and mechanical stresses, and
produces devices that have extremely stable quiescent Hall output voltages and precise recoverability after temperature cycling.
This technique is made possible through the use of a BiCMOS
process, which allows the use of low-offset, low-noise amplifiers
in combination with high-density logic integration and sampleand-hold circuits.
Regulator
Hall Element
Amp
Sample and
Hold
Clock/Logic
Low-Pass
Filter
Figure 3: Chopper Stabilization Circuit (Dynamic Quadrature Offset Cancellation)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
Chopper-Stabilized, Two-Wire
Hall-Effect Switches
A1150, A1152, A1153, A1155,
A1156, A1157, and A1158
Power Derating
The device must be operated below the maximum junction temperature of the device, TJ(max). Under certain combinations of
peak conditions, reliable operation may require derating supplied
power or improving the heat dissipation properties of the application. This section presents a procedure for correlating factors
affecting operating TJ. (Thermal data is also available on the
Allegro MicroSystems Web site.)
The Package Thermal Resistance, RθJA, is a figure of merit summarizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity, K,
of the printed circuit board, including adjacent devices and traces.
Radiation from the die through the device case, RθJC, is relatively
small component of RθJA. Ambient air temperature, TA, and air
motion are significant external factors, damped by overmolding.
The effect of varying power levels (Power Dissipation, PD), can
be estimated. The following formulas represent the fundamental
relationships used to estimate TJ, at PD. PD = VIN × IIN (1)
ΔT = PD × RθJA (2)
TJ = TA + ΔT
(3)
For example, given common conditions such as: TA= 25°C,
VCC = 12 V, ICC = 4 mA, and RθJA = 140 °C/W, then:
PD = VCC × ICC = 12 V × 4 mA = 48 mW
ΔT = PD × RθJA = 48 mW × 140 °C/W = 7°C
TJ = TA + ΔT = 25°C + 7°C = 32°C
A worst-case estimate, PD(max), represents the maximum allowable power level (VCC(max), ICC(max)), without exceeding
TJ(max), at a selected RθJA and TA.
Example: Reliability for VCC at TA = 150°C, package UA, using a
low-K PCB.
Observe the worst-case ratings for the device, specifically: RθJA = 165 °C/W, TJ(max) = 165°C, VCC(max) = 24 V, and
ICC(max) = 17 mA.
Calculate the maximum allowable power level, PD(max). First,
invert equation 3:
ΔTmax = TJ(max) – TA = 165 °C – 150 °C = 15 °C
This provides the allowable increase to TJ resulting from internal
power dissipation. Then, invert equation 2:
PD(max) = ΔTmax ÷ RθJA = 15°C ÷ 165 °C/W = 91 mW
Finally, invert equation 1 with respect to voltage:
VCC(est) = PD(max) ÷ ICC(max) = 91 mW ÷ 17 mA = 5 V
The result indicates that, at TA, the application and device can
dissipate adequate amounts of heat at voltages ≤VCC(est).
Compare VCC(est) to VCC(max). If VCC(est) ≤ VCC(max), then reliable operation between VCC(est) and VCC(max) requires enhanced
RθJA. If VCC(est) ≥ VCC(max), then operation between VCC(est)
and VCC(max) is reliable under these conditions.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
Chopper-Stabilized, Two-Wire
Hall-Effect Switches
A1150, A1152, A1153, A1155,
A1156, A1157, and A1158
PACKAGE OUTLINE DRAWINGS
For Reference Only – Not for Tooling Use
(Reference DWG-2840)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
+0.12
2.98 –0.08
D
1.49
4° ±4°
A
3
+0.020
0.180 –0.053
0.96
D
+0.19
1.91 –0.06
+0.10
2.90 –0.20
2.40
0.70
D
0.25 MIN
1.00
2
1
0.55 REF
0.25 BSC
0.95
Seating Plane
Branded Face
Gauge Plane
B
PCB Layout Reference View
8X 10°
REF
1.00 ±0.13
NNN
+0.10
0.05 –0.05
0.95 BSC
0.40 ±0.10
C
Standard Branding Reference View
N = Last three digits of device part number
A Active Area Depth, 0.28 mm
B Reference land pattern layout; all pads a minimum of 0.20 mm from all adjacent pads;
adjust as necessary to meet application process requirements and PCB layout tolerances
C Branding scale and appearance at supplier discretion
D Hall elements, not to scale
Figure 4: Package LH, 3-Pin SOT23W
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
Chopper-Stabilized, Two-Wire
Hall-Effect Switches
A1150, A1152, A1153, A1155,
A1156, A1157, and A1158
For Reference Only – Not for Tooling Use
(Reference DWG-9013)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
45°
B
4.09
+0.08
–0.05
1.52 ±0.05
E
2.04
C
2 X 10°
1.44 E
3.02
E
Mold Ejector
Pin Indent
+0.08
–0.05
45°
Branded
Face
A
1.02 MAX
0.79 REF
1
2
3
0.43
+0.05
–0.07
0.41
+0.03
–0.06
1.27 NOM
NNN
14.99 ±0.25
1
D
Standard Branding Reference View
= Supplier emblem
N = Last three digits of device part number
A
Dambar removal protrusion (6X)
B
Gate and tie bar burr area
C
Active Area Depth, 0.50 mm REF
D
Branding scale and appearance at supplier discretion
E
Hall element, not to scale
Figure 5: Package UA, 3-Pin SIP
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
Chopper-Stabilized, Two-Wire
Hall-Effect Switches
A1150, A1152, A1153, A1155,
A1156, A1157, and A1158
For Reference Only – Not for Tooling Use
(Reference DWG-9070)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
+0.06
4.00 –0.05
B
4 X 10°
1.50 ±0.05
E
2.00
C
1.75 E
4.00
Mold Ejector
Pin Indent
+0.06
–0.07
E
Branded
Face
A
4 X 2.50 REF
0.25 REF
NNN
YYWW
LLLL
45°
0.85 ±0.07
0.42 ±0.10
D Standard Branding Reference View
0.30 REF
2.54 REF
N
Y
W
L
4 X 0.85 REF
1
= Supplier emblem
= Last three digits of device part number
= Last 2 digits of year of manufacture
= Week of manufacture
= Lot number
2
1.00 ±0.10
12.20 ±0.10
0.25
4 X 7.37 REF
+0.07
–0.03
1.80
±0.10
A
Dambar removal protrusion (8X)
B
Gate and tie bar burr area
C
Active Area Depth, 0.38 mm REF
D
Branding scale and appearance at supplier discretion
E
Hall element; not to scale
F
Thermoplastic Molded Lead Bar for alignment during shipment
0.38 REF
0.25 REF
4 X 0.85 REF
0.85 ±0.07
1.80
+0.06
–0.07
F
4.00
+0.06
–0.05
1.50 ±0.05
Figure 6: Package UB, 2-Pin SIP
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
13
Chopper-Stabilized, Two-Wire
Hall-Effect Switches
A1150, A1152, A1153, A1155,
A1156, A1157, and A1158
Revision History
Revision
Revision Date
7
May 22, 2014
8
October 2, 2014
Description of Revision
Added UB Package
9
March 2, 2015
10
September 21, 2015
Revised UB packge drawing and reformatted document.
Updated branding info on package drawing
Corrected LH package Active Area Depth value; added AEC-Q100 qualification under Features and
Benefits
Copyright ©2015, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
14
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