C505A , C505CA Users Manual

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Addendum to C505/C505C User's Manual 09.97
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8-Bit CMOS Microcontroller
General Information
C515C
Edition 09.97
This edition was realized using the software system FrameMaker.
Published by Siemens AG,
Bereich Halbleiter, MarketingKommunikation, Balanstraße 73,
81541 München
© Siemens AG 97.
All Rights Reserved.
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Semiconductor Group
I-2
General Information
C505A
Contents
Page
1
1.1
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5
2
2.1
2.2
2.3
2.4
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
Program Memory, "Code Space" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
Data Memory, "Data Space" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
3
3.1
3.2
3.3
3.4
3.5
3.5.1
A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
A/D Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
A/D Converter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3
A/D Converter Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7
A/D Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8
A/D Converter Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12
A/D Converter Analog Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-13
4
4.1
4.2
4.3
4.4
4.4.1
4.4.2
4.5
4.6
4.6.1
4.7
OTP Memory Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
Programming Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
Programming Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
Basic Programming Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
OTP Memory Access Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6
Program / Read OTP Memory Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7
Lock Bits Programming / Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-9
Access of Version Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-11
OTP Verification Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-12
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.7.1
5.7.2
5.8
Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2
A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-5
AC Characteristics (12 MHz, 0.5 Duty Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-7
AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . .5-9
AC Characteristics (20 MHz, 0.5 Duty Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-12
OTP Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-17
Programming Mode Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-17
OTP Verification Mode Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-21
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-23
6
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1
Semiconductor Group
I-1
Introduction
C505A
1
Introduction
The C505A is an enhanced, upgraded version of the C505-2R eight bit microcontroller and
incorporates more on-chip RAM, a 10-bit A/D Converter and 32K bytes of on-chip OTP memory.
With a maximum external clock rate of 20 MHz, the C505A has an instruction cycle time of 300 ns.
With the C505A-4E fast OTP programming cycles are achieved (1 byte in 100 µsec). Also several
levels of OTP memory protection can be selected. The basic functionality of the C505A-4E as a
microcontroller is identical to the C505A-L (romless part) functionality. Therefore, the
programmable C505A-4E typically can be used for prototype system design.
The C505A-4E basically operates with internal OTP and/or external program memory. The C505AL is identical to the C505A-4E, except that it lacks the on-chip OTP memory. Therefore, in this
documentation the term C505A refers to all versions within this specification unless otherwise
noted.
The C505CA-4E and C505CA-L, are identical to the C505A-4E and the C505A-L respectively,
except that they have, in addition, the full CAN interface. The term C505A refers to all the above four
versions within this documentation unless otherwise noted.
On-Chip Emulation Support Module
Figure 1-1 shows the different functional units of the C505A and Figure 1-2 shows the simplified
logic symbol of the C505A.
Oscillator
Watchdog
RAM
256 × 8
XRAM
1K×8
10-bit ADC
Timer 2
Watchdog Timer
I/O
Port 1
8 analog inputs /
8 digit. I/O
T0
CPU
Full-CAN
Controller
Port 0
T1
8-bit
USART Port 2
I/O
Port 3
I/O
Port 4
I/O (2-bit I/O port)
8 datapointers
OTP
32K×8
Enhancements over C505/C505C.
C505CA only.
Figure 1-1
C505A Functional Units
Note: This specification describes only the improved functionality over C505/C505C. Please refer to
the C505/C505C User’s Manual for further details.
Semiconductor Group
1-1
Introduction
C505A
Listed below is a summary of the main features of the C505A family:
• Fully compatible to standard 8051 microcontroller
• Superset of the 8051 architecture with 8 datapointers
• Up to 20 MHz operating frequency
– 375 ns instruction cycle time @ 16 MHz
– 300 ns instruction cycle time @ 20 MHz (50 % duty cycle)
• 32K byte on-chip OTP memory
– C505A-4E : programmable OTP versions
– C505A-L : without on-chip program memory
– alternatively up to 64 K bytes of external program memory
• 256 byte on-chip RAM
• 1 K byte on-chip XRAM
• Five ports: 32 + 2 digital I/O lines(Port 1 with mixed analog/digital I/O capability)
• Three 16-bit timers/counters
– Timer 0 / 1 (C501 compatible)
– Timer 2 with 4 channels for 16-bit capture/compare operation
• Full CAN Module (C505CA only)
– 256 register/data bytes located in external data memory area
– 1 MBaud CAN baudrate when operating frequency is equal to or above 8 MHz
– internal CAN clock prescaler when input frequency is over 10 MHz
• Full duplex serial interface with programmable baudrate generator (USART)
• 10-bit A/D Converter with 8 multiplexed inputs
– Built-in self calibration
• Twelve interrupt sources with four priority levels
• On-chip emulation support logic
–Enhanced Hooks Technology TM 1)
• Programmable 15-bit Watchdog Timer
• Oscillator Watchdog
• Fast Power On Reset
• Power Saving Modes
– Slow-down mode
– Idle mode (can be combined with slow-down mode)
– Software power-down mode with wake up capability through P3.2/INT0 or P4.1/RXDC pin
• P-MQFP-44 package
• Pin configuration is compatible to C501, C504, C511/C513-family, C505, C505C
• Temperature ranges:
SAB-C505A versions
TA = 0 to 70 °C
SAF-C505A versions
TA = – 40 to 85°C
SAH-C505A versions
TA = – 40 to 110°C (max. operating frequency: TBD)
SAK-C505A versions
TA = –40 to 125°C (max. operating frequency: 12 MHz
with 50 % duty cycle)
1 “Enhanced Hooks Technology“ is a trademark and patent of Metalink Corporation licensed to Siemens.
Semiconductor Group
1-2
Introduction
C505A
VCC
VSS
VAREF
Port 0
8-bit Digital I/O
VAGND
XTAL1
Port 1
8-bit Digital I/O /
8-bit Analog Inputs
XTAL2
RESET
C505A
C505CA
Port 2
8-bit Digital I/O
EA
ALE
Port 3
8-bit Digital I/O
PSEN
Port 4
2-bit Digital I/O
RXDC
TXDC
C505CA only.
Figure 1-2
Logic Symbol
Semiconductor Group
1-3
Introduction
C505A
1.1
Pin Configuration
P0.4 / AD4
P0.5 / AD5
P0.6 / AD6
P0.7 / AD7
EA
P4.1 / RXDC
ALE
PSEN
P2.7 / A15
P2.6 / A14
P2.5 / A13
This section shows the pin configuration of the C505A in the P-MQFP-44 package.
P0.3 / AD3
P0.2 / AD2
P0.1 / AD1
P0.0 / AD0
VAREF
VAGND
P1.0 / AN0 / INT3 / CC0
P1.1 / AN1 / INT4 / CC1
P1.2 / AN2 / INT5 / CC2
P1.3 / AN3 / INT6 / CC3
P1.4 / AN4
33 32 31 30 29 28 27 26 25 24 23
34
22
35
21
36
20
37
19
38
C505A
C505CA
39
40
18
17
16
41
15
42
14
43
13
44
2
3
4
5
6 7
8
12
9 10 11
P1.5 / AN5 / T2EX
P1.6 / AN6 / CLKOUT
P1.7 / AN7 / T2
RESET
P3.0 / RxD
P4.0 / TXDC
P3.1 / TxD
P3.2 / INT0
P3.3 / INT1
P3.4 / T0
P3.5 / T1
1
This pin functionality is available in the C505CA only.
Figure 1-3
Pin Configuration (Top View)
Semiconductor Group
1-4
P2.4 / A12
P2.3 / A11
P2.2 / A10
P2.1 / A9
P2.0 / A8
VCC
VSS
XTAL1
XTAL2
P3.7 / RD
P3.6 / WR
Introduction
C505A
1.2
Pin Definitions and Functions
This section describes all external signals of the C505A with its function.
Table 1-1 :
Pin Definitions and Functions
Symbol
P1.0-P1.7
Pin Number
40-44,1-3
40
41
42
43
44
1
2
3
I/O
*)
Function
I/O
Port 1
is an 8-bit quasi-bidirectional port with internal pull-up
arrangement. Port 1 pins can be used for digital input/output
or as analog inputs of the A/D converter. Port 1 pins that
have 1’s written to them are pulled high by internal pull-up
transistors and in that state can be used as inputs. As
inputs, port 1 pins being externally pulled low will source
current (I IL , in the DC characteristics) because of the
internal pullup transistors. Port 1 pins are assigned to be
used as analog inputs via the register P1ANA.
As secondary digital functions, port 1 contains the interrupt,
timer, clock, capture and compare pins. The output latch
corresponding to a secondary function must be
programmed to a one (1) for that function to operate (except
for compare functions). The secondary functions are
assigned to the pins of port 1 as follows:
P1.0 / AN0 / INT3 / CC0
Analog input channel 0
interrupt 3 input /
capture/compare channel 0 I/O
P1.1 / AN1 / INT4 / CC1 Analog input channel 1/
interrupt 4 input /
capture/compare channel 1 I/O
P1.2 / AN2 / INT5 / CC2 Analog input channel 2 /
interrupt 5 input /
capture/compare channel 2 I/O
P1.3 / AN3 / INT6 / CC3 Analog input channel 3
interrupt 6 input /
capture/compare channel 4 I/O
P1.4 / AN4
Analog input channel 4
P1.5 / AN5 / T2EX
Analog input channel 5 / Timer 2
external reload / trigger input
P1.6 / AN6 / CLKOUT
Analog input channel 6 /
system clock output
P1.7 / AN7 / T2
Analog input channel 7 /
counter 2 input
*) I = Input
O = Output
Semiconductor Group
1-5
Introduction
C505A
Table 1-1 :
Pin Definitions and Functions (cont’d)
Symbol
Pin Number
I/O
*)
Function
RESET
4
I
RESET
A high level on this pin for two machine cycles while the
oscillator is running resets the device. An internal diffused
resistor to V SS permits power-on reset using only an
external capacitor to VCC.
P3.0-P3.7
5, 7-13
I/O
Port 3
is an 8-bit quasi-bidirectional port with internal pull-up
arrangement. Port 3 pins that have 1’s written to them are
pulled high by the internal pull-up transistors and in that
state can be used as inputs. As inputs, port 3 pins being
externally pulled low will source current (I IL , in the DC
characteristics) because of the internal pullup transistors.
The output latch corresponding to a secondary function
must be programmed to a one (1) for that function to operate
(except for TxD and WR). The secondary functions are
assigned to the pins of port 3 as follows:
P3.0 / RxD
Receiver data input (asynch.) or data
input/output (synch.) of serial interface
P3.1 / TxD
Transmitter data output (asynch.) or
clock output (synch.) of serial interface
P3.2 / INT0
External interrupt 0 input / timer 0 gate
control input
P3.3 / INT1
External interrupt 1 input / timer 1 gate
control input
P3.4 / T0
Timer 0 counter input
P3.5 / T1
Timer 1 counter input
P3.6 / WR
WR control output; latches the data
byte from port 0 into the external data
memory
P3.7 / RD
RD control output; enables the external
data memory
5
7
8
9
10
11
12
13
*) I = Input
O = Output
Semiconductor Group
1-6
Introduction
C505A
Table 1-1 :
Pin Definitions and Functions (cont’d)
Symbol
Pin Number
I/O
*)
Function
P4.0
P4.1
6
28
I/O
I/O
Port 4
is a 2-bit quasi-bidirectional port with internal pull-up
arrangement. Port 4 pins that have 1’s written to them are
pulled high by the internal pull-up transistors and in that
state can be used as inputs. As inputs, port 4 pins being
externally pulled low will source current (I IL , in the DC
characteristics) because of the internal pullup transistors.
The output latch corresponding to the secondary function
RXDC must be programmed to a one (1) for that function to
operate. The secondary functions are assigned to the two
pins of port 4 as follows (C505CA only) :
P4.0 / TXDC
Transmitter output of CAN controller
P4.1 / RXDC
Receiver input of CAN controller
XTAL2
14
O
XTAL2
Output of the inverting oscillator amplifier.
XTAL1
15
I
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock generator circuits.
To drive the device from an external clock source, XTAL1
should be driven, while XTAL2 is left unconnected. To
operate above a frequency of 16 MHz, a duty cycle of the
etxernal clock signal of 50 % should be maintained.
Minimum and maximum high and low times as well as rise/
fall times specified in the AC characteristics must be
observed.
*) I = Input
O = Output
Semiconductor Group
1-7
Introduction
C505A
Table 1-1 :
Pin Definitions and Functions (cont’d)
Symbol
Pin Number
I/O
*)
Function
P2.0-P2.7
18-25
I/O
Port 2
is a an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 2 pins that have 1’s written to them are pulled
high by the internal pullup resistors, and in that state can be
used as inputs. As inputs, port 2 pins being externally pulled
low will source current (I IL , in the DC characteristics)
because of the internal pullup resistors. Port 2 emits the
high-order address byte during fetches from external
program memory and during accesses to external data
memory that use 16-bit addresses (MOVX @DPTR). In this
application it uses strong internal pullup transistors when
issuing 1s. During accesses to external data memory that
use 8-bit addresses (MOVX @Ri), port 2 issues the
contents of the P2 special function register and uses only
the internal pullup resistors.
PSEN
26
O
The Program Store Enable
output is a control signal that enables the external program
memory to the bus during external fetch operations. It is
activated every three oscillator periods except during
external data memory accesses. Remains high during
internal program execution. This pin should not be driven
during reset operation.
ALE
27
O
The Address Latch Enable
output is used for latching the low-byte of the address into
external memory during normal operation. It is activated
every three oscillator periods except during an external data
memory access. When instructions are executed from
internal OTP (EA=1) the ALE generation can be disabled by
bit EALE in SFR SYSCON.
ALE should not be driven during reset operation.
*) I = Input
O = Output
Semiconductor Group
1-8
Introduction
C505A
Table 1-1 :
Pin Definitions and Functions (cont’d)
Symbol
Pin Number
I/O
*)
Function
EA
29
I
External Access Enable
When held at high level, instructions are fetched from the
internal OTP memory when the PC is less than 8000H.
When held at low level, the C505A/C505CA fetches all
instructions from external program memory. EA should not
be driven during reset operation.
For the C505A-L and the C505CA-L this pin must be tied
low.
P0.0-P0.7
37-30
I/O
Port 0
is an 8-bit open-drain bidirectional I/O port. Port 0 pins that
have 1’s written to them float, and in that state can be used
as high-impendance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external
program or data memory. In this application it uses strong
internal pullup transistors when issuing 1’s.
VAREF
38
–
Reference voltage for the A/D converter.
VAGND
39
–
Reference ground for the A/D converter.
VSS
16
–
Ground (0V)
VCC
17
–
Power Supply (+5V)
*) I = Input
O = Output
Semiconductor Group
1-9
Memory Organization
C505A
2
Memory Organization
The C505A CPU manipulates operands in the following four address spaces:
–
–
–
–
–
–
up to 64 Kbytes of program memory (32K on-chip OTP memory for C505A-4E)
up to 64 Kbytes of external data memory
256 bytes of internal data memory
1 Kbytes of internal XRAM data memory
256 bytes CAN controller registers / data memory (C505CA only)
a 128 byte special function register area
Figure 2-1 illustrates the memory address spaces of the C505A.
Alternatively
Internal
XRAM
FFFFH
Ext.
Data
Memory
ext.
8000H
7FFFH
int.
(EA = 1)
FFFFH
see table below
FC00H for detailed
Data memory
not used
partitioning
Int. CAN F7FFH
Contr.
(256 Byte)
F700H
F6FFH
indirect
direct
addr.
addr.
(1 K Byte)
Internal
RAM
Ext.
Data
Memory
ext.
(EA = 0)
0000H
"Code Space"
0000H
"Data Space"
FFH
80H
Internal
RAM
Device
CAN Area
Unused Area
Internal XRAM
C505A
-
C505CA
F700H-F7FFH
F700H-FBFFH
F800H-FBFFH
FC00H-FFFFH
FC00H−FFFFH
Semiconductor Group
2-1
7FH
00H
"internal Data Space"
Internal “Data Space” F700H-F7FFH :
Figure 2-1
C505A Memory Map
Special
Function
Regs.
FFH
80H
Memory Organization
C505A
2.1
Program Memory, "Code Space"
The C505A-4E has 32 Kbytes of on-chip OTP program memory which can be externally expanded
up to 64 Kbytes. If the EA pin is held high, the C505A-4E executes program code out of the OTP
memory unless the program counter address exceeds 7FFFH. Address locations 8000H through
FFFFH are then fetched from the external program memory. If the EA pin is held low, the C505A
fetches all instructions from the external program memory.
2.2
Data Memory, "Data Space"
The data memory address space consists of an internal and an external memory space. The
internal data memory is divided into three physically separate and distinct blocks : the lower 128
bytes of RAM, the upper 128 bytes of RAM, and the 128 byte special function register (SFR) area.
While the upper 128 bytes of data memory and the SFR area share the same address locations,
they are accessed through different addressing modes. The lower 128 bytes of data memory can
be accessed through direct or register indirect addressing; the upper 128 bytes of RAM can be
accessed through register indirect addressing; the special function registers are accessible through
direct addressing. Four 8-register banks, each bank consisting of eight 8-bit general-purpose
registers, occupy locations 0 through 1FH in the lower RAM area. The next 16 bytes, locations 20H
through 2FH, contain 128 directly addressable bit locations. The stack can be located anywhere in
the internal RAM area, and the stack depth can be expanded up to 256 bytes.
The external data memory can be expanded up to 64 Kbyte and can be accessed by instructions
that use a 16-bit or an 8-bit address. The internal CAN controller (in C505CA only) and the internal
1 Kbyte XRAM are located in the external memory address area at addresses F700H to F7FFH and
FC00H to FFFFH respectively. The CAN controller registers and internal XRAM can therefore be
accessed using MOVX instructions with addresses pointing to the respective address areas.
2.3
General Purpose Registers
The lower 32 locations of the internal RAM are assigned to four banks of eight general purpose
registers (GPRs) each. Only one of these banks may be enabled at a time. Two bits in the program
status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the
PSW in chapter 2). This allows fast context switching, which is useful when entering subroutines or
interrupt service routines.
The 8 general purpose registers of the selected register bank may be accessed by register
addressing. With register addressing the instruction op code indicates which register is to be used.
For indirect addressing R0 and R1 are used as pointer or index register to address internal or
external memory (e.g. MOV @R0).
Reset initializes the stack pointer to location 07H and increments it once to start from location 08H
which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one
register bank, the SP should be initialized to a different location of the RAM which is not used for
data storage.
Semiconductor Group
2-2
Memory Organization
C505A
2.4
Special Function Registers
The registers, except the program counter and the four general purpose register banks, reside in
the special function register area. The special function register area consists of two portions : the
standard special function register area and the mapped special function register area. One special
function register of the C505A (PCON1) is located in the mapped special function register area. For
accessing the mapped special function register area, bit RMAP in special function register
SYSCON must be set. All other special function registers are located in the standard special
function register area which is accessed when RMAP is cleared (“0“).
In the C505CA, the registers and data locations of the CAN controller (CAN-SFRs) are located in
the external data memory area at addresses F700 H to F7FFH. This is compatible to the C505C and
details about the access of these registers is described in the C505C User’s Manual.
Special Function Register SYSCON (Address B1H)
Reset Value : XX100X01B
(C505CA only) Reset Value : XX100001B
Bit No. MSB
7
B1H
–
6
5
–
EALE
4
3
LSB
0
2
1
CSWO
XMAP1 XMAP0
RMAP CMOD
1)
SYSCON
The functions of the shaded bits are not described here.
1) This bit is available in the C505CA only.
Bit
Function
CSWO
CAN Controller switch-off bit
CPWD = 0 : CAN Controller is enabled (default after reset).
CPWD = 1 : CAN Controller is switched off.
This function is an enhancement over the C505C-2R.
–
Reserved bits for future use. Read by CPU returns undefined values.
As long as bit RMAP is set, mapped special function register area can be accessed. This bit is not
cleared by hardware automatically. Thus, when non-mapped/mapped registers are to be accessed,
the bit RMAP must be cleared/set respectively by software.
All SFRs with addresses where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, ..., F8H, FFH) are
bitaddressable.
The 52 special function registers (SFRs) in the standard and mapped SFR area include pointers
and registers that provide an interface between the CPU and the other on-chip peripherals. The
SFRs of the C505A are listed in table 2-1 and table 2-2. In table 2-1 they are organized in groups
which refer to the functional blocks of the C505A. The CAN-SFRs (applicable to the C505CA only)
are also included in table 2-1. Table 2-2 illustrates the contents of the SFRs in numeric order of their
addresses. Table 2-3 list the CAN-SFRs in numeric order of their addresses.
Semiconductor Group
2-3
Memory Organization
C505A
Table 2-1
Special Function Registers - Functional Blocks
Block
Symbol
Name
Address
Contents after
Reset
CPU
ACC
B
DPH
DPL
DPSEL
PSW
SP
SYSCON2)
Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Data Pointer Select Register
Program Status Word Register
Stack Pointer
System Control Register
E0H 1)
F0H 1)
83H
82H
92H
D0H 1)
81H
B1H
VR0 4)
VR1 4)
VR2 4)
Version Register 0
Version Register 1
Version Register 2
FCH
FDH
FEH
00H
00H
00H
00H
XXXXX000B 3)
00H
07H
XX100X01B 3) 6)
XX100101B 3) 7)
C5H
05H
A/D Converter Control Register 0
A/D Converter Control Register 1
A/D Converter High Byte Data Register
A/D Converter Low Byte Data Register
Port 1 Analog Input Selection Register
D8H 1)
DCH
D9H
DAH
90H
00X00000B 3)
01XXX000B 3)
00H
00XXXXXXB 3)
FFH
A8H 1)
B8H 1)
A9H
B9H
88H 1)
C8H 1)
98H 1)
C0H 1)
00H
00H
00H
XX000000B 3)
00H
00X00000B
00H
00H
A/DADCON0 2)
Converter ADCON1
ADDATH
ADDATL
P1ANA 2) 4)
Interrupt
System
IEN0 2)
IEN1 2)
IP0 2)
IP1
TCON 2)
T2CON 2)
SCON 2)
IRCON
Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Priority Register 0
Interrupt Priority Register 1
Timer Control Register
Timer 2 Control Register
Serial Channel Control Register
Interrupt Request Control Register
XRAM
XPAGE
SYSCON2)
Page Address Register for Extended on-chip 91H
XRAM and CAN Controller
System Control Register
B1H
P0
P1
P1ANA 2) 4)
P2
P3
P4
Port 0
Port 1
Port 1 Analog Input Selection Register
Port 2
Port 3
Port 4
Ports
80H 1)
90H 1)
90H 1)
A0H 1)
B0H 1)
E8H 1)
5)
00H
XX100X01B 3) 6)
XX100101B 3 7)
FFH
FFH
FFH
FFH
FFH
XXXXXX11B
1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) “X“ means that the value is undefined and the location is reserved
4) This SFR is a mapped SFR. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
5) The content of this SFR varies with the actual step of the C505A (eg. 11H for the first step)
6) C505A only
7) C505CA only
Semiconductor Group
2-4
Memory Organization
C505A
Table 2-1
Special Function Registers - Functional Blocks (cont’d)
Block
Symbol
Name
Address
Contents after
Reset
Serial
Channel
ADCON0 2)
PCON 2)
SBUF
SCON
SRELL
SRELH
A/D Converter Control Register 0
Power Control Register
Serial Channel Buffer Register
Serial Channel Control Register
Serial Channel Reload Register, low byte
Serial Channel Reload Register, high byte
D8H 1)
87H
99H
98H 1)
AAH
BAH
00X00000B 3)
00H
XXH 3)
00H
D9H
XXXXXX11B 3)
Timer 0/
Timer 1
TCON
TH0
TH1
TL0
TL1
TMOD
Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register
88H 1)
8CH
8DH
8AH
8BH
89H
00H
00H
00H
00H
00H
00H
Compare/
Capture
Unit /
Timer 2
CCEN
CCH1
CCH2
CCH3
CCL1
CCL2
CCL3
CRCH
CRCL
TH2
TL2
T2CON
IEN0 2)
IEN1 2)
Comp./Capture Enable Reg.
Comp./Capture Reg. 1, High Byte
Comp./Capture Reg. 2, High Byte
Comp./Capture Reg. 3, High Byte
Comp./Capture Reg. 1, Low Byte
Comp./Capture Reg. 2, Low Byte
Comp./Capture Reg. 3, Low Byte
Reload Register High Byte
Reload Register Low Byte
Timer 2, High Byte
Timer 2, Low Byte
Timer 2 Control Register
Interrupt Enable Register 0
Interrupt Enable Register 1
C1H
C3H
C5H
C7H
C2H
C4H
C6H
CBH
CAH
CDH
CCH
C8H 1)
A8H 1)
B8H 1)
00H 3)
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00X00000B 3)
00H
00H
Watchdog Timer Reload Register
Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Priority Register 0
86H
A8H 1)
B8H 1)
A9H
00H
00H
00H
00H
Power Control Register
Power Control Register 1
87H
88H 1)
00H
0XX0XXXXB 3)
Watchdog WDTREL
IEN0 2)
IEN1 2)
IP0 2)
Power
Save
Modes
PCON 2)
PCON1 4)
1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) “X“ means that the value is undefined and the location is reserved
4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
Semiconductor Group
2-5
Memory Organization
C505A
Table 2-1
Special Function Registers - Functional Blocks (cont’d)
Block
Symbol
CR
CAN
Controller SR
IR
(C505CA BTR0
BTR1
only)
GMS0
GMS1
UGML0
UGML1
LGML0
LGML1
UMLM0
UMLM1
LMLM0
LMLM1
MCR0
MCR1
UAR0
UAR1
LAR0
LAR1
MCFG
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Name
Address
Contents after
Reset
Control Register
Status Register
Interrupt Register
Bit Timing Register Low
Bit Timing Register High
Global Mask Short Register Low
Global Mask Short Register High
Upper Global Mask Long Register Low
Upper Global Mask Long Register High
Lower Global Mask Long Register Low
Lower Global Mask Long Register High
Upper Mask of Last Message Register Low
Upper Mask of Last Message Register High
Lower Mask of Last Message Register Low
Lower Mask of Last Message Register High
Message Object Registers :
Message Control Register Low
Message Control Register High
Upper Arbitration Register Low
Upper Arbitration Register High
Lower Arbitration Register Low
Lower Arbitration Register High
Message Configuration Register
Message Data Byte 0
Message Data Byte 1
Message Data Byte 2
Message Data Byte 3
Message Data Byte 4
Message Data Byte 5
Message Data Byte 6
Message Data Byte 7
F700H
F701H
F702H
F704H
F705H
F706H
F707H
F708H
F709H
F70AH
F70BH
F70CH
F70DH
F70EH
F70FH
01H
XXH 3)
XXH 3)
UUH 3)
F7n0H 5)
F7n1H 5)
F7n2H 5)
F7n3H 5)
F7n4H 5)
F7n5H 5)
F7n6H 5)
F7n7H 5)
F7n8H 5)
F7n9H 5)
F7nAH 5)
F7nBH 5)
F7nCH 5)
F7nDH 5)
F7nEH 5)
UUH 3)
UUH 3)
UUH 3)
UUH 3)
UUH 3)
UUUUU000B 3)
UUUUUU00B3)
XXH 3)
XXH 3)
XXH 3)
XXH 3)
XXH 3)
XXH 3)
XXH 3)
XXH 3)
0UUUUUUUB 3)
UUH 3)
UUU11111B 3)
UUH 3)
UUH 3)
UUH 3)
UUUUU000B 3)
UUH 3)
UUH 3)
UUH 3)
UUUUU000B 3)
1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) “X“ means that the value is undefined and the location is reserved. “U“ means that the value is unchanged by
a reset operation. “U“ values are undefined (as “X“) after a power-on reset operation
4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
5) The notation “n“ (n= 1 to F) in the message object address definition defines the number of the related
message object.
Semiconductor Group
2-6
Memory Organization
C505A
Table 2-2
Contents of the SFRs, SFRs in numeric order of their addresses
Addr Register Content Bit 7
after
Reset1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
80H 2) P0
FFH
.7
.6
.5
.4
.3
.2
.1
.0
81H
SP
.7
.6
.5
.4
.3
.2
.1
.0
82H
DPL
07H
00H
.7
.6
.5
.4
.3
.2
.1
.0
83H
DPH
.7
.6
.5
.4
.3
.2
.1
.0
86H
00H
WDTREL 00H
WDT
PSEL
.6
.5
.4
.3
.2
.1
.0
87H
PCON
SMOD PDS
IDLS
SD
GF1
GF0
PDE
IDLE
TF1
TF0
TR0
IE1
IT1
IE0
IT0
88H 2) TCON
88H
3)
00H
00H
TR1
PCON1
0XX0XXXXB
EWPD –
–
WS
–
–
–
–
89H
TMOD
GATE
C/T
M1
M0
GATE
C/T
M1
M0
8AH
TL0
00H
00H
.7
.6
.5
.4
.3
.2
.1
.0
8BH TL1
8CH TH0
00H
00H
.7
.6
.5
.4
.3
.2
.1
.0
.7
.6
.5
.4
.3
.2
.1
.0
8DH TH1
.7
.6
.5
.4
.3
.2
.1
.0
90H 2) P1
00H
FFH
T2
CLKOUT
T2EX
.4
.3
INT5
INT4
.0
90H 3) P1ANA
FFH
EAN7
EAN6
EAN5
EAN4
EAN3
EAN2
EAN1
EAN0
91H
XPAGE
.7
.6
.5
.4
.3
.2
.1
.0
92H
DPSEL
00H
XXXXX000B
–
–
–
–
–
.2
.1
.0
00H
XXH
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
.7
.6
.5
.4
.3
.2
.1
.0
FFH
.7
.6
.5
.4
.3
.2
.1
.0
00H
00H
EA
WDT
ET2
ES
ET1
EX1
ET0
EX0
OWDS WDTS .5
.4
.3
.2
.1
.0
D9H
.7
.4
.3
.2
.1
.0
98H 2) SCON
99H
SBUF
A0H2) P2
A8H2) IEN0
A9H IP0
AAH SRELL
.6
.5
1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
Semiconductor Group
2-7
Memory Organization
C505A
Table 2-2
Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)
Addr Register Content Bit 7
after
Reset1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
B0H2) P3
FFH
B1H SYSCON XX103)
0X01B
RD
WR
T1
T0
INT1
INT0
TxD
RxD
–
–
EALE
RMAP
CMOD –
B1H
–
–
EALE
RMAP
CMOD CSWO XMAP1 XMAP0
SYSCON XX104)
0001B
XMAP1 XMAP0
B8H2) IEN1 3)
000000X0B
EXEN2 SWDT EX6
EX5
EX4
EX3
–
EADC
B8H2) IEN1 4)
B9H IP1
00H
XX000000B
EXEN2 SWDT EX6
EX5
EX4
EX3
ECAN
EADC
–
–
.5
.4
.3
.2
.1
.0
BAH SRELH
XXXXXX11B
–
–
–
–
–
–
.1
.0
C0H IRCON
00H
EXF2
TF2
IEX6
IEX5
IEX4
IEX3
SWI
IADC
C1H CCEN
00H
COCA
H3
COCA
L3
COCA
H2
COCA
L2
COCA
H1
COCA
L1
COCA
H0
COCA
L0
C2H CCL1
00H
00H
.7
.6
.5
.4
.3
.2
.1
.0
.7
.6
.5
.4
.3
.2
.1
.0
00H
00H
.7
.6
.5
.4
.3
.2
.1
.0
.7
.6
.5
.4
.3
.2
.1
.0
00H
00H
.7
.6
.5
.4
.3
.2
.1
.0
.7
.6
.5
.4
.3
.2
.1
.0
C8H T2CON
00X00000B
T2PS
I3FR
–
T2R1
T2R0
T2CM
T2I1
T2I0
CAH CRCL
.7
.6
.5
.4
.3
.2
.1
.0
CBH CRCH
00H
00H
.7
.6
.5
.4
.3
.2
.1
.0
CCH TL2
CDH TH2
00H
00H
.7
.6
.5
.4
.3
.2
.1
.0
.7
.6
.5
.4
.3
.2
.1
.0
D0H PSW
00H
CY
AC
F0
RS1
RS0
OV
F1
P
2)
C3H CCH1
C4H CCL2
C5H CCH2
C6H CCL3
C7H CCH3
2)
2)
1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
3) C505A only
4) C505CA only
Semiconductor Group
2-8
Memory Organization
C505A
Table 2-2
Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)
Addr Register Content Bit 7
after
Reset1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
D8H ADCON0 00X02)
0000B
BD
CLK
–
BSY
ADM
MX2
MX1
MX0
D9H ADDATH 00H
DAH ADDATL 00XXXXXXB
.9
.8
.7
.6
.5
.4
.3
.2
.1
.0
–
–
–
–
–
–
DCH ADCON1 01XXX000B
2)
E0H ACC
00H
ADCL1 ADCL0 –
–
–
MX2
MX1
MX0
.7
.6
.5
.4
.3
.2
.1
.0
E8H2) P4 3)
XXXXXX11B
–
–
–
–
–
–
–
–
E8H2) P4 4)
XXXXXX11B
–
–
–
–
–
–
RXDC
TXDC
F0H2) B
.7
.6
.5
.4
.3
.2
.1
.0
FCH VR0
00H
C5H
.7
.6
.5
.4
.3
.2
.1
.0
FDH VR1
05H
.7
.6
.5
.4
.3
.2
.1
.0
FEH VR2
7)
.7
.6
.5
.4
.3
.2
.1
.0
5) 6)
5) 6)
5) 6)
1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
3) C505A only
4) C505CA only
5) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
6) These are read-only registers
7) The content of this SFR varies with the actual of the step C505A (eg. 11H for the first step)
Semiconductor Group
2-9
Memory Organization
C505A
Table 2-3
Contents of the CAN Registers in numeric order of their addresses (C505CA only)
Addr.
Register Content Bit 7
after
n=1-FH
1)
Reset 2)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
F700H
CR
TEST
CCE
0
0
EIE
SIE
IE
INIT
F701H
SR
BOFF
EWRN –
LEC2
LEC1
LEC0
F702H
IR
F704H
BTR0
F705H
BTR1
0UUU. 0
UUUUB
F706H
GMS0
F707H
GMS1
UUH
UUU1.
1111B
F708H
UGML0
F709H
UGML1
F70AH
LGML0
F70BH
LGML1
01H
XXH
XXH
UUH
RXOK TXOK
INTID
SJW
BRP
TSEG2
TSEG1
ID28-21
ID20-18
1
UUH
UUH
UUH
UUH
F70EH
LMLM0
F70FH
LMLM1
UUH
UUUU.
U000B
F7n0H
MCR0
F7n1H
MCR1
F7n2H
UAR0
F7n3H
UAR1
UUH
UUH
F7n4H
LAR0
UUH
F7n5H
LAR1
UUUU.
U000B
F7n6H
MCFG
UUUU.
UU00B
UUH
UUH
1
1
1
0
0
0
0
0
ID28-21
ID20-13
UUH
UUUU.
U000B
F70CH UMLM0
F70DH UMLM1
1
ID12-5
ID4-0
ID28-21
ID20-18
ID17-13
ID12-5
ID4-0
0
MSGVAL
TXIE
RXIE
INTPND
RMTPND
TXRQ
MSGLST
CPUUPD
NEWDAT
ID28-21
ID20-18
ID17-13
ID12-5
ID4-0
DLC
DIR
0
0
0
XTD
0
0
1) The notation “n“ (n= 1 to F) in the address definition defines the number of the related message object.
2) “X“ means that the value is undefined and the location is reserved. “U“ means that the value is unchanged
by a reset operation. “U“ values are undefined (as “X“) after a power-on reset operation
Semiconductor Group
2-10
Memory Organization
C505A
Table 2-3
Contents of the CAN Registers in numeric order of their addresses (cont’d) (C505CA only)
Addr.
Register Content Bit 7
after
n=1-FH
1)
Reset 2)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
F7n7H
DB0
XXH
.7
.6
.5
.4
.3
.2
.1
.0
F7n8H
DB1
XXH
.7
.6
.5
.4
.3
.2
.1
.0
F7n9H
DB2
XXH
.7
.6
.5
.4
.3
.2
.1
.0
F7nAH
DB3
XXH
.7
.6
.5
.4
.3
.2
.1
.0
F7nBH
DB4
XXH
.7
.6
.5
.4
.3
.2
.1
.0
F7nCH DB5
XXH
.7
.6
.5
.4
.3
.2
.1
.0
F7nDH DB6
XXH
.7
.6
.5
.4
.3
.2
.1
.0
F7nEH
XXH
.7
.6
.5
.4
.3
.2
.1
.0
DB7
1) The notation “n“ (n= 1 to F) in the address definition defines the number of the related message object.
2) “X“ means that the value is undefined and the location is reserved. “U“ means that the value is unchanged
by a reset operation. “U“ values are undefined (as “X“) after a power-on reset operation
Semiconductor Group
2-11
10-bit A/D Converter
C505A
3
A/D Converter
The C505A includes a high performance / high speed 10-bit A/D-Converter (ADC) with 8 analog
input channels. It operates with a successive approximation technique and uses self calibration
mechanisms for reduction and compensation of offset and linearity errors. The A/D converter
provides the following features:
–
–
–
–
–
–
–
8 multiplexed input channels (port 1), which can also be used as digital inputs/outputs
10-bit resolution
Single or continuous conversion mode
Internal start-of-conversion trigger capability
Interrupt request generation after each conversion
Using successive approximation conversion technique via a capacitor array
Built-in hidden calibration of offset and linearity errors
The externally applied reference voltage range has to be held on a fixed value within the
specifications. The main functional blocks of the A/D converter are shown in figure 3-1.
3.1
A/D Converter Operation
An internal start of a single A/D conversion is triggered by a write-to-ADDATL instruction. The start
procedure itself is independent of the value which is written to ADDATL. When single conversion
mode is selected (bit ADM=0) only one A/D conversion is performed. In continuous mode (bit
ADM=1), after completion of an A/D conversion a new A/D conversion is triggered automatically
until bit ADM is reset.
The busy flag BSY (ADCON0.4) is automatically set when an A/D conversion is in progress. After
completion of the conversion it is reset by hardware. This flag can be read only, a write has no effect.
The interrupt request flag IADC (IRCON.0) is set when an A/D conversion is completed.
The bits MX0 to MX2 in special function register ADCON0 and ADCON1 are used for selection of
the analog input channel. The bits MX0 to MX2 are represented in both registers ADCON0 and
ADCON1; however, these bits are present only once. Therefore, there are two methods of selecting
an analog input channel : If a new channel is selected in ADCON1 the change is automatically done
in the corresponding bits MX0 to MX2 in ADCON0 and vice versa.
Port 1 is a dual purpose input/output port. These pins can be used either for digital I/O functions or
as the analog inputs. If less than 8 analog inputs are required, the unused analog inputs at port 1
are free for digital I/O functions.
Semiconductor Group
3-1
10-bit A/D Converter
C505A
Internal
Bus
IEN1 (B8H)
EX6
EXEN2 SWDT
EX5
EX4
EX3 ECAN EADC
IRCON (C0H)
EXF2
TF2
IEX6 IEX5 IEX4 IEX3
SWI
IADC
P1ANA (90H)
EAN7 EAN6 EAN5 EAN4 EAN3 EAN2 EAN1 EAN0
ADCON1 (DCH)
ADCL1 ADCL0
–
MX2
MX1 MX0
BSY ADM MX2
MX1 MX0
–
–
ADCON0 (D8H)
BD
CLK
–
Single /
Continuous Mode
ADDATH ADDATL
(D9H) (DA )
H
.2
–
.3
–
.4
–
.5
–
A/D
.6
–
Converter
.7
–
.8
LSB
MSB
.1
Port 1
MUX
S&H
f OSC
Clock
Prescaler
÷32, 16, 8, 4
Conversion Clock fADC
Input Clock fIN
VAREF
VAGND
Start of
conversion
Internal
Bus
Write to ADDATL
Shaded bit locations are not used in ADC-functions.
Figure 3-1
Block Diagram of the A/D Converter
Semiconductor Group
3-2
10-bit A/D Converter
C505A
3.2
A/D Converter Registers
This section describes the bits/functions of all registers which are used by the A/D converter.
Special Function Register ADDATH (Address D9H)
Special Function Register ADDATL (Address DAH)
Bit No. MSB
7
MSB
D9H
.9
DAH
.1
Reset Value : 00H
Reset Value : 00XXXXXXB
6
5
4
3
2
1
LSB
0
.8
.7
.6
.5
.4
.3
.2
ADDATH
LSB
.0
–
–
–
–
–
–
ADDATL
The registers ADDATH and ADDATL hold the 10-bit conversion result in left justified data format.
The most significant bit of the 10-bit conversion result is bit 7 of ADDATH. The least significant bit
of the 10-bit conversion result is bit 6 of ADDATL. To get a 10-bit conversion result, both ADDAT
registers must be read. If an 8-bit conversion result is required, only the reading of ADDATH is
necessary. The data remains in ADDAT until it is overwritten by the next converted data. ADDAT
can be read or written under software control. lf the A/D converter of the C505A is not used, register
ADDATH can be used as an additional general purpose register.
Semiconductor Group
3-3
10-bit A/D Converter
C505A
Special Function Register ADCON0 (Address D8H)
Special Function Register ADCON1 (Address DCH)
Bit No. MSB
7
D8H
DCH
BD
Reset Value : 00H
Reset Value : 01XXX000B
LSB
0
6
5
4
3
2
1
CLK
–
BSY
ADM
MX2
MX1
MX0
ADCON0
–
–
–
MX2
MX1
MX0
ADCON1
ADCL1 ADCL0
The shaded bits are not used for A/D converter control.
Bit
Function
–
Reserved bits for future use
BSY
Busy flag
This flag indicates whether a conversion is in progress (BSY = 1). The flag is
cleared by hardware when the conversion is finished.
ADM
A/D conversion mode
When set, a continuous A/D conversion is selected. If cleared during a running
A/D conversion, the conversion is stopped at its end.
MX2 - MX0
A/D converter input channel select bits
Bits MX2-0 can be written or read either in ADCON0 or ADCON1. The channel
selection done by writing to ADCON 1(0) overwrites the selection in ADCON
0(1) when ADCON 1(0) is written after ADCON 0(1).
The analog inputs are selected according the following table :
MX2
0
0
0
0
1
1
1
1
Semiconductor Group
MX1
MX0
Selected Analog Input
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
P1.0 / AN0 / INT3 / CC0
P1.1 / AN1 / INT4 / CC1
P1.2 / AN2 / INT5 / CC2
P1.3 / AN3 / INT6 / CC3
P1.4 / AN4
P1.5 / AN5 / T2EX
P1.6 / AN6 / CLKOUT
P1.7 / AN7 / T2
3-4
10-bit A/D Converter
C505A
Bit
Function
ADCL1
ADCL0
A/D converter clock prescaler selection
ADCL1 and ADCL0 select the prescaler ratio for the A/D conversion clock
fADC. Depending on the clock rate fOSC of the C505A, fADC must be adjusted
in a way that the resulting conversion clock fADC is less than or equal to 2 MHz
(see section 3.3).
The prescaler ratio is selected according to the following table :
ADCL1
0
0
1
1
ADCL0
0
1
0
1
Prescaler Ratio
divide by 4
divide by 8 (default after reset)
divide by 16
divide by 32
Note :Generally, before entering the power-down mode, an A/D conversion in progress must be
stopped. If a single A/D conversion is running, it must be terminated by polling the BSY bit or
waiting for the A/D conversion interrupt. In continuous conversion mode, bit ADM must be
cleared and the last A/D conversion must be terminated before entering the power-down
mode.
A single A/D conversion is started by writing to SFR ADDATL with dummy data. A continuous
conversion is started under the following conditions :
– By setting bit ADM during a running single A/D conversion
– By setting bit ADM when at least one A/D conversion has occurred after the last reset
operation.
– By writing ADDATL with dummy data after bit ADM has been set before (if no A/D conversion
has occurred after the last reset operation).
When bit ADM is reset by software in continuous conversion mode, the just running A/D conversion
is stopped after its end.
Semiconductor Group
3-5
10-bit A/D Converter
C505A
The A/D converter interrupt is controlled by bits which are located in the SFRs IEN1 and IRCON.
Special Function Register IEN1 (Address B8H)
Special Function Register IRCON (Address C0H)
Bit No.
B8H
C0H
MSB
BFH
BEH
EXEN2 SWDT
BDH
BCH
BBH
Reset Value : 00H
Reset Value : 00H
BAH
EX6
EX5
EX4
EX3
B9H
LSB
B8H
ECAN EADC
C7H
C6H
C5H
C4H
C3H
C2H
C1H
C0H
EXF2
TF2
IEX6
IEX5
IEX4
IEX3
SWI
IADC
IEN1
IRCON
The shaded bits are not used for A/D converter control.
Bit
Function
EADC
Enable A/D converter interrupt
If EADC = 0, the A/D converter interrupt is disabled.
SWI
This bit can be set by software to generate an interrupt. The interrupt service
routine is at 004BH. This bit is cleared when the interrupt is processed. This
interrupt is enabled by setting bit IEN1.1(ECAN).
Semiconductor Group
3-6
10-bit A/D Converter
C505A
3.3
A/D Converter Clock Selection
The ADC uses two clock signals for operation : the conversion clock f ADC (=1/tADC) and the input
clock fIN (=1/tIN). fADC is derived from the C505A system clock f OSC which is applied at the XTAL
pins via the ADC clock prescaler as shown in figure 3-2. The input clock fIN is equal to fOSC The
conversion fADC clock is limited to a maximum frequency of 2 MHz. Therefore, the ADC clock
prescaler must be programmed to a value which assures that the conversion clock does not exceed
2 MHz. The prescaler ratio is selected by the bits ADCL1 and ADCL0 of SFR ADCON1.
The table in figure 3-2 shows the prescaler ratio which must be selected by ADCL1 and ADCL0 for
typical system clock rates. Up to 8 MHz system clock the prescaler ratio 4 is selected. Using a
system clock greater than 8 MHz and less than 16 MHz, the prescaler ratio of at least 8 must be
selected. A prescaler ratio of at least 16 must be selected when using a system clock greater than
16 MHz. A prescaler ratio of 32 can used for any of the above frequency ranges.
ADCL0
ADCL1
f OSC
÷ 32
÷ 16
÷8
MUX
Conversion Clock fADC
A/D
Converter
÷4
Input Clock fIN
Clock Prescaler
Condition :
fADC max = 2 MHz
MCU System Clock fIN
[MHz]
Rate (fOSC)
fIN = f
OSC =
1
CLP
Prescaler
Ratio
fADC
[MHz]
ADCL1
ADCL0
2 MHz
2
÷4
0.5
0
0
6 MHz
6
÷4
1.5
0
0
8 MHz
8
÷4
2
0
0
12 MHz
12
÷8
1.5
0
1
16 MHz
16
÷8
2
0
1
20 MHz
20
÷ 16
1.25
1
0
Figure 3-2
A/D Converter Clock Selection
The duration of an A/D conversion is a multiple of the period of the fIN clock signal. The calculation
of the A/D conversion time is shown in the next section.
Semiconductor Group
3-7
10-bit A/D Converter
C505A
3.4
A/D Conversion Timing
An A/D conversion is started by writing into the SFR ADDATL with dummy data. A write to SFR
ADDATL will start a new conversion even if a conversion is currently in progress. The conversion
begins with the next machine cycle, and the BSY flag in SFR ADCON0 will be set.
The A/D conversion procedure is divided into three parts :
– Sample phase (tS), used for sampling the analog input voltage.
– Conversion phase (tCO), used for the real A/D conversion (includes calibration).
– Write result phase (tWR), used for writing the conversion result into the ADDAT registers.
The total A/D conversion time is defined by t ADCC which is the sum of the two phase times t S and
tCO. The duration of the three phases of an A/D conversion is specified by their corresponding
timing parameter as shown in figure 3-3.
Result is written
into ADDAT
Start of an
AD conversion
BSY Bit
Sample
Phase
Conversion Phase
tS
tCO
Write
Result
tWR Phase
tADCC
t WR = t IN
A/D Conversion Time Cycle Time
tADCC = tS + tCO
PS = Prescaler value
Prescaler Ratio tS
(=PS)
tCO
tADCC
32
64 x tIN
320 x tIN
384 x tIN
16
32 x tIN
160 x tIN
192 x tIN
8
16 x tIN
80 x tIN
96 x tIN
4
8 x tIN
40 x tIN
48 x tIN
Figure 3-3
A/D Conversion Timing
Sample Time tS :
During this time the internal capacitor array is connected to the selected analog input channel and
is loaded with the analog voltage to be converted. The analog voltage is internally fed to a voltage
comparator. With beginning of the sample phase the BSY bit in SFR ADCON0 is set.
Semiconductor Group
3-8
10-bit A/D Converter
C505A
Conversion Time tCO :
During the conversion time the analog voltage is converted into a 10-bit digital value using the
successive approximation technique with a binary weighted capacitor network. During an A/D
conversion also a calibration takes place. During this calibration alternating offset and linearity
calibration cycles are executed (see also section 3.5). At the end of the calibration time the BSY bit
is reset and the IADC bit in SFR IRCON is set indicating an A/D converter interrupt condition.
Write Result Time tWR :
At the result phase the conversion result is written into the ADDAT registers.
Figure 3-4 shows how an A/D conversion is embedded into the microcontroller cycle scheme using
the relation 6 x t IN = 1 instruction cycle. It also shows the behaviour of the busy flag (BSY) and the
interrupt flag (IADC) during an A/D conversion.
Prescaler
Selection
ADCL1 ADCL0
MOV ADDATL,#0
Write result cycle
MOV A, ADDATL
1 instruction cycle
7
8
9
10
11
12
5
15
16
17
18
19
20
4
5
31
32
33
34
35
36
4
5
63
64
65
66
67
68
0
0
X-1
X
1
2
3
4
5
0
1
X-1
X
1
2
3
4
1
0
X-1
X
1
2
3
1
1
X-1
X
1
2
3
6
tADCC
Start of A/D
conversion cycle
A/D Conversion Cycle
Start of next conversion
(in continuous mode)
Write
ADDAT
Cont. conv.
Single conv.
BSY Bit
IADC Bit
First instr. of an
interrupt routine
Figure 3-4
A/D Conversion Timing in Relation to Processor Cycles
Depending on the selected prescaler ratio (see figure 3-2), four different relationships between
machine cycles and A/D conversion are possible. The A/D conversion is started when SFR
ADDATL is written with dummy data. This write operation may take one or two machine cycles. In
figure 3-4, the instruction MOV ADDATL,#0 starts the A/D conversion (machine cycle X-1 and X).
The total A/D conversion (sample, conversion, and calibration phase) is finished with the end of the
8th, 16th, 32nd, or 64th machine cycle after the A/D conversion start. In the next machine cycle the
conversion result is written into the ADDAT registers and can be read in the same cycle by an
instruction (e.g. MOV A,ADDATL). If continuous conversion is selected (bit ADM set), the next
conversion is started with the beginning of the machine cycle which follows the write result cycle.
Semiconductor Group
3-9
10-bit A/D Converter
C505A
The BSY bit is set at the beginning of the first A/D conversion machine cycle and reset at the
beginning of the write result cycle. If continuous conversion is selected, BSY is again set with the
beginning of the machine cycle which follows the write result cycle.
The interrupt flag IADC is set at the end of the A/D conversion. If the A/D converter interrupt is
enabled and the A/D converter interrupt is prioritized to be serviced immediately, the first instruction
of the interrupt service routine will be executed in the third machine cycle which follows the write
result cycle. IADC must be reset by software.
Depending on the application, typically there are three methods to handle the A/D conversion in the
C505A.
– Software delay
The machine cycles of the A/D conversion are counted and the program executes a software
delay (e.g. NOPs) before reading the A/D conversion result in the write result cycle. This is
the fastest method to get the result of an A/D conversion.
– Polling BSY bit
The BSY bit is polled and the program waits until BSY=0. Attention : a polling JB instruction
which is two machine cycles long, possibly may not recognize the BSY=0 condition during the
write result cycle in the continuous conversion mode.
– A/D conversion interrupt
After the start of an A/D conversion the A/D converter interrupt is enabled. The result of the
A/D conversion is read in the interrupt service routine. If other C505A interrupts are enabled,
the interrupt latency must be regarded. Therefore, this software method is the slowest method
to get the result of an A/D conversion.
Depending on the oscillator frequency of the C505A and the selected divider ratio of the conversion
clock prescaler the total time of an A/D conversion is calculated according figure 3-3 and table 31. Figure 3-5 on the next page shows the minimum A/D conversion time in relation to the oscillator
frequency fOSC. The minimum conversion time is 6 µs and can be achieved at fOSC of 8 or 16 MHz
(or whenever fADC = 2 MHz).
Table 4-1
A/D Conversion Time for Dedicated System Clock Rates
fOSC [MHz]
Prescaler
Ratio PS
fADC [MHz]
Sample Time
tS [µs]
Total Conversion
Time tADCC [µs]
2 MHz
÷4
0.5
4
24
6 MHz
÷4
1.5
1.33
8
8 MHz
÷4
2
1
6
12 MHz
÷8
1.5
1.33
8
16 MHz
÷8
2
1
6
20 MHz
÷ 16
1.25
1.6
9.6
Note : The prescaler ratios in table 3-1 are minimum values.
Semiconductor Group
3-10
10-bit A/D Converter
C505A
tADCC
[µs]
30
t ADCC min = 6 µs
20
10
5
÷4
2
4
÷8
6
8
10
12
÷ 16
14
16
Figure 3-5
Minimum A/D Conversion Time in Relation to System Clock
Semiconductor Group
3-11
18
20
fOSC
[MHz]
10-bit A/D Converter
C505A
3.5
A/D Converter Calibration
The C505A A/D converter includes hidden internal calibration mechanisms which assure a safe
functionality of the A/D converter according to the DC characteristics. The A/D converter calibration
is implemented in a way that a user program which executes A/D conversions is not affected by its
operation. Further, the user program has no control over the calibration mechanism. The calibration
itself executes two basic functions :
– Offset calibration
– Linearity calibration
: correction of offset errors of comparator and the capacitor network
: correction of the binary weighted capacitor network
The A/D converter calibration operates in two phases : calibration after a reset operation and
calibration at each A/D conversion. The calibration phases are controlled by a state machine in the
A/D converter. This state machine executes the calibration phases and stores the calibration results
dynamically in a small calibration RAM.
After a reset operation the A/D calibration is automatically started. This reset calibration phase
which takes 3328 fADC clocks, alternating offset and linearity calibration is executed. Therefore, at
8 MHz oscillator frequency and with the default after reset prescaler value of 4, a reset calibration
time of approx. 1.66 ms is reached. For achieving a proper reset calibration, the fADC prescaler
value must satisfy the condition fADC max ≤ 2 MHz. If this condition is not met at a specific oscillator
frequency with the default prescaler value after reset, the fADC prescaler must be adjusted
immediately after reset by setting bits ADCL1 and ADCL0 in SFR ADCON1 to a suitable value. It is
also recommended to have the proper voltages, as specified in the DC specifications, applied at the
VAREF and VAREF pins before the reset calibration has started.
After the reset calibration phase the A/D converter is calibrated according to its DC characteristics.
Nevertheless, during the reset calibration phase single or continuous A/D can be executed. In this
case it must be regarded that the reset calibration is interrupted and continued after the end of the
A/D conversion. Therefore, interrupting the reset calibration phase by A/D conversions extends the
total reset calibration time. If the specified total unadjusted error (TUE) has to be valid for an A/D
conversion, it is recommended to start the first A/D conversions after reset when the reset
calibration phase is finished. Depending on the oscillator frequency used, the reset calibration
phase can be possibly shortened by setting ADCL1 and ADCL0 (prescaler value) to its final value
immediately after reset.
After the reset calibration, a second calibration mechanism is initiated. This calibration is coupled
to each A/D conversion. With this second calibration mechanism alternatively offset and linearity
calibration values, stored in the calibration RAM, are always checked when an A/D conversion is
executed and corrected if required.
Semiconductor Group
3-12
10-bit A/D Converter
C505A
3.5.1 A/D Converter Analog Input Selection
The analog inputs are located at port 1. The corresponding pins have a port structure, which allows
to use them either as digital I/O pins or as analog inputs (see section 6.1.3.2). The analog input
function of these digital/analog port lines are selected via the register P1ANA. This register lies in
the mapped SFR area and can be accessed when bit RMAP in SFR SYSCON is set when writing
to its address (90H). If a specific bit location of P1ANA is set, the corresponding port line is
configured as a digital input. With a 0 in the bit location the port line operates as analog port.
Special Function Registers P1ANA (Address 90H)
Bit No. MSB
7
90H
EAN7
Reset Value : FFH
6
5
4
3
2
1
EAN6
EAN5
EAN4
EAN3
EAN2
EAN1
LSB
0
EAN0
P1ANA
Bit
Function
EAN7 - EAN0
Enable analog port 1 inputs
If EANx (x = 7-0) is cleared, port pin P1.x is enabled for operation as an
analog input. If EANx is set, port pin P1.x is enabled for digital I/O function
(default after reset).
Semiconductor Group
3-13
OTP Memory Operation
C505A
4
OTP Memory Operation
The C505A-4E is the OTP version in the C505A microcontroller with a 32K byte one-time
programmable (OTP) program memory. With the C505A-4E fast programming cycles are achieved
(1 byte in 100 µsec). Also several levels of OTP memory protection can be selected. The basic
functionality of the C505A-4E as microcontroller is identical to the C505A-L (romless part)
functionality.
4.1
Programming Configuration
During normal program execution the C505A-4E behaves like the C505A-L. For programming the
device, the C505A-4E must be put into the programming mode. This, typically, is done not in-system
but in a special programming hardware. In the programming mode the C505A-4E operates as a
slave device similar as an EPROM standalone memory device and must be controlled with address/
data information, control lines, and an external 11.5 V programming voltage.
In the programming mode port 0 provides the bidirectional data lines and port 2 is used for the
multiplexed address inputs. The upper address information at port 2 is latched with the signal PALE.
For basic programming mode selection the inputs RESET, PSEN, EA/VPP, ALE and PMSEL1/0 and
PSEL are used. Further, the inputs PMSEL1,0 are required to select the access types (e.g.
program/verify data, write lock bits, ....) in the programming mode. In programming mode VCC/VSS
and a clock signal at the XTAL pins must be applied to the C505A-4E. The 11.5 V external
programming voltage is input through the EA/VPP pin.
Figure 4-1 shows the pins of the C505A-4E which are required for controlling of the OTP
programming mode.
VCC
P2.0-7
VSS
Port 2
Port 0
P0.0-7
PALE
PMSEL0
PMSEL1
C505A-4E
C505CA-4E
RESET
XTAL1
XTAL2
PSEN
PSEL
Figure 4-1
Programming Mode Configuration
Semiconductor Group
EA / VPP
PROG
PRD
4-1
OTP Memory Operation
C505A
4.2
Pin Configuration
D4
D5
D6
D7
EA / VPP
N.C.
PROG
PSEN
A7
A6 / A14
A5 / A13
Figure 4-2 shows the detailed pin configuration of the C505A-4E in programming mode.
D3
D2
D1
D0
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
33 32 31 30 29 28 27 26 25 24 23
34
22
35
21
36
20
37
19
38
C505A-4E
C505CA-4E
39
40
18
17
16
41
15
42
14
43
13
44
2
3
4
5
6 7
8
12
9 10 11
N.C.
N.C.
N.C.
RESET
PMSEL0
N.C.
PMSEL1
PSEL
PRD
PALE
N.C.
1
Figure 4-2
OTP Programming Mode Pin Configuration (Top View)
Semiconductor Group
4-2
A4 / A12
A3 / A11
A2 / A10
A1 / A9
A0 / A8
VCC
VSS
XTAL1
XTAL2
N.C.
N.C.
OTP Memory Operation
C505A
4.3
Pin Definitions
The following figure 4-1 contains the functional description of all C505A-4E pins which are required
for OTP memory programming
Table 4-1
Pin Definitions and Functions of the C505A-4E in Programming Mode
Symbol
Pin Number I/O *) Function
P-MQFP-44
RESET
4
I
Reset
This input must be at static “1“ (active) level during the whole
programming mode.
PMSEL0
PMSEL1
5
7
I
I
Programming mode selection pins
These pins are used to select the different access modes in
programming mode. PMSEL1,0 must satisfy a setup time to the
rising edge of PALE. When the logic level of PMSEL1,0 is
changed, PALE must be at low level.
PMSEL1
PMSEL0
Access Mode
0
0
Reserved
0
1
Read signature bytes
1
0
Program/read lock bits
1
1
Program/read OTP memory byte
PSEL
8
I
Basic programming mode select
This input is used for the basic programming mode selection
and must be switched according figure 4-3.
PRD
9
I
Programming mode read strobe
This input is used for read access control for OTP memory read,
version byte read, and lock bit read operations.
PALE
10
I
Programming address latch enable
PALE is used to latch the high address lines. The high address
lines must satisfy a setup and hold time to/from the falling edge
of PALE. PALE must be at low level when the logic level of
PMSEL1,0 is changed.
XTAL2
14
O
XTAL2
Output of the inverting oscillator amplifier.
XTAL1
15
I
XTAL1
Input to the oscillator amplifier.
*) I = Input
O = Output
Semiconductor Group
4-3
OTP Memory Operation
C505A
Table 4-1
Pin Definitions and Functions of the C505A-4E in Programming Mode (cont’d)
Symbol
Pin Number I/O *) Function
P-MQFP-44
VSS
16
–
Circuit ground potential
must be applied in programming mode.
VCC
17
–
Power supply terminal
must be applied in programming mode.
P2.0-7
18-25
I
Address lines
P2.0-7 are used as multiplexed address input lines A0-A7 and
A8-A14. A8-A14 must be latched with PALE.
PSEN
26
I
Program store enable
This input must be at static “0“ level during the whole
programming mode.
PROG
27
I
Programming mode write strobe
This input is used in programming mode as a write strobe for
OTP memory program, and lock bit write operations During
basic programming mode selection a low level must be applied
to PROG.
EA/VPP
29
–
Programming voltage
This pin must be at 11.5 V (VPP) voltage level during
programming of an OTP memory byte or lock bit. During an
OTP memory read operation this pin must be at VIHx high level.
This pin is also used for basic programming mode selection. At
basic programming mode selection a low level must be applied
to EA/VPP.
P0.7-0
30-37
I/O
Data lines 0-7
During programming mode, data bytes are transferred via the
bidirectional D7-0 lines which are located at port 0.
N.C.
1-3, 6, 11-13, –
28, 38-44
Not Connected
These pins should not be connected in programming mode.
*) I = Input
O = Output
Semiconductor Group
4-4
OTP Memory Operation
C505A
4.4
Programming Mode Selection
The selection for the OTP programming mode can be separated into two different parts :
– Basic programming mode selection
– Access mode selection
With the basic programming mode selection the device is put into the mode in which it is possible
to access the OTP memory through the programming interface logic. Further, after selection of the
basic programming mode, OTP memory accesses are executed by using one of the access modes.
These access modes are OTP memory byte program/read, version byte read, and program/read
lock byte operations.
4.4.1 Basic Programming Mode Selection
The basic programming mode selection scheme is shown in figure 4-3.
5V
VCC
Clock
(XTAL1/XTAL2)
stable
RESET
“1“
PSEN
“0“
0,1
PMSEL1,0
“0“
PROG
PRD
“1“
PSEL
“0“
PALE
EA/VPP
0V
During this period signals
are not actively driven
Figure 4-3
Basic Programming Mode Selection
Semiconductor Group
4-5
VPP
VIH2
Ready for access
mode selection
OTP Memory Operation
C505A
The basic programming mode is selected by executing the following steps :
– With a stable Vcc a clock signal is applied to the XTAL pins; the RESET pin is set to “1“ level
and the PSEN pin is set to “0“ level.
– PROG, PALE, PMSEL1 and EA/VPP are set to “0“ level; PRD, PSEL, and PMSEL0 are set to
“1“ level.
– PSEL is switched from “1“ to “0“ level and thereafter PROG is switched to “1“ level.
– PMSEL1,0 can now be changed; after EA/VPP has been set to VIHx high level or to VPP the
OTP memory is ready for access.
The pins RESET and PSEN must stay at “1“ respectively “0“ static signal level during the whole
programming mode. With a falling edge of PSEL the logic state of PROG and EA/VPP is internally
latched. These two signals are now used as programming write pulse signal (PROG) and as
programming voltage input pin VPP. After the falling edge of PSEL, PSEL must stay at “0“ state
during all programming operations.
Note: If protection level 1 to 3 has been programmed (see section 4.6) and the programming mode
has been left, it is no more possible to enter the programming mode !
4.4.2 OTP Memory Access Mode Selection
When the C505A-4E has been put into the programming mode using the basic programming mode
selection, several access modes of the OTP memory programming interface are available. The
conditions for the different control signals of these access modes are listed in table 4-2.
Table 4-2
Access Modes Selection
Access Mode
EA/
VPP
Program OTP memory byte
VPP
Read OTP memory byte
VIHx
Program OTP lock bits
VPP
Read OTP lock bits
VIHx
H
Read OTP version byte
VIHx
H
PROG
PRD
PMSEL
Address
(Port 2)
Data
(Port 0)
1
0
H
H
H
A0-7
A8-14
D0-7
H
H
L
–
D1,D0 see
table 4-3
L
H
Byte addr.
of version byte
D0-7
H
The access modes from the table above are basically selected by setting the two PMSEL1,0 lines
to the required logic level. The PROG and PRD signal are the write and read strobe signal. Data is
transferred via port 0 and addresses are applied to port 2.
The following sections describes the details of the different access modes.
Semiconductor Group
4-6
OTP Memory Operation
C505A
4.5
Program / Read OTP Memory Bytes
The program/read OTP memory byte access mode is defined by PMSEL1,0 = 1,1. It is initiated
when the PMSEL1,0 = 1,1 is valid at the rising edge of PALE. With the falling edge of PALE the
upper addresses A8-A14 of the 15-bit OTP memory address are latched. After A8-A14 has been
latched, A0-A7 is put on the address bus (port 2). A0-A7 must be stable when PROG is low or PRD
is low. If subsequent OTP address locations are accessed with constant address information at the
high address lines A8-14, A8-A14 must only be latched once (page address mechanism).
Figure 4-4 shows a typical basic OTP memory programming cycle with a following OTP memory
read operation. In this example A0-A14 of the read operation are identical to A8-A14 of the
preceeding programming operation.
1, 1
PMSEL1,0
Port 2
A8A14
A0-A7
PALE
Port 0
D0-D7
D0-D7
min. 100 µs
min.
100 ns
PROG
PRD
Figure 4-4
Programming / Verify OTP Memory Access Waveform
If the address lines A8-A14 must be updated, PALE must be activated for the latching of the new A8A14 value. Control, address, and data information must only be switched when the PROG and PRD
signals are at high level. The PALE high pulse must always be executed if a different access mode
has been used prior to the actual access mode.
Semiconductor Group
4-7
OTP Memory Operation
C505A
Figure 4-5 shows a waveform example of the program/read mode access for several OTP memory
bytes. In this example OTP memory locations 3FDH to 400H are programmed. Thereafter, OTP
memory locations 400H and 3FDH are read.
PMSEL1,0
1, 1
PALE
3FD
Port 2
03
Port 0
3FE
3FF
FD
FE
FF
Data 1
Data 2
Data 3
400
04
00
Data 4
PROG
PRD
Figure 4-5
Typical OTP Memory Programming/Verify Access Waveform
Semiconductor Group
4-8
3FD
400
00
Data 4
03
FD
Data 1
OTP Memory Operation
C505A
4.6
Lock Bits Programming / Read
The C505A-4E has two programmable lock bits which, when programmed according table 4-3,
provide four levels of protection for the on-chip OTP code memory.
Table 4-3
Lock Bit Protection Types
Lock Bits at D1,D0
D1
D0
Protection Protection Type
Level
1
1
Level 0
The OTP lock feature is disabled. During normal operation of
the C505A-4E, the state of the EA pin is not latched on reset.
1
0
Level 1
During normal operation of the C505A-4E, MOVC instructions
executed from external program memory are disabled from
fetching code bytes from internal memory. EA is sampled and
latched on reset. An OTP memory read operation is only
possible according to OTP verification mode. Further
programming of the OTP memory is disabled (reprogramming
security).
0
1
Level 2
Same as level 1, but also OTP memory read operation using
OTP verification mode is disabled.
0
0
Level 3
Same as level 2; but additionally external code execution by
setting EA=low during normal operation of the C505A-4E is no
more possible.
External code execution, which is initiated by an internal
program (e.g. by an internal jump instruction above the OTP
memory boundary), is still possible.
Note : A 1 means that the lock bit is unprogrammed. 0 means that lock bit is programmed.
For a OTP verify operation at protection level 1, the C505A-4E must be put into the OTP verification
mode.
If a device is programmed with protection level 2 or 3, it is no longer possible to verify the OTP
content of a customer rejected (FAR) OTP device.
When a protection level has been activated by programming of the lock bits, the basic programming
mode must be left for activation of the protection mechanisms. This means, after the activation of a
protection level further OTP program/verify operations are still possible if the basic programming
mode is maintained.
The state of the lock bits can always be read if protection level 0 is selected. If protection level 1 to
3 has been programmed and the programming mode has been left, it is not possible to re-enter the
programming mode. In this case, the lock bits cannot be read anymore.
Figure 4-6 shows the waveform of a lock bit write/read access. For a simple drawing, the PROG
pulse is shortened. In reality, for lock bit programming, a 100µs PROG low pulse must be applied.
Semiconductor Group
4-9
OTP Memory Operation
C505A
PMSEL1,0
1, 0
PALE
Port 0
1,0
1,0
(D1,D0)
PROG
PRD
The example shows the programming and reading of a protection level 1.
Figure 4-6
Write/Read Lock Bit Waveform
Semiconductor Group
4-10
OTP Memory Operation
C505A
4.6.1 Access of Version Bytes
The C505A-4E and C505CA-4E provide three version bytes at address locations FC H, FDH, and
FEH. The information stored in the version bytes, is defined by the mask of each microcontroller
step, Therefore, the version bytes can be read but not written. The three Version Registers hold
information as manufacturer code, device type, and stepping code.
For reading of the version bytes the control lines must be used according table 4-2 and figure 4-7.
The address of the version byte must be applied at the port 1 address lines. PALE must not be
activated.
PMSEL1,0
0, 1
PALE
Port 2
Port 0
FC
FD
VR0
VR1
FE
VR2
PROG
PRD
Figure 4-7
Read Version Register(s) Waveform
Version bytes are typically used by programming systems for adapting the programming firmware
to specific device characteristics such as OTP size etc.
Note: The 3 version bytes are implemented in a way that they can be also be read during normal
program execution mode as a mapped register with bit RMAP in SFR SYSCON set. The
addresses of the version bytes in normal mode and programming mode are identical and
therefore they are located in the SFR address range.
The steppings of the C505A versions will contain the following version byte information :
Stepping
Version Byte 0 = VR0 Version Byte 1 = VR1 Version Byte 2 = VR2
(mapped addr. FCH) (mapped addr. FDH) (mapped addr. FEH)
ES-AA Steps of
C505A-4E and
C505CA-4E
C5H
05H
Note:
Future steppings of C505A would have a different version byte 2 content.
Semiconductor Group
4-11
11H
OTP Memory Operation
C505A
4.7
OTP Verification Mode
The OTP verification mode as shown in figure 4-8 is used to verify the contents of the OTP when
the protection level 1 has been set. The detailed timing characteristics of the OTP verification mode
are shown in the AC specifications (chapter 5).
RESET
6 CLP
ALE
1. ALE pulse
after reset
3 CLP
Latch
Data for
Addr. 0
Port 0
Latch
Latch
Data for
Addr. 1
Data for Ad.
X·16 -1
Data for
Addr. X·16
Latch
Data for Ad.
X·16 +1
Low : Verify Error
High : Verify ok
P3.5
Inputs : ALE = VSS
PSEN = VIH, EA = VIH2
RESET =
Figure 4-8
OTP Verification Mode
OTP verification mode is selected if the inputs PSEN, EA, and ALE are put to the specified logic
levels. With RESET going inactive, the OTP verification mode sequence is started. The C505A-4E
outputs an ALE signal with a period of 3 CLP and expects data bytes at port 0. The data bytes at port
0 are assigned to the OTP addresses in the following way :
1. Data Byte =
2. Data Byte =
3. Data Byte =
:
16. Data Byte =
:
content of OTP address 0000H
content of OTP address 0001H
content of OTP address 0002H
content of OTP address 000FH
The C505A-4E does not output any address information during the OTP verification mode. The first
data byte to be verified is always the byte which is assigned to the OTP address 0000H and must
be put onto the data bus with the falling edge of RESET. With each following ALE pulse the OTP
address pointer is internally incremented and the expected data byte for the next OTP address must
be delivered externally.
Between two ALE pulses the data at port 0 is latched (at 3 CLP after ALE rising edge) and compared
internally with the OTP content of the actual address. If a verify error is detected, the error condition
Semiconductor Group
4-12
OTP Memory Operation
C505A
is stored internally. After each 16th data byte the cumulated verify result (pass or fail) of the last 16
verify operations is output at P3.5. This means that P3.5 stays at static level (low for fail and high for
pass) during the time when the following 16 bytes are checked. In OTP verification mode, the
C505A-4E must be provided with a system clock at the XTAL pins.
Figure 4-9 shows an application example of an external circuitry which allows to verify the OTP,
with protection level 1, inside the C505A-4E in the OTP verification mode. With RESET going
inactive, the C505A-4E starts the OTP verify sequence. Its ALE is clocking a 15-bit address counter.
This counter generates the addresses for an external EPROM which is programmed with the
contents of the OTP. The verify detect logic typically displays the pass/fail information of the verify
operation. P3.5 can be latched with the falling edge of ALE.
When the last byte of the OTP has been handled, the C505A-4E starts generating a PSEN signal.
This signal or the CY signal of the address counter indicate to the verify detect logic the end of the
OTP verification.
P3.5
Verify
Detect
Logic
Carry
ALE
CLK
2K
15-Bit
Address
Counter
C505A-4E
A0-A14
S
&
&
RESET
Vcc
Port 0
Compare
Code
ROM
D0-D7
Vcc
EA
CS
PSEN
Figure 4-9
OTP Verification Mode - External Circuitry Example
Semiconductor Group
4-13
OE
Device Specifications
C505A
5
5.1
Device Specifications
Absolute Maximum Ratings
Ambient temperature under bias (TA) .............................................................. – 40 °C to + 125 °C
Storage temperature (TST)................................................................................– 65 °C to + 150 °C
Voltage on VCC pins with respect to ground (VSS) ............................................– 0.5 V to 6.5 V
Voltage on any pin with respect to ground ( VSS) ..............................................– 0.5 V to VCC + 0.5 V
Input current on any pin during overload condition..........................................– 10 mA to + 10 mA
Absolute sum of all input currents during overload condition ..........................| 100 mA |
Power dissipation.............................................................................................TBD
Note:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for longer
periods may affect device reliability. During overload conditions ( VIN > VCC or VIN < VSS) the
Voltage on VCC pins with respect to ground (VSS) must not exceed the values defined by the
absolute maximum ratings.
Semiconductor Group
5-1
Device Specifications
C505A
5.2
DC Characteristics
TA = 0 to 70 °C
TA = -40 to 85 °C
TA = -40 to 110 °C
TA = -40 to 125 °C
VCC = 5V +10%, -15%; VSS = 0 V
Parameter
Symbol
Limit Values
for the SAB- versions
for the SAF- versions
for the SAH- versions
for the SAK- versions
Unit Test Condition
min.
max.
0.2 VCC - 0.1 V
0.2 VCC - 0.3 V
0.2 VCC + 0.1 V
Input low voltages
all except EA, RESET
EA pin
RESET pin
VIL
VIL1
VIL2
– 0.5
– 0.5
– 0.5
Input high voltages
all except XTAL1, RESET
XTAL1 pin
RESET pin
VIH
VIH1
VIH2
0.2 VCC + 0.9 VCC + 0.5
0.7 VCC
VCC + 0.5
0.6 VCC
VCC + 0.5
V
V
V
–
–
–
Output low voltages
Ports 1, 2, 3, 4
Port 0, ALE, PSEN
VOL
VOL1
–
–
0.45
0.45
V
V
IOL = 1.6 mA 1)
IOL = 3.2 mA 1)
Output high voltages
Ports 1, 2, 3, 4
VOH
2.4
0.9 VCC
2.4
0.9 VCC
–
–
–
–
V
V
V
V
IOH = – 80 µA
IOH = – 10 µA
IOH = – 800 µA
IOH = – 80 µA 2)
IIL
– 10
– 70
µA
VIN = 0.45 V
ITL
– 65
– 650
µA
VIN = 2 V
Input leakage current
Port 0, AN0-7 (Port 1), EA
ILI
–
±1
µA
0.45 < VIN < VCC
Pin capacitance
CIO
–
10
pF
fc = 1 MHz,
TA = 25 °C
Overload current
IOV
–
±5
mA
Programming voltage
VPP
10.9
12.1
V
11.5 V ± 5% 5)
30
mA
5)
Port 0 in external bus mode,
ALE, PSEN
Logic 0 input current
Ports 1, 2, 3, 4
Logical 0-to-1 transition current
Ports 1, 2, 3, 4
VOH2
Supply current at EA/VCC
Notes see next page
Semiconductor Group
5-2
–
–
–
3) 4)
Device Specifications
C505A
Power Supply Current
Parameter
Symbol
Limit Values
Unit Test Condition
typ. 11) max.12)
C505A
Active Mode
12 MHz
20 MHz
ICC
ICC
TBD
TBD
TBD
TBD
mA
6)
Idle Mode
12 MHz
20 MHz
ICC
ICC
TBD
TBD
TBD
TBD
mA
7)
Active Mode with
12 MHz
slow-down enabled 20 MHz
ICC
ICC
TBD
TBD
TBD
TBD
mA
8)
Idle Mode with
12 MHz
slow-down enabled 20 MHz
ICC
ICC
TBD
TBD
TBD
TBD
mA
9)
Power down current
IPD
TBD
60
µA
VCC = 2..5.5 V 10)
Notes :
1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE
and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these
pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise
pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger,
or use an address latch with a schmitt-trigger strobe input.
2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VCC
specification when the address lines are stabilizing.
3) Overload conditions occur if the standard operating conditions are exceeded, ie. the voltage on any pin
exceeds the specified range (i.e. VOV > VCC + 0.5 V or VOV < VSS - 0.5 V). The supply voltage VCC and VSS must
remain within the specified limits. The absolute sum of input currents on all port pins may not exceed 50 mA.
4) Not 100% tested, guaranteed by design characterization.
5) Only valid in porgramming mode.
6) ICC (active mode) is measured with:
XTAL1 driven with tR /tF = 5 ns, 50% duty cycle , VIL = VSS + 0.5 V, VIH = VCC – 0.5 V; XTAL2 = N.C.;
EA = Port0 = RESET =VCC; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is
used (approx. 1 mA)
7) ICC (idle mode) is measured with all output pins disconnected and with all peripherals disabled;
XTAL1 driven with tR/tF = 5 ns, 50% duty cycle, VIL = VSS + 0.5 V, VIH = VCC – 0.5 V; XTAL2 = N.C.;
RESET = EA = VSS ; Port0 = VCC ; all other pins are disconnected;
8) ICC (active mode with slow-down mode) is measured : TBD
9) ICC (idle mode with slow-down mode) is measured : TBD
10) IPD (power-down mode) is measured under following conditions:
EA = Port 0 = VCC; RESET =VSS; XTAL2 = N.C.; XTAL1 = VCC; VAGND = VSS; VAREF = VCC;
all other pins are disconnected.
11) The typical ICC values are periodically measured at TA = +25 °C but not 100% tested.
12) The maximum ICC values are measured under worst case conditions (TA = 0 °C or -40 °C and VCC = 5.5 V)
Semiconductor Group
5-3
Device Specifications
C505A
C505A
ICC
[mA]
30
25
20
TBD
ICC max
ICC typ
15
10
5
4
8
12
16
ICC Diagram
C505A : Power Supply Current Calculation Formulas
Parameter
Symbol
Formula
Active mode
ICC typ
ICC max
TBD
TBD
Idle mode
ICC typ
ICC max
TBD
TBD
Active mode with
slow-down enabled
ICC typ
ICC max
TBD
TBD
Idle mode with
slow-down enabled
ICC typ
ICC max
TBD
TBD
Note : fosc is the oscillator frequency in MHz. ICC values are given in mA.
Semiconductor Group
5-4
20
fOSC
[MHz]
Device Specifications
C505A
5.3
A/D Converter Characteristics
VCC = 5 V + 10%, – 15%; VSS = 0 V
TA = 0 to 70 °C
TA = – 40 to 85 °C
TA = – 40 to 110 °C
TA = – 40 to 125 °C
for the SAB-C505A versions
for the SAF-C505A versions
for the SAH-C505A versions
for the SAK-C505A versions
4 V ≤ VAREF ≤ VCC + 0.1 V ; VSS – 0.1 V ≤ VAGND ≤ Vss + 0.2 V
Parameter
Symbol
Limit Values
min.
max.
Unit
Test Condition
1)
Analog input voltage
VAIN
VAGND
VAREF
V
Sample time
tS
–
64 x tIN
32 x tIN
16 x tIN
8 x tIN
ns
Prescaler ÷ 32
Prescaler ÷ 16
Prescaler ÷ 8
Prescaler ÷ 4 2)
Conversion cycle time
tADCC
–
384 x tIN
192 x tIN
96 x tIN
48 x tIN
ns
Prescaler ÷ 32
Prescaler ÷ 16
Prescaler ÷ 8
Prescaler ÷ 4 3)
Total unadjusted error
TUE
–
±2
LSB
VSS+0.5V ≤ VAIN ≤ VCC-0.5V 4)
–
±4
LSB
VSS < VAIN < VCC+0.5V
VCC - 0.5 V < VAIN < VCC
Internal resistance of
reference voltage source
RAREF
Internal resistance of
analog source
RASRC
ADC input capacitance
CAIN
tADC / 250 kΩ
–
tADC in [ns]
- 0.25
tS / 500
–
kΩ
tS in [ns]
pF
6)
- 0.25
–
50
Notes see next page.
Clock calculation table :
Clock Prescaler ADCL1, 0
Ratio
tADC
tS
tADCC
÷ 32
1
1
32 x tIN
64 x tIN
384 x tIN
÷ 16
1
0
16 x tIN
32 x tIN
192 x tIN
÷8
0
1
8 x tIN
16 x tIN
96 x tIN
÷4
0
0
4 x tIN
8 x tIN
48 x tIN
Further timing conditions : tADC min = 500 ns
tIN = 1 / fOSC = tCLP
Semiconductor Group
5) 6)
5-5
2) 6)
4)
Device Specifications
C505A
Notes:
1) VAIN may exeed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in
these cases will be X000H or X3FFH, respectively.
2) During the sample time the input capacitance CAIN must be charged/discharged by the external source. The
internal resistance of the analog source must allow the capacitance to reach their final voltage level within tS.
After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result.
3) This parameter includes the sample time tS, the time for determining the digital result and the time for the
calibration. Values for the conversion clock tADC depend on programming and can be taken from the table on
the previous page.
4) TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VCC = 4.9 V. It is guaranteed by design characterization for all
other voltages within the defined voltage range.
If an overload condition occurs on maximum 2 unused analog input pins and the absolute sum of input overload
currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB is
permissible.
5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
resistance of the reference source must allow the capacitance to reach their final voltage level within the
indicated time. The maximum internal resistance results from the programmed conversion timing.
6) Not 100% tested, but guaranteed by design characterization.
Semiconductor Group
5-6
Device Specifications
C505A
5.4
AC Characteristics (12 MHz, 0.5 Duty Cycle)
TA = 0 to 70 °C
TA = -40 to 85 °C
TA = -40 to 110 °C
TA = -40 to 125 °C
VCC = 5V +10%, -15%; VSS = 0 V
for the SAB-C505A versions
for the SAF-C505A versions
for the SAH-C505A versions
for the SAK-C505A versions
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)
Program Memory Characteristics
Parameter
Symbol
Limit Values
Unit
12 MHz clock
Variable Clock
0.5 Duty Cycle 1/CLP = 2 MHz to 12 MHz
min.
max.
min.
max.
ALE pulse width
tLHLL
43
–
CLP - 40
–
ns
Address setup to ALE
tAVLL
17
–
CLP/2 - 25
–
ns
Address hold after ALE
tLLAX
17
–
CLP/2 - 25
–
ns
ALE to valid instruction in
tLLIV
–
80
–
2 CLP - 87
ns
ALE to PSEN
tLLPL
22
–
CLP/2 - 20
–
ns
PSEN pulse width
tPLPH
95
–
3/2 CLP
- 30
–
ns
PSEN to valid instruction in
tPLIV
–
60
–
3/2 CLP
- 65
ns
Input instruction hold after PSEN
tPXIX
0
–
0
–
ns
Input instruction float after PSEN
tPXIZ *)
–
32
–
CLP/2 - 10
ns
Address valid after PSEN
tPXAV
37
–
CLP/2 - 5
–
ns
Address to valid instruction in
tAVIV
–
148
–
5/2 CLP
- 60
ns
Address float to PSEN
tAZPL
0
–
0
–
ns
*)
*)
Interfacing the C505A to devices with float times up to 37 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.
Semiconductor Group
5-7
Device Specifications
C505A
AC Characteristics (12 MHz, 0.5 Duty Cycle, cont’d)
External Data Memory Characteristics
Parameter
Symbol
Limit Values
12 MHz clock
0.5 Duty Cycle
Unit
Variable Clock
1/CLP = 2 MHz to 12 MHz
min.
max.
min.
max.
RD pulse width
tRLRH
180
–
3 CLP - 70
–
ns
WR pulse width
tWLWH
180
–
3 CLP - 70
–
ns
Address hold after ALE
tLLAX2
56
–
CLP - 27
–
ns
RD to valid data in
tRLDV
–
118
–
5/2 CLP- 90
ns
Data hold after RD
tRHDX
0
–
0
–
ns
Data float after RD
tRHDZ
–
63
–
CLP - 20
ns
ALE to valid data in
tLLDV
–
200
–
4 CLP - 133
ns
Address to valid data in
tAVDV
–
220
–
9/2 CLP - 155 ns
ALE to WR or RD
tLLWL
75
175
3/2 CLP - 50
3/2 CLP + 50 ns
Address valid to WR
tAVWL
70
–
2 CLP - 97
–
ns
WR or RD high to ALE high
tWHLH
17
67
CLP/2 - 25
CLP/2 + 25
ns
Data valid to WR transition
tQVWX
5
–
CLP/2 - 37
–
ns
Data setup before WR
tQVWH
170
–
7/2 CLP - 122 –
ns
Data hold after WR
tWHQX
15
–
CLP/2 - 27
–
ns
Address float after RD
tRLAZ
–
0
–
0
ns
External Clock Drive Characteristics
Parameter
Symbol
Limit Values
Unit
Variable Clock
Freq. = 2 MHz to 12 MHz
min.
max.
Oscillator period
CLP
83.3
500
ns
High time
TCLH
20
CLP-TCLL
ns
Low time
TCLL
20
CLP-TCLH
ns
Rise time
tR
–
12
ns
Fall time
tF
–
12
ns
Oscillator duty cycle
DC
0.5
0.5
–
Semiconductor Group
5-8
Device Specifications
C505A
5.5
AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle)
TA = 0 to 70 °C
TA = -40 to 85 °C
VCC = 5V +10%, -15%; VSS = 0 V
for the SAB-C505A versions
for the SAF-C505A versions
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)
Program Memory Characteristics
Parameter
Symbol
Limit Values
Unit
16-MHz clock
Variable Clock
Duty Cycle 1/CLP= 2 MHz to 16 MHz
0.4 to 0.6
min.
max.
min.
max.
ALE pulse width
tLHLL
48
–
CLP - 15
–
ns
Address setup to ALE
tAVLL
10
–
TCLHmin -15
–
ns
Address hold after ALE
tLLAX
10
–
TCLHmin -15 –
ns
ALE to valid instruction in
tLLIV
–
75
–
2 CLP - 50
ns
ALE to PSEN
tLLPL
10
–
TCLLmin -15
–
ns
PSEN pulse width
tPLPH
73
–
CLP+
TCLHmin -15
–
ns
PSEN to valid instruction in
tPLIV
–
38
–
CLP+
ns
TCLHmin- 50
Input instruction hold after PSEN
tPXIX
0
–
0
–
ns
Input instruction float after PSEN
tPXIZ *)
–
15
–
TCLLmin -10
ns
Address valid after PSEN
tPXAV
20
–
TCLLmin - 5
–
ns
Address to valid instruction in
tAVIV
–
95
–
2 CLP +
TCLHmin -55
ns
Address float to PSEN
tAZPL
-5
–
-5
–
ns
*)
*)
Interfacing the C505A to devices with float times up to 20 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.
Semiconductor Group
5-9
Device Specifications
C505A
AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle, cont’d)
External Data Memory Characteristics
Parameter
Symbol
Limit Values
16-MHz clock
Duty Cycle
0.4 to 0.6
Unit
Variable Clock
1/CLP= 2 MHz to 16 MHz
min.
max.
min.
max.
RD pulse width
tRLRH
158
–
3 CLP - 30
–
ns
WR pulse width
tWLWH
158
–
3 CLP - 30
–
ns
Address hold after ALE
tLLAX2
48
–
CLP - 15
–
ns
RD to valid data in
tRLDV
–
100
–
2 CLP+
TCLHmin - 50
ns
Data hold after RD
tRHDX
0
–
0
–
ns
Data float after RD
tRHDZ
–
51
–
CLP - 12
ns
ALE to valid data in
tLLDV
–
200
–
4 CLP - 50
ns
Address to valid data in
tAVDV
–
200
–
4 CLP +
TCLHmin -75
ns
ALE to WR or RD
tLLWL
73
103
CLP +
TCLLmin - 15
CLP+
TCLLmin+ 15
ns
Address valid to WR
tAVWL
95
–
2 CLP - 30
–
ns
WR or RD high to ALE high
tWHLH
10
40
TCLHmin - 15
TCLHmin + 15
ns
Data valid to WR transition
tQVWX
5
–
TCLLmin - 20
–
ns
Data setup before WR
tQVWH
163
–
3 CLP +
TCLLmin - 50
–
ns
Data hold after WR
tWHQX
5
–
TCLHmin - 20
–
ns
Address float after RD
tRLAZ
–
0
–
0
ns
Semiconductor Group
5-10
Device Specifications
C505A
AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle, cont’d)
External Clock Drive Characteristics
Parameter
Symbol
CPU Clock = 16 MHz
Duty Cycle 0.4 to 0.6
Variable CPU Clock
1/CLP = 2 to 16 MHz
min.
max.
min.
max.
Unit
Oscillator period
CLP
62.5
62.5
62.5
500
ns
High time
TCLH
25
–
25
CLP - TCLL
ns
Low time
TCLL
25
–
25
CLP - TCLH
ns
Rise time
tR
–
10
–
10
ns
Fall time
tF
–
10
–
10
ns
Oscillator duty cycle
DC
0.4
0.6
25 / CLP
1 - 25 / CLP
–
Clock cycle
TCL
25
37.5
CLP * DCmin
CLP * DCmax ns
Note: The 16 MHz values in the tables are given as an example for a typical duty cycle variation of
the oscillator clock from 0.4 to 0.6.
Semiconductor Group
5-11
Device Specifications
C505A
5.6
AC Characteristics (20 MHz, 0.5 Duty Cycle)
TA = 0 to 70 °C
TA = -40 to 85 °C
VCC = 5V +10%, -15%; VSS = 0 V
for the SAB-C505A versions
for the SAF-C505A versions
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)
Program Memory Characteristics
Parameter
Symbol
Limit Values
Unit
20 MHz clock
Variable Clock
0.5 Duty Cycle 1/CLP = 2 MHz to 20 MHz
min.
max.
min.
max.
ALE pulse width
tLHLL
35
–
CLP - 15
–
ns
Address setup to ALE
tAVLL
10
–
CLP/2 - 15
–
ns
Address hold after ALE
tLLAX
10
–
CLP/2 - 15
–
ns
ALE to valid instruction in
tLLIV
–
55
–
2 CLP - 45
ns
ALE to PSEN
tLLPL
10
–
CLP/2 - 15
–
ns
PSEN pulse width
tPLPH
60
–
3/2 CLP
- 15
–
ns
PSEN to valid instruction in
tPLIV
–
25
–
3/2 CLP
- 50
ns
Input instruction hold after PSEN
tPXIX
0
–
0
–
ns
Input instruction float after PSEN
tPXIZ *)
–
20
–
CLP/2 - 5
ns
Address valid after PSEN
tPXAV *)
20
–
CLP/2 - 5
–
ns
Address to valid instruction in
tAVIV
–
65
–
5/2 CLP
- 60
ns
Address float to PSEN
tAZPL
-5
–
-5
–
ns
*)
Interfacing the C505A to devices with float times up to 20 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.
Semiconductor Group
5-12
Device Specifications
C505A
AC Characteristics (20 MHz, 0.5 Duty Cycle, cont’d)
External Data Memory Characteristics
Parameter
Symbol
Limit Values
20 MHz clock
0.5 Duty Cycle
Unit
Variable Clock
1/CLP = 2 MHz to 20 MHz
min.
max.
min.
max.
RD pulse width
tRLRH
120
–
3 CLP - 30
–
ns
WR pulse width
tWLWH
120
–
3 CLP - 30
–
ns
Address hold after ALE
tLLAX2
35
–
CLP - 15
–
ns
RD to valid data in
tRLDV
–
75
–
5/2 CLP- 50
ns
Data hold after RD
tRHDX
0
–
0
–
ns
Data float after RD
tRHDZ
–
38
–
CLP - 12
ns
ALE to valid data in
tLLDV
–
150
–
4 CLP - 50
ns
Address to valid data in
tAVDV
–
150
–
9/2 CLP - 75
ns
ALE to WR or RD
tLLWL
60
90
3/2 CLP - 15
3/2 CLP + 15 ns
Address valid to WR
tAVWL
70
–
2 CLP - 30
–
ns
WR or RD high to ALE high
tWHLH
10
40
CLP/2 - 15
CLP/2 + 15
ns
Data valid to WR transition
tQVWX
5
–
CLP/2 - 20
–
ns
Data setup before WR
tQVWH
125
–
7/2 CLP - 50
–
ns
Data hold after WR
tWHQX
5
–
CLP/2 - 20
–
ns
Address float after RD
tRLAZ
–
0
–
0
ns
External Clock Drive Characteristics
Parameter
Symbol
Limit Values
Unit
Variable Clock
Freq. = 2 MHz to 20 MHz
min.
max.
Oscillator period
CLP
50
500
ns
High time
TCLH
15
CLP-TCLL
ns
Low time
TCLL
15
CLP-TCLH
ns
Rise time
tR
–
10
ns
Fall time
tF
–
10
ns
Oscillator duty cycle
DC
0.5
0.5
–
Semiconductor Group
5-13
Device Specifications
C505A
Program Memory Read Cycle
Semiconductor Group
5-14
Device Specifications
C505A
Data Memory Read Cycle
Semiconductor Group
5-15
Device Specifications
C505A
Data Memory Write Cycle
tR
TCL H
tF
0.7 V CC
0.2 V CC - 0.1
TCL L
CLP
External Clock Drive on XTAL1
Semiconductor Group
5-16
MCT03310
Device Specifications
C505A
5.7
OTP Memory Characteristics
5.7.1 Programming Mode Timing Characteristics
VCC = 5 V ± 10 %; VPP = 11.5 V ± 5 %;
TA = 25 °C ± 10 °C
Parameter
Symbol
Limit Values
min.
max.
Unit
PALE pulse width
tPAW
35
–
PMSEL setup to PALE rising edge
tPMS
10
–
Address setup to PALE, PROG, or PRD
falling edge
tPAS
10
–
ns
Address hold after PALE, PROG, or PRD
falling edge
tPAH
10
–
ns
Address, data setup to PROG or PRD
tPCS
100
–
ns
Address, data hold after PROG or PRD
tPCH
0
–
ns
PMSEL setup to PROG or PRD
tPMS
10
–
ns
PMSEL hold after PROG or PRD
tPMH
10
–
ns
PROG pulse width
tPWW
100
–
µs
PRD pulse width
tPRW
100
–
ns
Address to valid data out
tPAD
–
75
ns
PRD to valid data out
tPRD
–
20
ns
Data hold after PRD
tPDH
0
–
ns
Data float after PRD
tPDF
–
20
ns
PROG high between two consecutive PROG tPWH1
low pulses
1
–
µs
PRD high between two consecutive PRD low tPWH2
pulses
100
XTAL clock period
tCLKP
83.3
Semiconductor Group
5-17
ns
ns
500
ns
Device Specifications
C505A
tPAW
PALE
tPMS
H, H
PMSEL1,0
tPAS
Port 2
tPAH
A0-7
A8-14
Port 0
D0-7
tPWW
tPWH
PROG
tPCS
tPCH
Notes : PRD must be high during a programming write cycle
Programming Code Byte - Write Cycle Timing
Semiconductor Group
5-18
Device Specifications
C505A
tPAW
PALE
tPMS
H, H
PMSEL1,0
tPAS
tPAH
A0-7
A8-14
Port 2
tPAD
tPDH
Port 0
D0-7
tPDF
tPRD
PRD
tPWH
tPCS
tPRW
Notes : PROG must be high during a programming read cycle
Verify Code Byte - Read Cycle Timing
Semiconductor Group
5-19
tPCH
Device Specifications
C505A
H, L
PMSEL1,0
Port 0
H, L
D0, D1
D0, D1
tPCH
tPCS
tPMS
tPMH
PROG
tPRD
tPDH
tPMS
tPWW
tPMH
PRD
tPRW
Note : PALE should be low during a lock bit read/write cycle
Lock Bit Access Timing
PMSEL1,0
L, H
e.g. FDH
Port 2
tPCH
D0-7
Port 0
tPCS
tPMS
tPDH
tPRD
tPDF
tPMH
PRD
tPRW
Note : PROG must be high during a programming read cycle
Version Registers - Read Timing
Semiconductor Group
5-20
tPDF
Device Specifications
C505A
5.7.2 OTP Verification Mode Characteristics
Parameter
Symbol
Limit Values
Unit
min.
typ
max.
ALE pulse width
tAWD
–
CLP
–
ns
ALE period
tACY
–
6 CLP
–
ns
Data valid after ALE
tDVA
–
–
2 CLP
ns
Data stable after ALE
tDSA
4 CLP
–
–
ns
P3.5 setup to ALE low
tAS
–
–
ns
Oscillator frequency
1/ CLP
4
TCLH
–
6
MHz
OTP Verification Mode
Note: This mode cannot be entered into if OTP protection levels of 1 to 3 are programmed.
Semiconductor Group
5-21
Device Specifications
C505A
AC Inputs during testing are driven at VCC - 0.5 V for a logic ’1’ and 0.45 V for a logic ’0’.
Timing measurements are made at VIHmin for a logic ’1’ and VILmax for a logic ’0’.
AC Testing: Input, Output Waveforms
For timing purposes a port pin is no longer floating when a 100 mV
change from load voltage occurs and begins to float when a 100 mV change from the loaded
VOH/VOL level occurs.
AC Testing : Float Waveforms
Crystal Oscillator Mode
Driving from External Source
C
XTAL2
N.C.
XTAL2
2 - 20
MHz
C
XTAL1
XTAL1
External Oscillator
Signal
Crystal Mode : C = 20 pF ± 10 pF (incl. stray capacitance)
Recommended Oscillator Circuits for Crystal Oscillator
Semiconductor Group
5-22
Device Specifications
C505A
5.8
Package Information
GPM05622
Plastic Package, P-MQFP-44-2 (SMD)
(Plastic Metric Quad Flat Pack)
Dimensions in mm
P-MQFP-44-2 Outline
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Semiconductor Group
5-23
Introduction
C505A
6
CCH3 . . . . . . . . . . . . . . . . . . . . . . . 2-5, 2-8
CCL1 . . . . . . . . . . . . . . . . . . . . . . . . 2-5, 2-8
CCL2 . . . . . . . . . . . . . . . . . . . . . . . . 2-5, 2-8
CCL3 . . . . . . . . . . . . . . . . . . . . . . . . 2-5, 2-8
CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9
CLKOUT . . . . . . . . . . . . . . . . . . . . . . . . .2-7
CMOD . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
COCAH0 . . . . . . . . . . . . . . . . . . . . . . . . .2-8
COCAH1 . . . . . . . . . . . . . . . . . . . . . . . . .2-8
COCAH2 . . . . . . . . . . . . . . . . . . . . . . . . .2-8
COCAH3 . . . . . . . . . . . . . . . . . . . . . . . . .2-8
COCAL0 . . . . . . . . . . . . . . . . . . . . . . . . .2-8
COCAL1 . . . . . . . . . . . . . . . . . . . . . . . . .2-8
COCAL2 . . . . . . . . . . . . . . . . . . . . . . . . .2-8
COCAL3 . . . . . . . . . . . . . . . . . . . . . . . . .2-8
CPUUPD . . . . . . . . . . . . . . . . . . . . . . . .2-10
CR . . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-10
CRCH . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5
CRCL . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5
CSWO . . . . . . . . . . . . . . . . . . . . . . . 2-3, 2-8
CY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
Index
Note: Bold page numbers refer to the main definition
part of SFRs or SFR bits.
A
A/D converter . . . . . . . . . . . . . . . .3-1–3-13
Analog input pin selection . . . . . . . . 3-13
Block diagram . . . . . . . . . . . . . . . . . . 3-2
Calibration mechanisms . . . . . . . . . 3-12
Clock selection . . . . . . . . . . . . . . . . . . 3-7
Conversion time calculation . . . . . . . 3-10
Conversion timing . . . . . . . . . . . . . . . 3-8
General operation . . . . . . . . . . . . . . . 3-1
Registers . . . . . . . . . . . . . . . . . . .3-3–3-6
System clock relationship . . . . . . . . . 3-9
A/D converter characteristics . . . . .5-5–5-6
Absolute maximum ratings . . . . . . . . . . 5-1
AC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
AC characteristics . . . . . . . . . . . . .5-7–5-13
12 MHz Timing . . . . . . . . . . . . . . .5-7–5-8
16 MHz Timing . . . . . . . . . . . . . .5-9–5-11
20 MHz Timing . . . . . . . . . . . . . 5-12–5-13
AC Testing
Float waveforms . . . . . . . . . . . . . . . 5-22
Input/output waveforms . . . . . . . . . . 5-22
ACC . . . . . . . . . . . . . . . . . . . . . . . . .2-4, 2-9
ADCL1 . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
ADCL1-0 . . . . . . . . . . . . . . . . . . . . . . . . 3-5
ADCON0 . . . . . . . . . . . . . 2-4, 2-5, 2-9, 3-4
ADCON1 . . . . . . . . . . . . . . . . . 2-4, 2-9, 3-4
ADDATH . . . . . . . . . . . . . . . . . 2-4, 2-9, 3-3
ADDATL . . . . . . . . . . . . . . . . . 2-4, 2-9, 3-3
ADM . . . . . . . . . . . . . . . . . . . . . . . .2-9, 3-4
D
DB0 . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-11
DB1 . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-11
DB2 . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-11
DB3 . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-11
DB4 . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-11
DB5 . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-11
DB6 . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-11
DB7 . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-11
DC characteristics . . . . . . . . . . . . . . 5-2–5-3
Device Characteristics . . . . . . . . . 5-1–5-23
DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
DLC . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
DPH . . . . . . . . . . . . . . . . . . . . . . . . 2-4, 2-7
DPL . . . . . . . . . . . . . . . . . . . . . . . . . 2-4, 2-7
DPSEL . . . . . . . . . . . . . . . . . . . . . . 2-4, 2-7
B
B . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4, 2-9
BD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
BOFF . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
BRP . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
BSY . . . . . . . . . . . . . . . . . . . . . . . . .2-9, 3-4
BTR0 . . . . . . . . . . . . . . . . . . . . . . .2-6, 2-10
BTR1 . . . . . . . . . . . . . . . . . . . . . . .2-6, 2-10
C
C/T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
CCE . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
CCEN . . . . . . . . . . . . . . . . . . . . . . .2-5, 2-8
CCH1 . . . . . . . . . . . . . . . . . . . . . . . .2-5, 2-8
CCH2 . . . . . . . . . . . . . . . . . . . . . . . .2-5, 2-8
Semiconductor Group
6-1
E
EA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
EADC . . . . . . . . . . . . . . . . . . . . . . . 2-8, 3-6
EALE . . . . . . . . . . . . . . . . . . . . . . . . 1-8, 2-8
EAN0 . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
EAN1 . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
EAN2 . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
EAN3 . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
EAN4 . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
EAN5 . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
Introduction
C505A
EAN6 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
EAN7 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
EAN7-0 . . . . . . . . . . . . . . . . . . . . . . . . 3-13
ECAN . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
EIE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
ES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
ET0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
ET1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
ET2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
EWPD . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
EWRN . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
EX0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
EX1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
EX3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
EX4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
EX5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
EX6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
EXEN2 . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
EXF2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
IEX4 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
IEX5 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
IEX6 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
INT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
INT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
INT4 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
INT5 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
INTID . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
INTPND . . . . . . . . . . . . . . . . . . . . . . . .2-10
IP0 . . . . . . . . . . . . . . . . . . . . . 2-4, 2-5, 2-7
IP1 . . . . . . . . . . . . . . . . . . . . . . . . . 2-4, 2-8
IR . . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-10
IRCON . . . . . . . . . . . . . . . . . . 2-4, 2-8, 3-6
IT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
IT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
L
LAR0 . . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-10
LAR1 . . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-10
LEC0 . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
LEC1 . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
LEC2 . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
LGML0 . . . . . . . . . . . . . . . . . . . . . 2-6, 2-10
LGML1 . . . . . . . . . . . . . . . . . . . . . 2-6, 2-10
LMLM0 . . . . . . . . . . . . . . . . . . . . . 2-6, 2-10
LMLM1 . . . . . . . . . . . . . . . . . . . . . 2-6, 2-10
Logic symbol . . . . . . . . . . . . . . . . . . . . . .1-3
F
F0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . .
Functional units . . . . . . . . . . . . . . . . . . .
2-8
2-8
1-2
1-1
G
GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
GF0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
GF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
GMS0 . . . . . . . . . . . . . . . . . . . . . .2-6, 2-10
GMS1 . . . . . . . . . . . . . . . . . . . . . .2-6, 2-10
M
M0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
M1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
MCFG . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-10
MCR0 . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-10
MCR1 . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-10
Memory organization . . . . . . . . . . . . . . .2-1
Data memory . . . . . . . . . . . . . . . . . . . .2-2
General purpose registers . . . . . . . . . .2-2
Memory map . . . . . . . . . . . . . . . . . . . .2-1
Program memory . . . . . . . . . . . . . . . .2-2
MSGLST . . . . . . . . . . . . . . . . . . . . . . . .2-10
MSGVAL . . . . . . . . . . . . . . . . . . . . . . . .2-10
MX0 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9
MX1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9
MX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9
MX2-0 . . . . . . . . . . . . . . . . . . . . . . . . . . .3-4
I
I3FR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
IADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
ID12 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
ID17 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
ID20 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
ID28 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
ID4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
IDLE . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
IDLS . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
IE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
IE0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
IE1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
IEN0 . . . . . . . . . . . . . . . . . . . . 2-4, 2-5, 2-7
IEN1 . . . . . . . . . . . . . . . . 2-4, 2-5, 2-8, 3-6
IEX3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Semiconductor Group
6-2
N
NEWDAT . . . . . . . . . . . . . . . . . . . . . . .2-10
Introduction
C505A
O
SCON . . . . . . . . . . . . . . . . . . . 2-4, 2-5, 2-7
SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
SIE . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
SJW . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
SM0 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
SM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
SM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
SMOD . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
SP . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4, 2-7
Special Function Registers . . . . . . . . . . .2-3
Access with RMAP . . . . . . . . . . . . . . .2-3
CAN registers - address ordered
2-10–2-11
Table - address ordered . . . . . . . 2-7–2-9
Table - functional order . . . . . . . . 2-4–2-6
SR . . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 2-10
SRELH . . . . . . . . . . . . . . . . . . . . . . 2-5, 2-8
SRELL . . . . . . . . . . . . . . . . . . . . . . 2-5, 2-7
SWDT . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
SWI . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
SYSCON . . . . . . . . . . . . . . . . . 2-3, 2-4, 2-8
OTP memory . . . . . . . . . . . . . . . . .4-1–4-13
Basic Mode Selection . . . . . . . . . . . . 4-5
Pin Configuration . . . . . . . . . . . . . . . . 4-1
Program/read operation . . . . . . . . . . . 4-7
OTP Protection
Protected Verification Mode . . . . . . . 4-12
Verification example . . . . . . . . . . . . 4-13
Verification timing . . . . . . . . . . . . . . 4-12
OV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
OWDS . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
P
P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
P0 . . . . . . . . . . . . . . . . . . . . . . . . . .2-4, 2-7
P1 . . . . . . . . . . . . . . . . . . . . . . . . . .2-4, 2-7
P1ANA . . . . . . . . . . . . . . . . . . 2-4, 2-7, 3-13
P2 . . . . . . . . . . . . . . . . . . . . . . . . . .2-4, 2-7
P3 . . . . . . . . . . . . . . . . . . . . . . . . . .2-4, 2-8
P4 . . . . . . . . . . . . . . . . . . . . . . . . . .2-4, 2-9
Package information . . . . . . . . . . . . . . 5-23
PCON . . . . . . . . . . . . . . . . . . . . . . .2-5, 2-7
PCON1 . . . . . . . . . . . . . . . . . . . . . .2-5, 2-7
PDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
PDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Pin Configuration . . . . . . . . . . . . . . . . . . 1-4
Pin Definitions and functions (Normal Mode)
1-5–1-9
Pin Definitions and functions (OTP Mode)
4-3–4-4
PSW . . . . . . . . . . . . . . . . . . . . . . . .2-4, 2-8
R
RB8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
RD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Recommended oscillator circuits . . . . . 5-22
REN . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
RI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
RMAP . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
RMTPND . . . . . . . . . . . . . . . . . . . . . . . 2-10
RS0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
RS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
RxD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
RXDC . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
RXIE . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
RXOK . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
S
SBUF . . . . . . . . . . . . . . . . . . . . . . . .2-5, 2-7
Semiconductor Group
6-3
T
T0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
T1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
T2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
T2CM . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
T2CON . . . . . . . . . . . . . . . . . . 2-4, 2-5, 2-8
T2EX . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
T2I0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
T2I1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
T2PS . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
T2R0 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
T2R1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
TB8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
TCON . . . . . . . . . . . . . . . . . . . 2-4, 2-5, 2-7
TEST . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
TF0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
TF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
TF2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
TH0 . . . . . . . . . . . . . . . . . . . . . . . . . 2-5, 2-7
TH1 . . . . . . . . . . . . . . . . . . . . . . . . . 2-5, 2-7
TH2 . . . . . . . . . . . . . . . . . . . . . . . . . 2-5, 2-8
TI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
Timings
Data memory read cycle . . . . . . . . . .5-15
Data memory write cycle . . . . . . . . . .5-16
External clock timing . . . . . . . . . . . . .5-16
Introduction
C505A
OTP verification mode . . . . . . . . . . . 5-21
Program memory read cycle . . . . . . 5-14
TL0 . . . . . . . . . . . . . . . . . . . . . . . . .2-5, 2-7
TL1 . . . . . . . . . . . . . . . . . . . . . . . . .2-5, 2-7
TL2 . . . . . . . . . . . . . . . . . . . . . . . . .2-5, 2-8
TMOD . . . . . . . . . . . . . . . . . . . . . . .2-5, 2-7
TR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
TR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
TSEG1 . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
TSEG2 . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
TxD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
TXDC . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
TXIE . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
TXOK . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
TXRQ . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
U
UAR0 . . . . . . . . . . . . . . . . . . . . . . .2-6, 2-10
UAR1 . . . . . . . . . . . . . . . . . . . . . . .2-6, 2-10
UGML0 . . . . . . . . . . . . . . . . . . . . .2-6, 2-10
UGML1 . . . . . . . . . . . . . . . . . . . . .2-6, 2-10
UMLM0 . . . . . . . . . . . . . . . . . . . . .2-6, 2-10
UMLM1 . . . . . . . . . . . . . . . . . . . . .2-6, 2-10
V
VR0 . . . . . . . . . . . . . . . . . . . . . . . . .2-4, 2-9
VR1 . . . . . . . . . . . . . . . . . . . . . . . . .2-4, 2-9
VR2 . . . . . . . . . . . . . . . . . . . . . . . . .2-4, 2-9
W
WDT . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
WDTPSEL . . . . . . . . . . . . . . . . . . . . . . . 2-7
WDTREL . . . . . . . . . . . . . . . . . . . . .2-5, 2-7
WDTS . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
WR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
WS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
X
XMAP0 . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
XMAP1 . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
XPAGE . . . . . . . . . . . . . . . . . . . . . .2-4, 2-7
XTD . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Semiconductor Group
6-4
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