C515C_8EM_bc

Errata Sheet
V 1.1, 2003-12
Device
C515C-8E
Marking/Step
Step BC
Package
P-MQFP-80
This Errata Sheet describes the deviations from the current user documentation.
The module oriented classification and numbering system uses an ascending sequence
over several derivatives, including already solved deviations. So gaps inside this
enumeration can occur.
Current Documentation
• C515C User's Manual 11.97
• C515C Data Sheet
Feb. 2003
• Instruction Set Manual 07.2000
Note: Devices marked with EES- or ES are engineering samples which may not be
completely tested in all functional and electrical characteristics, therefore they
should be used for evaluation only.
The specific test conditions for EES and ES are documented in a separate Status Sheet.
Contents
Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page
History List/Change Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Functional Deviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Deviations from Electrical- and Timing Specification. . . . . . . . . . . . . . . . . . . . . . . .8
Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Errata Sheet, C515C-8E, Step BC
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K. Yang, V 1.1, 2003-12
Errata Sheet
History List/Change Summary
1
History List/Change Summary
(since last CPU Step BB, previous Errata Sheet V1.0)
Table 1
Functional Deviations
Functional
Deviation
Short Description
CAN.2
Unexpected Remote Frame Transmission
CAN.3
Description in User's Manual regarding the reception
of remote frames and the data length code (DLC) field
is incorrect
CAN.4
Flowchart sequence in figure in User's Manual
regarding Micro-controller handling of the Last
Message Object is partly incorrect
CAN.5
Description in User's Manual section 6.5.5 regarding
the Configuration of the Bit Timing is partly incorrect
WDT.1
Watchdog Timer is not halted in Idle Mode
OTP.1
ROM Verification Mode 2 and verification error
signaling at Port 3.5
OTP.2
OTP module may fail under special conditions, leading
to undefined operation
Table 2
AC/DC Deviations
AC/DC
Deviation
Short Description
DC.3
VIH minimum on EA pin does not meet the
specification values
DC.4
VDD is valid for a smaller range than specified on
documents
DC.5
Minimum value of -3 µA for the logic 0 input current
(Ports 1, 2, 3, 4, 5, 7)
New
DC.6
Maximum limit values of the power supply current
(IDD)for Active Mode and Idle Mode
New
Errata Sheet, C515C-8E, Step BC
Fixed
Change
in Step
BC
Fixed
in Step
2/10
Change
K. Yang, V 1.1, 2003-12
Errata Sheet
History List/Change Summary
Table 3
Application Hints
Application
Hint
Short Description
Fixed
in Step
Change
None.
Errata Sheet, C515C-8E, Step BC
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K. Yang, V 1.1, 2003-12
Errata Sheet
Functional Deviations
2
Functional Deviations
CAN.2: Unexpected Remote Frame Transmission
The on-chip CAN module may send an unexpected remote frame with the identifier=0,
when a pending transmit request of a message object is disabled by software.
There are three possibilities to disable a pending transmit request of a message object
(n=1..14):
• Set CPUUPDn element
• Reset TXRQn element
• Reset MSGVALn element
Either of these actions will prevent further transmissions of message object n.
The symptom described above occurs when the CPU accesses CPUUPD, TXRQ or
MSGVAL, while the pending transmit request of the corresponding message object is
transferred to the CAN state machine (just before start of frame transmission). At this
particular time the transmit request is transferred to the CAN state machine before the
CPU prevents transmission. In this case the transmit request is still accepted from the
CAN state machine. However the transfer of the identifier, the data length code and the
data of the corresponding message object is prevented. Then the pre-charge values of
the internal “hidden buffer” are transmitted instead, this causes to a remote frame
transmission with identifier=0 (11 bit) and data length code=0.
This behavior occurs only when the transmit request of message object n is pending and
the transmit requests of other message objects are not active (single transmit request).
If this remote frame loses arbitration (to a data frame with identifier=0) or if it is disturbed
by an error frame, it is not retransmitted.
Effects to other CAN nodes in the network
The effect leads to delays of other pending messages in the CAN network due to the high
priority of the Remote Frame. Furthermore the unexpected remote frame can trigger
other data frames depending on the CAN node's configuration.
Workaround:
1. The behavior can be avoided if a message object is not updated by software when a
transmission of the corresponding message object is pending (TXRQ element is set)
and the CAN module is active (INIT = 0). If a re-transmission of a message (e.g. after
lost arbitration or after the occurrence of an error frame) needs to be cancelled, the
Errata Sheet, C515C-8E, Step BC
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K. Yang, V 1.1, 2003-12
Errata Sheet
Functional Deviations
TXRQ element should be cleared by software as soon as NEWDAT is reset from the
CAN module.
2. The nodes in the CAN system ignore the remote frame with the identifier=0 and no
data frame is triggered by this remote frame.
CAN.3: Description in User's Manual regarding the reception of remote frames and
the data length code (DLC) field is incorrect
It is inaccurately described in the User's Manual on page 6-94 under 'Arbitration
Registers' that 'When the CAN controller stores a remote frame, only the data length
code is stored into the corresponding message object'. The correct should be that the
DLC field remains unchanged in the receiving message object, and that the CPU has the
responsibility to define the DLC of the answering data frame.
This correction will be updated to the future versions of the User's Manuals.
Workaround:
Not applicable.
CAN.4: Flowchart sequence in figure in User's Manual regarding Micro-controller
handling of the Last Message Object is partly incorrect
For the software flowchart figure 6-48 in User's Manual 11.97, the correct would be to
first 'process message contents' and then to 'clear bit NEWDAT'.
process message
NEWDAT: = 0
This correction will be updated to the future versions of the User's Manuals.
Workaround:
Not applicable.
Errata Sheet, C515C-8E, Step BC
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K. Yang, V 1.1, 2003-12
Errata Sheet
Functional Deviations
CAN.5: Description in User's Manual section 6.5.5 regarding the Configuration of
the Bit Timing is partly incorrect
As described for the CAN Bit Timing Register High BTR1, the minimum total time
requirement for segment 1 and segment 2 is as follows:
tTSeg1 ≥ 3 x tq
tTSeg2 ≥ 2 x tq
The total bit time remains at (tTSeg1 + tTSeg2 ≥ 7 x tq).
This correction will be updated to the future versions of the User's Manuals.
Workaround:
Not applicable.
WDT.1: Watchdog Timer is not halted in Idle Mode
The Watchdog Timer (WDT) is not halted in the Idle Mode as defined. However, during
the Idle Mode, an overflow condition of the WDT does not initiate an internal reset. In
such a case, the WDT starts a new count sequence.
Workaround:
1. Do not use the Watchdog Timer function in combination with the Idle Mode
2. In case of WDT is running before entry into idle mode, to avoid a WDT initiated reset
upon exit of the Idle Mode, the following methods can be used.
a) The WDT is refreshed immediately upon exit from Idle Mode.
b) A timed interrupt can be used to exit the Idle Mode before the WDT reaches the
counter state 7FFCh. This can be achieved by using Timer 0, 1 or 2. This timer can
be programmed to generate an interrupt at a WDT counter state prior to overflow,
for e.g., at 7F00h. Prior to entering Idle Mode, the WDT can be refreshed and Timer
0, 1or 2 can be started immediately to synchronize the WDT. In the interrupt service
routine of Timer 0, 1 or 2, the WDT must be refreshed. If required, Idle Mode could
be entered again.
Errata Sheet, C515C-8E, Step BC
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K. Yang, V 1.1, 2003-12
Errata Sheet
Functional Deviations
OTP.1: ROM Verification Mode 2 and verification error signaling at Port 3.5
P3.5 does not remain at “0” permanently after detecting a verify error. It will return to “1”
when a block of 16 bytes is equal to the internal memory contents, i.e. the verify
procedure for these 16 bytes is passed.
Also, the last block of 16 bytes will always return verification error in the ROM Verification
Mode 2.
Workaround:
None.
Errata Sheet, C515C-8E, Step BC
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K. Yang, V 1.1, 2003-12
Errata Sheet
Deviations from Electrical- and Timing Specification
3
Deviations from Electrical- and Timing Specification
DC.3: VIH minimum on EA pin does not meet the specification values
The VIH min. voltage on pin EA does not meet the specified values:
VIH min. for EA pin is (0.6 • VDD) V, instead of (0.2 • VDD + 0.9) V.
The new value will be worked into future documentation.
Workaround:
None.
DC.4: VDD is valid for a smaller range than specified on documents
VDD is valid in the range from 4.5 V to 5.5 V at all specified temperatures, instead of
4.25 V to 5.5 V as specified on the documents. This smaller range is effective on devices
with date code 0115.
Workaround:
None.
DC.5: Minimum value of - 3 µA for the logic 0 input current (Ports 1, 2, 3, 4, 5, 7)
The minimum value of the logic 0 input current for ports 1, 2, 3, 4, 5, and 7 is lower than
the specified value:
IIL min. = - 3 µA
(instead of - 10 µA)
Workaround:
None.
Errata Sheet, C515C-8E, Step BC
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K. Yang, V 1.1, 2003-12
Errata Sheet
Deviations from Electrical- and Timing Specification
DC.6: Maximum limit values of the power supply current (IDD) for Active Mode and
Idle Mode
The maximum limit values of the power supply current (IDD) for Active Mode and Idle
Mode are shown in the table below, instead of the specified values stated in the Data
Sheet.
Power Supply Current
Parameter
Symbol Maximum Limit Values Unit
6 MHz
IDD
15.76
mA
10 MHz
IDD
24.16
mA
6 MHz
IDD
9.85
mA
10 MHz
IDD
14.45
mA
Active Mode
C515C-8E
with Slow-Down
enabled
6 MHz
IDD
5.66
mA
10 MHz
IDD
6.60
mA
Idle Mode with
Slow-Down
enabled
6 MHz
IDD
5.02
mA
10 MHz
IDD
5.60
mA
Active Mode
Idle Mode
C515C-8E
C515C-8E
C515C-8E
Workaround:
None.
Errata Sheet, C515C-8E, Step BC
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K. Yang, V 1.1, 2003-12
Errata Sheet
Application Hints
4
Application Hints
No application hints for this step.
Application Support Group, Singapore
Errata Sheet, C515C-8E, Step BC
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K. Yang, V 1.1, 2003-12
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