A1190, A1192, and A1193 Datasheet

A1190, A1192, and A1193
Programmable, Chopper-Stabilized, Two-Wire Hall-Effect Switches
Features and Benefits
Description
▪AEC-Q100 automotive qualified
▪High-speed, 4-phase chopper stabilization
▫Low switchpoint drift throughout temperature range
▫Low sensitivity to thermal and mechanical stresses
▪On-chip protection
▫Supply transient protection
▫Reverse-battery protection
▪On-board voltage regulator
▫3 to 24 V operation
▪Solid-state reliability
▪Robust EMC and ESD performance
▪Field programmable for optimized switchpoints
▪Industry-leading ISO 7637-2 performance through use of
proprietary, 40 V clamping structure
Packages
The A1190, A1192, and A1193 comprise a family of twowire, unipolar, Hall-effect switches, which can be trimmed
by the user at end-of-line to optimize magnetic switchpoint
accuracy in the application. These devices are produced on
the Allegro™ advanced BiCMOS wafer fabrication process,
which implements a patented high-frequency, 4-phase,
chopper stabilization technique. This technique achieves
magnetic stability over the full operating temperature range,
and eliminates offsets inherent in devices with a single Hall
element that are exposed to harsh application environments.
The A119x family has a number of automotive applications.
These include sensing seat track position, seat belt buckle
presence, hood/trunk latching, and shift selector position.
Two-wire unipolar switches are particularly advantageous in
cost-sensitive applications because they require one less wire
for operation versus the more traditional open-collector output
switches. Additionally, the system designer inherently gains
diagnostics because there is always output current flowing,
which should be in either of two narrow ranges. Any current
level not within these ranges indicates a fault condition.
3-pin ultramini SIP
1.5 mm × 4 mm × 3 mm
(suffix UA)
3-pin SOT23-W
2 mm × 3 mm × 1 mm
(suffix LH)
All family members are offered in two package styles. The LH
is a SOT-23W style, miniature, low-profile package for surfacemount applications. The UA is a 3-pin, ultra-mini, single inline
package (SIP) for through-hole mounting. Both packages are
lead (Pb) free, with 100% matte-tin leadframe plating.
Approximate footprint
Functional Block Diagram
V+
VCC
Regulator
Program / Lock
ICC Adjust
To all subcircuits
Amp
Offset Adjust
Sample and Hold
0.01 µF
Dynamic Offset
Cancellation
Clock/Logic
Polarity
Low-Pass
Filter
Schmitt
Trigger
GND
UA package only
A1190-DS, Rev. 5
GND
Programmable, Chopper-Stabilized,
Two Wire Hall-Effect Switches
A1190, A1192,
and A1193
Selection Guide
Part Number
Package
Packing1
Output (ICC) in
South Polarity
Field
Supply Current
at ICC(L)
(mA)
Low
2 to 5
A1190LLHLT-T2 LH (Surface mount) 7-in. reel, 3000 pieces/reel
A1190LLHLX-T LH (Surface mount) 13-in. reel, 10000 pieces/reel
A1190LUA-T3
UA (Through hole)
Bulk, 500 pieces/bag
A1192LLHLT-T2 LH (Surface mount) 7-in. reel, 3000 pieces/reel
A1192LLHLX-T LH (Surface mount) 13-in. reel, 10000 pieces/reel
A1192LUA-T3
UA (Through hole)
Bulk, 500 pieces/bag
A1193LLHLT-T2 LH (Surface mount) 7-in. reel, 3000 pieces/reel
A1193LLHLX-T LH (Surface mount) 13-in. reel, 10000 pieces/reel
A1193LUA-T3
UA (Through hole)
Bulk, 500 pieces/bag
1Contact Allegro™ for additional packing options.
2These variants available only through authorized distributors.
3Contact factory for availability.
Magnetic Operate
Point, BOP
(G)
10 to 200
Low
5 to 6.9
High
Absolute Maximum Ratings
Characteristic
Symbol
Forward Supply Voltage
VCC
Reverse Supply Voltage
Notes
Rating
Unit
28
V
VRCC
–18
V
Magnetic Flux Density
B
Unlimited
G
Operating Ambient Temperature
TA
–40 to 150
ºC
Maximum Junction Temperature
TJ(max)
165
ºC
Tstg
–65 to 170
ºC
Storage Temperature
Range L
Terminal List Table
Pin-Out Diagrams
3
Number
1
Name
LH package
UA package
VCC
VCC
NC
1
2
1
2
3
2
NC
GND
Function
Connects power supply to chip;
used to apply programming
signal
LH package: no connection, it
is highly recommended that this
pin be tied to GND
UA package: ground terminal
LH Package
UA Package
3
GND
GND
Ground terminal
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
Programmable, Chopper-Stabilized,
Two Wire Hall-Effect Switches
A1190, A1192,
and A1193
ELECTRICAL CHARACTERISTICS: Valid at TA = –40°C to 150°C, TJ < TJ(max), CBYP = 0.01 μF, through operating supply
voltage range, unless otherwise noted
Characteristics
Symbol
Supply Voltage1,2
VCC
ICC(L)
Supply Current
ICC(H)
Supply Zener Clamp Voltage
VZ(sup)
Test Conditions
Typ.
Max.
3.0
–
24
V
A1190
B > BOP
2.0
–
5.0
mA
A1192
B > BOP
5
–
6.9
mA
A1193
B < BRP
5
–
6.9
mA
A1190, A1192
B < BRP
12
–
17
mA
A1193
B > BOP
12
–
17
mA
28
–
–
V
mA
ICC = ICC(L)(max) + 3 mA, TA = 25°C
Unit
VZ(sup) = 28 V
–
–
ICC(L)(max)
+ 3 mA
IRCC
VRCC = –18 V
–
–
–1.6
mA
di/dt
No bypass capacitor, capacitance of probe
CS = 20 pF
–
90
–
mA / µs
–
700
–
kHz
Supply Zener Clamp Current
IZ(sup)
Reverse Supply Current
Output Slew Rate3
Min.
Operating, TJ ≤ 165 °C
Chopping Frequency
fC
Power-Up Time2,4,5
ton
Power-Up State6,7
POS
A1190, A1192
CBYP = 0.01 µF, B > BOP + 10 G
–
–
25
µs
A1193
CBYP = 0.01 µF, B < BRP – 10 G
–
–
25
µs
–
ICC(H)
–
–
ton < ton(max) , VCC slew rate > 25 mV / µs
1V
CC
2 The
represents the generated voltage between the VCC pin and the GND pin.
VCC slew rate must exceed 600 mV/ms from 0 to 3 V. A slower slew rate through this range can affect device performance.
3 Measured without bypass capacitor between VCC pin and the GND pin. Use of a bypass capacitor results in slower current change.
4 Power-Up Time is measured without and with a bypass capacitor of 0.01 µF. Adding a larger bypass capacitor would cause longer Power-Up Time.
5 Guaranteed by characterization and design.
6 Power-Up State as defined is true only with a V
CC slew rate of 25 mV / µs or greater.
7 For t > t and B
on
RP < B < BOP , Power-Up State is not defined.
MAGNETIC CHARACTERISTICS1: Valid at TA = –40°C to 150°C, TJ ≤ TJ (max), unless otherwise noted
Characteristics
Symbol
Initial Operate Point
Test Conditions
Min.
Typ.
Max.
Unit2
–
–14
10
G
TA = 25°C
10
–
200
G
TA = 25°C, VCC = 5 V
3
4.8
7.5
G
BOP(init)
Programmable Magnetic
Operating Point
BOP
Average Magnetic Step Size3
STEPBOP
Switchpoint Temperature Drift
ΔBOP
–
±20
–
G
Hysteresis
BHYS
5
–
30
G
1Relative
values of B use the algebraic convention, where positive values indicate south magnetic polarity, and negative values indicate north
magnetic polarity; therefore greater B values indicate a stronger south polarity field (or a weaker north polarity field, if present).
21 G (gauss) = 0.1 mT (millitesla).
3STEP
BOP is a calculated average from the cumulative programmed bits.
PROGRAMMABLE PARAMETERS
Name
Functional Description
Quantity
of Bits
BOP Trim
Fine trim of Programmable Magnetic Operating Point
6
Programming Lock
Lock access to programming
1
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
Programmable, Chopper-Stabilized,
Two Wire Hall-Effect Switches
A1190, A1192,
and A1193
THERMAL CHARACTERISTICS: may require derating at maximum conditions; see application information
Characteristic
Symbol
Test Conditions*
RθJA
Package Thermal Resistance
Value
Unit
Package LH, on 4-layer PCB based on JEDEC standard
228
ºC/W
Package LH, on 2-layer PCB with 0.463 in.2 of copper area each side
110
ºC/W
Package UA, on 1-layer PCB with copper limited to solder pads
165
ºC/W
*Additional thermal information available on the Allegro website
Maximum Allowable VCC (V)
Power Derating Curve
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
VCC(max)
2-layer PCB, Package LH
(RθJA = 110 ºC/W)
1-layer PCB, Package UA
(RθJA = 165 ºC/W)
4-layer PCB, Package LH
(RθJA = 228 ºC/W)
20
40
60
80
100
VCC(min)
120
140
160
180
Temperature (ºC)
Power Dissipation, PD (m W)
Power Dissipation versus Ambient Temperature
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
2l
(R aye
rP
θJ
C
A =
11 B, P
0 º ac
1-la
C/ ka
W
(R yer PC
) ge L
θJA =
B
H
165 , Pac
ºC/ kage
W)
UA
4-lay
er P
(R
CB,
θJA =
228 Packag
ºC/W
e LH
)
20
40
60
80
100
120
Temperature (°C)
140
160
180
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
Programmable, Chopper-Stabilized,
Two Wire Hall-Effect Switches
A1190, A1192,
and A1193
Characteristic Performance
A1190
Average Supply Current (Low) versus Temperature
A1190
Average Supply Current (Low) versus Supply Voltage
5.0
Supply Current, ICC(L) (mA)
Supply Current, ICC(L) (mA)
5.0
4.5
4.0
VCC = 24 V
3.5
VCC = 3.0 V
3.0
2.5
2.0
-60
-40
-20
0
20
40
60
80
100
120
140
4.5
4.0
3.5
TA = –40°C
3.0
2.5
2.0
160
2
6
A1192 and A1193
Average Supply Current (Low) versus Temperature
22
26
7.0
Supply Current, ICC(L) (mA)
Supply Current, ICC(L) (mA)
18
A1192 and A1193
6.5
VCC = 24 V
6.0
VCC = 3.0 V
5.5
-40
-20
0
20
40
60
80
100
120
140
6.5
TA = –40°C
6.0
TA = 25°C
5.5
5.0
160
TA = 150°C
2
6
10
14
18
22
26
Supply Voltage, VCC (V)
Ambient Temperature, TA (°C)
A1190/A1192/A1193
Average Supply Current (High) versus Temperature
A1190/A1192/A1193
Average Supply Current (High) versus Supply Voltage
17
Supply Current, ICC(H) (mA)
17
Supply Current, ICC(H) (mA)
14
Average Supply Current (Low) versus Supply Voltage
7.0
16
VCC = 24 V
15
VCC = 3.0 V
14
13
12
-60
10
Supply Voltage, VCC (V)
Ambient Temperature, TA (°C)
5.0
-60
TA = 150°C
TA = 25°C
16
-20
0
20
40
60
80
100
Ambient Temperature, TA (°C)
120
140
160
TA = 150°C
TA = 25°C
14
13
12
-40
TA = –40°C
15
2
6
10
14
18
22
26
Supply Voltage, VCC (V)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
Programmable, Chopper-Stabilized,
Two Wire Hall-Effect Switches
A1190, A1192,
and A1193
A1190/A1192/A1193
Applied Flux Density at
Switchpoint Hysteresis, BHYS (G)
Average Switchpoint Hysteresis versus Temperature
30
25
20
15
VCC = 24 V
VCC = 3.0 V
10
5
-60
-40
-20
0
20
40
60
80
100
120
140
160
Ambient Temperature, TA (°C)
A1190/A1192/A1193
Average Operate Point, BOP (G)
Average Operate Point versus Code
160
Bit #5
140
120
100
80
Bit #4
60
BOP(init)
40
Bit #3
20
Bit #2
Bit #1
Bit #0
0
-20
0
4
8
12
16
20
24
28
32
36
Code
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
Programmable, Chopper-Stabilized,
Two Wire Hall-Effect Switches
A1190, A1192,
and A1193
Functional Description
I+
B+
BHYS
(A) Hysteresis curve for A1190 and A1192
0
ICC(L)
B–
BRP
BOP
BRP
ICC(H)
ICC
ICC
ICC(L)
B–
I+
Switch to Low
0
Switch to Low
Switch to High
ICC(H)
The difference between the magnetic operate and release points
is called the hysteresis of the device, BHYS . This built-in hysteresis allows clean switching of the output even in the presence of
external mechanical vibration and electrical noise.
Switch to High
In the case of the reverse output polarity, as in the A1193, the
device output switches high after the magnetic field at the Hall
sensor IC exceeds the operate point threshold, BOP . When the
magnetic field is reduced to below the release point threshold,
BRP, the device output goes low (panel B).
BOP
The A1190 and A1192 output, ICC, switches low after the magnetic field at the Hall sensor IC exceeds the operate point threshold, BOP . When the magnetic field is reduced to below the release
point threshold, BRP , the device output goes high. This is shown
in figure 1, panel A.
B+
BHYS
(B) Hysteresis curve for A1193
Figure 1. Alternative switching behaviors are available in the A119x device family. On the horizontal axis, the B+ direction indicates
increasing south polarity magnetic field strength, and the B– direction indicates decreasing south polarity field strength (including the
case of increasing north polarity).
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
Programmable, Chopper-Stabilized,
Two Wire Hall-Effect Switches
A1190, A1192,
and A1193
RSENSE
V+
V+
VCC
VCC
CBYP
A119x
GND
GND
CBYP
0.01 µF
A119x
0.01 µF
GND
A
GND
A
ECU
A
RSENSE
Package UA Only
(A) Low side sensing
(B) High side sensing
Figure 2. Typical application circuits
Chopper Stabilization Technique
When using Hall-effect technology, a limiting factor for
switchpoint accuracy is the small signal voltage developed
across the Hall element. This voltage is disproportionally small
relative to the offset that can be produced at the output of the
Hall sensor IC. This makes it difficult to process the signal while
maintaining an accurate, reliable output over the specified operating temperature and voltage ranges. Chopper stabilization is
a unique approach used to minimize Hall offset on the chip. The
patented Allegro technique, namely Dynamic Quadrature Offset
Cancellation, removes key sources of the output drift induced by
thermal and mechanical stresses. This offset reduction technique
is based on a signal modulation-demodulation process. The
undesired offset signal is separated from the magnetic fieldinduced signal in the frequency domain, through modulation.
The subsequent demodulation acts as a modulation process for
the offset, causing the magnetic field-induced signal to recover
its original spectrum at base band, while the DC offset becomes
a high-frequency signal. The magnetic-sourced signal then can
pass through a low-pass filter, while the modulated DC offset is
suppressed. The chopper stabilization technique uses a 350 kHz
high frequency clock. For demodulation process, a sample and
hold technique is used, where the sampling is performed at twice
the chopper frequency. This high-frequency operation allows
a greater sampling rate, which results in higher accuracy and
faster signal-processing capability. This approach desensitizes
the chip to the effects of thermal and mechanical stresses, and
produces devices that have extremely stable quiescent Hall output voltages and precise recoverability after temperature cycling.
This technique is made possible through the use of a BiCMOS
process, which allows the use of low-offset, low-noise amplifiers
in combination with high-density logic integration and sampleand-hold circuits.
Regulator
Hall Element
Amp
Sample and
Hold
Clock/Logic
Low-Pass
Filter
Figure 3. Chopper stabilization circuit (Dynamic Quadrature Offset Cancellation)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
Programmable, Chopper-Stabilized,
Two Wire Hall-Effect Switches
A1190, A1192,
and A1193
Programming Guidelines
Overview
Programming is accomplished by sending a series of input voltage pulses serially through the VCC (supply) pin of the device.
A unique combination of different voltage level pulses controls
the internal programming logic of the device to select a desired
programmable parameter and change its value. There are three
voltage levels that must be taken into account when programming. These levels are referred to as high (VPH), mid (VPM), and
low (VPL) (see figure 1 and table 1).
Definition of Terms
Register. The section of the programming logic that controls the
choice of programmable modes and parameters.
Bit Field. The internal fuses unique to each register, represented
as a binary number. Changing the bit field selection in a particular register causes its programmable parameter to change, based
on the internal programming logic.
Key. A series of VPM voltage pulses used to select a register or mode.
The A119x family features two programmable modes, Try mode
and Blow mode.
tACTIVE
•In Try mode, programmable parameter values are set and measured. A parameter value is stored temporarily, and reset after
cycling the supply voltage.
Supply Voltage, VCC
VPH
•In Blow mode, the value of a programmable parameter may
be permanently set by blowing solid-state fuses internal to the
device. Device locking is also accomplished in this mode.
The programming sequence is designed to help prevent the
device from being programmed accidentally; for example, as a
result of noise on the supply line. Although any programmable
variable power supply can be used to generate the pulse waveforms, Allegro highly recommends using the Allegro Sensor IC
Evaluation Kit, available on the Allegro website On-line Store.
The manual for that kit is available for download free of charge,
and provides additional information on programming these
devices.
tBLOW
tPf
tPr
VPM
VPL
tLOW
tLOW
(Supply
cycled)
0
Programming
pulses
Blow
pulse
Figure 4. Programming pulse definition (see table 1)
Table 1. Programming Pulse Requirements, Protocol at TA = 25°C (refer also to figure 4)
Characteristic
Symbol
Programming Voltage
VPM
Notes
Min. Typ. Max. Unit
VPL
Measured at the VCC pin.
VPH
Programming Current
IPP
tLOW
Pulse Width
Pulse Rise Time
Pulse Fall Time
Blow Pulse Slew Rate
tPr = 11 µs, VCC = 5 → 26 V, CBLOW = 0.1 µF (min). Minimum supply current
required to ensure proper fuse blowing. CBLOW must be connected between the
VCC and GND pins during programming to provide the current necessary for fuse
blowing.
4.5
5
5.5
V
12.5
–
14
V
21
–
27
V
175
–
–
mA
Duration at VPL separating pulses at VPM or VPH.
20
–
–
µs
tACTIVE
Duration of pulses at VPM or VPH for key/code selection.
20
–
–
µs
tBLOW
Duration of pulse at VPH for fuse blowing.
90
100
–
µs
tPr
VPL to VPM , or VPL to VPH.
5
–
100
µs
tPf
VPH to VPL , or VPM to VPL.
5
–
100
µs
375
–
–
mV/ µs
SRBLOW
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
Programmable, Chopper-Stabilized,
Two Wire Hall-Effect Switches
A1190, A1192,
and A1193
Code. The number used to identify the combination of fuses
activated in a bit field, expressed as the decimal equivalent of the
binary value. The LSB of a bit field is denoted as code 1, or bit 0.
Programming Procedure
Programming involves selection of a register, a mode, and then
setting values for parameters in the register for evaluation or for
fuse blowing. Figure 10 provides an overview state diagram.
Addressing. Setting the bit field code in a selected register by
serially applying a pulse train through the VCC pin of the device.
Each parameter can be measured during the addressing process,
but the internal fuses must be blown before the programming
code (and parameter value) becomes permanent.
Blow Pulse. A VPH pulse of sufficient duration to blow the
addressed fuse.
Register Selection Each programmable parameter can be
accessed through a specific register. To select a register, a
sequence of voltage pulses consisting of a VPH pulse, a series of
VPM pulses, and a VPH pulse (with no VCC supply interruptions)
must be applied serially to the VCC pin. The quantity of VPM
pulses is called the key, and uniquely identifies each register. The
pulses for selection of register key 1, is shown in figure 5. No
VPM pulse is sent for key 0. The register selections are shown in
table 2.
Cycling the Supply. Powering-down, and then powering-up the
supply voltage. Cycling the supply is used to clear the programming settings in Try mode.
Mode Selection After register selection, the mode is selected,
either Try or Blow mode. Try mode is selected by default. To
select Blow mode, that mode selection key must be sent.
Fuse Blowing. Applying a VPH pulse of sufficient duration to
permanently set an addressed bit by blowing a fuse internal to the
device. Once a bit (fuse) has been blown, it cannot be reset.
Table 2. Programming Logic Table
Register
Key
Name
Bit Field Address (Code)
Binary Format
[MSB → LSB]
Decimal
Equivalent
Description
Try Mode
0
1
7
BOP Trim Up Counting
BOP Trim Down Counting
Fuse Check
000000
0
Initial value (below minimum |BOP| ) (Try mode sequence
starts with code 1); Code corresponds to bit field value (code
1 selects bit field value 000001)
111111
63
Maximum selectable value (above maximum |BOP| )
111111
0
Initial value (above maximum |BOP| ) (Try mode sequence
starts with code 1); Code is automatically inverted (code 1
selects bit field value 111110)
000000
63
Minimum selectable value (below minimum |BOP|)
000111
7
Check integrity of all fuse bits versus low threshold
001111
15
Check integrity of all fuse bits versus high threshold
Blow Mode
0
7
BOP Trim
Programming Lock
000000
0
Initial value (below minimum |BOP| ); (Only allows selection
of 1 bit per sequence)
111111
63
Maximum selectable value (above maximum |BOP| ); (Only
allows selection of 1 bit per sequence)
001000
8
Locks out access to all registers except Fuse Check
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
Programmable, Chopper-Stabilized,
Two Wire Hall-Effect Switches
A1190, A1192,
and A1193
Try Mode In Try mode, bit field addressing is accomplished by
applying a series of VPM pulses to the VCC pin of the device, as
shown in figure 6. Each pulse increases the bit field value for the
selected parameter, increasing by one on the falling edge of each
additional VPM pulse. When addressing the bit field in Try mode,
the quantity of VPM pulses is represented by a decimal number
called the code. Addressing activates the corresponding fuse
locations in the given bit field by increasing the binary value of
an internal DAC, up to the maximum possible code. As the value
of the bit field code increases, the value of the programmable
parameter changes. Measurements can be taken after each VPM
pulse to determine if the required result for the programmable
parameter has been reached. Cycling the supply voltage resets
all the locations in the bit field that have un-blown fuses to their
initial states.
When setting the BOP Trim parameter, as an aid to programming,
values can be traversed from low to high, or from high to low. To
accommodate this direction selection, the value of the bit field
(and code) defaults to the value 1, on the falling edge of the final
register selection VPH pulse (see figure 5). A complete example is
provided in figure 11.
Blow Mode After the required code is determined for a given
parameter, its value can be set permanently by blowing individual
fuses in the appropriate register bit field. Blowing is accomplished by selecting the register, then the Blow mode selection
key, followed by the appropriate bit field address, and ending
the sequence with the Blow pulse. The Blow mode selection key
is a sequence of nine VPM pulses followed by one VPH pulse. A
complete example is provided in figure 12.
The Blow pulse consists of a VPH pulse of sufficient duration,
tBLOW , to permanently set an addressed bit by blowing a fuse
internal to the device. Due to power requirements, the fuse for
each bit in the bit field must be blown individually. The A119x
family built-in circuitry allows only one fuse at a time to be
blown. During Blow mode, the bit field can be considered a “onehot” shift register. Table 3 relates the quantity of VPM pulses to
the binary and decimal values for Blow mode bit field addressing. It should be noted that the simple relationship between the
quantity of VPM pulses and the corresponding code is:
2n = Code,
where n is the quantity of VPM pulses. The bit field has an initial
state of decimal code 0 (binary 000000).
Supply Voltage, VCC
VPH
Bit Field Selection
Address Code Format
(Decimal Equivalent)
Code 5
VPM
Code in Binary
(Binary)
1 0 1
VPL
Fuse Blowing
Target Bits
Key
Fuse Blowing
Address Code Format
0
VPL
0
Figure 6. Try mode bit field addressing pulses
Bit 0
Code 4
Code 1
(Decimal Equivalents)
Figure 7. Example of code 5 broken into its binary components
Code 2n – 1
Code 2n – 2
Code 3
Supply Voltage, VCC
VPM
Code 2
Figure 5. Register selection pulse sequence
VPH
Bit 2
Table 3. Blow Mode Bit Field Addressing
Quantity of
VPM Pulses
Binary Register
Setting
Equivalent Code
1
000001
1
2
000010
2
3
000100
4
4
001000
8
5
010000
16
6
100000
32
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
A1190, A1192,
and A1193
Programmable, Chopper-Stabilized,
Two Wire Hall-Effect Switches
To correctly address the fuses to be blown, the code representing the required parameter value must be translated into a binary
number. For example, as shown in figure 7, decimal code 5 is
equivalent to the binary number 101. Therefore bit 2 must be
addressed and blown, the device power supply cycled, and then
bit 0 must be addressed and blown. The order of blowing bits,
however, is not important. Blowing bit 0 first, and then bit 2 is
acceptable.
Note: After blowing, the programming is not reversible, even
after cycling the supply power. Although a register bit field fuse
cannot be reset after it is blown, additional bits within the same
register can be blown at any time until the device is locked. For
example, if bit 1 (binary 10) has been blown, it is still possible to
blow bit 0. The end result would be binary 11 (decimal code 3).
Locking the Device
After the required code for each parameter is programmed, the
device can be locked to prevent further programming of any
parameters. To do so, perform the following steps:
1. Ensure that the CBLOW capacitor is mounted.
2. Select the Programming Lock register (key 7).
3. Select Blow mode (key 9).
4. Address bit 3 (001000) by sending four VPM pulses.
5. Send one Blow pulse, at IPP and SRBLOW, and sustain it for
tBLOW.
6. Delay for a tLOW interval, then power-down.
7. Optionally check all fuses.
Fuse Checking
Incorporated in the A119x family is circuitry to simultaneously
check the integrity of the fuse bits. The fuse checking feature is
enabled by using the Fuse Check register (selection key 7), and
while in Try mode, applying the codes shown in table 2. The
register is only valid in Try mode and is available before or after
the Programming Lock bit is set.
Setting the fuse threshold high checks that all blown fuses are
properly blown. Setting fuse threshold low checks all un-blown
fuses are properly intact. The supply current increases by 250 µA
if a marginal fuse is detected. If all fuses are correctly blown or
fully intact, there will be no change in supply current.
Additional Guidelines
The additional guidelines in this section should be followed to
ensure the proper behavior of these devices:
•A 0.1 μF blowing capacitor, CBLOW, must be mounted between
the VCC pin and the GND pin during programming, to ensure
enough current is available to blow fuses.
•The power supply used for programming must be capable of
delivering at least VPH and 175 mA.
•Be careful to observe the tLOW delay time before powering
down the device after blowing each bit.
•Lock the device (only after all other parameters have been programmed and validated) to prevent any further programming of
the device.
BOP Selection
Selecting BOP should be done in two stages. First, Try mode
should be used to adjust BOP and monitor the output state. Then
the optimum BOP is set permanently using Blow mode.
Use the BOP Trim Up Counting register to increase the BOP selection by one Magnetic Step Size, StepBOP , increment with each
bit field pulse (see figure 8). Use the BOP Trim Down Counting
register to decrease the BOP selection by one StepBOP with each
bit field pulse (see figure 9). As an aid to programming, when
using down-counting method, the A119x automatically inverts
the bit field selection (code 0 in down-counting sets the bit field
value 111111, and the actual bit field value decreases until code
63 sets bit field value 000000).
Note that the release point, BRP , is a value below BOP . The
difference is specified by the Hysteresis, BHYS , which is not
programmable.
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
Programmable, Chopper-Stabilized,
Two Wire Hall-Effect Switches
A1190, A1192,
and A1193
(Code 0,
Bit value 111111 )
(Code 63,
Bit value 111111 )
BOP
|BOP(max)|
BRP
|BOP(min)|
BHYS
(Code 0,
Bit value 000000 )
|BOP(max)|
BOP
BHYS
BRP
(Code 63,
Bit value 000000)
|BOP(min)|
BOP
BOP
BHYS
BRP
0
BRP
31
63
Try Mode, Bit Field Code
Figure 8. BOP Selection Up Counting
0
31
BHYS
63
Try Mode, Bit Field Code
Figure 9. BOP Selection Down Counting
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
13
A1190, A1192,
and A1193
Programmable, Chopper-Stabilized,
Two Wire Hall-Effect Switches
Figure 10. Programming state diagram
Figure 11. Example of Try mode pulse sequence, Register Key = BOP selection down counting
Figure 12. Example of Blow mode pulse sequence, Register Key = BOP selection bit field 2 (code 4)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
14
Programmable, Chopper-Stabilized,
Two Wire Hall-Effect Switches
A1190, A1192,
and A1193
Power Derating
The device must be operated below the maximum junction temperature of the device, TJ(max). Under certain combinations of
peak conditions, reliable operation may require derating supplied
power or improving the heat dissipation properties of the application. This section presents a procedure for correlating factors
affecting operating TJ. (Thermal data is also available on the
Allegro MicroSystems Web site.)
The Package Thermal Resistance, RθJA, is a figure of merit summarizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity, K,
of the printed circuit board, including adjacent devices and traces.
Radiation from the die through the device case, RθJC, is relatively
small component of RθJA. Ambient air temperature, TA, and air
motion are significant external factors, damped by overmolding.
The effect of varying power levels (Power Dissipation, PD), can
be estimated. The following formulas represent the fundamental
relationships used to estimate TJ, at PD. PD = VIN × IIN (1)
ΔT = PD × RθJA (2)
TJ = TA + ΔT
(3)
Example: Reliability for VCC at TA = 150°C, package UA, using a
low-K PCB.
Observe the worst-case ratings for the device, specifically: RθJA = 165 °C/W, TJ(max) = 165°C, VCC(max) = 24 V, and
ICC(max) = 17 mA.
Calculate the maximum allowable power level, PD(max). First,
invert equation 3:
ΔTmax = TJ(max) – TA = 165 °C – 150 °C = 15 °C
This provides the allowable increase to TJ resulting from internal
power dissipation. Then, invert equation 2:
PD(max) = ΔTmax ÷ RθJA = 15°C ÷ 165 °C/W = 91 mW
Finally, invert equation 1 with respect to voltage:
VCC(est) = PD(max) ÷ ICC(max) = 91 mW ÷ 17 mA = 5 V
The result indicates that, at TA, the application and device can
dissipate adequate amounts of heat at voltages ≤VCC(est).
Compare VCC(est) to VCC(max). If VCC(est) ≤ VCC(max), then reliable operation between VCC(est) and VCC(max) requires enhanced
RθJA. If VCC(est) ≥ VCC(max), then operation between VCC(est)
and VCC(max) is reliable under these conditions.
For example, given common conditions such as: TA= 25°C,
VCC = 12 V, ICC = 4 mA, and RθJA = 140 °C/W, then:
PD = VCC × ICC = 12 V × 4 mA = 48 mW
ΔT = PD × RθJA = 48 mW × 140 °C/W = 7°C
TJ = TA + ΔT = 25°C + 7°C = 32°C
A worst-case estimate, PD(max), represents the maximum allowable power level (VCC(max), ICC(max)), without exceeding
TJ(max), at a selected RθJA and TA.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
15
Programmable, Chopper-Stabilized,
Two Wire Hall-Effect Switches
A1190, A1192,
and A1193
Package LH, 3-Pin SOT23W
+0.12
2.98 –0.08
1.49 D
4°±4°
3
A
+0.020
0.180–0.053
0.96 D
+0.10
2.90 –0.20
+0.19
1.91 –0.06
2.40
0.70
D
0.25 MIN
1.00
2
1
0.55 REF
0.25 BSC
0.95
Seating Plane
Gauge Plane
8X 10° REF
B
PCB Layout Reference View
Branded Face
1.00 ±0.13
0.95 BSC
+0.10
0.05 –0.05
0.40 ±0.10
For Reference Only; not for tooling use (reference DWG-2840)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A
Active Area Depth, 0.28 mm REF
B
Reference land pattern layout
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
C
Branding scale and appearance at supplier discretion
D
Hall element, not to scale
NNT
1
C
Standard Branding Reference View
N = Last two digits of device part number
T = Temperature code
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
16
Programmable, Chopper-Stabilized,
Two Wire Hall-Effect Switches
A1190, A1192,
and A1193
Package UA, 3-Pin SIP
+0.08
4.09 –0.05
45°
B
C
E
+0.08
3.02 –0.05
2.05 NOM
1.52 ±0.05
1.44 NOM
E
10°
Mold Ejector
Pin Indent
E
Branded
Face
A
1.02
MAX
45°
NNN
0.79 REF
1
D Standard Branding Reference View
1
2
= Supplier emblem
N = Last three digits of device part number
3
+0.03
0.41 –0.06
14.99 ±0.25
+0.05
0.43 –0.07
For Reference Only; not for tooling use (reference DWG-9065)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A
Dambar removal protrusion (6X)
B
Gate and tie bar burr area
C
Active Area Depth, 0.50 mm REF
D
Branding scale and appearance at supplier discretion
E
Hall element (not to scale)
1.27 NOM
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
17
Programmable, Chopper-Stabilized,
Two Wire Hall-Effect Switches
A1190, A1192,
and A1193
Revision History
Revision
Revision Date
4
May 24, 2013
5
September 21, 2015
Description of Revision
Update application information
Added AEC-Q100 qualification under Features
and Benefits
Copyright ©2015, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
18
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