Delta Sheet XC164CM-8FF to XC164CS

Dr a f t De lt a S h e e t , V 1 . 0 D 3, M ar c h 2 00 4
Delta Sheet
XC164CM-8FF to XC164CS
M i c r o c o n t ro l le r s
N e v e r
s t o p
t h i n k i n g .
Edition 2004-03
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
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Terms of delivery and rights to technical change reserved.
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circuits, descriptions and charts stated herein.
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For further information on technology, delivery terms and conditions and prices please contact your nearest
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be endangered.
Dr a f t De lt a S h e e t , V 1 . 0 D 3, M ar c h 2 00 4
X C 164CM
1 6 -B it S in g l e -C h i p M i c r o c o n t ro l l e r
M i c r o c o n t ro l le r s
N e v e r
s t o p
t h i n k i n g .
XC164CM
Revision History:
2004-03
Previous Version:
2003-02
Page
V1.0D3
V1.0D2
Subjects (major changes since last revision)
This document has the status draft. All changes to previous version are
marked with change bars. Only major changes are listed below. Especially
formal changes and typos are not listed.
3-4
Setting reset configurations: depending on the mode now 2-4 pins are
used to select a reset configuration. Pin P1H5 is additionally used for
setting reset configurations. All configuration pins have an integrated pull
up. No integrated pull down any more. The configuration is latched with the
rising edge of RSTIN. Please read pages 3 to 4 carefully.
8
There was a line mismatch in the table of Port3.
Controller Area Network (CAN): License of Robert Bosch GmbH
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XC164CM-8FF
Delta Sheet XC164CM-8FF to XC164CS-16FF
1
Delta Sheet XC164CM-8FF to XC164CS-16FF
1.1
Blockdiagram XC164CM-8F
PSRAM
DPRAM
DSRAM
2 kBytes
2 kBytes
2 kBytes (no 4k option)
ProgMem
DMU
PMU
reduced
Flash
reduced to 64
kBytes
CPU
XBUS
Control
EBC
no external
BUS
C166SV2-Core
OCDS
Debug Support
Osc / PLL
XTAL
RTC
WDT
Interrupt & PEC
Clock Generation
Interrupt Bus
Peripheral Data Bus
ADC
GPT ASC0 ASC1 SSC0 SSC1
8/10-Bit
14
Channels
T2
(USART) (USART)
(SPI)
(SPI)
T3
no
CC1
CC2
CC6
T7
T12
T8
T13
Twin
CAN
T4
A B
T5
T6
Port 9
no PORT20
Figure 1
1.2
6
BRGen
BRGen
BRGen
BRGen
Port 5
14
no PORT4
Port 3
PORT1
13
no P1H.6 14
no P1H.7
no P3.12
no PORT0
no external BUS
Blockdiagram XC164CM-8FF with deltas to XC164CS-16FF
Delta Feature Table XC164CS-16FF to XC164CM-8FF
Table 1
List of feature differences
Feature
XC164CS-16FF
intermediate EES
XC164CM-8FF
Program Flash
Memory
128kB
C00000-C1FFFF
128kB
C00000-C1FFFF
64kB
C00000-C0FFFF
Program SRAM 2kB
E00000-E07FFF
2kB
E00000-E07FFF
2kB
E00000-E07FFF
Data SRAM
4kB
00C000-00CFFF
2kB
00C000-00C7FF
Draft Delta Sheet
2kB (4kB option)
00C000-00C7FF
1
V1.0D3, 2004-03
XC164CM-8FF
Delta Sheet XC164CM-8FF to XC164CS-16FF
Table 1
List of feature differences
Feature
XC164CS-16FF
intermediate EES
XC164CM-8FF
Package
TQFP100
TQFP64
TQFP64
CAPCOM1
on chip available, no
IOs, for interrupt
generation only
on chip available, no
IOs, for interrupt
generation only
no CAPCOM1
module on chip
CAPCOM2
fully available with all
16 channels, 12 IOs
CC16-27IO, Doubleregister-compare on 8
channels
fully available with all
16 channels, 10 IOs
CC16-25IO, Doubleregister-compare on 8
channels
fully available with all
16 channels, 10 IOs
CC16-25IO, Doubleregister-compare on 8
channels
CAN
IO pins on port 9 or 4 IO pins on port9 only
alternatively
IO pins on port9 only
External BUS
available
not available, single
chip mode only
not available, single
chip mode only
Port0
P0L.0-7, P0H0-7
no Port0 pins,
no Port0 pins, reset
no reset configuration configurations via P9,
with port0 functions
P1 and TRST
possible
Port1
P1L.0-7, P1H0-7
P1L.0-7, P1H0-5, no
P1H6-7, no external
bus functions
P1L.0-7, P1H0-5, no
P1H6-7, no external
bus functions
Port3
P3.1-13, P3.15
P3.1-11, P3.13,
P3.15, no pin P3.12
P3.1-11, P3.13,
P3.15, no pin P3.12
Port4
P4.0-7
no Port 4 pins
no Port 4 pins
Port5
P5.0-7, P5.10-15
all pins available, no
changes on Port5
all pins available, no
changes on Port5
Port20
P20.0-5, P20.12
no Port 20 pins, reset no Port 20 pins, reset
configurations via P9 configurations via P9,
possible
P1 and TRST
TRST
enables JTAG
enables JTAG
Draft Delta Sheet
2
enables JTAG and
configuration pins
sensing during reset
V1.0D3, 2004-03
XC164CM-8FF
Delta Sheet XC164CM-8FF to XC164CS-16FF
Table 2
List of differences in setting configuration modes during reset
Feature
XC164CS-16FF
intermediate EES
XC164CM-8FF
integrated pull up
(PU) /down (PD)
during reset
EA PU, RD PU,
ALE PD
P9.5 PU, P9.4 PD
P1H5 PU, P1H4 PU
P9.5 PU, P9.4 PU
Standard start from
internal memory at
C00000
EA=1,RD=1,ALE=0 P9.5=1, P9.4=0
default
(EA is always 1)
default
TRST=11)
P1H5=x, P1H4=x
P9.5 =1, P9.4=1
default
Bootstrap loader
ASC
EA=1,RD=0,
P9.5=0, P9.4=0
ALE=0
(EA is always 1)
EA=0, P0.5-2=1011
TRST = 1
P1H5=x, P1H4=x
P9.5=0, P9.4=1
Bootstrap loader
CAN
EA=1,RD=0,ALE=1 P9.5=0, P9.4=1
EA=0, P0.5-2=1001 (EA is always 1)
TRST = 1
P1H5=x, P1H4=1
P9.5=1, P9.4=0
Adapt mode
EA=0
P0.1=0
TRST = 1
P1H5=1, P1H4=1
P9.5=0, P9.4=0
not possible
Alternate start
EA=1,RD=1,ALE=1 P9.5=1, P9.4=1
(EA is always 1)
internal from C10000
1)
not supported
In XC164CM this mode is used for start from internal memory at C00000 in conjunction with OCDS. Standard
start from internal memory at C00000 is always performed if TRST=0 during reset.
Note: Bold means: to be set with external pull resistor.
Draft Delta Sheet
3
V1.0D3, 2004-03
XC164CM-8FF
Delta Sheet XC164CM-8FF to XC164CS-16FF
1.3
Bootstrap Loader, Adapt Mode, and Test Mode Settings
XC164CM
All system start up configurations are locked or enabled by TRST. If pin TRST is pulled
low for all the time, then OCDS (including JTAG) and all non standard system start up
configurations are always disabled.
For all applications it is recommended to have TRST pulled low for normal operation.
1.3.1
Enabling Non Standard System Start Up Configurations
If at the end of reset pin TRST is getting high, then pins P1H.5 (pin 6), P1H.4 (5), P9.5
(48), and P9.4 (47) are used to select one of the non standard system start up
configurations. This setting is latched with the rising edge of RSTIN.
.
Table 3
Mode Selection Overview
P1H P1H P9. P9. Selected Mode
.5
.4
5
4
x
x
1
1
Start internal: default setting, internal start from address
C00000 . To be used for internal start from C00000 with OCDS
debuggers (0011, 0111, 1011, 1111)
x
x
0
1
BSL-ASC: Bootstrap loader ASC
x
1
1
0
BSL-CAN: Bootstrap loader CAN
1
1
0
0
Adapt Mode: all pins are tristate
used for connecting an incircuit emulator
0
0
0
0
0
0
1
0
0
1
0
0
Test modes
do not use any of these settings.
In order to avoid such settings do not pull down P1H4 or P1H5
during reset and TRST=1
1
0
0
0
1
0
1
0
1.3.2
Enabling Normal Operation
If at the end of reset TRST is low, then always the default system start up configuration
is selected and the configuration 1111 is latched. Code execution is starting from
address C0 0000. For safety aspects keep TRST low for normal operation.
1.3.3
Enabling OCDS During Normal Operation
If only TRST is getting high while RSTIN remains low, then the microcontroller does not
perform a reset but the JTAG interface is getting enabled.
Draft Delta Sheet
4
V1.0D3, 2004-03
XC164CM-8FF
Delta Sheet XC164CM-8FF to XC164CS-16FF
1.4
Pin Configuration and Definition
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
NMI
RSTIN
TRST
XTAL2
XTAL1
VSS
VDDI
VDDP
P1L.7/CTRAP/CC22
P1L.6/COUT63
P1L.5/COUT62
P1L.4/CC62
P1L.3/COUT61
P1L.2/CC61
P1L.1/COUT60
P1L.0/CC60
The pins of the XC164CM are described in detail in Table 4, including all their alternate
functions. Figure 2 summarizes all pins in a condensed way, showing their location on
the 4 sides of the package. E*) and C*) mark pins to be used as alternate external
interrupt inputs, C*) marks pins that can have CAN interface lines assigned to them.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
XC164CM
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P9.5/CC21IO
P9.4/CC20IO
P9.3/CC19IO/C*)
P9.2/CC18IO/C*)
P9.1/CC17IO/C*)
P9.0/CC16IO/C*)
P3.15/CLKOUT/FO
VSSP
VDDP
P3.13/SCLK0/E*)
P3.11/RxD0/E*)
P3.10/TxD0/E*)
P3.9/MTSR0
P3.8/MRST0
P3.7/T2IN/BRKIN
P3.6/T3IN
P5.6/AN6
P5.7/AN7
VAREF
VAGND
P5.12/AN12/T6IN
P5.13/AN13/T5IN
P5.14/AN14/T4EUD
P5.15/AN15/T2EUD
VSS
VDDI
VDDP
P3.1/T6OUT/RxD1/TCK/E*)
P3.2/CAPIN/TDI
P3.3/T3OUT/TDO
P3.4/T3EUD/TMS
P3.5/T4IN/TxD1/BRKOUT
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P1H.0/C6P0/CC23/EX0IN
P1H.1/C6P1/MRST1/EX1IN
P1H.2/C6P2/MTSR1/EX2IN
P1H.3/T7IN/SCLK1/EX3IN/E*)
P1H.4/CC24/EX4IN
P1H.5/CC25/EX5IN
VSSP
VDDP
P5.0/AN0
P5.1/AN1
P5.2/AN2
P5.3/AN3
P5.4/AN4
P5.5/AN5
P5.10/AN10/T6EUD
P5.11/AN11/T5EUD
Figure 2
Pin Configuration (top view)
Draft Delta Sheet
5
V1.0D3, 2004-03
XC164CM-8FF
Delta Sheet XC164CM-8FF to XC164CS-16FF
Table 4
Pin Definitions and Functions
Symbol Pin
Num.
Input Function
Outp.
RSTIN
I
63
Reset Input with Schmitt-Trigger characteristics. A low level at
this pin while the oscillator is running resets the XC164CM.
A spike filter suppresses input pulses <10 ns. Input pulses
>100 ns safely pass the filter. The minimum duration for a
safe recognition should be 100 ns + 2 CPU clock cycles.
Note: The reset duration must be sufficient to let the hardware
configuration signals settle.
External circuitry must guarantee low level at the
RSTIN pin at least until both power supply voltages
have reached the operating range.
NMI
64
I
Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the XC164CM into power
down mode. If NMI is high, when PWRDN is executed, the
part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
P9
43-48
IO
P9.0
43
P9.1
44
P9.2
45
P9.3
46
P9.4
P9.5
47
48
I/O
I
I
I/O
O
I
I/O
I
I
I/O
O
I
I/O
I/O
Port 9 is a 6-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance state)
or output (configurable as push/pull or open drain driver). The
input threshold of Port 9 is selectable (standard or special).
The following Port 9 pins also serve for alternate functions:1)
CC16IO
CAPCOM2: CC16 Capture Inp./Compare Outp.,
CAN2_RxD CAN Node 2 Receive Data Input,
EX7IN
Fast External Interrupt 7 Input (alternate pin B)
CC17IO
CAPCOM2: CC17 Capture Inp./Compare Outp.,
CAN2_TxD CAN Node 2 Transmit Data Output,
EX6IN
Fast External Interrupt 6 Input (alternate pin B)
CC18IO
CAPCOM2: CC18 Capture Inp./Compare Outp.,
CAN1_RxD CAN Node 1 Receive Data Input,
EX7IN
Fast External Interrupt 7 Input (alternate pin A)
CC19IO
CAPCOM2: CC19 Capture Inp./Compare Outp.,
CAN1_TxD CAN Node 1 Transmit Data Output,
EX6IN
Fast External Interrupt 6 Input (alternate pin A)
CC20IO
CAPCOM2: CC20 Capture Inp./Compare Outp.2)
CC21IO
CAPCOM2: CC21 Capture Inp./Compare Outp.2)
Draft Delta Sheet
6
V1.0D3, 2004-03
XC164CM-8FF
Delta Sheet XC164CM-8FF to XC164CS-16FF
Table 4
Pin Definitions and Functions (cont’d)
Symbol Pin
Num.
Input Function
Outp.
PORT1
IO
P1L.0
P1L.1
P1L.2
P1L.3
P1L.4
P1L.5
P1L.6
P1L.7
49
50
51
52
53
54
55
56
P1H.0
1
P1H.1
2
P1H.2
3
P1H.3
4
P1H.4
5
P1H.5
6
XTAL2
XTAL1
61
60
Draft Delta Sheet
I/O
I
I
I/O
I
I
I/O
I
I
I/O
I
I/O
I
I/O
I
I/O
I
PORT1 consists of the two 8-bit bidirectional I/O ports P1L
and P1H. Each pin can be programmed for input (output driver
in high-impedance state) or output.
The PORT1 pins serve for the following functions:
CC60
CAPCOM6: Input / Output of Channel 0
COUT60 CAPCOM6: Output of Channel 0
CC61
CAPCOM6: Input / Output of Channel 1
COUT61 CAPCOM6: Output of Channel 1
CC62
CAPCOM6: Input / Output of Channel 2
COUT62 CAPCOM6: Output of Channel 2
COUT63 Output of 10-bit Compare Channel
CAPCOM6: Trap Input
CTRAP
CTRAP is an input pin with an internal pullup resistor. A low
level on this pin switches the CAPCOM6 compare outputs to
the logic level defined by software (if enabled).
CC22IO
CAPCOM2: CC22 Capture Inp./Compare Outp.
CC6POS0 CAPCOM6: Position 0 Input,
EX0IN
Fast External Interrupt 0 Input (default pin),
CC23IO
CAPCOM2: CC23 Capture Inp./Compare Outp.
CC6POS1 CAPCOM6: Position 1 Input,
EX1IN
Fast External Interrupt 1 Input (default pin),
MRST1
SSC1 Master-Receive/Slave-Transmit In/Out.
CC6POS2 CAPCOM6: Position 2 Input,
EX2IN
Fast External Interrupt 2 Input (default pin),
MTSR1
SSC1 Master-Transmit/Slave-Receive Out/Inp.
T7IN
CAPCOM2: Timer T7 Count Input,
SCLK1
SSC1 Master Clock Output / Slave Clock Input,
EX3IN
Fast External Interrupt 3 Input (default pin),
CC24IO
CAPCOM2: CC24 Capture Inp./Compare Outp.,
EX4IN
Fast External Interrupt 4 Input (default pin)2)
CC25IO
CAPCOM2: CC25 Capture Inp./Compare Outp.,
EX5IN
Fast External Interrupt 5 Input (default pin)2)
O
I
XTAL2:
XTAL1:
I/O
O
I/O
O
I/O
O
O
I
Output of the oscillator amplifier circuit
Input to the oscillator amplifier and input to
the internal clock generator
To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC Characteristics
must be observed.
7
V1.0D3, 2004-03
XC164CM-8FF
Delta Sheet XC164CM-8FF to XC164CS-16FF
Table 4
Pin Definitions and Functions (cont’d)
Symbol Pin
Num.
Input Function
Outp.
P3
IO
P3.1
28
P3.2
29
P3.3
30
P3.4
31
P3.5
32
P3.6
P3.7
33
34
P3.8
P3.9
P3.10
35
36
37
P3.11
38
P3.13
39
P3.15
42
TRST
62
Draft Delta Sheet
O
I/O
I
I
I
I
O
O
I
I
I
O
O
I
I
I
I/O
I/O
O
I
I/O
I
I/O
I
O
O
I
Port 3 is a 13-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance state)
or output (configurable as push/pull or open drain driver). The
input threshold of Port 3 is selectable (standard or special).
The following Port 3 pins also serve for alternate functions:
T6OUT
GPT2 Timer T6 Toggle Latch Output,
RxD1
ASC1 Data Input (Async.) or Inp./Outp. (Sync.),
EX1IN
Fast External Interrupt 1 Input (alternate pin A),
TCK
Debug System: JTAG Clock Input
CAPIN
GPT2 Register CAPREL Capture Input,
TDI
Debug System: JTAG Data In
T3OUT
GPT1 Timer T3 Toggle Latch Output,
TDO
Debug System: JTAG Data Out
T3EUD
GPT1 Timer T3 External Up/Down Control Input,
TMS
Debug System: JTAG Test Mode Selection
T4IN
GPT1 Timer T4 Count/Gate/Reload/Capture Inp
TxD1
ASC1 Clock/Data Output (Async./Sync.),
BRKOUT Debug System: Break Out
T3IN
GPT1 Timer T3 Count/Gate Input
T2IN
GPT1 Timer T2 Count/Gate/Reload/Capture Inp
Debug System: Break In
BRKIN
MRST0
SSC0 Master-Receive/Slave-Transmit In/Out.
MTSR0
SSC0 Master-Transmit/Slave-Receive Out/In.
TxD0
ASC0 Clock/Data Output (Async./Sync.),
EX2IN
Fast External Interrupt 2 Input (alternate pin B)
RxD0
ASC0 Data Input (Async.) or Inp./Outp. (Sync.),
EX2IN
Fast External Interrupt 2 Input (alternate pin A)
SCLK0
SSC0 Master Clock Output / Slave Clock Input.,
EX3IN
Fast External Interrupt 3 Input (alternate pin A)
CLKOUT System Clock Output (=CPU Clock),
FOUT
Programmable Frequency Output
Test-System Reset Input. A high level at this pin activates the
XC164CM’s debug system and/or the non default
configuration functions on ports 1 and 9. For normal system
operation, pin TRST should be held low.
8
V1.0D3, 2004-03
XC164CM-8FF
Delta Sheet XC164CM-8FF to XC164CS-16FF
Table 4
Pin Definitions and Functions (cont’d)
Symbol Pin
Num.
Input Function
Outp.
P5
I
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.10
P5.11
P5.6
P5.7
P5.12
P5.13
P5.14
P5.15
9
10
11
12
13
14
15
16
17
18
21
22
23
24
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Port 5 is a 14-bit input-only port.
The pins of Port 5 also serve as analog input channels for the
A/D converter, or they serve as timer inputs:
AN0
AN1
AN2
AN3
AN4
AN5
AN10,
T6EUD GPT2 Timer T6 Ext. Up/Down Ctrl. Inp.
AN11,
T5EUD GPT2 Timer T5 Ext. Up/Down Ctrl. Inp.
AN6
AN7
AN12,
T6IN
GPT2 Timer T6 Count/Gate Input
AN13,
T5IN
GPT2 Timer T5 Count/Gate Input
AN14,
T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp.
AN15,
T2EUD GPT1 Timer T2 Ext. Up/Down Ctrl. Inp.
VAREF
VAGND
VDDI
19
-
Reference voltage for the A/D converter.
20
-
Reference ground for the A/D converter.
26, 58 -
Core Supply Voltage (On-Chip Modules):
+2.5 V during normal operation and idle mode.
Please refer to the Operating Conditions
VDDP
8, 27, 40, 57
Pad Supply Voltage (Pin Output Drivers):
+5 V during normal operation and idle mode.
Please refer to the Operating Conditions
VSS
7, 25, 41, 59
Ground.
Connect decoupling capacitors to adjacent VDDx/VSS pin
pairs as close as possible to the pins.
All VSS pins must be connected to the ground-line or groundplane.
1)
The CAN interface lines are assigned to port P9 under software control.
2)
If at the end of an external reset TRST was high these pins are used for sensing configuration settings and
integrated pull up devices are activated during reset.
Draft Delta Sheet
9
V1.0D3, 2004-03
http://www.infineon.com
Published by Infineon Technologies AG
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