isl8205m

DATASHEET
5A Single Channel High Efficiency DC/DC Step-Down
Power Module
ISL8205M
Features
The ISL8205M power module is a single channel synchronous
step-down complete power supply, capable of delivering up to
5A of continuous current. Operating from a single 2.6V to 5.5V
input power rail and integrating controller, power inductor and
MOSFETs, the ISL8205M only requires a few external
components to operate and is optimized for space constrained
and portable battery operated applications.
• 5A single channel complete power supply
- Integrates controller, MOSFETs and inductor
- Pin/function compatible with the 3A ISL8202M
• 2.6V to 5.5V input voltage range
• Adjustable output voltage range
- As low as 0.6V with ±1.6% accuracy over
line/load/temperature
- Up to 95% efficiency
Based on current mode PWM control scheme, the ISL8205M
provides a fast transient response and excellent loop stability
as well as a very low duty cycle with an adjustable output
voltage as low as 0.6V and better than 1.6% accuracy over line
and load conditions. Operation frequency is selectable through
an external resistor, with a 1.8MHz default setting, or may be
synchronized with an external clock signal up to 3.5MHz. The
ISL8205M also implements a selectable PFM mode to
improve light-load efficiency and a 100% duty cycle LDO mode
to extend battery life. A programmable soft-start reduces the
inrush current required from the input supply while an
automatic output discharge ensures a soft stop. Dedicated
enable pin and power-good flag allow for easy system power
rails sequencing.
• Default 1.8MHz current mode control operations
- 680kHz to 3.5MHz resistor adjustable
- External synchronization up to 3.5MHz
- Selectable light-load efficiency mode
- 100% duty cycle LDO mode
• Programmable soft-start
• Soft-stop output discharge
• Dedicated enable pin and power-good flag
• UVLO, over-temperature, overcurrent, overvoltage and
negative overcurrent protections
- Overcurrent/short-circuit hiccup mode
An array of protection features, including input Undervoltage
Lockout (UVLO), over-temperature, overcurrent/short-circuit
with hiccup mode, overvoltage and negative overcurrent,
guarantees safe operations under abnormal operating
conditions.
• 4.5mmx7.5mmx1.85mm 22 Ld QFN package
Applications
The ISL8205M is available in a compact RoHS compliant
22 Ld 4.5x7.5x1.85mm QFN package.
• DC to DC POL power module
Related Literature
• Portable equipment
• TB389, “PCB Land Pattern Design and Surface Mount
Guidelines for QFN Packages”
• Battery operated equipment
• µC/µP, FPGA and DSP power
• UG072, “ISL8205MEVAL1Z Evaluation Board User Guide”
100.0
ISL8205M
CIN
2x22µF
1.2V 5A
OUTPUT
VIN
VOUT
EN
SW
PG
VSENSE
FB
FS
SS
RFS
124k
90.0
COUT
2x22µF
COMP
SYNC
EPAD
SGND
PGND
95.0
RSET
100k
CFF
820pF
EFFICIENCY (%)
2.6V TO 5.5V
INPUT
85.0
80.0
75.0
Vout=1.2V, Fsw=1.6MHz PWM
Vout=1.2V, Fsw=1.6MHz PFM
Vout=3.3V, Fsw=3MHz PFM
Vout=3.3V, Fsw=3MHz PWM
70.0
65.0
60.0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
LOAD CURRENT (A)
FIGURE 1. TYPICAL APPLICATION DIAGRAM AT 5VIN, 1.2VOUT, 1.6MHz fSW, 5A
May 19, 2016
FN8755.2
1
FIGURE 2. EFFICIENCY vs LOAD 5VIN
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL8205M
Table of Contents
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Efficiency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Output Voltage Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Load Transient Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Short-Circuit Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PFM (SKIP) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency Adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative Current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Synchronization Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Discharge Mode (Soft-Stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100% Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
15
15
15
16
16
16
16
16
16
16
16
16
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming the Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Feed-Forward Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Consideration and Current Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
16
17
17
17
17
18
18
PCB Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCB Layout Pattern Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stencil Pattern Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reflow Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
20
20
20
20
20
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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May 19, 2016
ISL8205M
Functional Block Diagram
SS
COMP
FS
SYNC
18
16
13
SHUTDOWN
SOFTSTART
17
SHUTDOWN
EN
FB
15
BANDGAP
OSCILLATOR
VREF
COMP
EAMP
PWM/PFM LOGIC
CONTROLLER
PROTECTION
HS DRIVER
L
LS
DRIVER
19
11
VIN
21
SW
6
VOUT
9
SW
3
PGND
20
PGND
14
PGND
4
VSENSE
2
VSENSE
22
SGND
0.8V
FB
SLOPE
COMP
1
OV
CSA
51
OCP
UV
0.85 x VREF
ISET
THRESHOLD
SKIP
PG
12
1ms
DELAY
NEGATIVE CURRENT
SENSING
ZERO-CROSSING
SENSING
SCP
0.5V
100
SGND
PGND
SHUTDOWN
100k0.5%
FIGURE 3. FUNCTIONAL BLOCK DIAGRAM
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ISL8205M
Pin Configuration
ISL8205M
(22 LD QFN)
TOP VIEW
PGND SYNC PG
EN
15
FS
16
SS
17
COMP
18
FB
19
13
NC
SW
11
10
9
12
m
7.5m
mm
4.5
14
VIN
1 .8 5
20
21
PGND
22
mm
SW
8
NC
7
NC
SGND
1
2
3
FB
VSENSE
PGND
4
5
VSENSE NC
6
VOUT
Pin Descriptions
PIN
NUMBER
PIN
NAME
1, 19
FB
Voltage setting pin. Module output voltage is set by connecting a resistor, RSET, from this pin to SGND. A ceramic
capacitor is also recommended to be placed in parallel with RSET from FB to SGND to ensure system stability in extreme
operation conditions. Refer to Table 2 on page 14 for the resistor and capacitor values for various typical output voltage.
2, 4
VSENSE
Voltage sense pin. Pins 2 and 4 are shorted together internally. An internal 51Ω resistor is connected from VOUT (Pad 6)
to VSENSE for local output voltage feedback in case remote sensing is not present. To achieve best regulation
performance at point of load, remote sensing trace needs to be directly routed to VSENSE.
3, 14
PGND
Power ground. Power ground pins. Place output capacitor across VOUT and PGND close to Pin 3 since it is the return
path for output current.
5, 7, 8, 10
NC
6
VOUT
Power output. Power output of the module. Output capacitors should be placed across this pad and Pin 3 PGND and
close to the module. Apply load between this pin and PGND Pin 3. Output voltage range: 0.6V to 5V.
9, 21
SW
Switching node. These pins can be used to monitor switch node waveform to examine switching frequency. These pins
can also be used for snubber connection. To improve system efficiency, it is recommended to connect Pins 9 and 21
with wide copper shape. However, avoid connecting SW to large copper shape to minimize radiated EMI noise.
11
VIN
Power input. Input voltage range: 2.6V to 5.5V. Tie directly to the input rail. It is required to have a minimum total input
capacitance of 44µF at module input. Add additional capacitance if possible. Use X5R or X7R ceramic capacitors. It is
critical to place input ceramic capacitors as close as possible to module input. Refer to “PCB Layout
Recommendations” on page 19 for more information.
12
PG
Power-good pin. Power-good is an open-drain output. Use a 10kΩ to 100kΩ pull-up resistor connected between VIN and
PG. During power-up or EN pin start-up, PG rising edge is delayed by 1ms upon output reached within regulation.
13
SYNC
Synchronization pin. Mode selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low
or ground for PFM mode. Connect to an external clock for synchronization with the positive edge trigger. There is an
internal 1MΩ pull-down resistor to prevent an undefined logic state in case SYNC pin is floating. Therefore, PFM mode
is enabled when SYNC is left floating.
15
EN
Power enable pin. Enables the output, when driven high. Shuts down the output and discharges the output capacitor
when driven low. Typically tie to VIN pin directly. Do not leave this pin floating.
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DESCRIPTION
No connection pins. These pins have no connections inside. Leave these pins floating.
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May 19, 2016
ISL8205M
Pin Descriptions (Continued)
PIN
NUMBER
PIN
NAME
16
FS
Frequency selection pin. This pin sets the module switching frequency. The default frequency is 1.8MHz if FS is
connected to VIN. In spite of default setting, a resistor, RFS, can be connected from the FS pin to SGND to adjust
switching frequency ranging from 680kHz to 3.5MHz.
17
SS
Soft-start pin. SS is used to adjust the soft-start time. Connect to SGND for internal 1ms rise time. Connect a capacitor
from SS to SGND to adjust the soft-start time. The capacitor value should be less than 33nF to ensure proper operation.
18
COMP
Compensation pin. COMP is the output of the voltage feedback error amplifier. For most applications, the internal
compensation network can be used to stabilize the system and achieve optimal transient response. This can be done
by directly connecting COMP to VIN. For other applications where external compensation is desired, COMP needs to be
disconnected from VIN and tied to the external compensation network.
Exposed
Pad 20
PGND
The exposed pad is connected internally to PGND. Solid connection should be made between Pad 20 and PGND plane
on PCB. Place as many vias as possible under the pad connecting to PGND plane(s) for optimal electrical and thermal
performance. Refer to “PCB Layout Recommendations” on page 19 for more information.
22
SGND
Signal ground pin. Connect PCB SGND plane to this pin. Internally, this pin is single-point connected to module PGND.
DESCRIPTION
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
TAPE AND REEL
(UNITS)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL8205MIRZ-T
ISL8205M
-40 to +85
4k
22 Ld QFN
L22.4.5x7.5
ISL8205MIRZ-T7A
ISL8205M
-40 to +85
250
22 Ld QFN
L22.4.5x7.5
ISL8205MEVAL1Z
Evaluation Board
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL8205M. For more information on MSL, please see Technical Brief
TB363.
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART
NUMBER
MAX OUTPUT CURRENT IOUT
(DC)
ISL8205M
5A
ISL8203M
3A dual, 6A single
ISL8202M
3A
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FN8755.2
May 19, 2016
ISL8205M
Absolute Maximum Ratings
Thermal Information
(Reference to GND)
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
22 Ld QFN (Notes 4, 5) . . . . . . . . . . . . . . . .
27.4
4.8
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.8V (DC) or 7V (20ms)
EN, FS, PG, SYNC, VFB . . . . . . . . . . . . . . . . . . . . . . . .-0.3V (DC) to VIN +0.3V
SW . . . . . . . . . . . . . . . -1.5V (100ns)/-0.3V (DC) to 6.5V (DC) or 7V (20ms)
COMP, SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
ESD Ratings
Human Body Model (Tested per JS-001-2010) . . . . . . . . . . . . . . . . . . 2kV
Charged Device Model (Tested per JS-002-2014) . . . . . . . . . . . . . . 750V
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . . 200V
Latch-Up (Tested per JESD-78D; Class 2, Level A) . . . . . 100mA at +85°C
Recommended Operating Conditions
VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6V to 5.5V
VOUT Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.6V to 5V
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 5A
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on the ISL8205MEVAL1Z evaluation board with “direct attach” features. Refer to
ISL8205MEVAL1Z User Guide for evaluation board details. Also see Tech Brief TB379 for general thermal metric information.
5. For JC, “case temperature” location is at the center of the exposed metal pad on the package underside.
Electrical Specifications Unless otherwise noted, typical specifications are measured at VIN = 3.6V, VOUT = 1.2V, TA = +25°C.
Boldface limits apply across the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
VIN Undervoltage Lockout Threshold (Note 7)
VUVLO
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
2.3
2.5
V
INPUT SUPPLY
Rising, no load
Falling, no load
Quiescent Supply Current
IVIN
Shutdown Supply Current
ISD
2.10
2.25
V
SYNC = GND, EN = high, IOUT = 0A
50
µA
SYNC = VIN, fSW = 1.6MHz, EN = high,
IOUT = 0A
18
24
mA
SYNC = GND, VIN = 5.5V, EN = low
5
20
µA
5
A
OUTPUT REGULATION
Output Continuous Current Range
IOUT(DC)
Line Regulation
ΔVOUT/VOUT VIN = 2.6V to 5.5V, VOUT = 1.2V, fSW = 1.6MHz,
IOUT = 0A, PWM mode
0.65
%
VIN = 2.6V to 5.5V, VOUT = 1.2V, fSW = 1.6MHz,
IOUT = 5A, PWM mode
0.46
%
VIN = 5V, VOUT = 1.2V, fSW = 1.6MHz,
IOUT = 0A to 5A, PWM mode
0.6
%
VIN = 5V, VOUT = 3.3V, fSW = 3MHz,
IOUT = 0A to 5A, PWM mode
0.62
%
Load Regulation
Output Voltage Accuracy (Note 8)
Over line/load/temperature range, PWM
mode, VOUT = 1.2V to 3.3V
Output Ripple Voltage
ΔVOUT
Reference Voltage (Note 7)
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VREF
6
-1.6
1.6
%
VIN = 5V, 2x22µF ceramic output capacitor,
PWM mode
IOUT = 0A, VOUT = 1.2V, fSW = 1.6MHz
11
mVP-P
IOUT = 5A, VOUT = 1.2V, fSW = 1.6MHz
12
mVP-P
IOUT = 0A, VOUT = 3.3V, fSW = 3MHz
8
mVP-P
IOUT = 5A, VOUT = 3.3V, fSW = 3MHz
10
mVP-P
0.594
0.600
0.606
V
FN8755.2
May 19, 2016
ISL8205M
Electrical Specifications Unless otherwise noted, typical specifications are measured at VIN = 3.6V, VOUT = 1.2V, TA = +25°C.
Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
VFB Bias Current (Note 7)
IFB
Soft-Start Ramp Time Cycle (Note 7)
Soft-Start Charging Current (Note 7)
TEST CONDITIONS
MIN
(Note 6)
VFB = 0.75V
SS = GND
ISS
VSS = 0.1V
1.45
TYP
MAX
(Note 6)
UNIT
0.1
µA
1
ms
1.85
2.25
µA
DYNAMIC CHARACTERISTICS
Voltage Change for Positive Load Step
ΔVOUT-DP
Current slew rate = 1A/µs, VIN = 5V, 2 x 22µF
ceramic output capacitor
VOUT = 1.2V, IOUT = 0A to 5A, fSW = 1.6MHz
120
mVP-P
69
mVP-P
VOUT = 1.2V, IOUT = 5A to 0A, fSW = 1.6MHz
127
mVP-P
VOUT = 3.3V, IOUT = 5A to 0A, fSW = 3MHz
79
mVP-P
VOUT = 3.3V, IOUT = 0A to 5A, fSW = 3MHz
Voltage Change for Negative Load Step
ΔVOUT-DP
Current slew rate = 1A/µs, VIN = 5V, 2 x 22µF
ceramic output capacitor
OVERCURRENT PROTECTION (Note 7)
Current Limit Blanking Time
tOCON
17
Clock pulses
Overcurrent and Auto Restart Period
tOCOFF
8
SS cycle
Positive Peak Overcurrent Limit
IPLIMIT
7.5
9
11
A
ISKIP
1
1.3
1.8
A
300
mA
Positive Skip Limit
Zero Cross Threshold
-300
Negative Current Limit
INLIMIT
-4.5
-3
-1.5
A
Rt
0.119
0.140
0.166
Ω
COMPENSATION (Note 7)
Current Sensing Gain
Error Amplifier Transconductance
Internal compensation
60
µA/V
External compensation
120
µA/V
VIN = 5V, IO = 200mA
36
63
mΩ
VIN = 2.7V, IO = 200mA
52
89
mΩ
VIN = 5V, IO = 200mA
13
30
mΩ
VIN = 2.7V, IO = 200mA
17
36
mΩ
SWITCH NODE (Note 7)
P-Channel MOSFET ON-Resistance
N-Channel MOSFET ON-Resistance
SW Maximum Duty Cycle
100
SW Minimum On-Time
SYNC = High
%
115
ns
2070
kHz
OSCILLATOR
Nominal Switching Frequency
fSW
SYNC = VIN
1835
fSW with RFS = 261kΩ
800
kHz
fSW with RFS = 124kΩ
1600
kHz
SYNC Logic LOW to HIGH Transition Range
0.70
SYNC Hysteresis
0.75
0.80
0.15
SYNC Logic Input Leakage Current
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1600
7
VIN = 3.6V
3.6
V
V
5
µA
FN8755.2
May 19, 2016
ISL8205M
Electrical Specifications Unless otherwise noted, typical specifications are measured at VIN = 3.6V, VOUT = 1.2V, TA = +25°C.
Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
0.3
V
0.10
µA
PG (Note 7)
Output Low Voltage
PG Pin Leakage Current
PG = VIN
0.01
OVP PG Rising Threshold
0.80
UVP PG Rising Threshold
80
UVP PG Hysteresis
85
V
90
30
PGOOD Delay Time (Rising Edge)
Time from VOUT reaching regulation
0.5
PGOOD Delay Time (Falling Edge)
1
%
mV
2
7.5
ms
µs
EN (Note 7)
Logic Input Low
0.4
Logic Input High
0.9
V
V
Enable Logic Input Leakage Current
Pulled up to 3.6V
0.1
1
µA
Thermal Shutdown
Temperature Rising
150
°C
Thermal Shutdown Hysteresis
Temperature Falling
25
°C
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. Parameters with MIN and/or MAX limits are 100% tested for internal IC prior to module assembly, unless otherwise specified. Temperature limits
established by characterization and are not production tested.
8. A 0.1% tolerance resistor is used for RSET.
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ISL8205M
Typical Performance Characteristics
Efficiency
TA = +25°C.
100.0
100.0
95.0
95.0
EFFICIENCY (%)
EFFICIENCY (%)
90.0
85.0
80.0
75.0
Vout=1V, Fsw=1.3MHz
Vout=1.2V, Fsw=1.6MHz
Vout=1.8V, Fsw=2MHz
Vout=2.5V, Fsw=2.5MHz
70.0
65.0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
85.0
80.0
Vout=1V, Fsw=1.3MHz
Vout=1.2V, Fsw=1.6MHz
Vout=1.8V, Fsw=2MHz
Vout=2.5V, Fsw=2.5MHz
Vout=3.3V, Fsw=3MHz
75.0
70.0
65.0
60.0
60.0
0
90.0
0
5
0.5
1
1.5
100.0
100.0
95.0
95.0
90.0
90.0
85.0
80.0
Vout=1V, Fsw=1.3MHz
Vout=1.2V, Fsw=1.6MHz
70.0
Vout=1.8V, Fsw=2MHz
65.0
2.5
3
3.5
4
4.5
5
FIGURE 5. EFFICIENCY TA = +25°C, VIN = 5V PFM MODE
EFFICIENCY (%)
EFFICIENCY (%)
FIGURE 4. EFFICIENCY TA = +25°C, VIN = 3.3V PFM MODE
75.0
2
LOAD CURRENT (A)
LOAD CURRENT (A)
85.0
80.0
Vout=1V, Fsw=1.3MHz
Vout=1.2V, Fsw=1.6MHz
Vout=1.8V, Fsw=2MHz
Vout=2.5V, Fsw=2.5MHz
Vout=3.3V, Fsw=3MHz
75.0
70.0
65.0
Vout=2.5V, Fsw=2.5MHz
60.0
60.0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
LOAD CURRENT (A)
FIGURE 6. EFFICIENCY TA = +25°C, VIN = 3.3V PWM MODE
Output Voltage Ripple
1µs/DIV
FIGURE 8. VIN = 5V, VOUT = 3.3V, IOUT = 0A, fSW = 3MHz,
COUT = 2 x 22µF CERAMIC CAPACITORS
9
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
LOAD CURRENT (A)
FIGURE 7. EFFICIENCY TA = +25°C, VIN = 5V PWM MODE
TA = +25°C.
20mV/DIV
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5
20mV/DIV
1µs/DIV
FIGURE 9. VIN = 5V, VOUT = 3.3V, IOUT = 5A, fSW = 3MHz,
COUT = 2 x 22µF CERAMIC CAPACITORS
FN8755.2
May 19, 2016
ISL8205M
Typical Performance Characteristics
(Continued)
20mV/DIV
20mV/DIV
1µs/DIV
1µs/DIV
FIGURE 10. VIN = 5V, VOUT = 1.2V, IOUT = 0A, fSW = 1.6MHz,
COUT = 2 x 22µF CERAMIC CAPACITORS
FIGURE 11. VIN = 5V, VOUT = 1.2V, IOUT = 5A, fSW = 1.6MHz,
COUT = 2 x 22µF CERAMIC CAPACITORS
20mV/DIV
20mV/DIV
1µs/DIV
1µs/DIV
FIGURE 12. VIN = 3.3V, VOUT = 2.5V, IOUT = 0A, fSW = 2.5MHz,
COUT = 2 x 22µF CERAMIC CAPACITORS
Load Transient Response
TA = +25°C, load current step slew rate: 1A/µs.
IOUT 2A/DIV
IOUT 2A/DIV
VOUT 50mV/DIV
VOUT 50mV/DIV
100µs/DIV
100µs/DIV
FIGURE 14. VIN = 5V, VOUT = 1V, IOUT = 0 TO 5A, fSW = 1.3MHz,
COUT = 2 x 22µF CERAMIC CAPACITORS
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FIGURE 13. VIN = 3.3V, VOUT = 2.5V, IOUT = 5A, fSW = 2.5MHz,
COUT = 2 x 22µF CERAMIC CAPACITORS
10
FIGURE 15. VIN = 5V, VOUT = 1.2V, IOUT = 0 TO 5A, fSW = 1.6MHz,
COUT = 2 x 22µF CERAMIC CAPACITORS
FN8755.2
May 19, 2016
ISL8205M
Typical Performance Characteristics
(Continued)
IOUT 2A/DIV
IOUT 2A/DIV
VOUT 50mV/DIV
VOUT 50mV/DIV
100µs/DIV
100µs/DIV
FIGURE 16. VIN = 5V, VOUT = 2.5V, IOUT = 0 TO 5A, fSW = 2.5MHz,
COUT = 2 x 22µF CERAMIC CAPACITORS
Start-Up
FIGURE 17. VIN = 5V, VOUT = 3.3V, IOUT = 0 TO 5A, fSW = 3MHz,
COUT = 2 x 22µF CERAMIC CAPACITORS
TA = +25°C, Resistor load is used in the test.
SW 5V/DIV
SW 5V/DIV
VOUT 500mV/DIV
VOUT 500mV/DIV
IOUT 2A/DIV
PGOOD 5V/DIV
PGOOD 5V/DIV
IOUT 1A/DIV
500µs/DIV
500µs/DIV
FIGURE 18. SOFT-START WITH 0A LOAD PWM MODE, VIN = 5V,
VOUT = 1.2V, IOUT = 0A, COUT = 2 x 22µF CERAMIC
CAPACITORS, CIN = 100µF POSCAP + 2 x 22µF
CERAMIC CAPACITORS
FIGURE 19. SOFT-START WITH 5A LOAD PWM MODE, VIN = 5V,
VOUT = 1.2V, IOUT = 5A, COUT = 2 x 22µF CERAMIC
CAPACITORS, CIN = 100µF POSCAP + 2 x 22µF
CERAMIC CAPACITORS
SW 5V/DIV
SW 5V/DIV
VOUT 500mV/DIV
VOUT 500mV/DIV
PGOOD 5V/DIV
IOUT 2A/DIV
PGOOD 5V/DIV
IOUT 2A/DIV
500µs/DIV
FIGURE 20. SOFT-START WITH 0A LOAD PFM MODE, VIN = 5V,
VOUT = 1.2V, IOUT = 0A, COUT = 2 x 22µF CERAMIC
CAPACITORS, CIN = 100µF POScap + 2 x 22µF
CERAMIC CAPACITORS
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500µs/DIV
FIGURE 21. SOFT-START WITH 5A LOAD PFM MODE, VIN = 5V,
VOUT = 1.2V, IOUT = 5A, COUT = 2 x 22µF CERAMIC
CAPACITORS, CIN = 100µF POSCAP + 2 x 22µF
CERAMIC CAPACITORS
FN8755.2
May 19, 2016
ISL8205M
Typical Performance Characteristics
(Continued)
SW 5V/DIV
SW 5V/DIV
VOUT 500mV/DIV
VOUT 500mV/DIV
PGOOD 5V/DIV
PGOOD 5V/DIV
IOUT 2A/DIV
IOUT 2A/DIV
500µs/DIV
500µs/DIV
FIGURE 23. PREBIAS SOFT-START WITH 0A LOAD PFM MODE,
VIN = 5V, VOUT = 1.2V, IOUT = 0A, COUT = 2 x 22µF
CERAMIC CAPACITORS, CIN = 100µF POSCAP +
2 x 22µF CERAMIC CAPACITORS
FIGURE 22. PREBIAS SOFT-START WITH 0A LOAD PWM MODE,
VIN = 5V, VOUT = 1.2V, IOUT = 0A, COUT = 2 x 22µF
CERAMIC CAPACITORS, CIN = 100µF POSCAP +
2 x 22µF CERAMIC CAPACITORS
Short-Circuit Protection TA = +25°C, VIN = 5V, VOUT = 1.2V, CIN = 100µF POScap + 22µF ceramic capacitors, COUT = 2 x 22µF ceramic
capacitors, output short-circuit during normal operation.
SW 2V/DIV
SW 2V/DIV
VOUT 500mV/DIV
VOUT 500mV/DIV
IIN 2A/DIV
IIN 2A/DIV
PGOOD 2V/DIV
PGOOD 2V/DIV
3.2ms/DIV
10µs/DIV
FIGURE 24. OUTPUT SHORT-CIRCUIT PROTECTION
FIGURE 25. OUTPUT SHORT-CIRCUIT PROTECTION, HICCUP MODE
SW 2V/DIV
VOUT 500mV/DIV
IIN 2A/DIV
PGOOD 2V/DIV
3.2ms/DIV
FIGURE 26. OUTPUT SHORT-CIRCUIT RECOVER FROM HICCUP
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ISL8205M
Typical Performance Characteristics
Overvoltage Protection
(Continued)
TA = +25°C, VIN = 5V, VOUT = 1.2V, CIN = 100µF POScap + 22µF ceramic capacitors, COUT = 2 x 22µF ceramic
capacitors.
SW 2V/DIV
VOUT 500mV/DIV
PGOOD 5V/DIV
500µs/DIV
FIGURE 27. OUTPUT OVERVOLTAGE PROTECTION
Power Loss
TA = +25°C, CIN = 100µF POScap + 22µF ceramic capacitors, COUT = 2 x 22µF ceramic capacitors.
2.0
Vout=1.2V, Fsw=1.6MHz PWM
1.8
Vout=3.3V, Fsw=3MHz PWM
2.2
1.6
POWER LOSS (W)
POWER LOSS (W)
2.2
1.4
1.2
1.0
0.8
0.6
2.0
Vout=1.2V, Fsw=1.6MHz PWM
1.8
Vout=2.5V, Fsw=2.5MHz PWM
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.4
0.2
0.2
0.0
0.0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
LOAD CURRENT (A)
FIGURE 28. POWER LOSS AT VIN = 5V, TA = +25°C
2.5
3
3.5
4
4.5
5
FIGURE 29. POWER LOSS AT VIN = 3.3V, TA = +25°C
All of the following curves were plotted at TJ = +120°C.
6.0
6.0
5.0
5.0
LOAD CURRENT (A)
LOAD CURRENT (A)
Derating
2
LOAD CURRENT (A)
4.0
3.0
2.0
200 LFM
1.0
4.0
3.0
2.0
200 LFM
1.0
0 LFM
0 LFM
0.0
0.0
0
10
20
30
40
50
60
70
80
90 100 110 120
AMBIENT TEMPERATURE (°C)
FIGURE 30. DERATING CURVES AT VIN = 5V, VOUT = 1.2V
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13
0
10
20
30
40
50
60
70
80
90 100 110 120
AMBIENT TEMPERATURE (°C)
FIGURE 31. DERATING CURVES AT VIN = 5V, VOUT = 3.3V
FN8755.2
May 19, 2016
ISL8205M
(Continued)
6.0
6.0
5.0
5.0
LOAD CURRENT (A)
LOAD CURRENT (A)
Typical Performance Characteristics
4.0
3.0
2.0
200 LFM
1.0
4.0
3.0
2.0
200 LFM
1.0
0 LFM
0 LFM
0.0
0.0
0
10
20
30
40
50
60
70
80
90 100 110 120
0
10
20
30
40
50
60
70
80
90 100 110 120
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 32. DERATING CURVES AT VIN = 3.3V, VOUT = 1.2V
FIGURE 33. DERATING CURVES AT VIN = 3.3V, VOUT = 2.5V
TABLE 2. ISL8205M DESIGN GUIDE MATRIX (REFER TO Figure 1)
VIN (V)
VOUT (V)
fSW (MHz)
CIN (µF)
COUT (µF)
RFS (kΩ)
RSET (kΩ)
CFF (pF)
5
0.6
0.8
2x22
1x100
261
OPEN
390
5
0.9
1.2
2x22
3x22
169
200
560
5
1
1.3
2x22
3x22
154
150
560
5
1.2
1.6
2x22
2x22
124
100
820
5
1.5
1.7
2x22
2x22
115
66.5
560
5
1.8
2
2x22
2x22
95.3
49.9
470
5
2.5
2.5
2x22
2x22
75
31.6
330
5
3.3
3
2x22
2x22
59
22.1
330
3.3
0.6
0.8
2x22
1x100
261
OPEN
390
3.3
0.9
1.2
2x22
3x22
169
200
560
3.3
1
1.3
2x22
3x22
154
150
560
3.3
1.2
1.6
2x22
2x22
124
100
820
3.3
1.5
1.7
2x22
2x22
115
66.5
560
3.3
1.8
2
2x22
2x22
95.3
49.9
470
3.3
2.5
2.5
2x22
2x22
75
31.6
330
PWM
PFM
PWM
CLOCK
16 CYCLES
PFM CURRENT LIMIT
IL
LOAD CURRENT
0
NOMINAL +1.2%
VOUT
NOMINAL
NOMINAL -2.5%
FIGURE 34. PFM MODE OPERATION WAVEFORMS
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ISL8205M
Functional Description
The ISL8205M is a single channel 5A step-down high efficiency
power module optimized for FPGA, DSP and Li-ion battery power
devices. The module switches at 1.8MHz by default when the FS
pin is shorted to VIN. The switching frequency is also adjustable
from 680kHz to 3.5MHz through a resistor, RFS, from FS to
SGND. To boost light-load efficiency, ISL8205M can also be
configured to operate in PFM mode by pulling the SYNC pin to
SGND. Peak current mode control scheme is implemented for
fast transient response. By shorting the COMP pin to VIN, the
module utilizes internal compensation to stabilize system and
optimize transient response. Other excellent features include
external synchronization, 100% duty cycle operation and very low
quiescent current.
PWM Control Scheme
Pulling the SYNC pin high (>0.8V) forces the module into PWM
mode, regardless of output current. The ISL8205M employs the
current-mode Pulse-Width Modulation (PWM) control scheme for
fast transient response and pulse-by-pulse current limiting. As
shown in Figure 3 on page 3, the current loop consists of the
oscillator, the PWM comparator, current sensing circuit and the
slope compensation for the current loop stability. The slope
compensation is 440mV/Ts, which changes with frequency. The
gain for the current sensing circuit is typically 140mV/A. The
control reference for the current loops comes from the Error
Amplifier's (EAMP) output.
The PWM operation is initialized by the clock from the oscillator.
The P-channel MOSFET is turned on at the beginning of a PWM
cycle and the current in the MOSFET starts to ramp-up. When the
sum of the current amplifier, CSA and the slope compensation
reaches the control reference of the current loop, the PWM
comparator COMP sends a signal to the PWM logic to turn off the
PFET and turn on the N-channel MOSFET. The NFET stays on until
the end of the PWM cycle. Figure 35 shows the typical operating
waveforms during the PWM operation. The dotted lines illustrate
the sum of the slope compensation ramp and the Current-Sense
Amplifier’s (CSA) output.
start-up and will be discussed separately, please refer to “Soft
Start-Up” on page 16. The error amplifier is a transconductance
amplifier that converts the voltage error signal to a current
output. When the COMP is tied to VIN, the voltage loop is
internally compensated with the 55pF and 100kΩ RC network.
PFM (SKIP) Mode
Pulling the SYNC pin LOW (<0.4V) forces the module into PFM
mode. The ISL8205M enters a pulse-skipping mode at light load
to minimize the switching losses by reducing the switching
frequency. Figure 34 illustrates the skip mode operation. A
zero-cross sensing circuit shown in Figure 3 on page 3 monitors
the NFET current for zero crossing. When 16 consecutive cycles
are detected, the module enters the skip mode. During the
sixteen detecting cycles, the current in the inductor is allowed to
become negative. The counter is reset to zero when the current in
any cycle does not cross zero.
Once the skip mode is entered, the pulse modulation starts being
controlled by the skip comparator shown in Figure 3 on page 3.
Each pulse cycle is still synchronized by the PWM clock. The PFET
is turned on at the clock's rising edge and turned off when the
output is higher than 1.2% of the nominal regulation or when its
current reaches the peak skip current limit value. Then, the
inductor current is discharged to 0A and stays at zero (the
internal clock is disabled) and the output voltage reduces
gradually due to the load current discharging the output
capacitor. When the output voltage drops to the nominal voltage,
the PFET will be turned on again at the rising edge of the internal
clock as it repeats the previous operations. The module resumes
normal PWM mode operation when the output voltage drops
2.5% below the nominal voltage.
Frequency Adjust
The switching frequency of ISL8205M is adjustable ranging from
680kHz to 3.5MHz via a simple resistor RFS across FS to SGND. The
switching frequency setting is based on Equation 1:
220  10 3
R FS  k  = ------------------------------ – 14
f OSC  kHz 
(EQ. 1)
When the FS pin is directly tied to VIN, the frequency of operation
is fixed at 1.8MHz. For selections of switching frequency of
typical operation conditions, refer to Table 2 on page 14. More
detailed information on recommended switching frequency is
provided in “Recommended Switching Frequency” on page 17.
VEAMP
VCSA
DUTY
CYCLE
Overcurrent Protection
IL
VOUT
FIGURE 35. PWM OPERATION WAVEFORMS
The output voltage is regulated by controlling the VEAMP voltage
to the current loop. The bandgap circuit outputs a 0.6V reference
voltage to the voltage loop. The feedback signal comes from the
VFB pin. The soft-start block only affects the operation during
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15
The overcurrent protection is realized by monitoring the CSA
output with the OCP comparator, as shown in Figure 3 on page 3.
The current sensing circuit has a gain of 140mV/A, from the
PFET current to the CSA output. When the CSA output reaches
the threshold, the OCP comparator is tripped and turns off the
PFET immediately. The overcurrent function protects the module
from a shorted output by monitoring the current flowing through
the upper MOSFET.
Upon detection of an overcurrent condition, the upper MOSFET
will be immediately turned off and will not be turned on again
until the next switching cycle. Upon detection of the initial
overcurrent condition, the overcurrent fault counter is set to 1. If,
FN8755.2
May 19, 2016
ISL8205M
on the subsequent cycle, another overcurrent condition is
detected, the OC fault counter will be incremented. If there are
17 sequential OC fault detections, the module will be shut down
under an overcurrent fault condition. An overcurrent fault
condition will result in the module attempting to restart in a
hiccup mode within the delay of eight soft-start periods. At the
end of the 8th soft-start wait period, the fault counters are reset
and soft-start is attempted again. If the overcurrent condition
goes away during the delay of 8 soft-start periods, the output will
resume back into regulation after hiccup mode expires.
Negative Current Protection
Similar to overcurrent, the negative current protection is realized
by monitoring the current across the low-side NFET, as shown in
Figure 3 on page 3. When the valley point of the inductor current
reaches -3A for 4 consecutive cycles, both PFET and NFET are
turned off. The 100Ω in parallel to the NFET will activate
discharging the output into regulation. The control will begin to
switch when output is within regulation. The module will be in PFM
for 20µs before switching to PWM, if necessary.
Power-Good
PG is an open-drain output of a window comparator that
continuously monitors the module output voltage. PG is actively
held low when EN is low and during the module soft-start period.
After 1ms delay of the soft-start period, PG becomes high
impedance as long as the output voltage is within the nominal
regulation voltage set by VFB. Under output overvoltage fault
condition (output voltage is 33% higher than nominal value) or
output undervoltage fault condition (output voltage is 15% lower
than nominal value), the PG will be pulled low. Any fault condition
forces PG low until the fault condition is cleared by attempts to
soft-start. For logic level output voltages, connect an external
pull-up resistor between PG and VIN. A 100kΩ resistor works well
in most applications.
Tie SS to SGND for internal soft-start, which is approximately
1ms. Connect a capacitor from SS to SGND to adjust the
soft-start time. This capacitor, along with an internal 1.85µA
current source sets the soft-start interval of the module, tSS, as
shown by Equation 2.
C SS  F  = 3.1  t SS  s 
(EQ. 2)
CSS must be less than 33nF to insure proper soft-start reset after
fault condition.
External Synchronization Control
The frequency of operation can be synchronized up to 3.5MHz by
an external signal applied to the SYNC pin. The rising edge of
SYNC signal triggers the rising edge of PWM ON pulse. To ensure
proper operation, it is recommended that the external SYNC
frequency is within ±25% of the switching frequency set by FS
pin.
Enable
The enable (EN) input allows the user to control the turning on or off
of the module for purposes such as power-up sequencing. When the
module is enabled, there is typically a 600µs delay for waking up
the bandgap reference and then the soft start-up begins.
Discharge Mode (Soft-Stop)
When a transition to shutdown mode occurs or the VIN UVLO is
set, the output discharges to PGND through an internal 100Ω
switch.
100% Duty Cycle
The ISL8205M features a 100% duty cycle operation to minimize
switching loss. When the input voltage drops to a level that the
ISL8205M can no longer maintain the regulation at the output,
the module completely turns on the PFET.
UVLO
Thermal Shutdown
When the input voltage is below the Undervoltage Lockout
(UVLO) threshold, the module is disabled.
The ISL8205M has built-in thermal protection. When the internal
temperature reaches +150°C, the module is completely shut down.
As the temperature drops to +125°C, the ISL8205M, resumes
operation by stepping through the soft-start.
Soft Start-Up
The soft start-up reduces the inrush current during the start-up.
The soft-start block outputs a ramp reference to the input of the
error amplifier. This voltage ramp limits the inductor current as
well as the output voltage speed, so that the output voltage rises
in a controlled fashion. When VFB is less than 0.1V at the
beginning of the soft-start, the switching frequency is reduced to
200kHz, so that the output can start-up smoothly at light load
condition. During soft-start, the IC operates in the Skip mode to
support prebiased output condition.
Applications Information
Programming the Output Voltage
The output voltage of the module is programmed by an external
resistor, as RSET in Figure 1 on page 1 applied from FB pin to
SGND. RSET in combination with the internal 100kΩ 0.5%
resistor connected from FB to VSENSE forms a resistor divider
that sets the output voltage. The output voltage is governed by
Equation 3.
R SET + 100k
V OUT = V REF  ---------------------------------------R
SET
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16
(EQ. 3)
FN8755.2
May 19, 2016
ISL8205M
Where:
TABLE 3. TYPICAL VOLTAGE SETTING RESISTOR VALUES
VOUT (V)
RSET (kΩ)
0.6
OPEN
0.8
300
1.0
150
1.2
100
1.8
49.9
2.5
31.6
3.3
22.1
• CIN(MIN) is the minimum required input capacitance (µF)
• IO is the output current (A)
• D is the duty cycle
• VP-P is the allowable peak-to-peak voltage (V)
• fSW is the switching frequency (Hz)
Please note that the output voltage accuracy is also dependent
on the resistor accuracy of RFS. The user needs to select high
accuracy resistors in order to achieve the overall output accuracy.
Recommended Switching Frequency
With varieties of input and output voltage combinations, one
must choose wisely on which frequency to operate at. Selection
of switching frequency for each VIN and VOUT combination needs
to take in to account a few trade-offs. Generally, lower switching
frequency will lead to higher efficiency. But switching frequency
should not be decreased too low due to negative current
protection limit. Moreover, when output voltage is relatively high,
low switching frequency will result in more sub-harmonic
oscillation. Therefore, operating frequency needs to be kept
relatively high under high VOUT conditions. However, again,
switching frequency cannot be increased too much. Otherwise,
the minimum on-time limit could be violated. Based on these
considerations, Figure 36 provides the recommended switching
frequency under various typical VIN and across VOUT range.
SWITCHING FREQUENCY (MHz)
4.0
VIN=5V
VIN=4V
Series3
VIN=2.6V
3.5
3.0
2.0
1.5
1.0
0.5
0.0
1
1.4
1.8
2.2 2.6
3
3.4 3.8
OUTPUT VOLTAGE (V)
4.2
4.6
5
(EQ. 5)
Each 22µF X5R or X7R ceramic capacitor is typically good for 2A
to 3A of RMS ripple current. Refer to the capacitor vendor to
check the RMS current ratings.
Based on the above considerations, minimum total input
capacitance of 44µF is required for ISL8205M. Add additional
capacitance if possible. Use X5R or X7R ceramic capacitors. The
placement of the input ceramic capacitors should be as close as
possible to the module input. Refer to “PCB Layout Pattern
Design” on page 20 for more information. A bulk input
capacitance may also be needed if the input source does not
have enough output capacitance. A typical value of bulk input
capacitor is 100µF. In such conditions, this bulk input
capacitance can supply the current during output load transient
conditions.
Input Capacitor Selection
Selection of the input filter capacitor is based on how much
ripple the supply can tolerate on the DC input line. The larger the
capacitor, the less ripple expected, however, consideration
should be given to the higher surge current during power-up. The
ISL8205M provides a soft-start function that controls and limits
the current surge. The total capacitance of the input capacitor
can be calculated based on Equation 4:
IO  D  1 – D 
C IN  MIN  = ----------------------------------V P-P  f SW
Ceramic capacitors are typically used as the output capacitors
for the ISL8205M. Refer to Table 2 on page 14 for recommended
output capacitor values. Bulk output capacitors that have
adequately low Equivalent Series Resistance (ESR), such as low
ESR polymer capacitors or a low ESR tantalum capacitor, may
also be used in combination with the ceramic capacitors,
depending on the output voltage ripple and transient
requirements.
Feed-Forward Capacitor Selection
FIGURE 36. SWITCHING FREQUENCY RECOMMENDATION
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Io D  1 – D 
I IN  RMS  = --------------------------------
Output Capacitor Selection
2.5
0.6
Low Equivalent Series Resistance (ESR) ceramic capacitance is
recommended to be placed as close as possible to the module
input to reduce input voltage ripple and decouple between the
VIN and PGND. This capacitance not only reduces voltage ringing
created by the switching current across parasitic circuit
elements, but also reduces the input noise seen by the module.
Moreover, the estimated RMS ripple current should be considered
in choosing ceramic capacitors. The RMS ripple current can be
calculated by Equation 5
In typical applications where the output capacitors are all ceramic,
a feed-forward capacitor, as shown as CFF in Figure 1 on page 1, is
needed to insure loop stability in extreme operating conditions.
With internal compensation mode enabled, the CFF values for
typical operating conditions are optimized and listed in Table 2 on
page 14. Please note that, for system parameters that are
different from Table 2 or external instead of internal
compensation is used, the optimized value of CFF needs to be
adjusted.
(EQ. 4)
17
FN8755.2
May 19, 2016
ISL8205M
Typical Application Circuit
to be derated. The derating curves (Figure 30 through 33) are
fully tested. They are on the basis of determining the maximum
continuous load current while limiting the maximum junction
temperature to +120°C, which provides 5°C margin of safety
from the rated junction temperature of +125°C. The test was
done across various typical operating conditions, providing a
starting point for system thermal design. Note that all the
derating curves are obtained based on tests in free air with the
module mounted on the ISL8205MEVAL1Z evaluation board with
“direct attach” features. Refer to ISL8205MEVAL1Z User Guide
for evaluation board details. Also see Tech Brief TB379 for
general thermal metric information.
Figure 1 on page 1 only illustrates the application circuit with
minimum external components required for operation in PWM
mode. A more comprehensive typical application circuit diagram
is shown in Figure 37. In this example, a pull-up resistor is added
to the PG pin to allow power-good signal monitoring. Soft start-up
time adjustment is achieved by adding a capacitor, CSS, to the SS
pin. Typical application circuit of PFM mode operation can also
be found in Figure 38.
Thermal Consideration and Current Derating
The ISL8205M’s thermally enhanced package offers typical
junction to ambient thermal resistance JA of approximately
27.4°C/W at natural convection with a typical 4-layer PCB board.
In applications with elevated ambient temperature, the
continuous current handling capability of the module may need
In real applications where the system parameters and layout are
different than the evaluation board, the customer can adjust the
margin of safety. Other heat sources and design margins also
need to be taken into consideration.
ISL8205M
2.6V TO 5.5V
INPUT
CIN
2x22µF
RPU
10k
1.2V 5A
OUTPUT
VIN
VOUT
EN
SW
SYNC
COUT
2x22µF
VSENSE
PG
COMP
FS
FB
PGOOD
SS
RFS
124k
CSS
EPAD
SGND
PGND
RSET
100k
CFF
820pF
15nF
FIGURE 37. COMPLETE APPLICATION CIRCUIT DIAGRAM
ISL8205M
2.6V TO 5.5V
INPUT
CIN
2x22µF
1.2V 5A
OUTPUT
VIN
VOUT
EN
SW
PG
VSENSE
SYNC
COMP
FS
SS
RFS
124k
SGND
COUT
2x22µF
FB
EPAD
PGND
RSET
100k
CFF
820pF
FIGURE 38. TYPICAL APPLICATION CIRCUIT DIAGRAM IN PFM MODE
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FN8755.2
May 19, 2016
ISL8205M
PCB Layout Recommendations
A few layout considerations need to be taken into account in
order to achieve proper operation of ISL8205M. An optimized
layout design also allows the module to have lower power loss
and good thermal performance. An illustrative layout example is
shown in Figures 39 and 40). Key points are listed in the following:
• Place the input ceramic capacitors as close as possible to the
module input. These ceramic capacitors are used to minimize
the high frequency noise by reducing parasitic inductance of
the switching loop. Optimized placement of these capacitors
will not only lead to less switch node ringing, but also minimize
the noise seen by the module to insure proper operation. It is
recommended to use X5R or X7R ceramic capacitors with a
minimum total capacitance of 44µF at module input. It is a
MUST that one of the input capacitors (CIN1), with no less than
3.3µF capacitance, should be placed on the same layer
(assuming top layer) as the module and within less than 70 mil
clearance to module input (refer to Figure 39). For capacitors
on the bottom layer, it is recommended to have one (CIN2)
placed from VIN to PGND copper close to exposed pad
(Pad 20) vias (as shown in the layout example in Figure 40).
FIGURE 39. LAYOUT EXAMPLE - TOP LAYER
• Use large copper areas for power path (VIN, PGND) to minimize
conduction loss and thermal stress. Also, it is recommended to
use multiple vias to connect the power planes in different
layers. Use at least 5 vias on the exposed Pad 20 connected to
PGND plane(s) for the best thermal relief.
• Use a separate SGND ground copper area for components that
are connected to signal ground. Connect SGND copper to
module Pad 22 through multiple vias (refer to Figure 40).
Because Pad 22 is connected to module internal PGND at
single location, the SGND copper area and PGND plane on the
PCB can be left separated.
• It is recommended to keep the SW pads only on the top and
inner layers of the PCB. Do not expose the SW pads to the
outside on the bottom layer of the PCB. In order to minimize
switch node resistance, connect Pads 21 and 9 using wide
trace or shape.
• If remote sense is needed, route remote sensing trace from
point-of-load to module VSENSE pin through quiet inner layer
that is shielded by PGND planes.
• Avoid routing noise-sensitive signal traces such as FB, COMP
near the noisy SW pins.
FIGURE 40. LAYOUT EXAMPLE - BOTTOM LAYER
• The feedback and compensation network should be placed as
close as possible to the FB pins and far away from the SW pins.
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FN8755.2
May 19, 2016
ISL8205M
Package Description
Stencil Pattern Design
The ISL8205M is integrated into a Quad Flatpack No-Lead (QFN)
package. This package has such advantages as good thermal
and electrical conductivity, low weight and small size. The QFN
package is applicable for surface mounting technology and is
becoming more common in the industry. The ISL8205M is a
copper leadframe based package with exposed copper thermal
pads, which have good electrical and thermal conductivity. The
copper leadframe and multicomponent assembly are
overmolded with polymer mold compound to protect these
devices.
Reflowed solder joints on the perimeter I/O lands should have
about a 50µm to 75µm (2 mil to 3 mil) standoff height. The
solder paste stencil design is the first step in developing
optimized, reliable solder joins. The stencil aperture size to land
size ratio should typically be 1:1. Aperture width may be reduced
slightly to help prevent solder bridging between adjacent I/O
lands.
The package outline, typical PCB layout pattern and typical
stencil pattern design are shown in the L22.4.5x7.5 “Package
Outline Drawing” on page 22. TB493 shows typical reflow profile
parameters. These guidelines are general design rules. Users can
modify parameters according to specific applications.
PCB Layout Pattern Design
The bottom of ISL8205M is a leadframe footprint, which is
attached to the PCB by surface mounting. The PCB layout pattern
is shown in the L22.4.5x7.5 “Package Outline Drawing” on
page 22. The PCB layout pattern is essentially 1:1 with the QFN
exposed pad and the I/O termination dimensions, except that the
PCB lands are slightly longer than the QFN terminations by about
0.2mm (0.4mm maximum). This extension allows for solder
filleting around the package periphery and ensures a more
complete and inspectable solder joint. The thermal lands on the
PCB layout should match 1:1 with the package exposed die pads.
Thermal Vias
A grid of 1.0mm to 1.2mm pitched thermal vias, which drops
down and connects to buried copper planes, should be placed
under the thermal land. The vias should be about 0.3mm to
0.33mm in diameter, with the barrel plated to about 2.0 ounce
copper. Although adding more vias (by decreasing pitch)
improves thermal performance, it also diminishes results as
more vias are added. Use only as many vias as needed for the
thermal land size and as your board design rules allow.
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To reduce solder paste volume on the larger thermal lands, an
array of smaller apertures instead of one large aperture is
recommended. The stencil printing area should cover 50% to
80% of the PCB layout pattern. Consider the symmetry of the
whole stencil pattern when designing the pads.
A laser-cut, stainless-steel stencil with electropolished
trapezoidal walls is recommended. Electropolishing smooths the
aperture walls, resulting in reduced surface friction and better
paste release, which reduces voids. Using a Trapezoidal Section
Aperture (TSA) also promotes paste release and forms a
brick-like paste deposit, which assists in firm component
placement.
Reflow Parameters
Due to the low mount height of the QFN, “No Clean” Type 3 solder
paste, per ANSI/J-STD-005, is recommended. Nitrogen purge is
also recommended during reflow. A system board reflow profile
depends on the thermal mass of the entire populated board,
thus, it is not practical to define a specific soldering profile just
for the QFN. The profile given in TB493 is provided as a guideline
to customize for varying manufacturing practices and
applications.
FN8755.2
May 19, 2016
ISL8205M
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web
to make sure that you have the latest revision.
DATE
REVISION
CHANGE
May 19, 2016
FN8755.2
Related Literature on page 1: Added UG072 link.
May 10, 2016
FN8755.1
Updated title on page 1
Updated default setting from 1.9MHz to 1.8MHz throughout datasheet.
Replaced Figure 1 on page 1.
Updated Figure 3 on page 3.
Updated typical specification for “Nominal Switching Frequency” on page 7 from 1900 to 1835.
Added Note 8 on page 8.
Added “Typical Application Circuit” section on page 18.
On page 25, replaced Recommended Stencil Perimeter Pads view to match POD.
March 21, 2016
FN8755.0
Initial release.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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FN8755.2
May 19, 2016
Submit Document Feedback
Package Outline Drawing
L22.4.5x7.5
22 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 9/15
1.300
4.5
A
B
22
2x 1.610
2x 1.360
0.05
C AB
4x 0.390
2x 0.390
4x 0.300
42x 0.220
0.10
0.05
2x 3.110
C A B
C
38x 0.500 BSC
2x 0.350
7.5
0.710
2.900
21x 0.250
(2X)
0.05 C
(2X)
PIN 1
INDEX AREA
0.05 C
1.500
1.385
1.000
PIN 1 IDENTIFICATION
0.450
2x 0.890
1.000
1.250
1.000
1.125
TOP VIEW
1.500
1.885
BOTTOM VIEW
SEE DETAIL “X”
1.90 MAX
0.05 C
C
C
0.203 REF
4
SEATING PLANE
(20x)
0 - 0.05
0.08 C 0.05
SIDE VIEW
DETAIL “X”
NOTES:
1. Dimensions are in millimeters.
2. Dimensioning and tolerancing conform to ASMEY 14.5m-1994.
3. Unless otherwise specified, tolerance: Decimal ± 0.05.
FN8755.2
May 19, 2016
4. Tiebar shown (if present) is a non-functional feature.
5. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
ISL8205M
11x 0.6
2x 1.230
3.450
3.950
0.640
0.650
0.950
0.640
ISL8205M
0.00
3.950
3.360
0.640
0.360
0.140
0.640
0.140
0.360
1.135
1.860
2.140
2.365
2.860
3.140
3.360
PCB LAND PATTERN
3.360
0.640
3.950
2.450
2.450
0.360
0.140
0.00
0.140
0.850
0.500
1.250
1.860
2.140
2.360
0.360
0.140
0.00
0.140
0.360
1.860
1.950
3.950
1.860
1.950
1.650
1.800
1.700
1.250
1.360
2.640
2.860
3.140
3.360
23
0.640
0.360
0.140
0.00
0.140
0.360
1.000
2.7500
3.150
Submit Document Feedback
0.865
0.860
0.640
0.250
0.365
1.360
1.250
1.140
1.125
2.450
2.450
1.650
FN8755.2
May 19, 2016
3.158
3.450
0.240
24
1.700
1.659
1.226
1.445
0.741
0.600
0.840
0.400
0.000
0.050
0.665
0.741
1.245
0.689
1.445
0.985
1.659
1.275
1.310
1.700
1.950
1.950
ISL8205M
3.450
3.158
2.100
1.900
0.000
0.740
0.690
1.160
1.810
2.190
2.810
2.340
3.175
3.460
FN8755.2
May 19, 2016
RECOMMENDED STENCIL INTERIOR PADS
2.100
1.900
0.740
0.000
0.750
2.100
1.810
0.850
0.515
0.835
1.450
1.900
2.550
Submit Document Feedback
1.950
1.950
1.050
1.245
0.000
0.340
0.000
2.425
1.655
1.975
1.345
1.345
0.845
0.845
1.155
1.155
0.655
0.655
0.345
0.345
0.155
0.155
0.155
0.155
0.345
0.655
0.345
0.655
0.845
0.845
0.975
1.155
1.155
1.345
1.345
1.675
1.655
0.000
ISL8205M
2.050
2.425
1.845
2.050
3.925
3.550
3.345
1.975
1.820
1.845
2.050
2.050
3.155
2.845
2.655
2.345
2.155
2.425
25
3.925
0.345
0.155
0.000
0.655
0.845
1.155
1.345
1.655
1.845
2.155
2.345
2.655
2.845
3.155
3.345
3.550
0.155
0.345
0.655
0.845
1.155
1.345
1.655
1.845
2.155
2.345
2.655
2.845
3.155
3.345
3.560
3.925
FN8755.2
May 19, 2016
RECOMMENDED STENCIL PERIMETER PADS
1.845
1.655
1.345
1.155
0.845
0.655
0.345
0.155
0.155
0.345
0.655
0.845
1.155
1.345
1.655
1.845
2.155
2.345
2.655
2.845
3.155
3.175
3.345
3.925
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2.425
1.675
0.000