ADC0803, ADC0804 ® Data Sheet August 2002 8-Bit, Microprocessor-Compatible, A/D Converters FN3094.4 Features The ADC080X family are CMOS 8-Bit, successiveapproximation A/D converters which use a modified potentiometric ladder and are designed to operate with the 8080A control bus via three-state outputs. These converters appear to the processor as memory locations or I/O ports, and hence no interfacing logic is required. The differential analog voltage input has good commonmode-rejection and permits offsetting the analog zero-inputvoltage value. In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution. Typical Application Schematic • 80C48 and 80C80/85 Bus Compatible - No Interfacing Logic Required • Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . <100µs • Easy Interface to Most Microprocessors • Will Operate in a “Stand Alone” Mode • Differential Analog Voltage Inputs • Works with Bandgap Voltage References • TTL Compatible Inputs and Outputs • On-Chip Clock Generator • Analog Voltage Input Range (Single + 5V Supply) . . . . . . . . . . . . . . . . . . . . . . 0V to 5V • No Zero-Adjust Required 1 CS 2 RD 3 WR 5 INTR ANY µPROCESSOR µP BUS 11 12 13 14 15 16 17 18 • 80C48 and 80C80/85 Bus Compatible - No Interfacing Logic Required V+ 20 +5V 150pF CLK R 19 CLK IN 4 10K Pinout ADC0803, ADC0804 (PDIP) DB7 TOP VIEW DB6 DB5 DB4 DB3 DB2 DB1 DB0 VIN (+) 6 V (-) 7 IN AGND 8 /2 9 V REF DGND 10 DIFF INPUTS VREF/2 8-BIT RESOLUTION OVER ANY DESIRED ANALOG INPUT VOLTAGE RANGE CS 1 RD 2 19 CLK R WR 3 18 DB0 (LSB) CLK IN 4 17 DB1 INTR 5 16 DB2 VIN (+) 6 15 DB3 VIN (-) 7 14 DB4 AGND 8 13 DB5 VREF/2 9 12 DB6 20 V+ OR VREF DGND 10 11 DB7 (MSB) Ordering Information PART NUMBER ERROR EXTERNAL CONDITIONS TEMP. RANGE (oC) PACKAGE PKG. NO ADC0803LCN ±1/2 LSB VREF/2 Adjusted for Correct Full Scale Reading 0 to 70 20 Ld PDIP E20.3 ADC0804LCN ±1 LSB VREF/2 = 2.500VDC (No Adjustments) 0 to 70 20 Ld PDIP E20.3 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved ADC0803, ADC0804 Functional Diagram RD CS WR 2 READ 1 3 SET “1” = RESET SHIFT REGISTER “0” = BUSY AND RESET STATE Q RESET INPUT PROTECTION FOR ALL LOGIC INPUTS CLK R 19 CLK INPUT CLK A CLK IN G1 RESET CLK OSC D BV = 30V CLK GEN CLKS 4 TO INTERNAL CIRCUITS DFF1 Q START F/F 10 DGND START CONVERSION CLK B MSB V+ (VREF) VREF/2 D 20 LADDER AND DECODER SUCCESSIVE APPROX. REGISTER AND LATCH 9 8-BIT SHIFT REGISTER IF RESET = “0” R RESET AGND DAC VOUT 8 LSB INTR F/F Q CLK A V+ D VIN (+) VIN (-) 6 + ∑ + DFF2 COMP Q Q XFER THREE-STATE OUTPUT LATCHES 7 G2 SET 5 LSB MSB CONV. COMPL. 11 12 13 14 15 16 17 18 8 X 1/f DIGITAL OUTPUTS THREE-STATE CONTROL “1” = OUTPUT ENABLE 2 INTR ADC0803, ADC0804 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V Voltage at Any Input. . . . . . . . . . . . . . . . . . . . . . -0.3V to (V+ +0.3V) Thermal Resistance (Typical, Note 1) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Maximum Junction Temperature Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . .300oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications (Notes 2, 8) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS - ±1/2 LSB - - ±1 LSB 1.0 1.3 - kΩ CONVERTER SPECIFICATIONS V+ = 5V, TA = 25oC and fCLK = 640kHz, Unless Otherwise Specified Total Unadjusted Error ADC0803 VREF/2 Adjusted for Correct Full Scale Reading ADC0804 VREF/2 = 2.500V - VREF/2 Input Resistance Input Resistance at Pin 9 Analog Input Voltage Range (Note 3) GND-0.05 - (V+) + 0.05 V DC Common-Mode Rejection Over Analog Input Voltage Range - ±1/16 ±1/8 LSB Power Supply Sensitivity V+ = 5V ±10% Over Allowed Input Voltage Range - ±1/16 ±1/8 LSB - ±1/2 LSB - - ±1 LSB 1.0 1.3 - kΩ CONVERTER SPECIFICATIONS V+ = 5V, 0oC to 70oC and fCLK = 640kHz, Unless Otherwise Specified Total Unadjusted Error ADC0803 VREF/2 Adjusted for Correct Full Scale Reading ADC0804 VREF/2 = 2.500V - VREF/2 Input Resistance Input Resistance at Pin 9 Analog Input Voltage Range (Note 3) GND-0.05 - (V+) + 0.05 V DC Common-Mode Rejection Over Analog Input Voltage Range - ±1/8 ±1/4 LSB Power Supply Sensitivity V+ = 5V ±10% Over Allowed Input Voltage Range - ±1/16 ±1/8 LSB V+ = 6V (Note 4) 100 640 1280 kHz V+ = 5V 100 640 800 kHz 62 - 73 Clocks/Conv - - 8888 Conv/s 100 - - ns AC TIMING SPECIFICATIONS V+ = 5V, and TA = 25oC, Unless Otherwise Specified Clock Frequency, fCLK Clock Periods per Conversion (Note 5), tCONV Conversion Rate In Free-Running Mode, CR INTR tied to WR with CS = 0V, fCLK = 640kHz Width of WR Input (Start Pulse Width), tW(WR)I CS = 0V (Note 6) Access Time (Delay from Falling Edge of RD to Output Data Valid), tACC CL = 100pF (Use Bus Driver IC for Larger CL) - 135 200 ns Three-State Control (Delay from Rising Edge of RD to Hl-Z State), t1H, t0H CL = 10pF, RL= 10K (See Three-State Test Circuits) - 125 250 ns Delay from Falling Edge of WR to Reset of INTR, tWI, tRI - 300 450 ns Input Capacitance of Logic Control Inputs, CIN - 5 - pF Three-State Output Capacitance (Data Buffers), COUT - 5 - pF 3 ADC0803, ADC0804 Electrical Specifications (Notes 2, 8) (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS DC DIGITAL LEVELS AND DC SPECIFICATIONS V+ = 5V, and TMIN to TMAX , Unless Otherwise Specified CONTROL INPUTS (Note 7) Logic “1“ Input Voltage (Except Pin 4 CLK IN), VINH V+ = 5.25V 2.0 - V+ V Logic “0“ Input Voltage (Except Pin 4 CLK IN), VINL V+ = 4.75V - - 0.8 V CLK IN (Pin 4) Positive Going Threshold Voltage, V+CLK 2.7 3.1 3.5 V CLK IN (Pin 4) Negative Going Threshold Voltage, V-CLK 1.5 1.8 2.1 V CLK IN (Pin 4) Hysteresis, VH 0.6 1.3 2.0 V Logic “1” Input Current (All Inputs), IINHI VlN = 5V - 0.005 1 µΑ Logic “0” Input Current (All Inputs), IINLO VlN = 0V -1 -0.005 - µA - 1.3 2.5 mA - 0.4 V Supply Current (Includes Ladder Current), I+ fCLK = 640kHz, TA = 25oC and CS = Hl DATA OUTPUTS AND INTR Logic “0” Output Voltage, VOL lO = 1.6mA, V+ = 4.75V - Logic “1” Output Voltage, VOH lO = -360µA, V+ = 4.75V 2.4 - - V Three-State Disabled Output Leakage (All Data Buffers), ILO VOUT = 0V -3 - - µA - - 3 µA Output Short Circuit Current, ISOURCE VOUT Short to GND, TA = 25oC 4.5 6 - mA Output Short Circuit Current, ISINK VOUT Short to V+, TA = 25oC 9.0 16 - mA VOUT = 5V NOTES: 2. All voltages are measured with respect to GND, unless otherwise specified. The separate AGND point should always be wired to the DGND, being careful to avoid ground loops. 3. For VIN(-) ≥ VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the V+ supply. Be careful, during testing at low V+ levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct - especially at elevated temperatures, and cause errors for analog inputs near full scale. As long as the analog VIN does not exceed the supply voltage by more than 50mV, the output code will be correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply voltage of 4.950V over temperature variations, initial tolerance and loading. 4. With V+ = 6V, the digital logic interfaces are no longer TTL compatible. 5. With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. 6. The CS input is assumed to bracket the WR strobe input so that timing is dependent on the WR pulse width. An arbitrarily wide pulse width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see Timing Diagrams). 7. CLK IN (pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately. 8. None of these A/Ds requires a zero-adjust. However, if an all zero code is desired for an analog input other than 0V, or if a narrow full scale span exists (for example: 0.5V to 4V full scale) the VIN(-) input can be adjusted to achieve this. See the Zero Error description in this data sheet. Timing Waveforms 2.4V V+ RD RD 0.8V DATA OUTPUT CS CL FIGURE 1A. t1H 4 10K VOH DATA OUTPUTS tr = 20ns tr 90% 50% 10% t1H 90% GND FIGURE 1B. t1H , CL = 10pF ADC0803, ADC0804 Timing Waveforms (Continued) tr = 20ns V+ tr V+ 2.4V RD 10K RD 0.8V DATA OUTPUT CS V+ CL DATA OUTPUTS FIGURE 1C. t0H VOI 90% 50% 10% t0H 10% FIGURE 1D. t0H , CL = 10pF FIGURE 1. THREE-STATE CIRCUITS AND WAVEFORMS 1.8 500 -55oC TO 125oC 1.7 400 DELAY (ns) LOGIC INPUT THRESHOLD VOLTAGE (V) Typical Performance Curves 1.6 1.5 300 200 1.4 1.3 4.50 4.75 5.00 5.25 100 5.50 0 200 V+ SUPPLY VOLTAGE (V) FIGURE 2. LOGIC INPUT THRESHOLD VOLTAGE vs SUPPLY VOLTAGE 800 1000 FIGURE 3. DELAY FROM FALLING EDGE OF RD TO OUTPUT DATA VALID vs LOAD CAPACITANCE 1000 3.5 R = 10K 3.1 VT(+) R = 50K 2.7 fCLK (kHz) CLK IN THRESHOLD VOLTAGE (V) 400 600 LOAD CAPACITANCE (pF) -55oC TO 125oC 2.3 1.9 1.5 4.50 VT(-) 4.75 5.00 5.25 R = 20K 5.50 V+ SUPPLY VOLTAGE (V) FIGURE 4. CLK IN SCHMITT TRIP LEVELS vs SUPPLY VOLTAGE 5 100 10 100 CLOCK CAPACITOR (pF) FIGURE 5. fCLK vs CLOCK CAPACITOR 1000 ADC0803, ADC0804 Typical Performance Curves (Continued) 16 6 VIN(+) = VIN(-) = 0V 14 ASSUMES VOS = 2mV 12 THIS SHOWS THE NEED FOR A ZERO ADJUSTMENT IF THE SPAN IS REDUCED V+ = 4.5V OFFSET ERROR (LSBs) FULL SCALE ERROR (LSBs) 7 5 4 3 V+ = 5V 2 1 10 8 6 4 2 V+ = 6V 0 0 400 800 1200 1600 0 0.01 2000 0.1 1.0 FIGURE 6. FULL SCALE ERROR vs fCLK FIGURE 7. EFFECT OF UNADJUSTED OFFSET ERROR 8 1.6 V+ = 5V fCLK = 640kHz POWER SUPPLY CURRENT (mA) OUTPUT CURRENT (mA) 7 DATA OUTPUT BUFFERS 6 ISOURCE VOUT = 2.4V 5 4 3 2 5 VREF/2 (V) fCLK (kHz) -ISINK VOUT = 0.4V -50 -25 0 25 50 75 100 1.5 V+ = 5.5V 1.4 1.3 V+ = 5.0V 1.2 V+ = 4.5V 1.1 1.0 -50 125 TA AMBIENT TEMPERATURE (oC) -25 0 25 50 75 100 FIGURE 8. OUTPUT CURRENT vs TEMPERATURE FIGURE 9. POWER SUPPLY CURRENT vs TEMPERATURE Timing Diagrams CS WR tWI ACTUAL INTERNAL STATUS OF THE CONVERTER “BUSY” tW(WR)I DATA IS VALID IN OUTPUT LATCHES “NOT BUSY” 1 TO 8 x 1/fCLK INTERNAL TC (LAST DATA READ) INTR INTR ASSERTED (LAST DATA NOT READ) tVI FIGURE 10A. START CONVERSION 6 125 TA AMBIENT TEMPERATURE (oC) 1/ f 2 CLK ADC0803, ADC0804 Timing Diagrams (Continued) INTR RESET INTR tRI CS RD VALID DATA DATA OUTPUTS tACC THREE-STATE VALID DATA (HI-Z) t1H , t0H +1 LSB D+1 5 6 D 3 4 D-1 ERROR DIGITAL OUTPUT CODE FIGURE 10B. OUTPUT ENABLE AND RESET INTR 1 +1/2 LSB 3 * QUANTIZATION ERROR 0 -1/2 LSB 1 2 5 2 4 6 -1 LSB A-1 A A-1 A+1 A A+1 ANALOG INPUT (VIN) ANALOG INPUT (VIN) TRANSFER FUNCTION ERROR PLOT +1 LSB 1 5 D+1 6 3 D 4 ERROR DIGITAL OUTPUT CODE FIGURE 11A. ACCURACY = ±0 LSB; PERFECT A/D 3 0 6 1 D-1 2 4 2 -1 LSB A-1 A A-1 A+1 A ANALOG INPUT (VIN) ANALOG INPUT (VIN) TRANSFER FUNCTION ERROR PLOT FIGURE 11B. ACCURACY = ±1/2 LSB FIGURE 11. CLARIFYING THE ERROR SPECS OF AN A/D CONVERTER 7 A+1 * QUANTIZATION ERROR ADC0803, ADC0804 Understanding A/D Error Specs A perfect A/D transfer characteristic (staircase wave-form) is shown in Figure 11A. The horizontal scale is analog input voltage and the particular points labeled are in steps of 1 LSB (19.53mV with 2.5V tied to the VREF/2 pin). The digital output codes which correspond to these inputs are shown as D-1, D, and D+1. For the perfect A/D, not only will centervalue (A - 1, A, A + 1, . . .) analog inputs produce the correct output digital codes, but also each riser (the transitions between adjacent output codes) will be located ±1/2 LSB away from each center-value. As shown, the risers are ideal and have no width. Correct digital output codes will be provided for a range of analog input voltages which extend ±1/2 LSB from the ideal center-values. Each tread (the range of analog input voltage which provides the same digital output code) is therefore 1 LSB wide. connecting INTR to the WR input with CS = 0. To ensure startup under all possible conditions, an external WR pulse is required during the first power-up cycle. A conversion-inprocess can be interrupted by issuing a second start command. Digital Operation The error curve of Figure 11B shows the worst case transfer function for the ADC080X. Here the specification guarantees that if we apply an analog input equal to the LSB analog voltage center-value, the A/D will produce the correct digital code. The converter is started by having CS and WR simultaneously low. This sets the start flip-flop (F/F) and the resulting “1” level resets the 8-bit shift register, resets the Interrupt (INTR) F/F and inputs a “1” to the D flip-flop, DFF1, which is at the input end of the 8-bit shift register. Internal clock signals then transfer this “1” to the Q output of DFF1. The AND gate, G1, combines this “1” output with a clock signal to provide a reset signal to the start F/F. If the set signal is no longer present (either WR or CS is a “1”), the start F/F is reset and the 8-bit shift register then can have the “1” clocked in, which starts the conversion process. If the set signal were to still be present, this reset pulse would have no effect (both outputs of the start F/F would be at a “1” level) and the 8-bit shift register would continue to be held in the reset mode. This allows for asynchronous or wide CS and WR signals. Next to each transfer function is shown the corresponding error plot. Notice that the error includes the quantization uncertainty of the A/D. For example, the error at point 1 of Figure 11A is +1/2 LSB because the digital code appeared 1/ LSB in advance of the center-value of the tread. The 2 error plots always have a constant negative slope and the abrupt upside steps are always 1 LSB in magnitude, unless the device has missing codes. After the “1” is clocked through the 8-bit shift register (which completes the SAR operation) it appears as the input to DFF2. As soon as this “1” is output from the shift register, the AND gate, G2, causes the new digital word to transfer to the Three-State output latches. When DFF2 is subsequently clocked, the Q output makes a high-to-low transition which causes the INTR F/F to set. An inverting buffer then supplies the INTR output signal. Detailed Description When data is to be read, the combination of both CS and RD being low will cause the INTR F/F to be reset and the threestate output latches will be enabled to provide the 8-bit digital outputs. The functional diagram of the ADC080X series of A/D converters operates on the successive approximation principle (see Application Notes AN016 and AN020 for a more detailed description of this principle). Analog switches are closed sequentially by successive-approximation logic until the analog differential input voltage [VlN(+) - VlN(-)] matches a voltage derived from a tapped resistor string across the reference voltage. The most significant bit is tested first and after 8 comparisons (64 clock cycles), an 8bit binary code (1111 1111 = full scale) is transferred to an output latch. The normal operation proceeds as follows. On the high-to-low transition of the WR input, the internal SAR latches and the shift-register stages are reset, and the INTR output will be set high. As long as the CS input and WR input remain low, the A/D will remain in a reset state. Conversion will start from 1 to 8 clock periods after at least one of these inputs makes a lowto-high transition. After the requisite number of clock pulses to complete the conversion, the INTR pin will make a high-to-low transition. This can be used to interrupt a processor, or otherwise signal the availability of a new conversion. A RD operation (with CS low) will clear the INTR line high again. The device may be operated in the free-running mode by 8 Digital Control Inputs The digital control inputs (CS, RD, and WR) meet standard TTL logic voltage levels. These signals are essentially equivalent to the standard A/D Start and Output Enable control signals, and are active low to allow an easy interface to microprocessor control busses. For non-microprocessor based applications, the CS input (pin 1) can be grounded and the standard A/D Start function obtained by an active low pulse at the WR input (pin 3). The Output Enable function is achieved by an active low pulse at the RD input (pin 2). Analog Operation The analog comparisons are performed by a capacitive charge summing circuit. Three capacitors (with precise ratioed values) share a common node with the input to an autozeroed comparator. The input capacitor is switched between VlN(+) and VlN(-) , while two ratioed reference capacitors are switched between taps on the reference voltage divider string. The net charge corresponds to the weighted difference between the input and the current total value set by the ADC0803, ADC0804 successive approximation register. A correction is made to offset the comparison by 1/2 LSB (see Figure 11A). Analog Differential Voltage Inputs and CommonMode Rejection This A/D gains considerable applications flexibility from the analog differential voltage input. The VlN(-) input (pin 7) can be used to automatically subtract a fixed voltage value from the input reading (tare correction). This is also useful in 4mA - 20mA current loop conversion. In addition, common-mode noise can be reduced by use of the differential input. The time interval between sampling VIN(+) and VlN(-) is 41/2 clock periods. The maximum error voltage due to this slight time difference between the input voltage samples is given by: 4.5 ∆V E ( MAX ) = ( V PEAK ) ( 2πf CM ) -----------f CLK where: ∆VE is the error voltage due to sampling delay, VPEAK is the peak value of the common-mode voltage, fCM is the common-mode frequency. For example, with a 60Hz common-mode frequency, fCM , and a 640kHz A/D clock, fCLK , keeping this error to 1/4 LSB (~5mV) would allow a common-mode voltage, VPEAK , given by: ∆V E ( MAX ) ( f –3 Input Source Resistance Large values of source resistance where an input bypass capacitor is not used will not cause errors since the input currents settle out prior to the comparison time. If a lowpass filter is required in the system, use a low-value series resistor (≤1kΩ) for a passive RC section or add an op amp RC active low-pass filter. For low-source-resistance applications (≤1kΩ), a 0.1µF bypass capacitor at the inputs will minimize EMI due to the series lead inductance of a long wire. A 100Ω series resistor can be used to isolate this capacitor (both the R and C are placed outside the feedback loop) from the output of an op amp, if used. Stray Pickup CLK ) V PEAK = -------------------------------------------------- , ( 2πf CM ) ( 4.5 ) or input at 5V, this DC current is at a maximum of approximately 5µA. Therefore, bypass capacitors should not be used at the analog inputs or the VREF/2 pin for high resistance sources (>1kΩ). If input bypass capacitors are necessary for noise filtering and high source resistance is desirable to minimize capacitor size, the effects of the voltage drop across this input resistance, due to the average value of the input current, can be compensated by a full scale adjustment while the given source resistor and input bypass capacitor are both in place. This is possible because the average value of the input current is a precise linear function of the differential input voltage at a constant conversion rate. 3 ( 5 × 10 ) ( 640 × 10 ) V PEAK = ---------------------------------------------------------- ≅ 1.9V . ( 6.28 ) ( 60 ) ( 4.5 ) The allowed range of analog input voltage usually places more severe restrictions on input common-mode voltage levels than this. An analog input voltage with a reduced span and a relatively large zero offset can be easily handled by making use of the differential input (see Reference Voltage Span Adjust). Analog Input Current The internal switching action causes displacement currents to flow at the analog inputs. The voltage on the on-chip capacitance to ground is switched through the analog differential input voltage, resulting in proportional currents entering the VIN(+) input and leaving the VIN(-) input. These current transients occur at the leading edge of the internal clocks. They rapidly decay and do not inherently cause errors as the on-chip comparator is strobed at the end of the clock perIod. Input Bypass Capacitors Bypass capacitors at the inputs will average these charges and cause a DC current to flow through the output resistances of the analog signal sources. This charge pumping action is worse for continuous conversions with the VIN(+) input voltage at full scale. For a 640kHz clock frequency with the VIN(+) 9 The leads to the analog inputs (pins 6 and 7) should be kept as short as possible to minimize stray signal pickup (EMI). Both EMI and undesired digital-clock coupling to these inputs can cause system errors. The source resistance for these inputs should, in general, be kept below 5kΩ. Larger values of source resistance can cause undesired signal pickup. Input bypass capacitors, placed from the analog inputs to ground, will eliminate this pickup but can create analog scale errors as these capacitors will average the transient input switching currents of the A/D (see Analog Input Current). This scale error depends on both a large source resistance and the use of an input bypass capacitor. This error can be compensated by a full scale adjustment of the A/D (see Full Scale Adjustment) with the source resistance and input bypass capacitor in place, and the desired conversion rate. Reference Voltage Span Adjust For maximum application flexibility, these A/Ds have been designed to accommodate a 5V, 2.5V or an adjusted voltage reference. This has been achieved in the design of the IC as shown in Figure 12. Notice that the reference voltage for the IC is either 1/2 of the voltage which is applied to the V+ supply pin, or is equal to the voltage which is externally forced at the VREF /2 pin. This allows for a pseudo-ratiometric voltage reference using, for the V+ supply, a 5V reference voltage. Alternatively, a voltage less than 2.5V can be applied to the VREF/2 input. The internal gain to the VREF/2 input is 2 to allow this factor of 2 reduction in the reference voltage. ADC0803, ADC0804 Such an adjusted reference voltage can accommodate a reduced span or dynamic voltage range of the analog input voltage. If the analog input voltage were to range from 0.5V to 3.5V, instead of 0V to 5V, the span would be 3V. With 0.5V applied to the VlN(-) pin to absorb the offset, the reference voltage can be made equal to 1/2 of the 3V span or 1.5V. The A/D now will encode the VlN(+) signal from 0.5V to 3.5V with the 0.5V input corresponding to zero and the 3.5V input corresponding to full scale. The full 8 bits of resolution are therefore applied over this reduced analog input voltage range. The requisite connections are shown in Figure 13. For expanded scale inputs, the circuits of Figures 14 and 15 can be used. V+ (VREF) 5V (VREF) R VIN ± 10V 2R 6 VIN(+) V+ 20 + ADC0803ADC0804 2R 7 10µF VIN(-) FIGURE 14. HANDLING ±10V ANALOG INPUT RANGE 20 5V (VREF) R R VREF/2 VIN ±5V 9 R 6 7 ANALOG CIRCUITS DECODE V+ 20 ADC0803ADC0804 DIGITAL CIRCUITS R VIN(+) + 10µF VIN(-) FIGURE 15. HANDLING ±5V ANALOG INPUT RANGE Reference Accuracy Requirements 8 AGND DGND 10 FIGURE 12. THE VREFERENCE DESIGN ON THE IC VREF (5V) ICL7611 FS ADJ. “SPAN”/2 5V 300 - TO VREF/2 + 0.1µF ZERO SHIFT VOLTAGE TO VIN(-) FIGURE 13. OFFSETTING THE ZERO OF THE ADC080X AND PERFORMING AN INPUT RANGE (SPAN) ADJUSTMENT 10 The converter can be operated in a pseudo-ratiometric mode or an absolute mode. In ratiometric converter applications, the magnitude of the reference voltage is a factor in both the output of the source transducer and the output of the A/D converter and therefore cancels out in the final digital output code. In absolute conversion applicatIons, both the initial value and the temperature stability of the reference voltage are important accuracy factors in the operation of the A/D converter. For VREF/2 voltages of 2.5V nominal value, initial errors of ±10mV will cause conversion errors of ±1 LSB due to the gain of 2 of the VREF/2 input. In reduced span applications, the initial value and the stability of the VREF/2 input voltage become even more important. For example, if the span is reduced to 2.5V, the analog input LSB voltage value is correspondingly reduced from 20mV (5V span) to 10mV and 1 LSB at the VREF/2 input becomes 5mV. As can be seen, this reduces the allowed initial tolerance of the reference voltage and requires correspondingly less absolute change with temperature variations. Note that spans smaller than 2.5V place even tighter requirements on the initial accuracy and stability of the reference source. In general, the reference voltage will require an initial adjustment. Errors due to an improper value of reference voltage appear as full scale errors in the A/D transfer ADC0803, ADC0804 function. IC voltage regulators may be used for references if the ambient temperature changes are not excessive. Zero Error The zero of the A/D does not require adjustment. If the minimum analog input voltage value, VlN(MlN) , is not ground, a zero offset can be done. The converter can be made to output 0000 0000 digital code for this minimum input voltage by biasing the A/D VIN(-) input at this VlN(MlN) value (see Applications section). This utilizes the differential mode operation of the A/D. The zero error of the A/D converter relates to the location of the first riser of the transfer function and can be measured by grounding the VIN(-) input and applying a small magnitude positive voltage to the VIN(+) input. Zero error is the difference between the actual DC input voltage which is necessary to just cause an output digital code transition from 0000 0000 to 0000 0001 and the ideal 1/2 LSB value (1/2 LSB = 9.8mV for VREF/2 = 2.500V). Full Scale Adjust The full scale adjustment can be made by applying a differential input voltage which is 11/2 LSB down from the desired analog full scale voltage range and then adjusting the magnitude of the VREF/2 input (pin 9) for a digital output code which is just changing from 1111 1110 to 1111 1111. When offsetting the zero and using a span-adjusted VREF/2 voltage, the full scale adjustment is made by inputting VMlN to the VIN(-) input of the A/D and applying a voltage to the VIN(+) input which is given by: Loads less than 50pF, such as driving up to 7 A/D converter clock inputs from a single CLK R pin of 1 converter, are allowed. For larger clock line loading, a CMOS or low power TTL buffer or PNP input logic should be used to minimize the loading on the CLK R pin (do not use a standard TTL buffer). Restart During a Conversion If the A/D is restarted (CS and WR go low and return high) during a conversion, the converter is reset and a new conversion is started. The output data latch is not updated if the conversion in progress is not completed. The data from the previous conversion remain in this latch. Continuous Conversions In this application, the CS input is grounded and the WR input is tied to the INTR output. This WR and INTR node should be momentarily forced to logic low following a powerup cycle to insure circuit operation. See Figure 17 for details. 10K 5V (VREF) ADC0803 - ADC0804 150pF N.O. START ANALOG INPUTS ( V MAX – V MIN ) V IN ( + ) f SADJ = V MAX – 1.5 ----------------------------------------- , 256 1 CS V+ 20 2 RD CLK R 19 3 WR DB0 18 4 CLK IN DB1 17 5 INTR DB2 16 6 VIN (+) DB3 15 7 VIN (-) DB4 14 8 AGND DB5 13 9 VREF/2 DB6 12 10 DGND DB7 11 + 10µF LSB DATA OUTPUTS MSB where: VMAX = the high end of the analog input range, and VMIN = the low end (the offset zero) of the analog range. (Both are ground referenced.) Clocking Option The clock for the A/D can be derived from an external source such as the CPU clock or an external RC network can be added to provIde self-clocking. The CLK IN (pin 4) makes use of a Schmitt trigger as shown in Figure 16. CLK R 19 R CLK IN C ADC0803ADC0804 4 fCLK ≅ 1 1.1 RC R ≅ 10kΩ CLK FIGURE 16. SELF-CLOCKING THE A/D Heavy capacitive or DC loading of the CLK R pin should be avoided as this will disturb normal converter operation. 11 FIGURE 17. FREE-RUNNING CONNECTION Driving the Data Bus This CMOS A/D, like MOS microprocessors and memories, will require a bus driver when the total capacitance of the data bus gets large. Other circuItry, which is tied to the data bus, will add to the total capacitive loading, even in threestate (high-impedance mode). Back plane busing also greatly adds to the stray capacitance of the data bus. There are some alternatives available to the designer to handle this problem. Basically, the capacitive loading of the data bus slows down the response time, even though DC specifications are still met. For systems operating with a relatively slow CPU clock frequency, more time is available in which to establish proper logic levels on the bus and therefore higher capacitive loads can be driven (see Typical Performance Curves). At higher CPU clock frequencies time can be extended for I/O reads (and/or writes) by inserting wait states (8080) or using clock-extending circuits (6800). ADC0803, ADC0804 Finally, if time is short and capacitive loading is high, external bus drivers must be used. These can be three-state buffers (low power Schottky is recommended, such as the 74LS240 series) or special higher-drive-current products which are designed as bus drivers. High-current bipolar bus drivers with PNP inputs are recommended. significant bits (MS) and one with the 4 least-significant bits (LS). The output is then interpreted as a sum of fractions times the full scale voltage: MS LS V OUT = --------- + ---------- ( 5.12 )V . 16 256 10kΩ Power Supplies Noise spikes on the V+ supply line can cause conversion errors as the comparator will respond to this noise. A low-inductance tantalum filter capacitor should be used close to the converter V+ pin, and values of 1µF or greater are recommended. If an unregulated voltage is available in the system, a separate 5V voltage regulator for the converter (and other analog circuitry) will greatly reduce digital noise on the V+ supply. An lCL7663 can be used to regulate such a supply from an input as low as 5.2V. Wiring and Hook-Up Precautions Standard digital wire-wrap sockets are not satisfactory for breadboarding with this A/D converter. Sockets on PC boards can be used. All logic signal wires and leads should be grouped and kept as far away as possible from the analog signal leads. Exposed leads to the analog inputs can cause undesired digital noise and hum pickup; therefore, shielded leads may be necessary in many applications. A single-point analog ground should be used which is separate from the logic ground points. The power supply bypass capacitor and the self-clockIng capacitor (if used) should both be returned to digital ground. Any VREF/2 bypass capacitors, analog input filter capacitors, or input signal shielding should be returned to the analog ground point. A test for proper grounding is to measure the zero error of the A/D converter. Zero errors in excess of 1/4 LSB can usually be traced to improper board layout and wiring (see Zero Error for measurement). Further information can be found in Application Note AN018. 150pF N.O. START For ease of testing, the VREF/2 (pin 9) should be supplied with 2.560V and a V+ supply voltage of 5.12V should be used. This provides an LSB value of 20mV. If a full scale adjustment is to be made, an analog input voltage of 5.090V (5.120 - 11/2 LSB) should be applied to the VIN(+) pin with the VIN(-) pin grounded. The value of the VREF/2 input voltage should be adjusted until the digital output code is just changing from 1111 1110 to 1111 1111. This value of VREF/2 should then be used for all the tests. The digital-output LED display can be decoded by dividing the 8 bits into 2 hex characters, one with the 4 most- 12 20 2 19 3 18 4 17 5 VIN (+) 6 0.1µF AGND 2.560V VREF/2 0.1µF + 5.120V 10µF TANTALUM LSB 16 ADC0803ADC0804 15 7 14 8 13 9 12 10 11 5V MSB 1.3kΩ LEDs (8) (8) DGND FIGURE 18. BASIC TESTER FOR THE A/D For example, for an output LED display of 1011 0110, the MS character is hex B (decimal 11) and the LS character is hex (and decimal) 6, so: 11 6 V OUT = ------ + ---------- ( 5.12 ) = 3.64V. 16 256 Figures 19 and 20 show more sophisticated test circuits. 8-BIT A/D UNDER TEST VANALOG OUTPUT 10-BIT DAC R R - “B” ANALOG INPUTS + A1 R “C” 100R R - Testing the A/D Converter There are many degrees of complexity associated with testing an A/D converter. One of the simplest tests is to apply a known analog input voltage to the converter and use LEDs to display the resulting digital output code as shown in Figure 18. 1 + “A” A2 100X ANALOG ERROR VOLTAGE FIGURE 19. A/D TESTER WITH ANALOG ERROR OUTPUT. THIS CIRCUIT CAN BE USED TO GENERATE “ERROR PLOTS” OF FIGURE 11. DIGITAL INPUTS DIGITAL OUTPUTS VANALOG 10-BIT DAC A/D UNDER TEST FIGURE 20. BASIC “DIGITAL” A/D TESTER Typical Applications Interfacing 8080/85 or Z-80 Microprocessors ADC0803, ADC0804 This converter has been designed to directly interface with 8080/85 or Z-80 Microprocessors. The three-state output capability of the A/D eliminates the need for a peripheral interface device, although address decoding is still required to generate the appropriate CS for the converter. The A/D can be mapped into memory space (using standard memory-address decoding for CS and the MEMR and MEMW strobes) or it can be controlled as an I/O device by using the I/OR and I/OW strobes and decoding the address bits A0 → A7 (or address bits A8 → A15, since they will contain the same 8-bit address information) to obtain the CS input. Using the I/O space provides 256 additional addresses and may allow a simpler 8-bit address decoder, but the data can only be input to the accumulator. To make use of the additional memory reference instructions, the A/D should be mapped into memory space. See AN020 for more discussion of memory-mapped vs I/O-mapped interfaces. An example of an A/D in I/O space is shown in Figure 21. The standard control-bus signals of the 8080 (CS, RD and WR) can be directly wired to the digital control inputs of the A/D, since the bus timing requirements, to allow both starting the converter, and outputting the data onto the data bus, are met. A bus driver should be used for larger microprocessor systems where the data bus leaves the PC board and/or must drive capacitive loads larger than 100pF. Interfacing 6800 Microprocessor Derivatives (6502, etc.) The control bus for the 6800 microprocessor derivatives does not use the RD and WR strobe signals. Instead it employs a single R/W line and additional timing, if needed, can be derived from the φ2 clock. All I/O devices are memory-mapped in the 6800 system, and a special signal, VMA, indicates that the current address is valid. Figure 23 shows an interface schematic where the A/D is memory-mapped in the 6800 system. For simplicity, the CS decoding is shown using 1/2 DM8092. Note that in many 6800 systems, an already decoded 4/5 line is brought out to the common bus at pin 21. This can be tied directly to the CS pin of the A/D, provided that no other devices are addressed at HEX ADDR: 4XXX or 5XXX. In Figure 24 the ADC080X series is interfaced to the MC6800 microprocessor through (the arbitrarily chosen) Port B of the MC6820 or MC6821 Peripheral Interface Adapter (PlA). Here the CS pin of the A/D is grounded since the PlA is already memory-mapped in the MC6800 system and no CS decoding is necessary. Also notice that the A/D output data lines are connected to the microprocessor bus under program control through the PlA and therefore the A/D RD pin can be grounded. Application Notes NOTE # DESCRIPTION It is useful to note that in systems where the A/D converter is 1 of 8 or fewer I/O-mapped devices, no address-decoding circuitry is necessary. Each of the 8 address bits (A0 to A7) can be directly used as CS inputs, one for each I/O device. AN016 “Selecting A/D Converters” AN018 “Do’s and Don’ts of Applying A/D Converters” Interfacing the Z-80 and 8085 AN020 “A Cookbook Approach to High Speed Data Acquisition and Microprocessor Interfacing” AN030 “The ICL7104 - A Binary Output A/D Converter for Microprocessors” The Z-80 and 8085 control buses are slightly different from that of the 8080. General RD and WR strobes are provided and separate memory request, MREQ, and I/O request, IORQ, signals have to be combined with the generalized strobes to provide the appropriate signals. An advantage of operating the A/D in I/O space with the Z-80 is that the CPU will automatically insert one wait state (the RD and WR strobes are extended one clock period) to allow more time for the I/O devices to respond. Logic to map the A/D in I/O space is shown in Figure 22. By using MREQ in place of IORQ, a memory-mapped configuration results. Additional I/O advantages exist as software DMA routines are available and use can be made of the output data transfer which exists on the upper 8 address lines (A8 to A15) during I/O input instructions. For example, MUX channel selection for the A/D can be accomplished with this operating mode. The 8085 also provides a generalized RD and WR strobe, with an IO/M line to distinguish I/O and memory requests. The circuit of Figure 22 can again be used, with IO/M in place of IORQ for a memory-mapped interface, and an extra inverter (or the logic equivalent) to provide IO/M for an I/O-mapped connection. 13 ADC0803, ADC0804 INT (14) I/O WR (27) (NOTE) I/O RD (25) (NOTE) 10K ADC0803 - ADC0804 ANALOG INPUTS 150pF 1 CS V+ 20 2 RD CLK R 19 5V + 10µF 3 WR DB0 18 LSB 4 CLK IN DB1 17 DB1 (16) (NOTE) 5 INTR DB2 16 DB2 (11) (NOTE) 6 VIN (+) DB3 15 DB3 (9) (NOTE) 7 VIN (-) DB4 14 DB4 (5) (NOTE) 8 AGND DB5 13 DB5 (18) (NOTE) 9 VREF/2 DB6 12 10 DGND DB7 11 MSB DB0 (13) (NOTE) DB6 (20) (NOTE) DB7 (7) (NOTE) 5V T5 OUT V+ T4 T3 T2 8131 BUS COMPARATOR B5 AD15 (36) B4 AD14 (39) B3 AD13 (38) B2 AD12 (37) T1 B1 AD11 (40) T0 B0 AD10 (1) NOTE: Pin numbers for 8228 System Controller: Others are 8080A. FIGURE 21. ADC080X TO 8080A CPU INTERFACE 14 ADC0803, ADC0804 IRQ (4) † R/W (34) [6] 10K + ADC0803 - ADC0804 RD RD ANALOG INPUTS 2 IORQ ADC0803ADC0804 150pF WR 1 CS V+ 20 2 RD CLK R 19 10µF ABC 5V (8) 1 2 3 3 WR DB0 18 LSB D0 (33) [31] 4 CLK IN DB1 17 D1 (32) [29] 5 INTR DB2 16 D2 (31) [K] 6 VIN (+) DB3 15 D3 (30) [H] 7 VIN (-) DB4 14 D4 (29) [32] 8 AGND DB5 13 D5 (28) [30] 9 VREF/2 DB6 12 10 DGND WR [D] †† DB7 11 MSB D6 (27) [L] D7 (26) [J] 3 1 74C32 2 6 3 1/ DM8092 2 4 5 A12 (22) [34] A13 (23) [N] A14 (24) [M] A15 (25) [33] VMA (5) [F] † Numbers in parentheses refer to MC6800 CPU Pinout. †† Numbers or letters in brackets refer to standard MC6800 System Common Bus Code. FIGURE 23. ADC080X TO MC6800 CPU INTERFACE FIGURE 22. MAPPING THE A/D AS AN I/O DEVICE FOR USE WITH THE Z-80 CPU 18 19 10K ADC0803 - ADC0804 ANALOG INPUTS 150pF 1 CS V+ 20 2 RD CLK R 19 CB1 CB2 MC6820 (MCS6520) 5V PIA 3 WR DB0 18 LSB 10 PB0 4 CLK IN DB1 17 11 PB1 5 INTR DB2 16 12 PB2 6 VIN (+) DB3 15 13 PB3 7 VIN (-) DB4 14 14 PB4 8 AGND DB5 13 15 PB5 DB6 12 16 PB6 17 PB7 9 VREF/2 10 DGND DB7 11 MSB FIGURE 24. ADC080X TO MC6820 PIA INTERFACE 15 ADC0803, ADC0804 Die Characteristics DIE DIMENSIONS PASSIVATION 101 mils x 93 mils Type: Nitride over Silox Nitride Thickness: 8kÅ Silox Thickness: 7kÅ METALLIZATION Type: Al Thickness: 10kÅ ±1kÅ Metallization Mask Layout ADC0803, ADC0804 AGND VIN (-) VIN (+) INTR CLK IN WR VREF/2 RD DGND CS DB7 (MSB) DB6 V+ OR VREF V+ OR VREF DB5 CLK R DB4 16 DB3 DB2 DB1 DB0 ADC0803, ADC0804 Dual-In-Line Plastic Packages (PDIP) E20.3 (JEDEC MS-001-AD ISSUE D) N 20 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AD E BASE PLANE -C- SEATING PLANE A2 A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.55 1.77 8 eA C 0.008 0.014 C D 0.980 1.060 eB NOTES: 0.355 - 26.9 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 0.204 24.89 0.100 BSC eA 0.300 BSC 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eB - 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. L 0.115 N 20 2.54 BSC 7.62 BSC 0.430 - 0.150 2.93 6 10.92 7 3.81 4 20 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 9 Rev. 0 12/93 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/quality/iso.asp. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com 17