® CT O D U C EM E N T t R P ra TE LA e nt e OL E R EP OBS ENDED upport C om/tsc il.c MM nical S nters ECO Sheet i h . R c w Data e O N ur T L or w w I act o cont -INTERS 8 8 8 1- 8-Bit, 60MSPS A/D Converter with Internal Voltage Reference The HI5667 is a monolithic, 8-bit, analog-to-digital converter fabricated in a CMOS process. It is designed for high speed applications where wide bandwidth and low power consumption are essential. Its high sample clock rate is made possible by a fully differential pipelined architecture with both an internal sample and hold and internal band-gap voltage reference. HI5667 March 2003 FN4584.2 Features • Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 60MSPS • 7.7Bits at fIN = 10MHz, fS = 60MSPS • Low Power at 60MSPS . . . . . . . . . . . . . . . . . . . . 350mW • Wide Full Power Input Bandwidth . . . . . . . . . . . . 250MHz • On-Chip Sample and Hold • Internal 2.5V Band-Gap Voltage Reference The 250MHz Full Power Input Bandwidth and superior high frequency performance of the HI5667 converter make it an excellent choice for implementing Digital IF architectures in communications applications. • Fully Differential or Single-Ended Analog Input The HI5667 has excellent dynamic performance while consuming only 350mW power at 60MSPS. Data output latches are provided which present valid data to the output bus with a latency of 7 clock cycles. • CMOS Compatible Digital Outputs. . . . . . . . . . 3.0V/5.0V • Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . +5V • TTL/CMOS Compatible Digital Inputs • Offset Binary or Two’s Complement Output Format Applications • Digital Communication Systems . Part Number Information PART NUMBER TEMP. RANGE (oC) • QAM Demodulators PKG. NO. PACKAGE SAMPLING RATE (MSPS) • Professional Video Digitizing • Medical Imaging HI5667/6CB 0 to 70 28 Ld SOIC M28.3 60 • High Speed Data Acquisition HI5667/6CA 0 to 70 28 Ld SSOP M28.15 60 Pinout HI5667EVAL2 25 Evaluation Board 60 HI5667 (SOIC, SSOP) TOP VIEW DVCC1 1 28 NC DGND 2 27 NC DVCC1 3 26 D0 DGND 4 25 D1 AVCC 5 24 D2 AGND 6 23 DVCC2 VREFIN 7 VREFOUT 8 21 DGND VIN+ 9 20 D3 VIN- 10 19 D4 VDC 11 18 D5 AGND 12 17 D6 AVCC 13 16 D7 OE 14 1 22 CLK 15 DFS CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HI5667 Functional Block Diagram VDC CLOCK BIAS CLK VINVREFOUT VIN+ REFERENCE VREFIN S/H STAGE 1 DFS 2-BIT FLASH 2-BIT DAC OE + ∑ DVCC2 X2 D7 (MSB) D6 D5 D4 DIGITAL DELAY AND DIGITAL ERROR CORRECTION STAGE M-1 D3 D2 D1 2-BIT FLASH 2-BIT DAC D0 (LSB) + ∑ - X2 DGND2 STAGE M 2-BIT FLASH AVCC 2 AGND DVCC1 DGND1 HI5667 Typical Application Schematic HI5667 (28) NC VREFIN (7) (27) NC VREFOUT (8) NC (LSB) (26) D0 D0 (25) D1 D1 (24) D2 D2 (20) D3 D3 DGND1 (2) (19) D4 D4 DGND1 (4) (18) D5 D5 DGND2 (21) (17) D6 D6 (MSB) (16) D7 D7 NC 0.1µF AGND (12) AGND (6) VIN + CLOCK VDC (11) (3) DVCC1 VIN - (10) (23) DVCC2 CLK (22) (13) AVCC DFS (15) (5) AVCC AGND BNC 10µF AND 0.1µF CAPS ARE PLACED AS CLOSE TO PART AS POSSIBLE (1) DVCC1 VIN + (9) VIN - DGND OE (14) 0.1µF + 10µF 0.1µF + 10µF +5V +5V Pin Descriptions PIN NO. NAME Digital Supply (+5.0V) 17 D6 Data Bit 6 Output DGND1 Digital Ground 18 D5 Data Bit 5 Output 3 DVCC1 Digital Supply (+5.0V) 19 D4 Data Bit 4 Output 4 DGND1 Digital Ground 20 D3 Data Bit 3 Output 5 AVCC Analog Supply (+5.0V) 21 DGND2 6 AGND Analog Ground 22 CLK 7 VREFIN +2.5V Reference Voltage Input 23 DVCC2 8 VREFOUT 24 D2 Data Bit 2 Output 9 VIN+ Positive Analog Input 25 D1 Data Bit 1 Output 10 VIN- Negative Analog Input 26 D0 Data Bit 0 Output 11 VDC DC Bias Voltage Output 27 NC No Connection 12 AGND Analog Ground 28 NC No Connection 13 AVCC Analog Supply (+5.0V) 14 OE Digital Output Enable Control Input 15 DFS Data Format Select Input 16 D7 Data Bit 7 Output (MSB) PIN NO. NAME 1 DVCC1 2 DESCRIPTION DESCRIPTION Digital Ground Sample Clock Input Digital Output Supply (+3.0V or +5.0V) +2.5V Reference Voltage Output 3 HI5667 Absolute Maximum Ratings TA = 25oC Thermal Information Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . . 6V DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DVCC Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVCC Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range HI5667/xCx (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications AVCC = DVCC1 = 5.0V, DVCC2 = 3.0V; VREFIN = VREFOUT; fS = 60MSPS at 50% Duty Cycle; CL = 10pF; TA = 25oC; Differential Analog Input; Typical Values are Test Results at 25oC, Unless Otherwise Specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ACCURACY Resolution 8 - - Bits Integral Linearity Error, INL fIN = 10MHz - ±0.3 ±1.75 LSB Differential Linearity Error, DNL (Guaranteed No Missing Codes) fIN = 10MHz - ±0.3 ±1.0 LSB Offset Error, VOS fIN = 10MHz -10 - 10 LSB Full Scale Error, FSE fIN = 10MHz - 1 - LSB 0.5 1 DYNAMIC CHARACTERISTICS Minimum Conversion Rate No Missing Codes - Maximum Conversion Rate No Missing Codes 60 MSPS Effective Number of Bits, ENOB fIN = 10MHz 7.3 7.7 - Bits Signal to Noise and Distortion Ratio, SINAD RMS Signal = -------------------------------------------------------------RMS Noise + Distortion fIN = 10MHz - 48 - dB Signal to Noise Ratio, SNR Signal= RMS -----------------------------RMS Noise Total Harmonic Distortion, THD fIN = 10MHz - 48.2 - dB fIN = 10MHz - -62 - dBc 2nd Harmonic Distortion fIN = 10MHz - -69 - dBc 3rd Harmonic Distortion fIN = 10MHz - -63 - dBc Spurious Free Dynamic Range, SFDR fIN = 10MHz - 63 - dBc MSPS Transient Response (Note 2) - 1 - Cycle Over-Voltage Recovery 0.2V Overdrive (Note 2) - 1 - Cycle Maximum Peak-to-Peak Differential Analog Input Range (VIN+ - VIN-) - ±0.5 - V Maximum Peak-to-Peak Single-Ended Analog Input Range - 1.0 - V - 1 - MΩ - 10 - pF ANALOG INPUT Analog Input Resistance, RIN (Note 3) Analog Input Capacitance, CIN Analog Input Bias Current, IB+ or IB- (Note 3) -10 - +10 µA Differential Analog Input Bias Current IBDIFF = (IB+ - IB-) (Note 3) - ±0.5 - µA Full Power Input Bandwidth, FPBW - 250 - MHz 0.25 - 4.75 V Reference Voltage Output, VREFOUT (Loaded) - 2.5 - V Reference Output Current, IREFOUT - 1 2 mA Analog Input Common Mode Voltage Range (VIN+ + VIN-) / 2 Differential Mode (Note 2) INTERNAL REFERENCE VOLTAGE 4 HI5667 Electrical Specifications AVCC = DVCC1 = 5.0V, DVCC2 = 3.0V; VREFIN = VREFOUT; fS = 60MSPS at 50% Duty Cycle; CL = 10pF; TA = 25oC; Differential Analog Input; Typical Values are Test Results at 25oC, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS Reference Temperature Coefficient MIN TYP MAX UNITS - 120 - ppm/oC REFERENCE VOLTAGE INPUT Reference Voltage Input, VREFIN - 2.5 - V Total Reference Resistance, RREFIN - 2.5 - kΩ Reference Input Current, IREFIN - 1 - mA DC Bias Voltage Output, VDC - 3.0 - V Maximum Output Current - - 0.2 mA V DC BIAS VOLTAGE DIGITAL INPUTS Input Logic High Voltage, VIH CLK, DFS, OE 2.0 - - Input Logic Low Voltage, VIL CLK, DFS, OE - - 0.8 V Input Logic High Current, IIH CLK, DFS, OE, VIH = 5V -10.0 - +10.0 µA Input Logic Low Current, IIL CLK, DFS, OE, VIL = 0V -10.0 - +10.0 µA - 7 - pF V Input Capacitance, CIN DIGITAL OUTPUTS Output Logic High Voltage, VOH IOH = 100µA; DVCC2 = 5V 4.0 - - Output Logic Low Voltage, VOL IOL = 100µA; DVCC2 = 5V - - 0.8 V Output Three-State Leakage Current, IOZ VO = 0/5V; DVCC2 = 5V -10 ±1 10 µA Output Logic High Voltage, VOH IOH = 100µA; DVCC2 = 3V 2.4 - - V Output Logic Low Voltage, VOL IOL = 100µA; DVCC2 = 3V - - 0.5 V Output Three-State Leakage Current, IOZ VO = 0/5V; DVCC2 = 3V -10 ±1 10 µA - 10 - pF Aperture Delay, tAP - 5 - ns Aperture Jitter, tAJ - 5 - psRMS Output Capacitance, COUT TIMING CHARACTERISTICS Data Output Hold, tH - 5 - ns Data Output Delay, tOD - 6 - ns Data Output Enable Time, tEN - 5 - ns Data Output Enable Time, tDIS - 5 - ns Data Latency, tLAT For a Valid Sample (Note 2) - - 7 Cycles Power-Up Initialization Data Invalid Time (Note 2) - - 20 Cycles Sample Clock Pulse Width (Low) fS = 60MSPS 7.5 8.33 - ns Sample Clock Pulse Width (High) fS = 60MSPS 7.5 8.33 - ns Sample Clock Duty Cycle Variation fS = 60MSPS - ±5 - % Analog Supply Voltage, AVCC 4.75 5.0 5.25 V Digital Supply Voltage, DVCC1 4.75 5.0 5.25 V POWER SUPPLY CHARACTERISTICS Digital Output Supply Voltage, DVCC2 At 3.0V 2.7 3.0 3.3 V At 5.0V 4.75 5.0 5.25 V Total Supply Current, ICC fIN = 10MHz and DFS = “0” - 70 92 mA Analog Supply Current, AICC fIN = 10MHz and DFS = “0” - 47 63 mA Digital Supply Current, DICC fIN = 10MHz and DFS = “0” - 21 25 mA Output Supply Current, DICC2 fIN = 10MHz and DFS = “0” - 2 4 mA Power Dissipation fIN = 10MHz and DFS = “0” - 346 452 mW Offset Error Sensitivity, ∆VOS AVCC or DVCC = 5V ±5% - ±0.175 - LSB Gain Error Sensitivity, ∆FSE AVCC or DVCC = 5V ±5% - ±0.025 - LSB NOTES: 2. Parameter guaranteed by design or characterization and not production tested. 3. With the clock low and DC input. 5 HI5667 Timing Waveforms ANALOG INPUT CLOCK INPUT SN - 1 HN - 1 SN HN SN + 1 HN + 1 SN + 2 SN + 5 HN + 5 S N + 6 HN + 6 S N + 7 HN + 7 S N + 8 HN + 8 INPUT S/H 1ST STAGE 2ND STAGE B1 , N - 1 B2 , N - 2 MTH STAGE DATA OUTPUT B1 , N B1 , N + 1 B2 , N - 1 B2 , N BM, N - 5 BM , N - 4 DN - 7 B1 , N + 4 DN - 6 DN - 2 B1 , N + 5 B1 , N + 6 B2 , N + 4 B2 , N + 5 B2 , N + 6 BM, N BM, N + 1 B M, N + 2 DN - 1 tLAT NOTES: 4. SN : N-th sampling period. 5. HN : N-th holding period. 6. BM , N : M-th stage digital output corresponding to N-th sampled input. 7. DN : Final data output corresponding to N-th sampled input. FIGURE 1. HI5667 INTERNAL CIRCUIT TIMING ANALOG INPUT tAP tAJ CLOCK INPUT 1.5V 1.5V tOD tH 2.4V DATA OUTPUT DATA N-1 DATA N 0.5V FIGURE 2. INPUT-TO OUTPUT TIMING 6 B1 , N + 7 DN BM, N + 3 DN + 1 HI5667 Detailed Description Theory of Operation The HI5667 is an 8-Bit fully differential sampling pipeline A/D converter with digital error correction logic. Figure 3 depicts the circuit for the front end differential-in-differential-out sample-and-hold (S/H). The switches are controlled by an internal sampling clock which is a non-overlapping two phase signal, Φ1 and Φ2 , derived from the master sampling clock. During the sampling phase, Φ1 , the input signal is applied to the sampling capacitors, CS . At the same time the holding capacitors, CH, are discharged to analog ground. At the falling edge of Φ1 the input signal is sampled on the bottom plates of the sampling capacitors. In the next clock phase, F2 , the two bottom plates of the sampling capacitors are connected together and the holding capacitors are switched to the op amp output nodes. The charge then redistributes between CS and CH completing one sampleand-hold cycle. The front end sample-and-hold output is a fully-differential, sampled-data representation of the analog input. The circuit not only performs the sample-and-hold function but will also convert a single-ended input to a fullydifferential output for the converter core. During the sampling phase, the VIN pins see only the on-resistance of a switch and CS . The relatively small values of these components result in a typical full power input bandwidth of 250MHz for the converter. Φ1 VIN+ Φ1 Φ1 Φ1 CS Φ2 VIN- CH -+ VOUT+ +- VOUT- CS Φ1 CH Φ1 FIGURE 3. ANALOG INPUT SAMPLE-AND-HOLD As illustrated in the functional block diagram and the timing diagram in Figure 1, identical pipeline subconverter stages, each containing a two-bit flash converter and a two-bit multiplying digital-to-analog converter, follow the S/H circuit with the last stage being a two bit flash converter. Each converter stage in the pipeline will be sampling in one phase and amplifying in the other clock phase. Each individual subconverter clock signal is offset by 180 degrees from the previous stage clock signal resulting in alternate stages in the pipeline performing the same operation. The output of each of the identical two-bit subconverter stages is a two-bit digital word containing a supplementary bit to be used by the digital error correction logic. The output of each subconverter stage is input to a digital delay line which is controlled by the internal sampling clock. The function of the digital delay line is to time align the digital 7 outputs of the identical two-bit subconverter stages with the corresponding output of the last stage flash converter before applying the results to the digital error correction logic. The digital error correction logic uses the supplementary bits to correct any error that may exist before generating the final ten bit digital data output of the converter. Because of the pipeline nature of this converter, the digital data representing an analog input sample is output to the digital data bus on the 7th cycle of the clock after the analog sample is taken. This time delay is specified as the data latency. After the data latency time, the digital data representing each succeeding analog sample is output during the following clock cycle. The digital output data is synchronized to the external sampling clock by a double buffered latching technique. The digital output data is available in two’s complement or offset binary format depending on the state of the Data Format Select (DFS) control input (see Table 1, A/D Code Table). Internal Reference Voltage Output, VREFOUT The HI5667 is equipped with an internal reference voltage generator, therefore, no external reference voltage is required. VREFOUT must be connected to VREFIN when using the internal reference voltage. An internal band-gap reference voltage followed by an amplifier/buffer generates the precision +2.5V reference voltage used by the converter. A 4:1 array of substrate PNPs generates the “delta-VBE” and a two-stage op amp closes the loop to create an internal +1.25V band-gap reference voltage. This voltage is then amplified by a wideband uncompensated operational amplifier connected in a gain-of-two configuration. An external, user-supplied, 0.1µF capacitor connected from the VREFOUT output pin to analog ground is used to set the dominant pole and to maintain the stability of the operational amplifier. Reference Voltage Input, VREFIN The HI5667 is designed to accept a +2.5V reference voltage source at the VREFIN input pin. Typical operation of the converter requires VREFIN to be set at +2.5V. The HI5667 is tested with VREFIN connected to VREFOUT yielding a fully differential analog input voltage range of ±0.5V. The user does have the option of supplying an external +2.5V reference voltage. As a result of the high input impedance presented at the VREFIN input pin, 2.5kΩ typically, the external reference voltage being used is only required to source 1mA of reference input current. In the situation where an external reference voltage will be used an external 0.1mF capacitor must be connected from the VREFOUT output pin to analog ground in order to maintain the stability of the internal operational amplifier. In order to minimize overall converter noise it is recommended that adequate high frequency decoupling be provided at the reference voltage input pin, VREFIN . HI5667 Analog Input, Differential Connection The analog input to the HI5667 is a differential input that can be configured in various ways depending on the signal source and the required level of performance. A fully differential connection (Figure 4 and Figure 5) will deliver the best performance from the converter. Since the HI5667 is powered by a single +5V analog supply, the analog input is limited to be between ground and +5V. For the differential input connection this implies the analog input common mode voltage can range from 0.25V to 4.75V. The performance of the ADC does not change significantly with the value of the analog input common mode voltage. connected from VIN+ to VIN- will help filter any high frequency noise on the inputs, also improving performance. Values around 20pF are sufficient and can be used on AC coupled inputs as well. Note, however, that the value of capacitor C chosen must take into account the highest frequency component of the analog input signal. Analog Input, Single-Ended Connection The configuration shown in Figure 6 may be used with a single ended AC coupled input. VIN+ VIN R HI5667 VDC VIN+ VIN R HI5667 VIN- FIGURE 6. AC COUPLED SINGLE ENDED INPUT VDC R -VIN VIN- FIGURE 4. AC COUPLED DIFFERENTIAL INPUT A DC voltage source, VDC , equal to 3.2V (typical), is made available to the user to help simplify circuit design when using an AC coupled differential input. This low output impedance voltage source is not designed to be a reference but makes an excellent DC bias source and stays well within the analog input common mode voltage range over temperature. For the AC coupled differential input (Figure 4) and with VREFIN connected to VREFOUT , full scale is achieved when the VIN and -VIN input signals are 0.5VP-P , with -VIN being 180 degrees out of phase with VIN . The converter will be at positive full scale when the VIN+ input is at VDC + 0.25V and the VIN- input is at VDC - 0.25V (VIN+ - VIN- = +0.5V). Conversely, the converter will be at negative full scale when the VIN+ input is equal to VDC - 0.25V and VIN- is at VDC + 0.25V (VIN+ - VIN- = -0.5V). The analog input can be DC coupled (Figure 5) as long as the inputs are within the analog input common mode voltage range (0.25V ≤ VDC ≤ 4.75V). VIN VIN+ VDC R C HI5667 VDC -VIN R VDC VIN- FIGURE 5. DC COUPLED DIFFERENTIAL INPUT The resistors, R, in Figure 5 are not absolutely necessary but may be used as load setting resistors. A capacitor, C, 8 Again, with VREFIN connected to VREFOUT, if VIN is a 1VP-P sinewave, then VIN+ is a 1.0VP-P sinewave riding on a positive voltage equal to VDC. The converter will be at positive full scale when VIN+ is at VDC + 0.5V (VIN+ - VIN- = +0.5V) and will be at negative full scale when VIN+ is equal to VDC - 0.5V (VIN+ - VIN= -0.5V). Sufficient headroom must be provided such that the input voltage never goes above +5V or below AGND. In this case, VDC could range between 0.5V and 4.5V without a significant change in ADC performance. The simplest way to produce VDC is to use the DC bias source, VDC, output of the HI5667. The single ended analog input can be DC coupled (Figure 7) as long as the input is within the analog input common mode voltage range. VIN VIN+ VDC R C VDC HI5667 VIN- FIGURE 7. DC COUPLED SINGLE ENDED INPUT The resistor, R, in Figure 7 is not absolutely necessary but may be used as a load setting resistor. A capacitor, C, connected from VIN+ to VIN- will help filter any high frequency noise on the inputs, also improving performance. Values around 20pF are sufficient and can be used on AC coupled inputs as well. Note, however, that the value of capacitor C chosen must take into account the highest frequency component of the analog input signal. A single ended source may give better overall system performance if it is first converted to differential before driving the HI5667. HI5667 TABLE 1. A/D CODE TABLE OFFSET BINARY OUTPUT CODE (DFS LOW) CODE CENTER DESCRIPTION DIFFERENTIAL INPUT VOLTAGE (VIN+ - VIN-) +Full Scale (+FS) -7/16 LSB +FS - 17/16 LSB +9/16 LSB -7/16 LSB -FS + 19/16 LSB -Full Scale (-FS) + 9/16 LSB M S B D7 D6 D5 D4 D3 D2 D1 TWO’S COMPLEMENT OUTPUT CODE (DFS HIGH) L S B M S B D0 D7 L S B D6 D5 D4 D3 D2 D1 D0 0.498291V 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0.494385V 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 2.19727mV 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1.70898V 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -0.493896V 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 -0.497803V 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 NOTE: 8. The voltages listed above represent the ideal center of each output code shown with VREFIN = +2.5V. Digital Output Control and Clock Requirements The HI5667 provides a standard high-speed interface to external TTL logic families. In order to ensure rated performance of the HI5667, the duty cycle of the clock should be held at 50% ±5%. It must also have low jitter and operate at standard TTL levels. Performance of the HI5667 will only be guaranteed at conversion rates above 1MSPS. This ensures proper performance of the internal dynamic circuits. Similarly, when power is first applied to the converter, a maximum of 20 cycles at a sample rate above 1MSPS will have to be performed before valid data is available. A Data Format Select (DFS) pin is provided which will determine the format of the digital data outputs. When at logic low, the data will be output in offset binary format. When at logic high, the data will be output in two’s complement format. Refer to Table 1 for further information. The output enable pin, OE, when pulled high will three-state the digital outputs to a high impedance state. Set the OE input to logic low for normal operation. OE INPUT DIGITAL DATA OUTPUTS 0 Active 1 High Impedance Supply and Ground Considerations frequency decoupling capacitors mounted as close as possible to the converter. If the part is powered off a single supply then the analog supply should be isolated with a ferrite bead from the digital supply. Refer to the application note “Using Intersil High Speed A/D Converters” (AN9214) for additional considerations when using high speed converters. Static Performance Definitions Offset Error (VOS) The midscale code transition should occur at a level 1/4 LSB above half-scale. Offset is defined as the deviation of the actual code transition from this point. Full-Scale Error (FSE) The last code transition should occur for an analog input that is 3/4 LSB below Positive Full Scale (+FS) with the offset error removed. Full scale error is defined as the deviation of the actual code transition from this point. Differential Linearity Error (DNL) DNL is the worst case deviation of a code width from the ideal value of 1 LSB. Integral Linearity Error (INL) INL is the worst case deviation of a code center from a best fit straight line calculated from the measured data. The HI5667 has separate analog and digital supply and ground pins to keep digital noise out of the analog signal path. The digital data outputs also have a separate supply pin, DVCC2 , which can be powered from a 3.0V or 5.0V supply. This allows the outputs to interface with 3.0V logic if so desired. Power Supply Sensitivity The part should be mounted on a board that provides separate low impedance connections for the analog and digital supplies and grounds. For best performance, the supplies to the HI5667 should be driven by clean, linear regulated supplies. The board should also have good high Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the HI5667. A low distortion sine wave is applied to the input, it is coherently sampled, and the output is stored in RAM. The data is then transformed into the frequency domain with an FFT and analyzed to evaluate the 9 Each of the power supplies are moved plus and minus 5% and the shift in the offset and full scale error (in LSBs) is noted. Dynamic Performance Definitions HI5667 dynamic performance of the A/D. The sine wave input to the part is typically -0.5dB down from full scale for all these tests. SNR and SINAD are quoted in dB. The distortion numbers are quoted in dBc (decibels with respect to carrier) and DO NOT include any correction factors for normalizing to full scale. The Effective Number of Bits (ENOB) is calculated from the SINAD data by: ENOB = (SINAD - 1.76 + VCORR) / 6.02, where: VCORR = 0.5 dB (Typical). Full Power Input Bandwidth (FPBW) Full power input bandwidth is the analog input frequency at which the amplitude of the digitally reconstructed output has decreased 3dB below the amplitude of the input sine wave. The input sine wave has an amplitude which swings from -FS to +FS. The bandwidth given is measured at the specified sampling frequency. Video Definitions VCORR adjusts the SINAD, and hence the ENOB, for the amount the analog input signal is backed off from full scale. Differential Gain and Differential Phase are two commonly found video specifications for characterizing the distortion of a chrominance signal as it is offset through the input voltage range of an ADC. Signal To Noise and Distortion Ratio (SINAD) Differential Gain (DG) SINAD is the ratio of the measured RMS signal to RMS sum of all the other spectral components below the Nyquist frequency, fS/2, excluding DC. Differential Gain is the peak difference in chrominance amplitude (in percent) relative to the reference burst. Signal To Noise Ratio (SNR) Differential Phase is the peak difference in chrominance phase (in degrees) relative to the reference burst. SNR is the ratio of the measured RMS signal to RMS noise at a specified input and sampling frequency. The noise is the RMS sum of all of the spectral components below fS /2 excluding the fundamental, the first five harmonics and DC. Differential Phase (DP) Timing Definitions Refer to Figure 1 and Figure 2 for these definitions. Total Harmonic Distortion (THD) Aperture Delay (tAP) THD is the ratio of the RMS sum of the first 5 harmonic components to the RMS value of the fundamental input signal. Aperture delay is the time delay between the external sample command (the falling edge of the clock) and the time at which the signal is actually sampled. This delay is due to internal clock path propagation delays. 2nd and 3rd Harmonic Distortion This is the ratio of the RMS value of the applicable harmonic component to the RMS value of the fundamental input signal. Spurious Free Dynamic Range (SFDR) Aperture Jitter (tAJ) Aperture jitter is the RMS variation in the aperture delay due to variation of internal clock path delays. SFDR is the ratio of the fundamental RMS amplitude to the RMS amplitude of the next largest spectral component in the spectrum below fS /2. Data Hold Time (tH) Intermodulation Distortion (IMD) Data Output Delay Time (tOD) Nonlinearities in the signal path will tend to generate intermodulation products when two tones, f1 and f2 , are present at the inputs. The ratio of the measured signal to the distortion terms is calculated. The terms included in the calculation are (f1+f2), (f1-f2), (2f1), (2f2), (2f1+f2), (2f1-f2), (f1+2f2), (f1-2f2). The ADC is tested with each tone 6dB below full scale. Data output delay time is the time from the rising edge of the external sample clock to where the new data (N) is valid. Transient Response Transient response is measured by providing a full-scale transition to the analog input of the ADC and measuring the number of cycles it takes for the output code to settle within 8-Bit accuracy. Over-Voltage Recovery Over-Voltage Recovery is measured by providing a full-scale transition to the analog input of the ADC which overdrives the input by 200mV, and measuring the number of cycles it takes for the output code to settle within 8-Bit accuracy. 10 Data hold time is the time to where the previous data (N - 1) is no longer valid. Data Latency (tLAT) After the analog sample is taken, the digital data representing an analog input sample is output to the digital data bus on the 7th cycle of the clock after the analog sample is taken. This is due to the pipeline nature of the converter where the analog sample has to ripple through the internal subconverter stages. This delay is specified as the data latency. After the data latency time, the digital data representing each succeeding analog sample is output during the following clock cycle. The digital data lags the analog input sample by 7 sample clock cycles. Power-Up Initialization This time is defined as the maximum number of clock cycles that are required to initialize the converter at power-up. The requirement arises from the need to initialize the dynamic circuits within the converter.