HI5703 Datasheet

NDS
OMME
C
E
R
ERSIL
6KCB
S, INT
N
G
I
HI574
S
E
R
D
O
Data
Sheet
November 1998
CB
EW
FOR N HE HI5767/4
T
HI5703
TM
File Number
3950.7
10-Bit, 40 MSPS A/D Converter
Features
The HI5703 is a monolithic, 10-bit, analog-to-digital
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 40 MSPS
[ /Title converter fabricated in Intersil’s BiCMOS process. It is
(HI5703 designed for high speed applications where wide bandwidth
and low power consumption are essential. Its 40 MSPS
)
speed is made possible by a fully differential pipeline
/Subarchitecture with an internal sample and hold.
ject (10Bit, 40 The HI5703 has excellent dynamic performance while
MSPS consuming only 400mW power at 40 MSPS. Data output
latches are provided which present valid data to the output
A/D
bus with a latency of 7 clock cycles. It is pin-to-pin
Concompatible with the HI5702.
verter)
For lower power consumption or internal reference, please
/Author refer to the HI5746 or HI5767.
()
/KeyOrdering Information
words
(Intersil
TEMP.
PKG.
PART NUMBER RANGE (oC)
PACKAGE
NO.
Semi0 to 70
28 Ld SOIC (W)
M28.3
conduc- HI5703KCB
tor,
HI5703EVAL
25
Evaluation Board
A/D,
Pinout
Analog
HI5703
to Digi(SOIC)
tal ConTOP VIEW
verter,
28 D0
DVCC1 1
Narrow
27 D1
2
DGND
Band,
26 D2
DVCC1 3
Com25 D3
4
DGND
munica24 D4
5
AVCC
tions,
23 DVCC2
AGND 6
High
22 CLK
VREF + 7
Speed
21 DGND
VREF - 8
Convert20 D5
VIN+ 9
19 D6
ers,
VIN- 10
18 D7
11
VDC
High
17 D8
12
AGND
Resolu16 D9
AVCC 13
tion
15 DFS
OE 14
Converters, Basestation,
4-1
• 8.55 Bits Guaranteed at fIN = 10MHz
• Low Power
• Wide Full Power Input Bandwidth. . . . . . . . . . . . . 250MHz
• On Chip Sample and Hold
• Fully Differential or Single-Ended Analog Input
• Single Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . +5V
• TTL Compatible Interface
• 3.3V Digital Outputs Available
Applications
• Professional Video Digitizing
• Medical Imaging
• Digital Communication Systems
• High Speed Data Acquisition
• Additional Reference Documents
- AN9534 Using the HI5703 Evaluation Board
- AN9413 Driving the Analog Input of the HI5702
- AN9214 Using Intersil High Speed A/D Converters
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-7143 | Copyright © Intersil Corporation 1998
Typical Application Schematic
HI5703
3.25V
2.0V
VREF+ (7)
VREF - (8)
(LSB) (28) D0
D0
(27) D1
D1
(26) D2
D2
(25) D3
D3
(24) D4
D4
DGND (2)
(20) D5
D5
DGND (21)
(19) D6
D6
DGND (4)
(18) D7
D7
(17) D8
D8
(MSB) (16) D9
D9
AGND (12)
AGND (6)
VIN +
VIN -
CLOCK
VIN + (9)
VDC (11)
(3) DVCC1
VIN - (10)
(23) DVCC2
CLK (22)
(13) AVCC
DFS (15)
(5) AVCC
OE (14)
4-2
(1) DVCC1
DGND
AGND
BNC
10µF AND 0.1µF CAPS
ARE PLACED AS CLOSE
TO PART AS POSSIBLE
0.1µF
+
10µF
0.1µF
+
10µF
+5V
+5V
Functional Block Diagram
VDC
CLOCK
BIAS
CLK
VINVIN+
S/H
STAGE 1
DFS
2-BIT
FLASH
2-BIT
DAC
OE
+
∑
-
X2
D9 (MSB)
D8
D7
D6
DIGITAL DELAY
AND
DIGITAL ERROR
CORRECTION
STAGE 9
D5
D4
D3
2-BIT
FLASH
2-BIT
DAC
D2
D1
+
∑
D0 (LSB)
-
X2
STAGE 10
1-BIT
FLASH
AVCC
4-3
AGND
DVCC1
DVCC2
DGND
VREF +
VREF -
Absolute Maximum Ratings
TA = 25oC
Thermal Information
Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . +6V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DVCC
Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVCC
Operating Conditions
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
Temperature Range, HI5703KCB . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AVCC = DVCC1 = DVCC2 = +5.0V; VREF+ = 3.25V; VREF - = 2.0V; fS = 36 MSPS at 50% Duty
Cycle; CL = 20pF; TA = 25oC; Differential Analog Input; Unless Otherwise Specified
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
10
-
-
Bits
ACCURACY
Resolution
Integral Linearity Error, INL
fIN = DC
-
±1
±2.0
LSB
Differential Linearity Error, DNL
(Guaranteed No Missing Codes)
fIN = DC
-
±0.5
±1
LSB
Offset Error, VOS
fIN = DC
-
4
-
LSB
Full Scale Error, FSE
fIN = DC
-
1
-
LSB
Minimum Conversion Rate
No Missing Codes
-
0.5
1
MSPS
Maximum Conversion Rate
No Missing Codes
40
-
-
MSPS
Effective Number of Bits, ENOB
fIN = 1MHz
-
9.2
-
Bits
fIN = 5MHz
-
9.2
-
Bits
fIN = 10MHz
8.55
8.9
-
Bits
fIN = 1MHz
-
57
-
dB
fIN = 5MHz
-
57
-
dB
fIN = 10MHz
53.2
55
-
dB
fIN = 1MHz
-
58
-
dB
fIN = 5MHz
-
58
-
dB
fIN = 10MHz
53.2
57
-
dB
fIN = 1MHz
-
-64
-
dBc
fIN = 5MHz
-
-63
-
dBc
fIN = 10MHz
-
-60
-
dBc
fIN = 1MHz
-
-75
-
dBc
fIN = 5MHz
-
-75
-
dBc
fIN = 10MHz
-
-73
-
dBc
fIN = 1MHz
-
-66
-
dBc
fIN = 5MHz
-
-64
-
dBc
fIN = 10MHz
-
-63
-
dBc
DYNAMIC CHARACTERISTICS
Signal to Noise and Distortion Ratio, SINAD
RMS Signal
= -------------------------------------------------------------RMS Noise + Distortion
Signal to Noise Ratio, SNR
RMS Signal
= --------------------------------RMS Noise
Total Harmonic Distortion, THD
2nd Harmonic Distortion
3rd Harmonic Distortion
4-4
Electrical Specifications
AVCC = DVCC1 = DVCC2 = +5.0V; VREF+ = 3.25V; VREF - = 2.0V; fS = 36 MSPS at 50% Duty
Cycle; CL = 20pF; TA = 25oC; Differential Analog Input; Unless Otherwise Specified (Continued)
PARAMETER
Spurious Free Dynamic Range, SFDR
TEST CONDITION
MIN
TYP
MAX
UNITS
fIN = 1MHz
-
66
-
dBc
fIN = 5MHz
-
64
-
dBc
fIN = 10MHz
54
63
-
dBc
Intermodulation Distortion, IMD
f1 = 1MHz, f2 = 1.02MHz
-
-59
-
dBc
Differential Gain Error
fS = 17.72MHz, 6 Step, Mod Ramp
-
0.5
-
%
Differential Phase Error
fS = 17.72MHz, 6 Step, Mod Ramp
-
0.1
-
Degree
-
1
-
Cycle
-
1
-
Cycle
Maximum Peak-to-Peak Differential Analog Input Range (VIN+ - VIN-)
-
±1.25
-
V
Maximum Peak-to-Peak Single-Ended
Analog Input Range
-
2.5
-
V
MΩ
Transient Response
Over-Voltage Recovery
0.2V Overdrive
ANALOG INPUT
(Note 3)
Analog Input Resistance, RIN
Analog Input Capacitance, CIN
Analog Input Bias Current, IB+ or IB-
(Note 3)
Differential Analog Input Bias Current
IB DIFF = (IB+ - IB-)
Analog Input Common Mode Voltage Range
(VIN+ + VIN-) / 2
Differential Mode (Note 1)
Full Power Input Bandwidth (FPBW)
-
1
-
-
7
-
pF
-10
-
+10
µA
-
±0.5
-
µA
0.625
-
4.375
V
-
250
-
MHz
REFERENCE INPUT
Total Reference Resistance, RL
300
400
500
Ω
Reference Current
2.5
3.125
4.2
mA
-
3.25
3.3
V
Positive Reference Voltage Input, VREF+
(Note 2)
Negative Reference Voltage Input, VREF -
(Note 2)
1.95
2.0
-
V
Reference Common Mode Voltage
(VREF+ + VREF -) / 2
(Note 2)
2.575
2.625
2.675
V
DC Bias Voltage Output, VDC
-
2.8
-
V
Max Output Current
-
-
1
mA
2.0
-
-
V
DC BIAS VOLTAGE
DIGITAL INPUTS
Input Logic High Voltage, VIH
-
-
0.8
V
Input Logic High Current, IIH
VIH = 5V
-
-
10.0
µA
Input Logic Low Current, IIL
VIL = 0V
-
-
10.0
µA
-
7
-
pF
Input Logic Low Voltage, VIL
Input Capacitance, CIN
DIGITAL OUTPUTS
Output Logic Sink Current, IOL
VO = 0.4V; DVCC2 = 5V
1.6
-
-
mA
Output Logic Source Current, IOH
VO = 2.4V; DVCC2 = 5V
-0.2
-
-
mA
Output Three-State Leakage Current, IOZ
VO = 0/5V; DVCC2 = 5V
-
±1
±10
µA
Output Logic Sink Current, IOL
VO = 0.4V; DVCC2 = 3.3V
1.6
-
-
mA
Output Logic Source Current, IOH
VO = 2.4V; DVCC2 = 3.3V
-0.2
-
-
mA
Output Three-State Leakage Current, IOZ
VO = 0/3.3V; DVCC2 = 3.3V
-
±1
±10
µA
-
5
-
pF
Output Capacitance, COUT
4-5
Electrical Specifications
AVCC = DVCC1 = DVCC2 = +5.0V; VREF+ = 3.25V; VREF - = 2.0V; fS = 36 MSPS at 50% Duty
Cycle; CL = 20pF; TA = 25oC; Differential Analog Input; Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
Aperture Delay, tAP
-
5
-
ns
Aperture Jitter, tAJ
-
5
-
ps
Data Output Delay, tOD
-
7
-
ns
5
7
18
ns
TIMING CHARACTERISTICS
AVCC = DVCC1 = 5V ±10%,
DVCC2 = 3.3V ±5%,
0oC ≤TA ≤70oC
Data Output Hold, tH
-
4
-
ns
Data Output Enable Time, tEN
-
7
-
ns
Data Output Enable Time, tDIS
-
7
-
ns
ns
Clock Pulse Width (Low)
40 MSPS Clock
11.875
12.5
13.125
Clock Pulse Width (High)
40 MSPS Clock
11.875
12.5
13.125
ns
Data Latency, tLAT
For a Valid Sample (Note 2)
-
-
7
Cycles
Power-Up Initialization
Data Invalid Time (Note 2)
-
-
20
Cycles
Analog Supply Voltage, AVCC
4.75
5.0
5.25
V
Digital Supply Voltage, DVCC1
4.75
5.0
5.25
V
At 3.30V
3.135
3.3
3.465
V
At 5.0V
POWER SUPPLY CHARACTERISTICS
Digital Output Supply Voltage, DVCC2
4.75
5.0
5.25
V
Total Supply Current, ICC
VIN+ - VIN- = +1.25V and DFS = “0”
-
80
-
mA
Analog Supply Current, AICC
VIN+ - VIN- = +1.25V and DFS = “0”
-
48
-
mA
Digital Supply Current, DICC1
VIN+ - VIN- = +1.25V and DFS = “0”
-
30
-
mA
Digital Output Supply Current, DICC2
VIN+ - VIN- = +1.25V and DFS = “0”
-
2
-
mA
Power Dissipation
VIN+ - VIN- = +1.25V and DFS = “0”
-
400
-
mW
Offset Error Sensitivity, ∆VOS
AVCC or DVCC = 5V ±5%
-
±1.5
-
LSB
Full Scale Error Sensitivity, ∆FSE
AVCC or DVCC = 5V ±5%
-
±0.2
-
LSB
NOTES:
2. Parameter guaranteed by design or characterization and not production tested.
3. With the clock low and DC input.
4-6
Timing Waveforms
ANALOG
INPUT
CLOCK
INPUT
SN - 1
HN - 1
SN
HN
SN + 1 H N + 1
SN + 2
SN + 5 HN + 5 SN + 6
H N + 6 SN + 7
HN + 7 SN + 8 HN + 8
INPUT
S/H
1ST
STAGE
2ND
STAGE
B1, N - 1
B2, N - 2
10TH
STAGE
DATA
OUTPUT
B1, N
B1, N + 1
B1, N + 4
B1, N + 5
B2, N
B2, N + 4
B2, N + 5
B2, N + 6
B10, N - 5
B10, N - 4
B10, N
B10, N + 1
B10, N + 2
DN - 6
DN - 2
DN - 1
tLAT
NOTES:
4. SN : N-th sampling period.
5. HN : N-th holding period.
6. BM , N : M-th stage digital output corresponding to N-th sampled input.
7. DN : Final data output corresponding to N-th sampled input.
FIGURE 1. HI5703 INTERNAL CIRCUIT TIMING
ANALOG
INPUT
tAP
tAJ
1.5V
1.5V
tOD
tH
DATA
OUTPUT
2.0V
DATA N - 1
DATA N
0.8V
FIGURE 2. INPUT-TO-OUTPUT TIMING
4-7
B1, N + 7
B2, N - 1
DN - 7
CLOCK
INPUT
B1, N + 6
DN
B10, N + 3
DN + 1
Typical Performance Curves
fS = 40 MSPS
TEMPERATURE = 25oC
-40
fS = 40 MSPS
TEMPERATURE = 25oC
-45
THD
8.0
-50
dBc
EFFECTIVE NUMBER OF BITS (ENOB)
-35
9.0
-55
-60
7.0
-65
SFDR
-70
6.0
1
2
4
6
8 10
20
40
-75
60 80 100
1
2
4
6
8
10
20
40
60 80 100
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
NOTE: SFDR depicted here does not include any harmonic distortion.
FIGURE 3. EFFECTIVE NUMBER OF BITS (ENOB) vs INPUT
FREQUENCY
FIGURE 4. TOTAL HARMONIC DISTORTION (THD) AND
SPURIOUS FREE DYNAMIC RANGE (SFDR) vs
INPUT FREQUENCY
450
65
430
SNR
60
POWER DISSIPATION (mW)
-THD
dB
55
SINAD
50
fS = 40 MSPS
TEMPERATURE = 25oC
45
40
VIN + - VIN- = +1.25V AND DFS = “0”
TEMPERATURE = 25oC
410
390
370
350
330
310
290
270
250
35
1
2
4
6 8 10
20
INPUT FREQUENCY (MHz)
40
60 80 100
FIGURE 5. SINAD, SNR, AND -THD vs INPUT FREQUENCY
4-8
0
5
10
15
20
25
30
fS (MSPS)
35
40
45
50
FIGURE 6. POWER DISSIPATION vs SAMPLE FREQUENCY
Typical Performance Curves
(Continued)
10.0
40 MSPS
8.5
OUTPUT DELAY TIME (ns)
EFFECTIVE NUMBER OF BITS (ENOB)
9.0
8.0
45 MSPS
7.5
7.0
6.5
fIN = 10MHz
6.0
50 MSPS
9.0
8.0
7.0
tOD
6.0
5.5
5.0
-40
-20
0
20
40
60
80
5.0
-40 -30 -20 -10
100
0
TEMPERATURE (oC)
FIGURE 7. EFFECTIVE NUMBER OF BITS (ENOB) vs
TEMPERATURE AND SAMPLE FREQUENCY
EFFECTIVE NUMBER OF BITS (ENOB)
POWER DISSIPATION (mW)
30
40
50
60
70
80 85
9.0
fS = 40 MSPS
VIN+ - VIN- = 1.25V, DFS = 0
430
420
410
400
390
380
-40
20
FIGURE 8. OUTPUT DELAY TIME (TOD) vs TEMPERATURE
450
440
10
TEMPERATURE (oC)
fS = 40 MSPS
fIN = 10MHz
TEMPERATURE = 25oC
8.5
8.0
7.5
-20
0
20
40
60
80
TEMPERATURE (oC)
FIGURE 9. POWER DISSIPATION vs TEMPERATURE
4-9
85
45
46
47
48
49
50
51
52
DUTY CYCLE (%)
53
54
55
FIGURE 10. EFFECTIVE NUMBER OF BITS (ENOB) vs DUTY
CYCLE (TH/TTOTAL)
Typical Performance Curves
(Continued)
9.0
INTERMODULATION DISTORTION (dBc)
EFFECTIVE NUMBER OF BITS (ENOB)
9.5
12.5ns
8.5
50%
8.0
fIN = fS/ 4
TEMPERATURE = 25oC
7.5
7.0
0
10
20
30
40
50
58.0
IMD 1MHz
56.0
54.0
IMD 10MHz
-40 -30 -20 -10
fS (MSPS)
FIGURE 11. EFFECTIVE NUMBER OF BITS (ENOB) vs
SAMPLE FREQUENCY
0
10 20 30 40
TEMPERATURE
50
60
70
FIGURE 12. INTERMODULATION DISTORTION (IMD) vs
TEMPERATURE
0dB
fIN = 10MHz
-10dB
fS = 40 MSPS
OUTPUT LEVEL (dB)
-20dB
-30dB
-40dB
-50dB
-60dB
-70dB
-80dB
-90dB
-100dB
0
200
400
600
800
1000
1200
1400
FREQUENCY BIN
FIGURE 13. 4096 POINT FFT SPECTRAL PLOT
4-10
1600
1800
2047
80 85
Typical Performance Curves
(Continued)
0dB
fIN = 1MHz
-10dB
fS = 40 MSPS
OUTPUT LEVEL (dB)
-20dB
-30dB
-40dB
-50dB
-60dB
-70dB
-80dB
-90dB
-100dB
0
200
400
600
800
1000
1200
1400
FREQUENCY BIN
FIGURE 14. 4096 POINT FFT SPECTRAL PLOT
4-11
1600
1800
2047
TABLE 1. PIN DESCRIPTION
PIN #
NAME
DESCRIPTION
1
DVCC1
Digital Supply (+5.0V)
2
DGND
Digital Ground
3
DVCC1
Digital Supply (+5.0V)
4
DGND
Digital Ground
5
AVCC
Analog Supply (+5.0V)
6
AGND
Analog Ground
7
VREF+
Positive Reference Voltage Input
8
VREF -
Negative Reference Voltage Input
9
VIN+
Positive Analog Input
10
VIN-
Negative Analog Input
11
VDC
DC Bias Voltage Output
12
AGND
Analog Ground
13
AVCC
Analog Supply (+5.0V)
14
OE
Digital Output Enable Control Input
15
DFS
Data Format Select Input
16
D9
Data Bit 9 Output (MSB)
17
D8
Data Bit 8 Output
18
D7
Data Bit 7 Output
19
D6
Data Bit 6 Output
20
D5
Data Bit 5 Output
21
DGND
22
CLK
23
DVCC2
24
D4
Data Bit 4 Output
25
D3
Data Bit 3 Output
26
D2
Data Bit 2 Output
27
D1
Data Bit 1 Output
28
D0
Data Bit 0 Output (LSB)
Digital Ground
Sample Clock Input
Digital Output Supply (+3.3V to +5V)
Detailed Description
Theory of Operation
The HI5703 is a 10-bit fully differential sampling pipeline A/D
converter with digital error correction. Figure 15 depicts the
circuit for the front end differential-in-differential-out sampleand-hold (S/H). The switches are controlled by an internal
clock which is a non-overlapping two phase signal, φ1 and
φ2 , derived from the master clock. During the sampling
phase, φ1 , the input signal is applied to the sampling
capacitors, CS . At the same time the holding capacitors, CH ,
are discharged to analog ground. At the falling edge of φ1
the input signal is sampled on the bottom plates of the
sampling capacitors. In the next clock phase, φ2 , the two
bottom plates of the sampling capacitors are connected
4-12
together and the holding capacitors are switched to the opamp output nodes. The charge then redistributes between
CS and CH completing one sample-and-hold cycle. The
output is a fully-differential, sampled-data representation of
the analog input. The circuit not only performs the sampleand-hold function but will also convert a single-ended input
to a fully-differential output for the converter core. During the
sampling phase, the VIN pins see only the on-resistance of a
switch and CS . The relatively small values of these
components result in a typical full power input bandwidth of
250MHz for the converter.
φ1
VIN+
φ1
φ1
φ1
CS
φ2
VIN-
CH
-+
VOUT+
+-
VOUT-
CS
φ1
CH
φ1
FIGURE 15. ANALOG INPUT SAMPLE-AND-HOLD
As illustrated in the functional block diagram and the timing
diagram in Figure 1, nine identical pipeline subconverter
stages, each containing a two-bit flash converter and a twobit multiplying digital-to-analog converter, follow the S/H
circuit with the tenth stage being a one bit flash converter.
Each converter stage in the pipeline will be sampling in one
phase and amplifying in the other clock phase. Each
individual subconverter clock signal is offset by 180 degrees
from the previous stage clock signal resulting in alternate
stages in the pipeline performing the same operation.
The two-bit digital output of each stage is fed to a digital delay
line controlled by the internal clock. The purpose of the delay
line is to align the digital output data to the corresponding
sampled analog input signal. This delayed data is fed to the
digital error correction circuit which corrects the error in the
output data with the information contained in the redundant
bits to form the final ten bit output for the converter.
Because of the pipeline nature of this converter, the data on
the bus is output at the 7th cycle of the clock after the analog
sample is taken. This delay is specified as the data latency.
After the data latency time, the data representing each
succeeding sample is output at the following clock pulse.
The output data is synchronized to the external clock by a
double buffered latching technique.
The digital output bits are available in offset binary or two’s
complement format, the format being set by the Data Format
Select (DFS) input.
Reference Voltage Inputs, VREF - and VREF+
The HI5703 requires two reference voltages connected to the
VREF pins. The HI5703 is tested with VREF - equal to 2V and
VREF+ equal to 3.25V for a fully differential input voltage
range of ±1.25V. VREF+ and VREF - can differ from the above
voltages as long as the reference common mode voltage,
((VREF+ + VREF -)/2), does not exceed 2.625V ±50mV and
the limits on VREF+ and VREF - are not exceeded.
In order to minimize overall converter noise it is recommended
that adequate high frequency decoupling be provided at the
reference voltage input pins, VREF+ and VREF -.
Analog Input, Differential Connection
VIN+
R
HI5703
VDC
VIN+
R
C
HI5703
VDC
-VIN
R
VDC
VIN-
The resistors, R, in Figure 17 are not absolutely necessary
but may be used as load setting resistors. A capacitor, C,
connected from VIN+ to VIN- will help filter any high
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
Analog Input, Single-Ended Connection
The configuration shown in Figure 18 may be used with a
single ended AC coupled input.
R
-VIN
VIN
VDC
FIGURE 17. DC COUPLED DIFFERENTIAL INPUT
The analog input to the HI5703 is a differential input that can
be configured in various ways depending on the signal
source and the required level of performance. A fully
differential connection (Figure 16 and Figure 17) will give the
best performance for the converter.
VIN
The analog input can be DC coupled (Figure 17) as long as
the inputs are within the analog input common mode voltage
range (0.625V ≤ VDC ≤ 4.375V).
VIN-
FIGURE 16. AC COUPLED DIFFERENTIAL INPUT
Since the HI5703 is powered by a single +5V analog supply,
the analog input is limited to be between ground and +5V.
For the differential input connection this implies the analog
input common mode voltage can range from 0.625V to
4.375V. The performance of the ADC does not change
significantly with the value of the analog input common
mode voltage.
A DC voltage source, VDC , equal to 2.8V (typical), is made
available to the user to help simplify circuit design when using
an AC coupled differential input. This low output impedance
voltage source is not designed to be a reference but makes an
excellent bias source and stays within the analog input
common mode voltage range over temperature. It has a
temperature coefficient of approximately +200ppm/oC.
For the AC coupled differential input (Figure 16) assume the
difference between VREF+, typically 3.25V, and VREF-,
typically 2V, is 1.25V. Fullscale is achieved when the VIN+
and VIN- inputs are 1.25VP-P, with VIN- being 180 degrees
out of phase with VIN+. The converter will be at positive
fullscale when the VIN+ input is at VDC + 0.625V and VIN- is
at VDC - 0.625V (VIN+ - VIN- = 1.25V). Conversely, the
converter will be at negative full scale when the VIN+ input is
equal to VDC - 0.625V and VIN- is at VDC + 0.625V (VIN+ VIN- = -1.25V).
4-13
VIN+
VIN
R
VDC
HI5703
VIN-
FIGURE 18. AC COUPLED SINGLE ENDED INPUT
Again, assume the difference between VREF+, typically
3.25V, and VREF-, typically 2V, is 1.25V. If VIN is a 2.5VP-P
sinewave, then VIN+ is a 2.5VP-P sinewave riding on a
positive voltage equal to VDC. The converter will be at
positive fullscale when VIN+ is at VDC + 1.25V and will be at
negative fullscale when VIN+ is equal to VDC - 1.25V.
Sufficient headroom must be provided such that the input
voltage never goes above +5V or below AGND. In this case,
VDC could range between 1.25V and 3.75V without a
significant change in ADC performance. The simplest way to
produce VDC is to use the VDC output of the HI5703.
The single ended analog input can be DC coupled
(Figure 19) as long as the input is within the analog input
common mode voltage range.
VIN
VIN+
VDC
R
C
VDC
HI5703
VIN-
FIGURE 19. DC COUPLED SINGLE ENDED INPUT
The resistor, R, in Figure 19 is not absolutely necessary but
may be used as a load setting resistor. A capacitor, C,
connected from VIN+ to VIN- will help filter any high
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
A single ended source may give better overall system
performance if it is first converted to differential before
driving the HI5703. Refer to the application notes AN9534,
“Using the HI5703 Evaluation Board”, and AN9413, “Driving
the Analog Input of the HI5702”. Application note AN9413
applies to the HI5703 as well as the HI5702 and describes
several different ways of driving the analog differential
inputs.
Digital Output Control and Clock Requirements
The HI5703 provides a standard high-speed interface to
external TTL logic families.
In order to ensure rated performance of the HI5703, the duty
cycle of the clock should be held at 50% ±5%. It must also
have low jitter and operate at standard TTL levels.
Performance of the HI5703 will only be guaranteed at
conversion rates above 1 MSPS. This ensures proper
performance of the internal dynamic circuits. Similarly, when
power is first applied to the converter, a maximum of 20
cycles at a sample rate above 1 MSPS will have to be
performed before valid data is available.
A Data Format Select (DFS) pin is provided which will
determine the format of the digital data outputs. When at
logic low, the data will be output in offset binary format.
When at logic high, the data will be output in two’s
complement format. Refer to Table 2 for further information.
The output enable pin, OE, when pulled high will three-state
the digital outputs to a high impedance state. Set the OE
input to logic low for normal operation.
4-14
OE INPUT
DIGITAL DATA OUTPUTS
0
Active
1
High Impedance
Supply and Ground Considerations
The HI5703 has separate analog and digital supply and
ground pins to keep digital noise out of the analog signal
path. The digital data outputs also have a separate supply
pin, DVCC2 , which can be powered from a 3.3V to 5.0V
supply. This allows the outputs to interface with 3.3V logic if
so desired.
The part should be mounted on a board that provides
separate low impedance connections for the analog and
digital supplies and grounds. For best performance, the
supplies to the HI5703 should be driven by clean, linear
regulated supplies. The board should also have good high
frequency decoupling capacitors mounted as close as
possible to the converter. If the part is powered off a single
supply then the analog supply and ground pins should be
isolated by ferrite beads from the digital supply and ground
pins.
Refer to the application notes “Using Intersil High Speed A/D
Converters” (AN9214) for additional considerations when
using high speed converters.
Static Performance Definitions
Offset Error (VOS)
The midscale code transition should occur at a level 1/4 LSB
above half-scale. Offset is defined as the deviation of the
actual code transition from this point.
Full-Scale Error (FSE)
The last code transition should occur for an analog input that
is 3/4 LSB below positive Fullscale (+FS) with the offset error
removed. Full-scale error is defined as the deviation of the
actual code transition from this point.
Differential Linearity Error (DNL)
DNL is the worst case deviation of a code width from the
ideal value of 1 LSB.
Integral Linearity Error (INL)
INL is the worst case deviation of a code center from a best
fit straight line calculated from the measured data.
Power Supply Sensitivity
Each of the power supplies are moved plus and minus 5%
and the shift in the offset and full scale error (in LSBs) is
noted.
TABLE 2. A/D CODE TABLE
OFFSET BINARY OUTPUT CODE
(DFS LOW)
CODE CENTER
DESCRIPTION
TWO’S COMPLEMENT OUTPUT CODE
(DFS HIGH)
M
S
B
DIFFERENTIAL
INPUT VOLTAGE
(VIN+ - VIN-)
D9
L
S
B
M
S
B
L
S
B
D8
D7
D6
D5
D4
D3
D2
D1
D0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
+Full Scale (+FS) -
1.24939V
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
+FS - 11/4 LSB
1.24695V
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
+3/4 LSB
1.83mV
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-1/4 LSB
-0.610mV
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-FS + 13/4 LSB
-1.24573V
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
-Full Scale (-FS)
+ 3/4 LSB
-1.24817V
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1/ LSB
4
NOTES:
8. The voltages listed above represent the ideal center of each output code shown as a function of the reference voltage.
9. VREF+ = 3.25V and VREF - = 2.0V.
Dynamic Performance Definitions
Total Harmonic Distortion (THD)
Fast Fourier Transform (FFT) techniques are used to evaluate
the dynamic performance of the HI5703. A low distortion sine
wave is applied to the input, it is coherently sampled, and the
output is stored in RAM. The data is then transformed into the
frequency domain with an FFT and analyzed to evaluate the
dynamic performance of the A/D. The sine wave input to the
part is -0.5dB down from full scale for all these tests.
THD is the ratio of the RMS sum of the first 5 harmonic
components to the RMS value of the fundamental input
signal.
SNR and SINAD are quoted in dB. The distortion numbers are
quoted in dBc (decibels with respect to carrier) and DO NOT
include any correction factors for normalizing to full scale.
Effective Number Of Bits (ENOB)
The effective number of bits (ENOB) is calculated from the
SINAD data by:
2nd and 3rd Harmonic Distortion
This is the ratio of the RMS value of the applicable harmonic
component to the RMS value of the fundamental input signal.
Spurious Free Dynamic Range (SFDR)
SFDR is the ratio of the fundamental RMS amplitude to the
RMS amplitude of the next largest spectral component in the
spectrum below fS /2.
Intermodulation Distortion (IMD)
VCORR adjusts the ENOB for the amount the input is below
fullscale.
Nonlinearities in the signal path will tend to generate
intermodulation products when two tones, f1 and f2 , are
present at the inputs. The ratio of the measured signal to the
distortion terms is calculated. The terms included in the
calculation are (f1+f2), (f1-f2), (2f1), (2f2), (2f1+f2), (2f1-f2),
(f1+2f2), (f1-2f2). The ADC is tested with each tone 6dB
below full scale.
Signal To Noise and Distortion Ratio (SINAD)
Transient Response
SINAD is the ratio of the measured RMS signal to RMS sum
of all the other spectral components below the Nyquist
frequency, fS /2, excluding DC.
Transient response is measured by providing a full scale
transition to the analog input of the ADC and measuring the
number of cycles it takes for the output code to settle within
10-bit accuracy.
ENOB = (SINAD - 1.76 + VCORR) / 6.02
where:
VCORR = 0.5 dB
Signal To Noise Ratio (SNR)
SNR is the ratio of the measured RMS signal to RMS noise at
a specified input and sampling frequency. The noise is the
RMS sum of all of the spectral components below fS /2
excluding the fundamental, the first five harmonics and DC.
4-15
Over-Voltage Recovery
Over-Voltage Recovery is measured by providing a full scale
transition to the analog input of the ADC which overdrives
the input by 200mV, and measuring the number of cycles it
takes for the output code to settle within 10-bit accuracy.
Full Power Input Bandwidth (FPBW)
Full power input bandwidth is the analog input frequency at
which the amplitude of the digitally reconstructed output has
decreased 3dB below the amplitude of the input sine wave.
The input sine wave has an amplitude which swings from
-FS to +FS. The bandwidth given is measured at the
specified sampling frequency.
Video Definitions
Differential Gain and Differential Phase are two commonly
found video specifications for characterizing the distortion of
a chrominance signal as it is offset through the input voltage
range of an ADC.
at which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
Aperture Jitter (tAJ)
Aperture jitter is the RMS variation in the aperture delay due
to variation of internal clock path delays.
Data Hold Time (tH)
Data hold time is the time to where the previous data (N - 1)
is no longer valid.
Data Output Delay Time (tOD)
Data output delay time is the time to where the new data (N)
is valid.
Differential Gain (DG)
Data Latency (tLAT)
Differential Gain is the peak difference in chrominance
amplitude (in percent) relative to the reference burst.
After the analog sample is taken, the digital data is output on
the bus at the 7th cycle of the clock. This is due to the pipeline
nature of the converter where the data has to ripple through
the stages. This delay is specified as the data latency. After
the data latency time, the data representing each succeeding
sample is output at the following clock pulse. The digital data
lags the analog input sample by 7 cycles.
Differential Phase (DP)
Differential Phase is the peak difference in chrominance
phase (in degrees) relative to the reference burst.
Timing Definitions
Power-Up initialization
Refer to Figure 1 and Figure 2 for these definitions.
Aperture Delay (tAP)
Aperture delay is the time delay between the external
sample command (the falling edge of the clock) and the time
A/D
AMP
HFA1100
HFA1105
HFA1106
HFA1135
HFA1145
HFA1245
HFA1100:
HFA1105:
HFA1106:
HFA1135:
HFA1145:
HFA1245:
HI5702:
HI5703:
HSP9501:
HSP48410:
HI5702
HI5703
This time is defined as the maximum number of clock cycles
that are required to initialize the converter at power-up. The
requirement arises from the need to initialize the dynamic
circuits within the converter.
DSP/µP
D/A
HSP9501
HSP48410
HSP48908
HSP48212
HSP43891
HSP43168
HSP43216
850MHz Video Op Amp
300MHz Video Op Amp
250MHz Video Op Amp with Bandwidth Limit Control
350MHz Video Op Amp with Output Limiting
300MHz Video Op Amp with Output Disable
Dual 350MHz Video Op Amp with Output Disable
10-Bit, 40 MSPS, A/D Converter
10-Bit, 40 MSPS, Low Power A/D Converter
Programmable Data Buffer
Histogrammer/Accumulating Buffer, 10-Bit Pixel
Resolution
HSP48908: 2-D Convolver, 3 x 3 Kernal Convolution, 8-Bit
HI5780
HI1171
CA3338
HSP48212:
HSP43891:
HSP43168:
HSP43216:
HI5780:
HI1171:
CA3338:
HA5020:
HA2842:
HFA1115:
HFA1212:
HFA1412:
HA5020
HA2842
HFA1115
HFA1212
HFA1412
Digital Video Mixer
Digital Filter, 30MHz, 9-Bit
Dual FIR Filter, 10-Bit, 33MHz/45MHz
Digital Half Band Filter
10-Bit, 80 MSPS, Video D/A Converter
8-Bit, 40 MSPS, Video D/A Converter
8-Bit, 50 MSPS, Video D/A Converter
100MHz Video Op Amp
High Output Current, Video Op Amp
225MHz Programmable Gain Video Buffer with
Output Limiting
350MHz, Dual Programmable Gain Video Buffer
350MHz, Quad Programmable Gain Video Buffer
In addition, CMOS Logic Families in HC/HCT, AC/ACT, FCT and CD4000 are available.
FIGURE 20. 10-BIT VIDEO IMAGING COMPONENTS
4-16
AMP
A/D
AMP
HFA1100
HFA1110
HFA3101
HFA3102
HFA3600
HI5702
HI5703
DSP/µP
HSP43168
HSP43216
HSP43220
HSP43891
HSP50016
HSP50110
HSP50210
D/A
HI5721
HI5780
HI20201
HI20203
AMP
HFA1112
HFA1113
HFA1100: 850MHz Op Amp
HFA1110: 750MHz Unity Gain Video Buffer
HFA3101: Gilbert Cell Transistor Array
HFA3102: Dual Long-Tailed Pair Transistor Array
HFA3600: Low Noise Amplifier/Mixer
HI5702: 10-Bit, 40 MSPS, A/D Converter
HI5703: 10-Bit, 40 MSPS, Low Power A/D Converter
HSP43168: Dual FIR Filter, 10-Bit, 33MHz/45MHz
HSP43216: Digital Half Band Filter
HSP43220: Decimating Digital Filter
HSP43891: Digital Filter, 30MHz, 9-Bit
HSP50016: Digital Down Converter
HSP50110: Digital Quadrature Tuner
HSP50210: Digital Costas Loop
HI5721: 10-Bit, 100 MSPS, Communications D/A Converter
HI5780: 10-Bit, 80 MSPS, D/A Converter
HI20201: 10-Bit, 160 MSPS, High Speed D/A Converter
HI20203: 8-Bit, 160 MSPS, High Speed D/A Converter
HFA1112: 850MHz Programmable Gain Video Buffer
HFA1113: 850MHz Programmable Gain Video Buffer with Output Limiting
In addition, CMOS Logic Families in HC/HCT, AC/ACT, FCT and CD4000 are available.
FIGURE 21. 10-BIT COMMUNICATIONS COMPONENTS
4-17
HI5703
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
B S
MILLIMETERS
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.6969
0.7125
17.70
18.10
3
E
0.2914
0.2992
7.40
7.60
4
0.05 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.01
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
MAX
A1
e
α
MIN
α
28
0o
28
7
8o
Rev. 0 12/93
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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4-18
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