CA3224 Datasheet

CA3224E
®
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October 2002
FN1553.2
Automatic Picture Tube Bias Control
Circuit
Features
Description
• Automatic Background Color Balance
The CA3224E is an automatic picture tube bias control circuit used in color TV receiver CRT drive circuits. It is used to
provide dynamic bias control of the grey scale both initially
and over the CRT operating life, compensating for CRT cutoff changes.
• Eliminates Grey Scale Adjustments
The CA3224E provides automatic continuous control of the
cutoff current in each gun of a three-gun color CRT. From an
input pulse amplitude proportional to the difference between
the desired and the actual CRT cutoff, a gated sample/hold
circuit generates a DC correction voltage which correctly
biases the CRT driver circuit. The sample/hold bias
correction takes place each frame following the vertical
blanking. Figure 1 shows a block diagram of the CA3224E.
The functions include three identical servo loop
transconductance amplifiers with a sample/hold switch and
buffer amplifier plus control logic, internal bias and a mode.
• Wide Dynamic Range
• Automatic Picture Tube Bias Cutoff Control
• Compensates for Cathode-to-Heater Leakage
• Electrostatic Protection on All Pins
• Servo Loop Design
• Three-Gun Control
• Minimal External Components
Part Number Information
PART
NUMBER
TEMP. RANGE
(oC)
CA3224E
-40 to 85
PACKAGE
22 Ld PDIP
PKG. NO.
E22.4
Pinout
CA3224E
(PDIP)
TOP VIEW
GROUND
1
22
VCC
CHANNEL 1 INPUT
2
21
CHANNEL 1 HOLD CAP
CHANNEL 1 FREQ COMPENSATION
3
20
CHANNEL 1 OUTPUT
CHANNEL 2 INPUT
4
19
CHANNEL 2 HOLD CAP
CHANNEL 2 FREQ COMPENSATION
5
18
CHANNEL 2 OUTPUT
CHANNEL 3 INPUT
6
17
CHANNEL 3 HOLD CAP
CHANNEL 3 FREQ COMPENSATION
7
16
CHANNEL 3 OUTPUT
VERTICAL INPUT
8
15
VREF BYPASS
GROUND
9
14
AUTO BIAS LEVEL ADJUST
HORIZONTAL INPUT
10
13
AUTO BIAS PULSE OUTPUT
GRID PULSE OUTPUT
11
12
PROGRAM PULSE OUTPUT
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright © Intersil Americas Inc. 2002. All Rights Reserved
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CA3224E
Absolute Maximum Ratings TA = 25oC
Thermal Information
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1 to VCC
Output Current . . . . . . . . . . . . . . . . . . . . . . .Short Circuit Protected
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . . . . 10V ±10%
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications At TA = 25oC, VCC = 10V, VBIAS = 3.75V, VV (Pin 8) = VH (Pin 10) = 6.0V, S1 = A, S2 = A,
See Test Circuit and Timing Diagrams
PARAMETER
TEST PIN NO. SYMBOL
MIN
TYP
MAX
UNITS
-
-
65
mA
5.6
6.0
6.4
V
VIN = 7.2V, S1 = B
-
-
250
nA
lOM+
VBIAS = 0.5V, Measure at t 6, S1 = B
-
-
-0.8
mA
lOM-
VBIAS = 7.0V, Measure at t 6, S1 = B
0.8
-
-
mA
-
-
150
nA
0.97
-
1.07
-
50
-
100
mS
Supply Current
22
Reference Voltage
2, 4, 6
VREF
Input Current
2, 4, 6
II
Output Current
Source
17,19, 21
Sink
Output Buffer
Input Current
17,19, 21
Voltage Gain
Grid Pulse Output
II
AV
Measure at t4
VOUT = 6.5V, VIN
At pins 16, 18, 20,
Measure at t4 , S1 = B
gM
Measure at t6, VIN = 8mVP-P
at 40kHz, S1 = B
13
VOL
Measure at t1
-
-
0.3
V
High
VOH
Measure at t4
6.05
-
-
V
Current Sink
lOM-
Measure at t4, S2 = B
2.5
-
-
mA
VOL
Measure at t4
-
-
0.4
V
VOH
Measure at t1
4.2
-
-
V
VOL
Measure at t6
-
-
0.4
V
VOH
Measure at t1
8.2
-
-
V
Output Low
Low
11
High
Program Pulse Output
ICC
17,19, 21
Transconductance
Auto Bias Pulse
TEST CONDITIONS
Low
12
High
Vertical Input
8
VV
See Figure 3
-
6.0
-
V
Horizontal Input
10
VH
See Figure 3
-
6.0
-
V
Auto Bias Pulse Timing Start
13
t0 to t2, Note 2
835
-
842
µs
t0 to t7, Note 2
1270
-
1275
µs
t0 to t3, Note 2
899
-
905
µs
t0 to t5, Note 2
1080
-
1084
µs
t0 to t5, Note 2
1080
-
1084
µs
t0 to t7, Note 2
1270
-
1275
µs
Finish
Grid Pulse Timing
Start
11
Finish
Program Pulse Timing
Start
12
Finish
NOTE:
2. All time measurements are made from 50% point to 50% point.
2
CA3224E
Test Circuit
+10V
output goes high. This is used to set the RGB drive of the
companion chroma/luma circuit to black level. The auto-bias
pulse stays high for 7 horizontal periods during the auto-bias
cycle.
VBIAS
3.65K
1
22
2
21
B
VIN1
3
20
4
19
VOUT1
0.047
µF
VIN2
B
18
6
17
VOUT2
0.047
µF
VIN3
B
VERTICAL
INPUT
7
16
8
15
9
14
3.65K
0.12µF
A
S1
CA3224E
0.047
µF
3.65K
0.12µF
A
S1
5
On the 15th horizontal sync pulse, the internal logic initiates the
setup interval. During the setup interval, the cathode current is
increased to a reference value (A in Figure 5) through the
action of the grid pulse. The cathode current causes a voltage
drop across R S. This voltage drop, together with the program
pulse output results in a reference voltage at VS (summing
point) which causes capacitor C1 to charge to a voltage
proportional to the reference cathode current. The setup
interval lasts for 3 horizontal periods.
0.12µF
A
S1
VOUT3
47µF
+
+20V
3.32K
1.0K
1.50K
+10V
B
HORIZONTAL
INPUT
10
13
11
12
On the 18th horizontal sync pulse the grid pulse output
goes high, which through the grid pulse amplifier/inverter,
causes the cathode current to decrease. The decrease in
cathode current results in a positive recovered voltage
pulse with respect to the setup reference level at the VS
summing point. The positive recovered voltage pulse is
summed with a negative voltage pulse caused by the
program pulse output going low (cutting off Diode D1 and
switching in resistors R1 and R2). Any difference between
the positive and negative pulses is fed through capacitor
C1 to the transconductance amplifier. The difference signal
is amplified in the transconductance amplifier and charges
the hold capacitor C2, which, through the buffer amplifier,
adjusts the bias on the driver circuit.
A
S2
20K
1.5K
Device Description and Operation (See Figures
Components RS, R1, and R2 must be chosen such that the
program pulse and the recovered pulse just cancel at the
desired cathode cutoff level.
1, 2, 4 and 5)
During the vertical retrace interval, 13 horizontal sync pulses
are counted. On the 14th sync pulse the auto-bias pulse
CHAN FREQ
1 IN COMP
HOLD
CHAN CHAN FREQ
CAPACITOR 1 OUT 2 IN COMP
3
2
21
AMPLIFER
NO. 1
1
4
2
+
3
CHAN
2 OUT
19
18
5
AMPLIFER
NO. 2
BUFFER
AMP
gM
20
HOLD
CAPACITOR
1
-
x1
+
2
CHAN FREQ
3 IN COMP
6
CHAN
3 OUT
17
16
7
AMPLIFER
NO. 3
BUFFER
AMP
1
-
x1
BUFFER
AMP
2
x1
+
3
gM
HOLD
CAPACITOR
3
gM
MODE
SWITCH
VREF
BIAS
LOGIC
1
9
22
15
8
10
11
12
13
14
GND
GND
VCC
VREF
BYPASS
VERT
IN
HORIZ
IN
GRID
PULSE
OUT
PROG
PULSE
OUT
AUTO
BIAS
PULSE
OUT
AUTO
BIAS
LEVEL
ADJUST
MODE SWITCH
STATE
1
2
3
SET-UP
SENSE
OPEN
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
3
CA3224E
t1
t0
VERTICAL INPUT
(PIN 8)
t2
t3
t4 t5
t6
t7
VERTICAL
BLANKING
HORIZONTAL INPUT
(PIN 10)
1
2
3
12
13 14 15
16 17
18
19
20 21
22
23
AUTO BIAS
PULSE OUTPUT
(PIN 13)
GRID PULSE OUTPUT
(PIN 11)
PROGRAM PULSE
OUTPUT
(PIN 12)
MODE SWITCH
(SEE FIGURE 1)
OPEN
SET-UP
SENSE
FIGURE 2. FUNCTIONAL TIMING DIAGRAMS
VERTICAL SIGNAL 0V
VV
0.5ms
16.683ms
HORIZONTAL SIGNAL
VH
fV = 59.94Hz
fH = 15734.264Hz
0V
12µs
63.55
µs
FIGURE 3. VERTICAL AND HORIZONTAL INPUT SIGNALS
4
OPEN
CA3224E
+230V
+10V
+
12K
33µF
R
2.2K
G
10K
B
+12V
RFB
160K
TO R
DRIVER
R
Q1
CATH
DRIVE
RIN
RS
560Ω
1%
SUMMING POINT
200Ω
TO B
DRIVER
0.12
VS
R2
62K
1%
Q2
BIAS
20K
B
9.1K
2
20
3
19
0.047
+
10µF
BIN
ROUT
+
4
18
TO BCH
AUTO-BIAS PULSE
10µF
5
17
CA224E
6
16
7
15
12
14
22
10
9
8
13
11
GOUT GIN
+
10µF
+
BOUT
0.047
47µF
+10V
R1
39K
1%
GRID PULSE
AMPLIFIER
INVERTER
C2
CC
GIN
D1
2.7K
21
0.047
TO RCH
-24V
PROGRAM
RGB TO
BLACK LEVEL
1
Q3
SG
C1
BIAS
5K
CHROMA/
LUMA
2.7K
CIRCUIT G
1.5K
3.9K
20K
AUTO BIAS
LEVEL ADJUST
HORIZONTAL
INPUT
VERTICAL
INPUT
NOTE:
3. One of three identical driver circuits shown.
FIGURE 4. TYPICAL APPLICATION CIRCUIT
Electrostatic Protection (Note)
ICATHODE
(mA)
A
B
NOTE: For further information on CA3224E protection structures refer to: AN7304, “Using SCRs as Transient Protection Structures in Integrated Circuits”, by L.R. Avery.
0
SET-UP
When correctly designed for ESD protection, SCRs can be
highly effective, enabling circuits to be protected to well in
excess of 4kV. The SCR ESD-EOS protection structures
used on each terminal of the CA3224E are shown
schematically in either Figures 6A or 6B. Although ESD-EOS
protection is included in the CA3224E, proper circuit board
layout and grounding techniques should be observed.
SENSE
VCATHODE GRID (V)
FIGURE 5. PICTURE TUBE V-I CURVE
TO ACTIVE
CIRCUIT
RSENSE
RHOLD
RHOLD
POSITIVE
SUBSTRATE
TRANSIENT
NEG. TRANSIENT
PROTECT
(A) PROTECT
NEGATIVE
POSITIVE
TRANSIENT
TRANSIENT
PROTECT (B) PROTECT
FIGURE 6A.
FIGURE 6B.
FIGURE 6. TRANSIENT PROTECTION
5
TO ACTIVE
CIRCUIT
CA3224E
Dual-In-Line Plastic Packages (PDIP)
E22.4 (JEDEC MS-010-AA ISSUE C)
N
22 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AD
E
BASE
PLANE
-C-
A2
SEATING
PLANE
A
L
D1
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.125
0.195
3.18
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.065
1.15
1.65
8
eA
C
0.009
0.015
C
D
1.065
1.120
27.06
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3.
0.229
0.381
28.44
D1
0.005
-
0.13
E
0.390
0.425
9.91
10.79
6
E1
0.330
0.390
8.39
9.90
5
e
0.100 BSC
-
5
2.54 BSC
5
-
eA
0.400 BSC
10.16 BSC
6
eB
-
0.500
-
7
L
0.115
0.160
2.93
N
22
12.70
4.06
22
4
9
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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6
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