HIP9011 Datasheet

HIP9011
®
Data Sheet
January 6, 2006
Engine Knock Signal Processor
Features
The HIP9011 is used to provide a method of detecting
premature detonation often referred to as “Knock or Ping” in
internal combustion engines.
• Two Sensor Inputs
FN4367.2
• Microprocessor Programmable
• Accurate and Stable Filter Elements
The IC is shown in the Simplified Block Diagram. The chip
can select between one of two sensors, if needed for
accurate monitoring or for “V” type engines. Internal control
via the SPI bus is fast enough to switch sensors between
each firing cycle. A programmable bandpass filter
processes the signal from either of the sensor inputs. The
bandpass filter can be selected to optimize the extraction
the engine knock or ping signals from the engine
background noise. Further single processing is obtained by
full wave rectification of the filtered signal and applying it to
an integrator whose output voltage level is proportional to
the knock signal amplitude. The chip is under
microprocessor control via a SPI interface bus.
• Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
Applications
PART
NUMBER
PART
MARKING
HIP9011AB
HIP9011AB
HIP9011ABZ HIP9011ABZ
(See Note)
• Digitally Programmable Gain
• Digitally Programmable Time Constants
• Digitally Programmable Filter Characteristics
• On-Chip Crystal Oscillator
• Programmable Frequency Divider
• External Clock Frequencies up to 24MHz
- 4, 5, 6, 8, 10, 12, 16, 20, and 24MHz
• Operating Temperature Range -40oC to 125oC
• Engine Knock Detector Processor
TEMP.
RANGE
(oC)
PACKAGE
PKG.
DWG. #
-40 to 125
20 Ld SOIC
M20.3
-40 to 125
20 Ld SOIC
(Pb-free)
M20.3
• Analog Signal Processing Where Controllable Filter
Characteristics are Required
Add “T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Simplified Block Diagram
CH0NI
+
CH1FB
CH1IN
CH1NI
+
3RD ORDER
ANTIALIASING FILTER
CH0IN
CHANNEL SELECT
SWITCHES
CH0FB
PROGRAMMABLE
GAIN
STAGE
2- 0.111
64 STEPS
PROGRAMMABLE
BANDPASS
FILTER
1-20kHz
64 STEPS
ACTIVE
FULL WAVE
RECTIFIER
PROGRAMMABLE
INTEGRATOR
40 - 600µs
32 STEPS
PROGRAMMABLE
DIVIDER
TO SWITCHED
CAPACITOR
NETWORKS
POWER SUPPLY
AND
BIAS CIRCUITS
VMID
1
VDD
GND
REGISTERS
AND
STATE MACHINE
SPI
INTERFACE
OUTPUT
DRIVER INTOUT
AND
SAMPLE
AND HOLD
OSCIN
CLOCK OSCOUT
SCK
CS
SI
SO
INT/HOLD
TEST
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1999, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HIP9011
Pinout
HIP9011
(SOIC)
TOP VIEW
VDD
1
20 CH0NI
GND
2
19 CH0IN
VMID
3
18 CH0FB
INTOUT
4
17 CH1FB
NC
5
16 CH1IN
NC
6
15 CH1NI
INT/HOLD
7
14 TEST
CS
8
13 SCK
OSCIN
9
12 SI
OSCOUT 10
11 SO
Pin Descriptions
PIN
NUMBER
DESIGNATION
1
VDD
Five volt power input.
2
GND
This pin is tied to ground.
3
VMID
This pin is connected to the internal mid-supply generator and is brought out for bypassing by a 0.022µF capacitor.
4
INTOUT
Buffered output of the integrator. Output signal is held by an internal Sample and Hold circuit when INT/HOLD is
low.
5, 6
NC
7
INT/HOLD
8
CS
9
OSCIN
10
OSCOUT
11
SO
Output of the chip SPI data bus. This is a three-state output that is controlled via the SPI bus. The output is
placed in the high impedance state by setting CS high when the chip is not selected. This high impedance state
can also be programmed by setting the LSB of the prescaler word to 1. This will take precedence over CS. A 0
enables the active state. The Diagnostic Mode overrides these conditions.
12
SI
Input of the chip SPI data bus. Data length is eight bits. This pin has an internal pull-up.
13
SCK
Input from the SPI clock. Normally low, the data is transferred to the chip internal circuitry on the falling clock
edge. This pin has an internal pull up.
14
TEST
A low on this pin places the chip in the diagnostic mode. For normal operation this pin is tied high or left open.
This pin has an internal pull up.
15
CH1NI
Non-inverting input of Channel one.
16
CH1IN
Inverting input to channel one amplifier. A resistor is tied from this summing input to the transducer. A second
resistor is tied between this pin and pin 17, CH1FB to establish the gain of the amplifier.
17
CH1FB
Output of the channel one amplifier. This pin is used to apply feedback.
18
CH0FB
Output of the channel zero amplifier. This pin is used to apply feedback.
19
CH0IN
Inverting input to channel zero amplifier. Remainder same as channel one amplifier except feedback is applied
from pin 18.
20
CH0NI
Non-inverting input of Channel 0. Remainder the same as pin 16, except feedback is applied from terminal 18.
DESCRIPTION
These pins are not internally connected. Do Not Use.
Selects whether the chip is in the Integrate Mode (Input High) or in the Hold Mode (Input Low). This pin has an
internal pull down.
A low input on this pin enables the chip to communicate over the SPI bus. This pin has an internal pull-up.
Input to inverter used for the oscillator circuit. A 4MHz crystal or ceramic resonator is connected between this pin and
pin 10. To bias the inverter, a 1.0MΩ to 10MΩ resistor is usually connected between this pin and pin 10.
Output of the inverter used for the oscillator. See pin 9 above.
2
FN4367.2
January 6, 2006
HIP9011
Absolute Maximum Ratings
Thermal Information
DC Logic Supply, VDD . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
Output Voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Max
Thermal Resistance (Typical, Note 1)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 125oC
θJA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
120
Maximum Power Dissipation, PD
For TA = -40oC to 70oC . . . . . . . . . . . . . . . . . . . . . . . 400mW Max
For TA = 70oC to 125oC, Derate Linearly at . . . . . . . . . . 6mW/oC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range, TSTG . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
At a Distance 1/16 ±1/32 inch, (1.59 ±0.79mm) from Case for
10s Max. (SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
VDD = 5V ±5%, GND = 0V, Clock Frequency 4MHz ±0.1%, TA = -40oC to 125oC,
Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
5.0
8.0
mA
DC ELECTRICAL SPECIFICATIONS
Quiescent Supply Current
IDD
VDD = 5.25V, GND = 0V
Midpoint Voltage, Pin 3
VMID
VDD = 5.0V, IL = 2mA Source
2.3
2.45
2.55
V
Midpoint Voltage, Pin 3
VMID
VDD = 5.0V, IL = 0mA
2.4
2.5
2.6
V
Low Input Voltage, Pins INT/HOLD, CS, SI, SCK
VIL
-
-
30
% of VDD
High Input Voltage, Pins INT/HOLD, CS, SI, SCK
VIH
70
-
-
% of VDD
Hysteresis voltage, Pins INT/HOLD, CS, SI, SCK
VHYST
0.85
-
-
V
-
50
-
µA
I Source CS, SI, VDD = 5.0V, Measured at GND
SCK, TEST
Internal Pull-Up Current
Internal Pull-Down Current
I Sink,
INT/HOLD
VDD = 5.0V, Measured at VDD
-
-50
-
µA
Low Level Output, Pin SO
VOL
ISOURCE = 1.6mA, VDD = 5.0V
0.01
-
0.30
V
High Level Output, Pin SO
VOH
ISINK = 200µA, VDD = 5.0V
4.8
4.9
5.0
V
IL
Measured at GND; VDD = 5.0V
-
-
±10
µA
Low Level Output, Pin 10, OSCOUT
VOL
ISOURCE = 500µA; VDD = 5.0V
-
-
1.5
V
High Level Output, Pin 10, OSCOUT
VOH
ISINK = -500µA; VDD = 5.0V
4.4
-
-
V
Three-State Leakage Pin SO
SPI BUS INTERFACE AC Parametrics
CS Falling to SCLK Rising
tCCH
10
-
-
ns
CS Rising to SCLK Falling
tCCL
80
-
-
ns
SCLK Low
tPWL
60
-
-
ns
SCLK High
tPWH
60
-
-
ns
SCLK Falling to CS Rising
tSCCH
60
-
-
ns
Data High Setup Time
tSUH
20
-
-
ns
Data Low Setup Time
tSUL
20
-
-
ns
Data High Hold Time
tHH
10
-
-
ns
Data Low Hold Time
tHL
10
-
-
ns
Min Time Between 2 Programmed Words
tCSH
200
-
-
ns
CS Rising to INT/Hold Rising
tCIH
8
-
-
µs
3
FN4367.2
January 6, 2006
HIP9011
VDD = 5V ±5%, GND = 0V, Clock Frequency 4MHz ±0.1%, TA = -40oC to 125oC,
Unless Otherwise Specified (Continued)
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
4.7
4.9
-
V
-
15
200
mV
+18
+20
+21
dB
INPUT AMPLIFIERS
CH0 and CH1 High Output Voltage
VOUTHI
ISINK = 100µA, VDD = 5.0V
CH0 and CH1 Low Output Voltage
VOUTLO
ISOURCE = 100µA; VDD = 5.0V
Voltage Gain
ACL
Input R = 47.5K, Feedback
R = 475kΩ
BW
Test Mode
-
-0.5
-
dB
ATTEN
Test Mode
-10
-15
-
dB
VOUT
Run Mode
3.5
4.0
-
VP-P
Q
Run Mode
-
2.5
-
Q
%G
Run Mode
-
±1
-
%
75
125
175
mV
ANTIALIASING FILTER
Response 1kHz to 20kHz, Referenced to 1kHz
Attenuation at 180kHz, Referenced
to 1kHz
PROGRAMMABLE FILTERS
Peak to Peak Voltage Output
Filters Q (Note 2)
PROGRAMMABLE GAIN AMPLIFIERS
Percent Amplifier Gain Deviation
INTEGRATOR
Integrator Reset Voltage
VRESET
Pin 4 Voltage at Start of
Integration
Cycle; VDD = 5.0V
Integrator Droop after 500µs
VDROOP
Hold Mode, Pin 7 = 0V,
VDD = 5.0V
Pin 4 set to 20% to 80% of VDD
-
±3
±50
mV
DIFFERENTIAL CONVERTER
Differential to Single Ended Converter Offset
Voltage
DIFVIO
By Design
-
0.1
-
mV
Change In Converter Output
DIFOUT
Run Mode, 500µA Sinking Load
to No Load Condition
-
±1
±10
mV
VOUT VRESET
Run Mode, maximum signal
output from Input Amplifier
<2.25VP-P, Equation Output X
0.95 + Device Reset Voltage;
For Total VOUT ≤ 4.7V
SYSTEM GAIN DEVIATION
Gain Deviation from “Ideal Equation” Correlation
Factor + 5.0% (Note 3)
8%,
-8%,
Equatio
±100mV
±100mV
n
X 0.95
VRESET
V
NOTES:
2. Q = fo/BW, where: fo = Center Frequency, BW = 3dB Bandwidth
3. Ideal Equation: INTOUT (Volts) = [VIN * GIN * GPR * GBPF * 1/π * (N/tC(ms) * fQ(kHz)) * GDSE] + VRESET
Where: VIN = input signal amplitude (VP-P)
GIN = External Input Gain; GIN = RF/RIN
GPR = Programmed Gain
GBPF = Gain of Bandpass Filter (2 for Ideal Case at Center)
tINT = Integration Time; tINT = N/fQ
0.318 = 1/π
N = Number of Cycles of Input Signal
fQ = Frequency of Input Signal
RF = Feedback Resistor Value
RIN = Signal Input Resistor Value
tC = Programmed Time Constant
GDSE = Gain of DSE Converter (2 for Ideal Case)
VRESET = Integrator Reset Voltage = 0.125V, Typ
4
FN4367.2
January 6, 2006
HIP9011
Timing Diagrams
INT/HOLD
tCIH
tCSH
CS
tPWL
tCSCH
tSCCH
SCK
tCSCF
tPWH
SI
B7
tSUH
B6
B5
B4
B3
B2
B1
B0
tHH
SO
B7
B6
B5
B4
B3
B2
B1
B0
FIGURE 1. SPI TIMING
TABLE 1. SPI TIMING REQUIREMENTS
SYMBOL
REQUIREMENT
TIME
tCSCH
Minimum time from CS falling edge to SCK rising edge.
10ns
tCSCF
Minimum time from CS falling edge to SCK falling edge.
80ns
tPWL
Minimum time for the SCK low.
60ns
tPWH
Minimum time for the SCK high.
60ns
tSCCH
Minimum time from SCK falling after 8 bits to CS raising edge.
80ns
tSUH
Minimum time from data high to falling edge of spiclk.
20ns
tSUL
Minimum time from data low to falling edge of spiclk.
20ns
tHH
Minimum time for data high after the falling edge of the spiclk.
10ns
tHL
Minimum time for data low after the falling edge of the spiclk.
10ns
tCIH
Minimum time after CS raises until INT/HOLD goes high.
8µs
tCSH
Minimum time between programming 2 internal registers.
200ns
t3
t1
INT/HOLD
t2
t4
INTOUT
FIGURE 2. INTEGRATOR TIMING
TABLE 2. INTEGRATE/HOLD TIMING REQUIREMENTS
SYMBOL
REQUIREMENT
TIME
t1
Maximum rise time of the INT/HOLD signal.
45ns
t2
Maximum time after INT/HOLD rises for INTOUT to begin to integrate.
20µs
t3
Maximum fall time of INT/HOLD signal.
45ns
t4
Typical time after INT/HOLD goes low before chip goes into hold state.
20µs
5
FN4367.2
January 6, 2006
HIP9011
+5V
VDD
EXAMPLE CASE USING IDEAL SYSTEM EQUATION
HIP9011
VMID
0.022µF
When the Input Signal is Present for the Period tINT:
GND
INTOUT (Volts) =
CH0NI
SO
CH1IN
Rin
SCK
CH1FB
RF
Rin

1 t int
V IN × G IN ×  G BPR × G PR × --- × -------- × G DSE + V RESET
π tc 

SI
CH1NI
SPI BUS
CS
CH0IN
CH0FB
INT/HOLD
OSCIN
TEST
RF
TRANSDUCERS
20pF
4MHz
OSCOUT
INTOUT
20pF
+5V
Where:
VIN = 200mVP-P, Continuous AC Signal
GIN = 1.0, Ratio of RF to RIN
GPR = 0.190
GBPF = 2.0 Ideal Gain Value
tC = 200µs
tINT = 2ms
GDSE = 2.0 Ideal Gain Value
VRESET = 0.125V, Typical Value
INTOUT (Volts) =
200x10-3*1* [2 * 0.19 * 0.318 * 2x10-3/200x10-6*
2]+0.125
= 0.4833 + 0.125
= 0.608V
1MΩ
A/D
CONVERTER
MICROPROCESSOR
FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE HIP9011 IN AN AUTOMOTIVE APPLICATION
Description of the HIP9011 Operation
This IC is designed to be a universal digitally controlled, analog
interface between engine acoustical sensors or accelerometers
and internal combustion engine fuel management systems.
Two wideband input amplifiers are provided which will allow the
use of two sensors. These sensors be of the piezoelectric type,
that can be mounted in optimum locations on either in-line or V
type engine configurations.
Output from these input amplifiers are directed to a channel
select mux switch and then into a 3rd order antialiasing filter.
The output signal is then directed to two programmable gain
stages, where one stage inverts or shifts the knock signal 180
degrees. The gain stage signals are outputted to two
programmable bandpass filter stages. Outputs from the two
BPF stages are then full wave rectified before being digitally
integrated by the programmable integrator. The integrator
output is applied to a line driver for further processing by the
engine fuel management control system. The gain, bandpass
filter and integrator stage settings are programmable from a
microprocessor via the SPI Bus Interface
6
Broadband piezoelectric ceramic transducers used for the
engine signal pickup have device capacitances in the order
of 1100pF and output voltages that range from 5mV to 8V
RMS. During normal engine operation, a single input
channel is selected and applied to the HIP9011. The engine
background noise is typically well below in amplitude than
the pre-detonation noise. Therefore, the bandpass filter
stages can be optimized to further discriminate between
engine background and combustion noise and predetonation noise.
A basic approach to engine pre-detonation systems is to
only observe engine background during the time interval
that noise is expected and if detected, retard timing. This
basic approach does not require the sensitivity and
selectivity that is needed for a continuously adjustable
solution. Enhanced fuel economy and performance is
obtainable when this IC is coupled with a microprocessor
controlled fuel management system.
FN4367.2
January 6, 2006
HIP9011
Circuit Block Description
Programmable Gain Stage
Input Amplifiers
Two amplifiers can be selected to interface to the engine
sensors. These amplifiers have a typical open loop gain of
100dB, with a typical bandwidth of 2.6MHz. The common
mode input voltage range extends to within 0.5V of either
supply rail. The amplifier output has a similar output range.
Sufficient gain, bandwidth and output swing capability is
provided to ensure that the amplifier can handle
attenuation gain settings of 20 to 1 or -26dB. This would be
needed when high peak output signals, in the range of
8VRMS are obtained from the transducer. Gain settings of
10 times can also be needed when the transducers have
output levels of 5mVRMS .
In a typical application the input signal frequency may vary
from 1kHz to 20kHz. External capacitors are used to
decouple the IC from the sensor (C1 and C2) refer to
Figure 4. A typical value of the capacitor would be 3.3nF.
Series input resistors, R1 and R2, are used to connect the
inverting inputs of the amplifiers, (pins 19 and 16.)
Feedback resistors, R3 and R4, in conjunction with R3 and
R4 are used to set the gain of the amplifiers.
The gains for two identical programmable gain stages can
be adjusted, so that the knock energies can be
compensated if needed. This adjustment can be made with
64 different gain settings, ranging between 2 and 0.111.
The signals can swing between 20 to 80 percent of VDD .
Programming is discussed in the SPI Communications
Protocol section.
Programmable Bandpass Filter
Two identical programmable filters are used to detect the
frequencies of interest. The Band Pass Filter (BPF) is
programmed to pass the frequency component of the engine
knock. The filter frequency is established by the characteristics
of the particular engine and transducer. By integrating the
rectified outputs from these two filters at the INTEGRATOR
stage, a knock can be detected if it has occurred.
The filters have a nominal differential gain of 4. Their
frequency is set by a programmable word (discussed in the
SPI Communications Protocol section.) Center frequencies
can be programed from 1.22kHz to 19.98kHz, in 64 steps.
The filter Qs are typically 2.4.
Active Full Wave Rectifier
A mid voltage level is generated internally within the IC. This
level is set to be half way between VDD and ground.
Throughout the IC this level is used as a quiet, DC reference
for the signal processing circuits within the IC. This point is
brought out for several reasons, it can be used as a
reference voltage, and it must be bypassed to insure that it
remains as a quiet reference for the internal circuitry.
The output of the bandpass filters are unity gain buffered prior
to full wave rectification using switch capacitor techniques.
Each side of the rectifier circuit provides both negative and
positive values of the knock frequency bandpass frequency
filter outputs. The output is able to swing from 20 to 80 percent
of VDD . Care was taken to minimize the RMS variations from
input to output of this stage.
The input amplifiers are designed with power down
capability, which, when activated disables their bias circuit
and their output goes into a three-state state condition. This
is utilized during the diagnostic mode, in which the output
terminals of the amplifiers are driven by the outside world
with various test signals.
Programmable Integrator Stage
Antialiasing Filter
The IC has a 3rd order Butterworth filter with a 3dB point at
70kHz. Double poly capacitors and implanted resistors are
used to set poles in the filter. This filter is required to have no
more than 1dB attenuation at 20kHz (highest frequency off
interest) and a minimum attenuation of 10dB at 180kHz. This
filter precedes the switch capacitor filter stages which run at
the system frequency of 200kHz.
The signals from the rectifier stage are separated into 2 output
signal paths which are then integrated together. A differential
system is used to minimize noise. One side integrates the
positive energy value from the Knock Frequency Rectifier.
The second side does the integration of the negative energy
value. The positive and negative energy signals are opposite
phase signals. Using this technique reduces system noise
from affecting the actual signal.
The integrator time constant is software programmable by
the Integrator Time Constant discussed in the
Communications Protocol section. The time constant can be
programmed from 40µs to 600µs, with a total of 32 steps. If
for example, we program a time constant to 200µs, then with
one volt difference between each channel, the output of the
integrator will change by volt in 200µs.
R3
C1
R1
19
SENSOR
VMID
R4
C2
-
18
R2
16
SENSOR
+
VMID
20
-
17
+
15
FIGURE 4. INPUT AMPLIFIER CONNECTIONS
7
FN4367.2
January 6, 2006
HIP9011
Integration is enabled by the rising edge of the input control
signal INT/HOLD. Within 20µs after the integrate input
reaches a logic high level, the output of the integrator will fall
to approximately VRESET, 0.125V. The output of the
integrator is an analog voltage.
Differential to Single-Ended Converter
This circuit takes the differential output of the integrators
(through the test-multiplexer circuit) and provides a signal
that is the sum of the two signals. This technique is used to
improve the noise immunity of the system.
Output Buffer
This output amplifier is the same amplifier circuits as the
input amplifier used to interface with the sensors. For
diagnostic purposes when the output of the antialias filter is
being evaluated, this amplifier is in the power down mode.
Test Multiplexer
This circuit receives the positive and negative outputs from
the integrator, together with the outputs from different parts
of the IC. The Test Mux output is controlled by the fifth
programming word of the communications protocol. This
multiplexes the switch capacitor filter output, the gain control
output and the antialias filter output.
SPI Communications Protocol
Communicating to the Knock Sensor via the SPI Bus
(MOSI). A chip select pin (CS) is used to enable the chip,
which, in conjunction with the SPI clock (SCK), which moves
an eight bit programming word. Five different programming
words are used to set the following internal programmable
registers: GAIN, BANDPASS FREQUENCY FILTER,
INTEGRATOR TIME CONSTANT, CHANNEL SELECT, SO
output mode, and TEST MODES.
When chip select (CS) goes low, on the next falling edge of
the SPI clock (SCK), data is latched into the SPI register.
The data is shifted with the most significant bit first and least
significant bit last. Each word is divided into two parts: first
the address and then the value. Depending on the function
being controlled, the address is 2 or 3 bits, and the value is
either 5 or 6 bits long. All five programming words can be
entered into the IC during the HOLD mode of operation. The
integration or hold mode of operation is controlled by the
INT/HOLD input signal.
8
Programming Words
1. Band Pass Filter Frequency: Defines the center
frequency of the Band Pass Filter in the system. The first
2 bits are used for the address and the last 6 bits are used
for its value. 00FFFFFF Example: 00001010 would be
the Band Pass Filter at a center frequency of 1.78kHz (bit
value of 10 in Table 3).
2. Gain Control: defines the value of the gain stage
attenuation of gain setting. The first 2 bits are again used
for the address and the last 6 bits for its value.
10GGGGGG Example: 10010100 would be the Gain
Control (10 for the first two bits) with an attenuation of
0.739 (bit value of 20 in Table 3).
3. Integrator Time Constant: Defines the Integration Time
Constant for the system. The first 3 bits are used for the
address and the last 5 bits for the value. 110TTTTT
Example: 11000011 would be the Integrator Time
Constant (110 for the first 3 bits) and an Integration Time
Constant of 55µs (bit value 3 in Table 3).
4. Test/Channel Select Control: Again the first three bits, 111
are the address for this function, and the last five bits
define the functions that may be programmed. Example:
111B4B3B2B1B0; The options are:
A) If B0 is “0”, than channel 0 is selected. If B0 is “1”;
than channel 1 is selected as the input.
B) The remaining bits are used for selection of the various
diagnostic modes. TEST pin (14) = low. Not applicable
in Run Mode.
5. Prescaler/SO terminal status: Defines the division ratio of
the internal frequency prescaler and the status of the SO
terminal, pin 11. P1 to P4 bits define the frequency that
may be used with an external clock. The status of the
three state SO pin is set by the last, Z bit.
01P5P4P3P2P1Z; Example: 0100000, Note, in this case
bit P5 is not used. (01 for the first 2 bits sets the
Prescaler/SO function) P1 to P4 set Prescaler for a clock
frequency of 4MHz and the last bit sets the S0 terminal to
an active state.
FN4367.2
January 6, 2006
HIP9011
TABLE 3. FREQUENCY, GAIN, AND INTEGRATOR TIME CONSTANT
BIT VALUE PER
FUNCTION
FREQUENCY
(kHz)
GAIN
TIME
CONSTANT (µs)
BIT VALUE PER
FUNCTION
FREQUENCY
(kHz)
GAIN
0
1.22
2.000
40
32
4.95
0.421
1
1.26
1.882
45
33
5.12
0.400
2
1.31
1.778
50
34
5.29
0.381
3
1.35
1.684
55
35
5.48
0.364
4
1.40
1.600
60
36
5.68
0.348
5
1.45
1.523
65
37
5.90
0.333
6
1.51
1.455
70
38
6.12
0.320
7
1.57
1.391
75
39
6.37
0.308
8
1.63
1.333
80
40
6.64
0.296
9
1.71
1.280
90
41
6.94
0.286
10
1.78
1.231
100
42
7.27
0.276
11
1.87
1.185
110
43
7.63
0.267
12
1.96
1.143
120
44
8.02
0.258
13
2.07
1.063
130
45
8.46
0.250
14
2.18
1.000
140
46
8.95
0.236
15
2.31
0.944
150
47
9.50
0.222
16
2.46
0.895
160
48
10.12
0.211
17
2.54
0.850
180
49
10.46
0.200
18
2.62
0.810
200
50
10.83
0.190
19
2.71
0.773
220
51
11.22
0.182
20
2.81
0.739
240
52
11.65
0.174
21
2.92
0.708
260
53
12.10
0.167
22
3.03
0.680
280
54
12.60
0.160
23
3.15
0.654
300
55
13.14
0.154
24
3.28
0.630
320
56
13.72
0.148
25
3.43
0.607
360
57
14.36
0.143
26
3.59
0.586
400
58
15.07
0.138
27
3.76
0.567
440
59
15.84
0.133
28
3.95
0.548
480
60
16.71
0.129
29
4.16
0.500
520
61
17.67
0.125
30
4.39
0.471
560
62
18.76
0.118
31
4.66
0.444
600
63
19.98
0.111
TABLE 4. PRESCALER
TABLE 5. SO TERMINAL STATUS
CLOCK FREQUENCY
(MHz)
P5
P4
P3
P2
P1
4
X
0
0
0
0
5
X
0
0
0
1
6
X
0
0
1
0
SO TERMINAL STATUS
8
X
0
0
1
1
10
X
0
1
0
0
12
X
0
1
0
1
16
X
0
1
1
0
20
X
0
1
1
1
24
X
1
0
0
0
Z
High Impedance
1
SO Terminal Active
0
NOTE: X = Don’t care, P5 not used.
9
FN4367.2
January 6, 2006
HIP9011
ADDRESS DECODER
PRESCALER/SO TERMINAL STATUS
SI
GAIN CONTROL
INTEGRATOR TIME CONSTANT
TEST/CHANNEL SELECT CONTROL
SI
DIGITAL MULTIPLEXER
CS
SPI INTERFACE
SCK
BANDPASS FILTER
SO
TEST
COMP OUT
FIGURE 5. PROGRAMMABLE REGISTERS AND STATE MACHINE
The Digital SPI Block diagram in Figure 5 shows the
programming flow of the chip. An eight bit word is received at
the SI port. Data is shifted in by the SCK clock when the chip
is enable by the CS pin. The word is decoded by the address
decoding circuit, and the information is directed to one of 5
registers. These registers control the following chip functions:
1. Band Pass Filter frequency.
2. Gain control or attenuation.
3. Integration time constant of the rectified BPF output.
4. Prescaler.
5. Test/Channel Select.
a) Test conditions of the part.
b) Channel select to one of two input amplifiers.
A crystal oscillator circuit is provided. The chip requires at
minimum a 4MHz crystal to be connected across OSCIN and
OSCOUT pins. An external 4MHz signal may also be
provided to the OSCIN Terminal Pin 9.
10
In the diagnostic mode, we can use the digital multiplexer to
output one of the following results through the SO pin (11):
1. Value of one of the five registers in the chip
2. Buffered value of the SI pin (12).
3. Value of an internal comparator used to rectify the analog
signal
A digital SPI filter is located in the SPI Block which provides
a pseudo noise immunity characteristic.
The digital SPI filter operation requires that the SCK be low
prior to the fall of CS, followed by 8 SCK pulses (low-highlow transitions). With the SCK ending the pulse sequence in
a logic low condition, the transition of CS from a low to high
transition will cause the data-word in the SPI Buffer to be
loaded into the proper addressed programmable register.
During the Integration mode, INT/HOLD pin is high, any
single SPI byte that is entered will be acted upon if the
conditions of the digital SPI filter are met. The digital SPI
filter allows for only 8 bits per word to be accepted.
FN4367.2
January 6, 2006
HIP9011
Small Outline Plastic Packages (SOIC)
M20.3 (JEDEC MS-013-AC ISSUE C)
20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
-B-
1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
C
0.10(0.004)
0.25(0.010) M
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.014
0.019
0.35
0.49
9
C
0.0091
0.0125
0.23
0.32
-
D
0.4961
0.5118
12.60
13.00
3
E
0.2914
0.2992
7.40
7.60
4
e
α
B S
0.050 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
20
0°
20
8°
0°
7
8°
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
Rev. 2 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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11
FN4367.2
January 6, 2006