Data Sheet

HEF4067B-Q100
16-channel analog multiplexer/demultiplexer
Rev. 2 — 11 September 2014
Product data sheet
1. General description
The HEF4067B-Q100 is a 16-channel analog multiplexer/demultiplexer. It has four
address inputs (A0 to A3), an active LOW enable input (E), 16 independent inputs/outputs
(Y0 to Y15) and a common input/output (Z). The device contains 16 bidirectional analog
switches. Each switch has one side connected to an independent input/output (Y0 to
Y15) and the other side connected to the common input/output (Z). With E LOW, one of
the 16 switches is selected (low-impedance ON-state) by A0 to A3. All unselected
switches are in the high-impedance OFF-state. With E HIGH all switches are in the
high-impedance OFF-state, independent of A0 to A3. The analog inputs/outputs (Y0 to
Y15 and Z) can swing between VDD as a positive limit and VSS as a negative limit. VDD to
VSS may not exceed 15 V.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 3) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 3)
 Specified from 40 C to +85 C
 Fully static operation
 5 V, 10 V, and 15 V parametric ratings
 Standardized symmetrical output characteristics
 ESD protection:
 MIL-STD-883, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
 Complies with JEDEC standard JESD 13-B
3. Applications
 Analog multiplexing and demultiplexing
 Digital multiplexing and demultiplexing
 Signal gating
HEF4067B-Q100
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
HEF4067BT-Q100 40 C to +85 C
Name
Description
Version
SO24
plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
5. Functional diagram
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Fig 1.
Functional diagram
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Fig 2.
Schematic diagram (one switch)
HEF4067B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
2 of 17
HEF4067B-Q100
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
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Fig 3.
Logic diagram
HEF4067B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
3 of 17
HEF4067B-Q100
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
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Fig 4.
Pin configuration
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
Z
1
common input/output
Y0 to Y15
9, 8, 7, 6, 5, 4, 3, 2, 23, 22, 21, 20, 19, 18, 17, 16
independent input/output
A0 to A3
10, 11, 14, 13
address input
VSS
12
ground (0 V)
E
15
enable input (active LOW)
VDD
24
supply voltage
HEF4067B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
4 of 17
HEF4067B-Q100
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
7. Functional description
Table 3.
Function table[1]
Control
Address
E
A3
A2
A1
A0
L
L
L
L
L
Y0 = Z
L
L
L
L
H
Y1 = Z
L
L
L
H
L
Y2 = Z
L
L
L
H
H
Y3 = Z
L
L
H
L
L
Y4 = Z
L
L
H
L
H
Y5 = Z
L
L
H
H
L
Y6 = Z
L
L
H
H
H
Y7 = Z
L
H
L
L
L
Y8 = Z
L
H
L
L
H
Y9 = Z
L
H
L
H
L
Y10 = Z
L
H
L
H
H
Y11 = Z
L
H
H
L
L
Y12 = Z
L
H
H
L
H
Y13 = Z
L
H
H
H
L
Y14 = Z
L
H
H
H
H
Y15 = Z
H
X
X
X
X
none
[1]
Channel ON
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol
Parameter
VDD
supply voltage
IIK
input clamping current
VI
input voltage
II/O
input/output current
IDD
Conditions
pins An and E;
VI < 0.5 V or VI > VDD + 0.5 V
Min
Max
Unit
0.5
+18
V
-
10
mA
0.5
VDD + 0.5
V
-
10
mA
supply current
-
50
mA
Tstg
storage temperature
65
+150
C
Tamb
ambient temperature
Ptot
total power dissipation
Tamb = 40 C to +125 C
P
power dissipation
per output
[1]
[2]
40
+85
C
-
500
mW
-
100
mW
[1]
To avoid drawing VDD current from terminal Z, when switch current flows into terminals Yn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal Z, no VDD current flows from terminals Yn. In this case, there is no
limit for the voltage drop across the switch, but the voltages at Y and Z may not exceed VDD or VSS.
[2]
For SO24 packages: above Tamb = 70 C, Ptot derates linearly at 8 mW/K.
HEF4067B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
5 of 17
HEF4067B-Q100
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
VDD
Conditions
Min
Typ
Max
Unit
supply voltage
3
-
15
V
VI
input voltage
0
-
VDD
V
Tamb
ambient temperature
in free air
40
-
+85
C
t/V
input transition rise and fall rate
VDD = 5 V
-
-
3.75
s/V
VDD = 10 V
-
-
0.5
s/V
VDD = 15 V
-
-
0.08
s/V
10. Static characteristics
Table 6.
Static characteristics
VSS = 0 V; VI = VSS or VDD; unless otherwise specified.
Symbol Parameter
VIL
VIH
LOW-level input
voltage
HIGH-level input
voltage
Conditions
VDD
Tamb = 40 C Tamb = +25 C Tamb = +85 C Unit
Min
Max
Min
Max
Min
Max
-
1
-
1
-
1
IO < 1 A
VO = 0.5 V or 4.5 V
5V
V
VO = 1.0 V or 9.0 V
10 V
-
2
-
2
-
2
V
VO = 1.5 V or 13.5 V
15 V
-
2.5
-
2.5
-
2.5
V
VO = 0.5 V or 4.5 V
5V
4
-
4
-
4
-
V
VO = 1.0 V or 9.0 V
10 V
8
-
8
-
8
-
V
VO = 1.5 V or 13.5 V
15 V
12.5
-
12.5
-
12.5
-
V
15 V
-
0.3
-
0.3
-
1.0
A
A
IO < 1 A
II
input leakage
current
IOZ
OFF-state output output at VDD
current
output at VSS
15 V
-
1.6
-
1.6
-
12.0
15 V
-
1.6
-
1.6
-
12.0 A
OFF-state
leakage current
Z port; all channels OFF;
see Figure 5
15 V
-
-
-
1000
-
-
nA
Yn port; per channel;
see Figure 6
15 V
-
-
-
200
-
-
nA
all valid input combinations;
IO = 0 A
5V
-
20
-
20
-
150
A
10 V
-
40
-
40
-
300
A
15 V
-
80
-
80
-
600
A
15 V
-
-
-
7.5
-
-
pF
IS(OFF)
IDD
CI
supply current
VI = 0 V or 15 V
input capacitance digital inputs
HEF4067B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
6 of 17
HEF4067B-Q100
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
10.1 Test circuits
VDD
A0 to A3
VDD or VSS
Z
Yn
E
IS
VSS
VDD
VI
VO
001aal616
Fig 5.
Test circuit for measuring OFF-state leakage current Z port
VDD
VDD or VSS
A0 to A3
Y0 1
Z
Yn 2
switch
IS
E
VSS
VSS
VI
VO
001aal617
Fig 6.
Test circuit for measuring OFF-state leakage current Yn port
10.2 On resistance
Table 7.
ON resistance
Tamb = 25 C; ISW = 200 A; VSS = 0 V.
Symbol
Parameter
Conditions
VDD
RON(peak)
ON resistance (peak)
VI = 0 V to VDD; see Figure 7 and
Figure 8
5V
10 V
15 V
RON(rail)
ON resistance (rail)
VI = 0 V; see Figure 7 and Figure 8
VI = VDD; see Figure 7 and Figure 8
RON
ON resistance mismatch
between channels
HEF4067B_Q100
Product data sheet
VI = 0 V to VDD; see Figure 7
Max
Unit
350
2500

80
245

60
175

5V
115
340

10 V
50
160

15 V
40
115

5V
120
365

10 V
65
200

15 V
50
155

5V
25
-

10 V
10
-

15 V
5
-

All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 September 2014
Typ
© NXP Semiconductors N.V. 2014. All rights reserved.
7 of 17
HEF4067B-Q100
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
10.2.1 On resistance waveform and test circuit
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Iis = 200 A; VSS = 0 V.
RON = VSW / ISW.
Fig 7.
9,9
DDJ
Test circuit for measuring RON
Fig 8.
Typical RON as a function of input voltage
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Tamb = 25 C; VSS = 0 V; for test circuit, see Figure 12.
Symbol
Parameter
Conditions
VDD
Min
Typ
Max
Unit
tPHL
HIGH to LOW propagation delay
Yn, Z to Z, Yn; see Figure 9
5V
-
30
60
ns
10 V
-
15
25
ns
15 V
-
10
20
ns
5V
-
190
380
ns
10 V
-
70
145
ns
15 V
-
50
100
ns
5V
-
25
50
ns
10 V
-
10
20
ns
15 V
-
10
20
ns
5V
-
175
345
ns
10 V
-
70
140
ns
15 V
-
50
100
ns
5V
-
195
385
ns
10 V
-
140
280
ns
An to Yn, Z; see Figure 10
tPLH
LOW to HIGH propagation delay
Yn, Z to Z, Yn; see Figure 9
An to Yn, Z; see Figure 10
tPHZ
tPLZ
HIGH to OFF-state propagation delay
LOW to OFF-state propagation delay
HEF4067B_Q100
Product data sheet
E to Yn, Z; see Figure 11
E to Yn, Z; see Figure 11
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 September 2014
15 V
-
130
260
ns
5V
-
215
435
ns
10 V
-
180
355
ns
15 V
-
170
340
ns
© NXP Semiconductors N.V. 2014. All rights reserved.
8 of 17
HEF4067B-Q100
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
Table 8.
Dynamic characteristics …continued
Tamb = 25 C; VSS = 0 V; for test circuit, see Figure 12.
Symbol
Parameter
Conditions
VDD
Min
Typ
Max
Unit
tPZH
OFF-state to HIGH propagation delay
E to Yn, Z; see Figure 11
5V
-
155
315
ns
10 V
-
70
135
ns
15 V
-
50
100
ns
5V
-
170
340
ns
10 V
-
70
140
ns
15 V
-
50
100
ns
E to Yn, Z; see Figure 11
OFF-state to LOW propagation delay
tPZL
11.1 Waveforms and test circuit
VDD
9,
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VSS
9
tPLH
W3+/
W3/+
tPHL
VO
VY
Yn or Z
output
92+
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VM
An input
90
90
90
VSS
switch OFF
92/
VX
switch ON
DDJ
switch OFF
001aal618
Measurement points are given in Table 9.
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur
with the output load.
Fig 9.
Yn, Z to Z, Yn propagation delays
HEF4067B_Q100
Product data sheet
Fig 10. Sn to Yn, Z propagation delays
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Rev. 2 — 11 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
9 of 17
HEF4067B-Q100
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
9,
90
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9
W3/=
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Measurement points are shown in Table 9.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 11. Enable and disable times
Table 9.
Measurement points
Supply voltage
Input
Output
VCC
VM
VI
VM
VX
VY
5 V to 15 V
0.5VDD
GND to VDD
0.5VDD
10%
90%
9''
9''
9,
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Test data is given in Table 10.
Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator
CL = load capacitance including jig and probe capacitance
RL = load resistor
S1 = test selection switch
Fig 12. Test circuit for measuring switching times
Table 10.
Test data
Input
Yn, Z
Load
An and E
tr, tf
VDD or VSS VDD or VSS  20 ns
[1]
S1 position
VM
CL
RL
tPHL[1]
0.5VDD
50 pF
10 k
VDD or VSS VSS
tPLH
tPZH, tPHZ tPZL, tPLZ other
VSS
VDD
VSS
For Yn to Z or Z to Yn propagation delays, use VSS. For An or to Yn or Z propagation delays, use VDD.
HEF4067B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
10 of 17
HEF4067B-Q100
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
11.2 Additional dynamic parameters
Table 11. Additional dynamic characteristics
VSS = 0 V; Tamb = 25 C.
Symbol
Parameter
THD
Conditions
total harmonic distortion
3 dB frequency response
f(3dB)
VDD
Typ
Max
Unit
see Figure 13; RL = 10 k; CL = 15 pF; 5 V
channel ON; VI = 0.5VDD (p-p);
10 V
fi = 1 kHz
15 V
[1]
0.25
-
%
[1]
0.04
-
%
[1]
0.04
-
%
see Figure 14; RL = 1 k; CL = 5 pF;
channel ON; VI = 0.5VDD (p-p)
5V
[1]
13
-
MHz
10 V
[1]
40
-
MHz
70
-
50
15 V
[1]
iso
isolation (OFF-state)
see Figure 15; fi = 1 MHz; RL = 1 k;
CL = 5 pF; channel OFF;
VI = 0.5VDD (p-p)
10 V
[1]
Vct
crosstalk voltage
digital inputs to switch; see Figure 16;
RL = 10 k; CL = 15 pF;
E or An = VDD (square-wave)
10 V
Xtalk
crosstalk
between switches; see Figure 17;
fi = 1 MHz; RL = 1 k;
VI = 0.5VDD (p-p)
10 V
[1]
50
[1]
MHz
-
-
50
dB
mV
-
dB
fi is biased at 0.5 VDD; VI = 0.5VDD (p-p).
Table 12. Dynamic power dissipation PD
PD can be calculated from the formulas shown; VSS = 0 V; tr = tf  20 ns; Tamb = 25 C.
Symbol
Parameter
dynamic power
dissipation
PD
VDD
Typical formula for PD (W)
5V
where:
PD = 1000  fi + (fo  CL)  VDD
2
fi = input frequency in MHz;
10 V
PD = 5500  fi + (fo  CL)  VDD
2
fo = output frequency in MHz;
15 V
PD = 15000  fi + (fo  CL)  VDD2
CL = output load capacitance in pF;
VDD = supply voltage in V;
(CL  fo) = sum of the outputs.
11.2.1 Test circuits
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Fig 13. Test circuit for measuring total harmonic
distortion
Product data sheet
966
966
5/
HEF4067B_Q100
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DDJ
Fig 14. Test circuit for measuring frequency response
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
11 of 17
HEF4067B-Q100
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
VDD
VDD or VSS
A0 to A3
Y0 1
Z
Yn 2
switch
E
VSS
VSS
RL
CL
dB
fi
001aal619
Fig 15. Test circuit for measuring isolation (OFF-state)
9''
9''
5/
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RQ
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92
9FW
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b. Input and output pulse definitions
Fig 16. Test circuit for measuring crosstalk voltage between digital inputs and switch
9''
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5/
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a. Switch closed condition
5/
92
DDJ
b. Switch open condition
Fig 17. Test circuit for measuring crosstalk between switches
HEF4067B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
12 of 17
HEF4067B-Q100
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
12. Package outline
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Fig 18. Package outline SOT137-1 (SO24)
HEF4067B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
13 of 17
HEF4067B-Q100
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
13. Abbreviations
Table 13.
Abbreviations
Acronym
Description
HBM
Human Body Model
ESD
ElectroStatic Discharge
MM
Machine Model
MIL
Military
14. Revision history
Table 14.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
HEF4067B-Q100 v.2
20140911
Product data sheet
-
HEF4067B-Q100 v.1
-
-
Modifications:
HEF4067B-Q100 v.1
HEF4067B_Q100
Product data sheet
•
Figure 16: Test circuit modified
20130924
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
14 of 17
HEF4067B-Q100
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
HEF4067B_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
15 of 17
HEF4067B-Q100
NXP Semiconductors
16-channel analog multiplexer/demultiplexer
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
HEF4067B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
16 of 17
NXP Semiconductors
HEF4067B-Q100
16-channel analog multiplexer/demultiplexer
17. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
10.1
10.2
10.2.1
11
11.1
11.2
11.2.1
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
On resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 7
On resistance waveform and test circuit. . . . . . 8
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms and test circuit . . . . . . . . . . . . . . . . 9
Additional dynamic parameters . . . . . . . . . . . 11
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 September 2014
Document identifier: HEF4067B_Q100