Data Sheet

74LVC1G53-Q100
2-channel analog multiplexer/demultiplexer
Rev. 1 — 29 January 2013
Product data sheet
1. General description
The 74LVC1G53-Q100 is a low-power, low-voltage, high-speed, Si-gate CMOS device.
The 74LVC1G53-Q100 provides one analog multiplexer/demultiplexer with a digital select
input (S), two independent inputs/outputs (Y0 and Y1), a common input/output (Z) and an
active LOW enable input (E). When pin E is HIGH, the switch is turned off.
Schmitt-trigger action at the select and enable inputs makes the circuit tolerant to slower
input rise and fall times across the entire VCC range from 1.65 V to 5.5 V.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +85 C and from 40 C to +125 C
 Wide supply voltage range from 1.65 V to 5.5 V
 Very low ON resistance:
 7.5  (typical) at VCC = 2.7 V
 6.5  (typical) at VCC = 3.3 V
 6  (typical) at VCC = 5 V
 Switch current capability of 32 mA
 High noise immunity
 CMOS low power consumption
 TTL interface compatibility at 3.3 V
 Latch-up performance meets requirements of JESD 78 Class I
 Multiple package options
 ESD protection:
 MIL-STD-883, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
74LVC1G53-Q100
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC1G53DP-Q100 40 C to +125 C
TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
74LVC1G53DC-Q100 40 C to +125 C
VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
SOT505-2
4. Marking
Table 2.
Marking codes
Type number
Marking code[1]
74LVC1G53DC-Q100
V53
74LVC1G53DP-Q100
V53
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Y1
S
Y0
Z
E
001aah795
Fig 1.
Logic symbol
Y0
S
Z
Y1
E
Fig 2.
001aad387
Logic diagram
74LVC1G53_Q100
Product data sheet
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Rev. 1 — 29 January 2013
© NXP B.V. 2013. All rights reserved.
2 of 20
74LVC1G53-Q100
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
/9&*4
=
9&&
(
<
*1'
<
*1'
6
DDD
Fig 3.
Pin configuration SOT505-2 and SOT765-1
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
Z
1
common output or input
E
2
enable input (active LOW)
GND
3
ground (0 V)
GND
4
ground (0 V)
S
5
select input
Y1
6
independent input or output
Y0
7
independent input or output
VCC
8
supply voltage
7. Functional description
Table 4.
Function table[1]
Input
Channel on
S
E
L
L
Y0 to Z or Z to Y0
H
L
Y1 to Z or Z to Y1
X
H
Z (switch off)
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
74LVC1G53_Q100
Product data sheet
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Rev. 1 — 29 January 2013
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74LVC1G53-Q100
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
Conditions
[1]
VI
input voltage
IIK
input clamping current
VI < 0.5 V or VI > VCC + 0.5 V
ISK
switch clamping current
VI < 0.5 V or VI > VCC + 0.5 V
[2]
Min
Max
Unit
0.5
+6.5
V
0.5
+6.5
V
50
-
mA
-
50
mA
0.5
VCC + 0.5
V
VSW
switch voltage
enable and disable mode
ISW
switch current
VSW > 0.5 V or VSW < VCC + 0.5 V
-
50
mA
ICC
supply current
-
100
mA
IGND
ground current
100
-
mA
Tstg
storage temperature
65
+150
C
-
250
mW
total power dissipation
Ptot
Tamb = 40 C to +125 C
[3]
[1]
The minimum input voltage rating may be exceeded if the input current rating is observed.
[2]
The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed.
[3]
For TSSOP8 packages: above 55 C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 packages: above 110 C the value of Ptot derates linearly with 8.0 mW/K.
9. Recommended operating conditions
Table 6.
Operating conditions
Symbol
Parameter
VCC
supply voltage
VI
input voltage
VSW
Conditions
switch voltage
Tamb
ambient temperature
t/V
input transition rise and fall rate
Min
Max
Unit
1.65
5.5
V
0
5.5
V
0
VCC
V
enable and disable mode
[1]
40
+125
C
VCC = 1.65 V to 2.7 V
[2]
-
20
ns/V
VCC = 2.7 V to 5.5 V
[2]
-
10
ns/V
[1]
To avoid sinking GND current from terminal Z when switch current flows in terminal Yn, the voltage drop across the bidirectional switch
must not exceed 0.4 V. If the switch current flows into terminal Z, no GND current flows from terminal Yn. In this case, there is no limit for
the voltage drop across the switch.
[2]
Applies to control signal levels.
74LVC1G53_Q100
Product data sheet
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Rev. 1 — 29 January 2013
© NXP B.V. 2013. All rights reserved.
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74LVC1G53-Q100
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground 0 V).
Symbol Parameter
HIGH-level
input voltage
VIH
Tamb = 40 C to +85 C
Conditions
LOW-level
input voltage
Min
Max
Min
Max
0.65  VCC
-
-
0.65  VCC
-
V
VCC = 2.3 V to 2.7 V
1.7
-
-
1.7
-
V
VCC = 3 V to 3.6 V
2.0
-
-
2.0
-
V
0.7  VCC
-
-
0.7  VCC
-
V
VCC = 1.65 V to 1.95 V
VCC = 4.5 V to 5.5 V
VIL
Tamb = 40 C to +125 C Unit
Typ[1]
VCC = 1.65 V to 1.95 V
-
-
0.35  VCC
-
0.35  VCC
V
VCC = 2.3 V to 2.7 V
-
-
0.7
-
0.7
V
VCC = 3 V to 3.6 V
-
-
0.8
-
0.8
V
VCC = 4.5 V to 5.5 V
-
-
0.3  VCC
-
0.3  VCC
V
-
0.1
2
-
10
A
II
input leakage
current
pin S and pin E;
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
[2]
IS(OFF)
OFF-state
leakage
current
VCC = 5.5 V;
see Figure 4
[2]
-
0.1
5
-
20
A
IS(ON)
ON-state
leakage
current
VCC = 5.5 V;
see Figure 5
[2]
-
0.1
5
-
20
A
ICC
supply current VI = 5.5 V or GND;
VSW = GND or VCC;
VCC = 1.65 V to 5.5 V
[2]
-
0.1
10
-
40
A
ICC
additional
pin S and pin E;
supply current VI = VCC  0.6 V;
VSW = GND or VCC;
VCC = 5.5 V
[2]
-
5
500
-
5000
A
CI
input
capacitance
-
2.5
-
-
-
pF
CS(OFF)
OFF-state
capacitance
-
6.0
-
-
-
pF
CS(ON)
ON-state
capacitance
-
18
-
-
-
pF
[1]
Typical values are measured at Tamb = 25 C.
[2]
These typical values are measured at VCC = 3.3 V.
74LVC1G53_Q100
Product data sheet
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Rev. 1 — 29 January 2013
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74LVC1G53-Q100
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
10.1 Test circuits
VCC
S
VIL or VIH
Y0
Z
Y1
1
switch
switch
S
E
1
VIL
VIH
2
VIH
VIH
IS
2
E
GND
VIH
VI
VO
001aad390
VI = VCC or GND; VO = GND or VCC.
Fig 4.
Test circuit for measuring OFF-state leakage current
VCC
S
VIL or VIH
IS
Z
Y0
1
Y1
2
switch
S
E
1
VIL
VIL
2
VIH
VIL
switch
E
GND
VIL
VO
VI
001aad391
VI = VCC or GND and VO = open circuit.
Fig 5.
Test circuit for measuring ON-state leakage current
10.2 ON resistance
Table 8.
ON resistance
At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 7 to Figure 12.
Symbol
RON(peak)
Parameter
ON resistance (peak)
74LVC1G53_Q100
Product data sheet
40 C to +85 C
Conditions
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
ISW = 4 mA;
VCC = 1.65 V to 1.95 V
-
34.0
130
-
195

ISW = 8 mA; VCC = 2.3 V to 2.7 V
-
12.0
30
-
45

ISW = 12 mA; VCC = 2.7 V
-
10.4
25
-
38

VI = GND to VCC; see Figure 6
ISW = 24 mA; VCC = 3 V to 3.6 V
-
7.8
20
-
30

ISW = 32 mA; VCC = 4.5 V to 5.5 V
-
6.2
15
-
23

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© NXP B.V. 2013. All rights reserved.
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74LVC1G53-Q100
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
Table 8.
ON resistance …continued
At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 7 to Figure 12.
Symbol
Parameter
RON(rail)
40 C to +85 C
Conditions
ON resistance (rail)
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
ISW = 4 mA;
VCC = 1.65 V to 1.95 V
-
8.2
18
-
27

ISW = 8 mA; VCC = 2.3 V to 2.7 V
-
7.1
16
-
24

ISW = 12 mA; VCC = 2.7 V
-
6.9
14
-
21

VI = GND; see Figure 6
ISW = 24 mA; VCC = 3 V to 3.6 V
-
6.5
12
-
18

ISW = 32 mA; VCC = 4.5 V to 5.5 V
-
5.8
10
-
15

ISW = 4 mA;
VCC = 1.65 V to 1.95 V
-
10.4
30
-
45

ISW = 8 mA; VCC = 2.3 V to 2.7 V
-
7.6
20
-
30

ISW = 12 mA; VCC = 2.7 V
-
7.0
18
-
27

ISW = 24 mA; VCC = 3 V to 3.6 V
-
6.1
15
-
23

-
4.9
10
-
15

-
26.0
-
-
-

VI = VCC; see Figure 6
ISW = 32 mA; VCC = 4.5 V to 5.5 V
ON resistance
(flatness)
RON(flat)
[2]
VI = GND to VCC
ISW = 4 mA;
VCC = 1.65 V to 1.95 V
ISW = 8 mA; VCC = 2.3 V to 2.7 V
-
5.0
-
-
-

ISW = 12 mA; VCC = 2.7 V
-
3.5
-
-
-

ISW = 24 mA; VCC = 3 V to 3.6 V
-
2.0
-
-
-

ISW = 32 mA; VCC = 4.5 V to 5.5 V
-
1.5
-
-
-

[1]
Typical values are measured at Tamb = 25 C and nominal VCC.
[2]
Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and
temperature.
10.3 ON resistance test circuit and graphs
VSW
VCC
VIL or VIH
S
Y0
1
Z
Y1
2
switch
S
E
1
VIL
VIL
2
VIH
VIL
switch
E
GND
VIL
ISW
VI
001aad392
RON = VSW / ISW.
Fig 6.
Test circuit for measuring ON resistance
74LVC1G53_Q100
Product data sheet
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Rev. 1 — 29 January 2013
© NXP B.V. 2013. All rights reserved.
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74LVC1G53-Q100
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
mna673
40
RON
(Ω)
30
(1)
20
(2)
(3)
10
(4)
(5)
0
0
1
2
3
4
5
VI (V)
(1) VCC = 1.8 V.
(2) VCC = 2.5 V.
(3) VCC = 2.7 V.
(4) VCC = 3.3 V.
(5) VCC = 5.0 V.
Typical ON resistance as a function of input voltage; Tamb = 25 C
Fig 7.
001aaa712
55
RON
(Ω)
001aaa708
15
RON
(Ω)
45
13
35
11
(4)
(3)
(2)
(1)
(1)
(2)
25
9
(3)
(4)
15
7
5
5
0
0.4
0.8
1.2
1.6
2.0
0
0.5
VI (V)
(1) Tamb = 125 C.
(2) Tamb = 85 C.
(2) Tamb = 85 C.
(3) Tamb = 25 C.
(3) Tamb = 25 C.
(4) Tamb = 40 C.
(4) Tamb = 40 C.
ON resistance as a function of input voltage;
VCC = 1.8 V
74LVC1G53_Q100
Product data sheet
1.5
2.0
2.5
VI (V)
(1) Tamb = 125 C.
Fig 8.
1.0
Fig 9.
ON resistance as a function of input voltage;
VCC = 2.5 V
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74LVC1G53-Q100
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
001aaa709
13
001aaa710
10
RON
(Ω)
RON
(Ω)
11
8
(1)
(1)
9
(2)
(2)
6
(3)
(3)
7
(4)
(4)
5
4
0
0.5
1.0
1.5
2.0
2.5
3.0
VI (V)
0
1
2
3
4
VI (V)
(1) Tamb = 125 C.
(1) Tamb = 125 C.
(2) Tamb = 85 C.
(2) Tamb = 85 C.
(3) Tamb = 25 C.
(3) Tamb = 25 C.
(4) Tamb = 40 C.
(4) Tamb = 40 C.
Fig 10. ON resistance as a function of input voltage;
VCC = 2.7 V
Fig 11. ON resistance as a function of input voltage;
VCC = 3.3 V
001aaa711
7
RON
(Ω)
6
5
(1)
(2)
(3)
4
(4)
3
0
1
2
3
4
5
VI (V)
(1) Tamb = 125 C.
(2) Tamb = 85 C.
(3) Tamb = 25 C.
(4) Tamb = 40 C.
Fig 12. ON resistance as a function of input voltage; VCC = 5.0 V
74LVC1G53_Q100
Product data sheet
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Rev. 1 — 29 January 2013
© NXP B.V. 2013. All rights reserved.
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74LVC1G53-Q100
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
11. Dynamic characteristics
Table 9.
Dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 15.
Symbol Parameter
tpd
ten
40 C to +85 C
Conditions
Min
Max
Min
Max
VCC = 1.65 V to 1.95 V
-
-
2
-
2.5
ns
VCC = 2.3 V to 2.7 V
-
-
1.2
-
1.5
ns
VCC = 2.7 V
-
-
1.0
-
1.25
ns
VCC = 3.0 V to 3.6 V
-
-
0.8
-
1.0
ns
VCC = 4.5 V to 5.5 V
-
-
0.6
-
0.8
ns
VCC = 1.65 V to 1.95 V
2.6
6.7
10.3
2.6
12.9
ns
VCC = 2.3 V to 2.7 V
1.9
4.1
6.4
1.9
8.0
ns
VCC = 2.7 V
1.9
4.0
5.5
1.8
7.0
ns
VCC = 3.0 V to 3.6 V
1.8
3.4
5.0
1.8
6.3
ns
1.3
2.6
3.8
1.3
4.8
ns
VCC = 1.65 V to 1.95 V
1.9
4.0
7.3
1.9
9.2
ns
VCC = 2.3 V to 2.7 V
1.4
2.5
4.4
1.4
5.5
ns
VCC = 2.7 V
1.1
2.6
3.9
1.1
4.9
ns
VCC = 3.0 V to 3.6 V
1.2
2.2
3.8
1.2
4.8
ns
VCC = 4.5 V to 5.5 V
1.0
1.7
2.6
1.0
3.3
ns
VCC = 1.65 V to 1.95 V
2.1
6.8
10.0
2.1
12.5
ns
VCC = 2.3 V to 2.7 V
1.4
3.7
6.1
1.4
7.7
ns
VCC = 2.7 V
1.4
4.9
6.2
1.4
7.8
ns
VCC = 3.0 V to 3.6 V
1.1
4.0
5.4
1.1
6.8
ns
1.0
2.9
3.8
1.0
4.8
ns
VCC = 1.65 V to 1.95 V
2.3
5.6
8.6
2.3
11.0
ns
VCC = 2.3 V to 2.7 V
1.2
3.2
4.8
1.2
6.0
ns
VCC = 2.7 V
1.4
4.0
5.2
1.4
6.5
ns
VCC = 3.0 V to 3.6 V
2.0
3.7
5.0
2.0
6.3
ns
VCC = 4.5 V to 5.5 V
1.3
2.9
3.8
1.3
4.8
ns
propagation delay Z to Yn or Yn to Z; see Figure 13
enable time
S to Z or Yn; see Figure 14
[2][3]
[4]
VCC = 4.5 V to 5.5 V
E to Z or Yn; see Figure 14
tdis
disable time
40 C to +125 C Unit
Typ[1]
S to Z or Yn; see Figure 14
[4]
[5]
VCC = 4.5 V to 5.5 V
E to Z or Yn; see Figure 14
[1]
Typical values are measured at Tamb = 25 C and nominal VCC.
[5]
[2]
tpd is the same as tPLH and tPHL.
[3]
Propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified capacitance when
driven by an ideal voltage source (zero output impedance).
[4]
ten is the same as tPZH and tPZL.
[5]
tdis is the same as tPLZ and tPHZ.
74LVC1G53_Q100
Product data sheet
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Rev. 1 — 29 January 2013
© NXP B.V. 2013. All rights reserved.
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2-channel analog multiplexer/demultiplexer
11.1 Waveforms and test circuits
VI
Yn or Z
input
VM
VM
GND
tPLH
tPHL
VOH
Z or Yn
output
VM
VM
VOL
001aac361
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 13. Input (Yn or Z) to output (Z or Yn) propagation delays
VI
S, E input
VM
GND
tPLZ
Z, Yn
VCC
output
LOW to OFF
OFF to LOW
output
HIGH to OFF
OFF to HIGH
VM
VX
VOL
Z, Yn
tPZL
tPHZ
VOH
tPZH
VY
VM
GND
switch
enabled
switch
disabled
switch
enabled
001aad393
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 14. Enable and disable times
Table 10.
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
VX
VY
1.65 V to 2.7 V
0.5  VCC
0.5  VCC
VOL + 0.15 V
VOH  0.15 V
2.7 V to 5.5 V
0.5  VCC
0.5  VCC
VOL + 0.3 V
VOH  0.3 V
74LVC1G53_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 January 2013
© NXP B.V. 2013. All rights reserved.
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74LVC1G53-Q100
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
VEXT
VCC
VI
RL
VO
G
DUT
RT
CL
RL
mna616
Test data is given in Table 11.
Definitions test circuit:
RT = Termination resistance (should be equal to output impedance Zo of the pulse generator).
CL = Load capacitance (including jig and probe capacitance).
RL = Load resistance.
VEXT = External voltage for measuring switching times.
Fig 15. Test circuit for measuring switching times
Table 11.
Test data
Supply voltage
Input
Load
VEXT
VCC
VI
tr, tf
CL
RL
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
1.65 V to 1.95 V
VCC
 2.0 ns
30 pF
1 k
open
GND
2  VCC
2.3 V to 2.7 V
VCC
 2.0 ns
30 pF
500 
open
GND
2  VCC
2.7 V
VCC
 2.5 ns
50 pF
500 
open
GND
2  VCC
3 V to 3.6 V
VCC
 2.5 ns
50 pF
500 
open
GND
2  VCC
4.5 V to 5.5 V
VCC
 2.5 ns
50 pF
500 
open
GND
2  VCC
11.2 Additional dynamic characteristics
Table 12. Additional dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C.
Symbol
Parameter
Conditions
THD
total harmonic distortion
fi = 600 Hz to 20 kHz; RL = 600 ;
CL = 50 pF; VI = 0.5 V (p-p); see Figure 16
f(3dB)
Min
Typ
Max
Unit
VCC = 1.65 V
-
0.260
-
%
VCC = 2.3 V
-
0.078
-
%
VCC = 3.0 V
-
0.078
-
%
VCC = 4.5 V
-
0.078
-
%
3 dB frequency response RL = 50 ; CL = 5 pF; see Figure 17
74LVC1G53_Q100
Product data sheet
VCC = 1.65 V
-
200
-
MHz
VCC = 2.3 V
-
300
-
MHz
VCC = 3.0 V
-
300
-
MHz
VCC = 4.5 V
-
300
-
MHz
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Rev. 1 — 29 January 2013
© NXP B.V. 2013. All rights reserved.
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74LVC1G53-Q100
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
Table 12. Additional dynamic characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C.
Symbol
Parameter
Conditions
iso
isolation (OFF-state)
RL = 50 ; CL = 5 pF; fi = 10 MHz;
see Figure 18
Typ
Max
Unit
VCC = 1.65 V
-
42
-
dB
VCC = 2.3 V
-
42
-
dB
VCC = 3.0 V
-
40
-
dB
VCC = 4.5 V
-
40
-
dB
VCC = 1.8 V
-
3.3
-
pC
VCC = 2.5 V
-
4.1
-
pC
VCC = 3.3 V
-
5.0
-
pC
VCC = 4.5 V
-
6.4
-
pC
VCC = 5.5 V
-
7.5
-
pC
CL = 0.1 nF; Vgen = 0 V; Rgen = 0 ;
fi = 1 MHz; RL = 1 M; see Figure 19
charge injection
Qinj
Min
11.3 Test circuits
0.5VCC
VCC
S
VIL or VIH
0.1 μF
Z
Y0
1
Y1
2
switch
S
E
1
VIL
VIL
2
VIH
VIL
RL
10 μF
switch
E
VIL
CL
600 Ω
fi
D
GND
001aad394
Fig 16. Test circuit for measuring total harmonic distortion
0.5VCC
VCC
S
VIL or VIH
0.1 μF
Z
Y0
1
Y1
2
RL
switch
S
E
1
VIL
VIL
2
VIH
VIL
switch
E
VIL
fi
CL
50 Ω
dB
GND
001aad395
Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads 3 dB.
Fig 17. Test circuit for measuring the frequency response when switch is in ON-state
74LVC1G53_Q100
Product data sheet
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Rev. 1 — 29 January 2013
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74LVC1G53-Q100
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
0.5VCC
0.5VCC
VCC
RL
S
VIL or VIH
0.1 μF
switch
S
E
1
VIH
VIH
2
VIL
VIH
RL
Z
Y0
1
Y1
2
switch
E
VIH
dB
CL
50 Ω
fi
GND
001aad396
Adjust fi voltage to obtain 0 dBm level at input.
Fig 18. Test circuit for measuring isolation (OFF-state)
VCC
S
Y0
1
Z
Y1
2
switch
E
Rgen
VIL
VI G
VO
RL
CL
Vgen
GND
001aad398
a. Test circuit
logic
(S) off
input
on
VO
off
ΔVO
001aac478
b. Input and output pulse definitions
Qinj = VO  CL.
VO = output voltage variation.
Rgen = generator resistance.
Vgen = generator voltage.
Fig 19. Test circuit for measuring charge injection
74LVC1G53_Q100
Product data sheet
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Rev. 1 — 29 January 2013
© NXP B.V. 2013. All rights reserved.
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74LVC1G53-Q100
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
12. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
D
E
A
SOT505-2
X
c
HE
y
v M A
Z
5
8
A
A2
(A3)
A1
pin 1 index
θ
Lp
L
1
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(1)
e
HE
L
Lp
v
w
y
Z(1)
θ
mm
1.1
0.15
0.00
0.95
0.75
0.25
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
0.65
4.1
3.9
0.5
0.47
0.33
0.2
0.13
0.1
0.70
0.35
8°
0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT505-2
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
02-01-16
---
Fig 20. Package outline SOT505-2 (TSSOP8)
74LVC1G53_Q100
Product data sheet
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Rev. 1 — 29 January 2013
© NXP B.V. 2013. All rights reserved.
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74LVC1G53-Q100
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
D
E
SOT765-1
A
X
c
y
HE
v M A
Z
5
8
Q
A
A2
A1
pin 1 index
(A3)
θ
Lp
1
4
e
L
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(2)
e
HE
L
Lp
Q
v
w
y
Z(1)
θ
mm
1
0.15
0.00
0.85
0.60
0.12
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
0.5
3.2
3.0
0.4
0.40
0.15
0.21
0.19
0.2
0.13
0.1
0.4
0.1
8°
0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT765-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
02-06-07
MO-187
Fig 21. Package outline SOT765-1 (VSSOP8)
74LVC1G53_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 January 2013
© NXP B.V. 2013. All rights reserved.
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74LVC1G53-Q100
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
13. Abbreviations
Table 13.
Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
TTL
Transistor-Transistor Logic
HBM
Human Body Model
ESD
ElectroStatic Discharge
MM
Machine Model
CDM
Charged Device Model
DUT
Device Under Test
MIL
Military
14. Revision history
Table 14.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LVC1G53_Q100 v.1
20130129
Product data sheet
-
-
74LVC1G53_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 January 2013
© NXP B.V. 2013. All rights reserved.
17 of 20
74LVC1G53-Q100
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74LVC1G53_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 January 2013
© NXP B.V. 2013. All rights reserved.
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74LVC1G53-Q100
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVC1G53_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 January 2013
© NXP B.V. 2013. All rights reserved.
19 of 20
74LVC1G53-Q100
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
17. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
10.1
10.2
10.3
11
11.1
11.2
11.3
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ON resistance test circuit and graphs. . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Waveforms and test circuits . . . . . . . . . . . . . . 11
Additional dynamic characteristics . . . . . . . . . 12
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Contact information. . . . . . . . . . . . . . . . . . . . . 19
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 29 January 2013
Document identifier: 74LVC1G53_Q100