ESD108-B1-CSP0201 Data Sheet (901 KB, EN)

Protection Devices
TVS (Transient Voltage Suppressor Diodes)
ESD108-B1-CSP0201
Bi-directional, 5.5 V, 0.28 pF, 0201, RoHS and Halogen Free compliant
ESD108-B1-CSP0201
Data Sheet
Revision 1.4, 2016-04-21
Final
Power Management & Multimarket
Edition 2016-04-21
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2016 Infineon Technologies AG
All Rights Reserved.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com)
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
ESD108-B1-CSP0201
Product Overview
1
Product Overview
1.1
Features
•
ESD / transient protection of high speed data lines according to:
– IEC61000-4-2 (ESD): ±25 kV (air/contact discharge)
– IEC61000-4-4 (EFT): ±2.5 kV / ±50 A (5/50 ns)
– IEC61000-4-5 (surge): ±2.5 A (8/20 µs)
Bi-directional working voltage up to: VRWM = ±5.5 V
Line capacitance: CL = 0.28 pF (typical) at f = 1 MHz
Clamping voltage: VCL = 20 V (typical) at ITLP = 16 A with RDYN = 0.78 Ω (typical)
Very low reverse current: IR < 1 nA (typical)
Minimized clamping overshoot due to extremely low parasitic inductance
Small form factor SMD Size 0201 and low profile (0.58 mm x 0.28 mm x 0.15 mm)
Bidirectional and symmetric I/V characteristics for optimized design and assembly
Pb-free (RoHS compliant) and halogen free package
•
•
•
•
•
•
•
•
Guidelines for optimized PCB design and assembly process available [2]
1.2
•
•
•
Application Examples
USB 3.0, Firewire, DVI, HDMI, S-ATA, DisplayPort, Thunderbolt
Mobile HDMI Link, MDDI, MIPI, SWP / NFC
Dedicated solution to boost space saving and high performance in miniaturized modern electronics
1.3
Product Description
a) Pin configuration
b) Schematic diagram
Configutation_Schematic_Diagram.vsd
Figure 1-1 Pin Configuration and Schematic Diagram
Table 1-1
Part Information
Type
Package
Configuration
Marking code
ESD108-B1-CSP0201
WLL-2-1
1 line, bi-directional
C1)
1) The device does not have any marking or date code on the device backside. The Marking code is on pad side.
Final Data Sheet
3
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ESD108-B1-CSP0201
Maximum Ratings
2
Maximum Ratings
Table 2-1
Maximum Ratings at TA = 25 °C, unless otherwise specified 1)
Parameter
Symbol
Reverse working voltage
Values
VRWM
±5.5
VESD
±25
Reverse working current
IRWM
10
Peak pulse power
PPK
ESD (air / contact) discharge
2)
tp = 8 / 20 μs3)
tp = 100 ns2)
Unit
kV
mA
W
27.5
18000
Peak pulse current3)
IPP
±2.5
A
Operating temperature range
TOP
-55 to 125
°C
Storage temperature
Tstg
-65 to 150
°C
1) Device is electrically symmetrical
2) VESD according to IEC61000-4-2 (R = 330 Ω, C = 150 pF discharge network)
3) Stress pulse: 8/20μs current waveform according to IEC61000-4-5
Attention: Stresses above the max. values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the component.
Table 2-2
Thermal Resistance
Parameter
Symbol
Values
Min.
1)
Typ.
Unit
Max.
Junction - soldering point
RthJS
330
1) For calculation of RthJA please refer to Application Note [3] 077 Thermal Resistance Calculation.
Final Data Sheet
4
K/W
Revision 1.4, 2016-04-21
ESD108-B1-CSP0201
Electrical Characteristics at TA = 25 °C, unless otherwise specified
3
Electrical Characteristics at TA = 25 °C, unless otherwise specified
( )!! %! )*
!
+! )#! % ##%# !"!!""!" #$%"&!'!! Figure 3-1 Definitions of electrical characteristics
Table 3-1
DC Characteristics at TA = 25 °C, unless otherwise specified1)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note /
Test Condition
VR = ±5.5 V
Reverse current
IR
–
<1
20
nA
Trigger voltage
Vt1
–
9.5
12.5
V
Holding voltage
Vh
5.5
6.5
9.5
V
IT = 0.5 mA
Unit
Note /
Test Condition
pF
VR = 0 V, f = 1 MHz
1) Device is electrically symmetrical
Table 3-2
AC Characteristics at TA = 25 °C, unless otherwise specified
Parameter
Line capacitance
Final Data Sheet
Symbol
CL
Values
Min.
Typ.
Max.
–
0.28
0.38
–
0.22
0.38
5
VR = 0 V, f = 1 GHz
Revision 1.4, 2016-04-21
ESD108-B1-CSP0201
Electrical Characteristics at TA = 25 °C, unless otherwise specified
Table 3-3
ESD and Surge Characteristics at TA = 25 °C, unless otherwise specified 1)
Parameter
Symbol
2)
Clamping voltage
VCL
3)
Clamping voltage
4)
Clamping voltage
Dynamic resistance
2)
RDYN
Values
Unit
Note / Test Condition
V
ITLP = 16 A, tp = 100 ns
Min.
Typ.
Max.
–
20
27
–
30.5
41
ITLP = 30 A, tp = 100 ns
–
20
–
VESD = 8 kV
–
29
–
VESD = 15 kV
–
8.5
12
IPP = 1 A, tp = 8/20 µs
–
11
18.5
IPP = 2.5 A, tp = 8/20 µs
–
0.78
–
Ω
tp = 100 ns
1) Device is electrically symmetrical
2) Please refer to Application Note AN210[1]. TLP parameter: Z0 = 50 Ω , tp = 100ns, tr = 0.6 ns
3) VESD according to IEC61000-4-2 (contact discharge), VCL at 30 ns (R = 330 Ω, C = 150 pF discharge network)
4) Stress pulse: 8/20μs current waveform according to IEC61000-4-5
Final Data Sheet
6
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ESD108-B1-CSP0201
Typical Characteristics Diagrams
4
Typical Characteristics Diagrams
Typical charateristics diagrams at TA = 25 °C, unless otherwise specified
-6
10
10-7
10-8
IR [A]
10-9
10-10
10-11
10-12
-13
10
0
0.5
1
1.5
2
2.5
3
VR [V]
3.5
4
4.5
5
5.5
Figure 4-1 Reverse leakage current IR = f(VR)
400
350
CL [fF]
300
1 MHz
250
1 GHz
200
150
100
0
0.5
1
1.5
2
2.5
3
VR [V]
3.5
4
4.5
5
5.5
Figure 4-2 Line capacitance CL = f(VR)
Final Data Sheet
7
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ESD108-B1-CSP0201
Typical Characteristics Diagrams
14
12
TA
TS
IRWM [mA]
10
8
6
4
2
0
0
50
100
150
TS, TA [°C]
Figure 4-3 Reverse working current IRWM = f(TS, TA), Device mounted on PCB with Rth = 200 K/W [3]
Final Data Sheet
8
Revision 1.4, 2016-04-21
ESD108-B1-CSP0201
Typical Characteristics Diagrams
175
Scope: 6 GHz, 20 GS/s
150
125
VCL [V]
100
VCL-max-peak = 141 V
75
VCL-30ns-peak = 20 V
50
25
0
-25
-50
0
50
100
150
200
tp [ns]
250
300
350
400
450
Figure 4-4 Clamping voltage (ESD): VCL = f(t), 8 kV positiv pulse
25
Scope: 6 GHz, 20 GS/s
0
-25
VCL [V]
-50
-75
-100
VCL-max-peak = -137 V
-125
VCL-30ns-peak = -16 V
-150
-175
-50
0
50
100
150
200
tp [ns]
250
300
350
400
450
Figure 4-5 Clamping voltage (ESD): VCL = f(t), 8 kV negativ pulse
Final Data Sheet
9
Revision 1.4, 2016-04-21
ESD108-B1-CSP0201
Typical Characteristics Diagrams
175
Scope: 6 GHz, 20 GS/s
150
125
VCL [V]
100
VCL-max-peak = 165 V
75
VCL-30ns-peak = 29 V
50
25
0
-25
-50
0
50
100
150
200
tp [ns]
250
300
350
400
450
Figure 4-6 Clamping voltage (ESD): VCL = f(t), 15 kV positiv pulse
25
Scope: 6 GHz, 20 GS/s
0
-25
VCL [V]
-50
-75
-100
VCL-max-peak = -162 V
-125
VCL-30ns-peak = -27 V
-150
-175
-50
0
50
100
150
200
tp [ns]
250
300
350
400
450
Figure 4-7 Clamping voltage (ESD): VCL = f(t), 15 kV negativ pulse
Final Data Sheet
10
Revision 1.4, 2016-04-21
ESD108-B1-CSP0201
Typical Characteristics Diagrams
60
30
ESD108-B1-CSP0201
RDYN
50
25
40
20
30
15
20
10
10
5
0
0
-10
-5
-20
-10
Equivalent VIEC [kV]
ITLP [A]
RDYN = 0.78 Ω
RDYN = 0.78 Ω
-30
-15
-40
-20
-50
-25
-60
-50
-40
-30
-20
-10
0
10
20
30
40
-30
50
VTLP [V]
Figure 4-8 Clamping voltage (TLP): ITLP = f(VTLP) [1]
Final Data Sheet
11
Revision 1.4, 2016-04-21
ESD108-B1-CSP0201
Typical Characteristics Diagrams
3
2
IPP [A]
1
0
-1
-2
-3
-15
-10
-5
0
VCL [V]
5
10
15
Figure 4-9 Clamping voltage (Surge): IPP = f(VCL) [1]
Final Data Sheet
12
Revision 1.4, 2016-04-21
ESD108-B1-CSP0201
Typical Characteristics Diagrams
0
-1
Insertion Loss [dB]
-2
-3
-4
-5
-6
ESD108-B1-CSP0201
-7
-8
10
100
1000
f [MHz]
10000
Figure 4-10 Insertion loss vs. frequency in a 50 Ω system
Final Data Sheet
13
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ESD108-B1-CSP0201
Package Information
5
Package Information
5.1
WLL-2-1
Top view
Bottom view
0.15 ±0.01
0.28 ±0.03
0.58 ±0.03
1
0.2 ±0.02
0.36
(0.16)
2
0.26 ±0.02
SG-WLL-2-1-PO V01
Figure 5-1 WLL-2-1 Package outline (dimension in mm)
0.19
0.24
Solder mask
0.19
0.57
0.14
0.62
Copper
0.19
0.27
0.24
0.32
Stencil apertures
SG-WLL-2-1-FP V01
Figure 5-2 WLL-2-1 Footprint (dimension in mm) Recommendation for Printed Circuit Board Assembly[2]
8
0.68
0.23
2
0.21
0.35
SG-WLL-2-1-TP V02
Figure 5-3 WLL-2-1 Packing (dimension in mm)
Marking on pad-side
Type code
1
1
1
Type code
1
SG-WLL-2-1-MK V03
Figure 5-4 WLL-2-1 Marking example Table 1-1 “Part Information” on Page 3
Final Data Sheet
14
Revision 1.4, 2016-04-21
ESD108-B1-CSP0201
References
References
[1]
Infineon AG - Application Note AN210: Effective ESD Protection Design at System Level Using VF-TLP
Characterization Methodology
[2]
Infineon AG - Recommendation for Printed Circuit Board Assembly of Infineon WLL Packages
http://www.infineon.com/dgdl/?fileId=db3a304344f7b4f9014503db540027c0 [3]
Infineon AG - Application Note AN077: Thermal Resistance Calculation
[4]
Infineon AG - Application Note AN392: TVS Diodes in ChipScalePackage reduce size and save cost
Final Data Sheet
12
Revision 1.4, 2016-04-21
ESD108-B1-CSP0201
Revision History: Rev. 1.3: 2015-01-19
Page or Item
Subjects (major changes since previous revision)
Revision 1.4, 2016-04-21
All
Layout update
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Last Trademarks Update 2010-10-26
Final Data Sheet
2
Revision 1.4, 2016-04-21
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Published by Infineon Technologies AG
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