Data Sheet

Freescale Semiconductor
Technical Data
Document Number: MM908E625
Rev 10, 04/2012
Integrated Quad Half H-Bridge
with Power Supply, Embedded
MCU, and LIN Serial
Communication
908E625
H-BRIDGE POWER SUPPLY WITH
EMBEDDED MCU AND LIN
The 908E625 is an integrated single package solution including a
high performance HC08 microcontroller with a SMARTMOS analog
control IC. The HC08 includes flash memory, a timer, enhanced serial
communications interface (ESCI), an analog-to-digital converter
(ADC), internal serial peripheral interface (SPI), and an internal clock
generator (ICG) module. The analog control die provides fully
protected H-Bridge/high side outputs, voltage regulator, autonomous
watchdog with cyclic wake-up, and local interconnect network (LIN)
physical layer.
The single package solution, together with LIN, provides optimal
application performance adjustments and space saving PCB design.
It is well-suited for the control of automotive mirror, door lock, and
light-leveling applications.
EK SUFFIX
98ARL10519D
54-PIN SOICW-EP
Features
•
•
•
•
•
•
•
•
•
•
•
•
High-performance M68HC908EY16 core
16 KB of on-chip flash memory & 512 B of RAM
Internal clock generation module
Two 16-bit, two-channel timers
10-bit ADC
LIN physical layer
Autonomous watchdog with cyclic wake-up
Three two-pin Hall effect sensor input ports
One analog input with switchable current source
Four low RDS(ON) half-bridge outputs
One low RDS(ON) high side output
13 micro controller I/Os
ORDERING INFORMATION
Device
(Add an R2 suffix for Tape
and reel orders)
Temperature
Range (TA
)
Package
MM908E625ACPEK
-40 to 85 °C
54 SOICW
EP
908E625
VSP1:3]
LIN
HB1
VREFH
VDDA
EVDD
HB2
VDD
HB3
VREFL
HB4
VSSA
HS
EVSS
VSS
HVDD
RST A
RST
H1
IRQ A
H2
IRQ
SS
H3
PTB1/AD1
RXD
PTE1/RXD
PA1
PTD1/TACH1
PORTA I/Os
FGEN
PORTB I/Os
BEMF
PORTC I/Os
PTD0/TACH0/BEMF
GND[1:2]
EP
M
M
M
Four Half-bridges
Controlling 3 Loads
High Side Output
Switchable Internal VDD Output
Three 2-pin Hall-effect Sensor Inputs
Analog Input with Current Source
Microcontroller Ports
Figure 1. 908E625 Simplified Application Diagram
* This document contains information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2012. All rights reserved.
FLSVPP
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
PTB7/AD7/TBCH1
PTB6/AD6/TBCH0
PTB5/AD5
PTB4/AD4
PTB3/AD3
PTA4/KBD4
VDD
VSS
PTA6/SS
PTA5/SPSCK
PTA4/KBD4
PTA3/KBD3
PTA2/KBD2
PTA1/KBD1
PTA0/KBD0
PTE0/TxD
PTE1/RxD
PTD0/TACH0
PTD1/TACH1
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
PTC1/MOSI
PTC0/MISO
BEMF Module
Prescaler Module
Power-On Reset
Module
Security Module
Arbiter Module
Periodic Wake-Up
Timebase Module
Configuration Register
Module
Serial Pheripheral
Interface Module
Computer Operating
Properly Module
Enhanced Serial
Communication
Interface Module
2-channel Timer
Interface Module B
2-Channel Timer
Interface Module A
5-Bit Keyboard
Interrupt Module
Single Breakpoint
Break Module
POWER
10 Bit Analog-toDigital Converter
Module
Single External IRQ
Module
24 Internal System
Integration Module
Internal Clock
Generator Module
PTB7/AD7/TBCH1
PTB6/AD6/TBCH0
PTB5/AD5
PTB4/AD4
PTB3/AD3
PTB2/AD2
PTB1/AD1
PTB0/AD0
VREFH
VDDA
VREFL
VSSA
IRQ
RST
OSC2
OSC1
User Flash Vector Space,
36 Bytes
Flash Programming (burn in)
ROM, 1024 Bytes
Monitor ROM, 310 Bytes
User RAM, 512 Bytes
User Flash, 15,872 Bytes
PORT A
PORT B
2
PTA3/KBD3
VDDA
PTA2/KBD2
EVDD
PTA1/KBD1
VSSA
Control and Status Register,
64 Bytes
IRQ
DDRA
PTA0/KBD0
EVSS
ALU
VREFL
M68HC08 CPU
RST
Internal Bus
PTB1/AD1
DDRB
PTD0/TACH0
DDRC
PTE1/RXD
PTD1/TACH1
MCU Die
PTB0/AD0
PTA5/SPSCK
PTC1/MOSI
PTC0/MISO
PTE0/TXD
ADOUT
SPSCK
MOSI
MISO
SS
TXD
SS
PORT C
RXD
Analog Die
Analog
Multiplexer
VSUP
Prescaler
Chip Temp
Autonomous
Watchdog
SPI
&
CONTROL
Interrupt
Control
Module
Reset Control
Module
LIN Physical
Layer
LIN
DDRD
FGEN
PORT D
BEMF
FGEN
BEMF
FGEN
BEMF
FGEN
BEMF
FGEN
FGEN
RST_A
DDRE
Analog Input
with Current
Source
Hall-Effect
Sensor Inputs
Half Bridge
Driver &
Diagnostic
Half Bridge
Driver &
Diagnostic
Half Bridge
Driver &
Diagnostic
Half Bridge
Driver &
Diagnostic
High Side
Driver &
Diagnostic
Switched VDD
Driver &
Diagnostic
Voltage
Regulator
VSUP1-3
PORT E
GND1-2
CPU
Registers
VSUP
VSUP
VSUP
VSUP
VSUP
PA1
H3
H2
H1
HB4
HB3
HB2
HB1
HS
HVDD
VDD
VSS
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
IRQ_A
BEMF
VREFH
Figure 2. 908E625 Simplified Internal Block Diagram
908E625
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
PTB7/AD7/TBCH1
PTB6/AD6/TBCH0
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
PTB5/AD5
PTB4/AD4
PTB3/AD3
1
54
2
53
3
52
4
51
5
50
6
49
7
48
8
47
IRQ
RST
9
46
10
45
PTB1/AD1
PTD0/TACH0/BEMF
PTD1/TACH1
NC
FGEN
BEMF
11
44
12
43
16
39
RST_A
17
38
IRQ_A
SS
18
37
19
36
LIN
NC
NC
HB1
VSUP1
GND1
HB2
VSUP2
20
35
21
34
22
33
23
32
24
31
25
30
26
29
27
28
13
14
15
42
Exposed
Pad
41
40
PTA0/KBD0
PTA1/KBD1
PTA2/KBD2
FLSVPP
PTA3/KBD3
PTA4/KBD4
VREFH
VDDA
EVDD
EVSS
VSSA
VREFL
PTE1/RXD
RXD
VSS
PA1
VDD
H1
H2
H3
HVDD
NC
HB4
VSUP3
GND2
HB3
HS
Figure 3. 908E625 Pin Connections (Transparent Package Top View)
Table 1. 908E625 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 14.
Pin Function
Pin
Pin Name
Formal Name
Definition
MCU
1
2
6
7
8
11
PTB7/AD7/TBCH1
PTB6/AD6/TBCH0
PTB5/AD5
PTB4/AD4
PTB3/AD3
PTB1/AD1
Port B I/Os
These pins are special function, bi-directional I/O port pins that
are shared with other functional modules in the MCU.
MCU
3
4
5
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
Port C I/Os
These pins are special function, bi-directional I/O port pins that
are shared with other functional modules in the MCU.
MCU
9
IRQ
MCU
10
RST
External Reset
This pin is bi-directional, allowing a reset of the entire system.
It is driven low when any internal reset source is asserted.
MCU
12
13
PTD0/TACH0/BEMF
PTD1/TACH1
Port D I/Os
These pins are special function, bi-directional I/O port pins that
are shared with other functional modules in the MCU.
–
14, 21, 22, 33
NC
No Connect
Not connected.
External Interrupt Input This pin is an asynchronous external interrupt input pin.
908E625
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
Table 1. 908E625 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on page 14.
Pin Function
Pin
Pin Name
Formal Name
Definition
MCU
42
PTE1/RXD
Port E I/O
This pin is a special function, bi-directional I/O port pin that can
is shared with other functional modules in the MCU.
MCU
43
48
VREFL
VREFH
ADC References
These pins are the reference voltage pins for the analog-todigital converter (ADC).
MCU
44
47
VSSA
VDDA
ADC Supply pins
These pins are the power supply pins for the analog-to-digital
converter.
MCU
45
46
EVSS
EVDD
MCU Power Supply
Pins
These pins are the ground and power supply pins, respectively.
The MCU operates from a single power supply.
MCU
49
50
52
53
54
PTA4/KBD4
PTA3/KBD3
PTA2/KBD2
PTA1/KBD1
PTA0/KBD0
Port A I/Os
These pins are special function, bi-directional I/O port pins that
are shared with other functional modules in the MCU.
MCU
51
FLSVPP
Test Pin
Analog
15
FGEN
Current Limitation
Frequency Input
Analog
16
BEMF
Analog
17
RST_A
Internal Reset
Analog
18
IRQ_A
Internal Interrupt
Output
Analog
19
SS
Slave Select
For test purposes only. Do not connect in the application.
This is the input pin for the half-bridge current limitation and the
high side inrush current limiter PWM frequency.
Back Electromagnetic This pin gives the user information about back electromagnetic
Force Output
force (BEMF).
This pin is the bi-directional reset pin of the analog die.
This pin is the interrupt output pin of the analog die indicating
errors or wake-up events.
This pin is the SPI slave select pin for the analog chip.
Analog
20
LIN
LIN Bus
This pin represents the single wire bus transmitter and receiver.
Analog
23
26
29
32
HB1
HB2
HB3
HB4
Half-bridge Outputs
This device includes power MOSFETs configured as four halfbridge driver outputs. These outputs may be configured for step
motor drivers, DC motor drivers, or as high side and low side
switches.
Analog
24
27
31
VSUP1
VSUP2
VSUP3
Power Supply Pins
These pins are device power supply pins.
Analog
25
30
GND1
GND2
Power Ground Pins
These pins are device power ground connections.
Analog
28
HS
High-Side Output
This output pin is a low RDS(ON) high side switch.
Analog
34
HVDD
Analog
35
36
37
H3
H2
H1
Hall-effect Sensor
Inputs
These pins provide inputs for Hall-effect sensors and switches.
Analog
38
VDD
Voltage Regulator
Output
The +5.0 V voltage regulator output pin is intended to supply
the embedded microcontroller.
Analog
39
PA1
Analog Input
This pin is an analog input port with selectable source values.
Analog
40
VSS
Voltage Regulator
Ground
Analog
41
RXD
–
EP
Exposed Pad
Switchable VDD Output This pin is a switchable VDD output for driving resistive loads
requiring a regulated 5.0 V supply; e.g., 3-pin Hall-effect
sensors.
Ground pin for the connection of all non-power ground
connections (microcontroller and sensors).
LIN Transceiver Output This pin is the output of LIN transceiver.
Exposed Pad
The exposed pad pin on the bottom side of the package
conducts heat from the chip to the PCB board.
908E625
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
Analog Chip Supply Voltage under Normal Operation, Steady State
VSUP(SS)
-0.3 to 28
Analog Chip Supply Voltage under Transient Conditions (1)
VSUP(PK)
-0.3 to 40
VDD
-0.3 to 6.0
VIN (ANALOG)
-0.3 to 5.5
VIN (MCU)
VSS -0.3 to VDD +0.3
All Pins Except VDD, VSS, PTA0:PTA6, PTC0:PTC1
IPIN(1)
±15
Pins PTA0:PTA6, PTC0:PTC1
IPIN(2)
±25
Maximum Microcontroller VSS Output Current
IMVSS
100
mA
Maximum Microcontroller VDD Input Current
IMVDD
100
mA
ELECTRICAL RATINGS
V
Supply Voltage
Microcontroller Chip Supply Voltage
Input Pin Voltage
V
Analog Chip
Microcontroller Chip
mA
Maximum Microcontroller Current per Pin
LIN Supply Voltage
V
Normal Operation (Steady-State)
Transient Conditions (1)
VBUS(SS)
-18 to 28
VBUS(DYNAMIC)
40
VESD
±3000
V
ESD Voltage
(2)
Human Body Model (HBM)
±150
Machine Model (MM)(3)
±500
Charge Device Model (CDM)(4)
THERMAL RATINGS
TSTG
-40 to 150
°C
Ambient Operating Temperature
TA
-40 to 85
°C
Operating Case Temperature (5)
TC
-40 to 85
°C
Operating Junction Temperature(6)
TJ
-40 to 125
°C
TPPRT
Note 8
°C
Storage Temperature
Peak Package Reflow Temperature During Reflow(7)(8)
Notes
1. Transient capability for pulses with a time of t < 0.5 sec.
2. ESD voltage testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω)
3.
ESD voltage testing is performed in accordance with the Machine Model (CZAP =200 pF, RZAP = 0 Ω)
4.
ESD voltage testing is performed in accordance with Charge Device Model, robotic (CZAP =4.0 pF).
5.
6.
The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking.
The temperature of analog and MCU die is strongly linked via the package, but can differ in dynamic load conditions, usually because
of higher power dissipation on the analog die. The analog die temperature must not exceed 150 °C under these conditions.
Pin soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause
malfunction or permanent damage to the device.
Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
7.
8.
908E625
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
All characteristics are for the analog chip only. Refer to the 68HC908EY16 specification for characteristics of the
microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40 °C ≤ TJ ≤ 125 °C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
VSUP
8.0
–
18
V
SUPPLY VOLTAGE
Nominal Operating Voltage
SUPPLY CURRENT
Normal Mode
IRUN
VSUP = 12 V, Power Die ON (PSON=1), MCU Operating Using
Internal Oscillator at 32 MHz (8.0 MHz Bus Frequency), SPI, ESCI,
ADC Enabled
STOP Mode (9)
VSUP = 12 V, Cyclic Wake-up Disabled
mA
–
20
–
μA
ISTOP
–
–
60
DIGITAL INTERFACE RATINGS (ANALOG DIE)
Output Pins RST_A, IRQ_A
Low State Output Voltage (IOUT = -1.5 mA)
VOL
–
–
0.4
High State Output Voltage (IOUT = 1.0 μA)
VOH
3.85
–
–
VOL
–
–
0.4
VOH
3.85
–
–
CIN
–
4.0
–
pF
V
V
Output Pins BEMF, RXD
Low State Output Voltage (IOUT = -1.5 mA)
High State Output Voltage (IOUT = 1.5 mA)
Output Pin RXD–Capacitance (10)
V
Input Pins RST_A, FGEN, SS
Input Logic Low Voltage
VIL
–
–
1.5
Input Logic High Voltage
VIH
3.5
–
–
CIN
–
4.0
–
pF
Pins RST_A, IRQ_A –Pull-up Resistor
RPULLUP1
–
10
–
kΩ
Pin SS –Pull-up Resistor
RPULLUP2
–
60
–
kΩ
RPULLDOWN
–
60
–
kΩ
IPULLUP
–
35
–
μA
Input Pins RST_A, FGEN, SS –Capacitance (10)
Pins FGEN, MOSI, SPSCK–Pull-down Resistor
Pin TXD–Pull-up Current Source
Notes
9. STOP mode current will increase if VSUP exceeds 15 V.
10.
This parameter is guaranteed by process monitoring but is not production tested.
908E625
6
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
All characteristics are for the analog chip only. Refer to the 68HC908EY16 specification for characteristics of the
microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40 °C ≤ TJ ≤ 125 °C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Threshold
VHVRON
27
30
33
Hysteresis
VHVRH
–
1.5
–
VLVRON
3.6
4.0
4.5
V
VLVRH
–
100
–
mV
Threshold
VHVION
17.5
21
23
Hysteresis
VHVIH
–
1.0
–
SYSTEM RESETS AND INTERRUPTS
High Voltage Reset
V
Low Voltage Reset
Threshold
Hysteresis
High Voltage Interrupt
V
Low Voltage Interrupt
V
Threshold
VLVION
6.5
–
8.0
Hysteresis
VLVIH
–
0.4
–
Threshold
TRON
–
170
–
Hysteresis
TRH
5.0
–
–
Threshold
TION
–
160
–
Hysteresis
TIH
5.0
–
–
4.75
5.0
5.25
°C
High Temperature Reset (11)
°C
High Temperature Interrupt (12)
VOLTAGE REGULATOR
Normal Mode Output Voltage
VDDRUN
IOUT = 60 mA, 6.0 V < VSUP < 18 V
Load Regulation
VLR
IOUT = 80 mA, VSUP = 9.0 V, TJ = 125°C
Stop Mode Output Voltage (Maximum Output Current 100 μA)
V
VDDSTOP
mV
–
–
100
4.45
4.7
5.0
–
–
1.4
VSUP -1.0
–
–
20
30
60
0.0
–
20
V
LIN PHYSICAL LAYER
Output Low Level
VLIN-LOW
TXD LOW, 500 Ω Pull-up to VSUP
Output High Level
VLIN-HIGH
TXD HIGH, IOUT = 1.0 μA
Pullup Resistor to VSUP
Leakage Current to GND
V
RSLAVE
V
μA
IBUS_PAS_rec
Recessive State (-0.5 V < VLIN < VSUP)
kΩ
μA
Leakage Current to GND (VSUP Disconnected)
Including Internal Pull-up Resistor, VLIN @ -18 V
IBUS_NO_GND
–
-600
–
Including Internal Pull-up Resistor, VLIN @ +18 V
IBUS
–
25
–
Notes
11. This parameter is guaranteed by process monitoring but is not production tested.
12. High Temperature Interrupt (HTI) threshold is linked to High Temperature Reset (HTR) threshold (HTR = HTI + 10°C).
908E625
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
All characteristics are for the analog chip only. Refer to the 68HC908EY16 specification for characteristics of the
microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40 °C ≤ TJ ≤ 125 °C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Recessive
VIH
0.6 VLIN
–
VSUP
Dominant
VIL
0.0
–
0.4 VLIN
Threshold
VITH
–
VSUP /2
–
VIHY
0.01 VSUP
–
0.1 VSUP
VWTH
–
VSUP /2
–
V
RDS(ON)HS
–
600
700
mΩ
IHSOC
3.9
–
7.0
A
High Side
RDS(ON)HB_HS
–
425
500
Low Side
RDS(ON)HB_LS
–
400
500
High Side Over-current Shutdown
IHBHSOC
4.0
–
7.5
A
Low Side Over-current Shutdown
IHBLSOC
2.8
–
7.5
A
ICL1
–
55
–
Current Limit 2 (CLS2 = 1, CLS1 = 0, CLS0 = 0)
ICL2
210
260
315
Current Limit 3 (CLS2 = 1, CLS1 = 0, CLS0 = 1)
ICL3
300
370
440
Current Limit 4 (CLS2 = 1, CLS1 = 1, CLS0 = 0)
ICL4
450
550
650
Current Limit 5 (CLS2 = 1, CLS1 = 1, CLS0 = 1)
ICL5
600
740
880
Half-bridge Output High Threshold for BEMF Detection
VBEMFH
–
-30
0
V
Half-bridge Output Low Threshold for BEMF Detection
VBEMFL
–
-60
-5.0
mV
VBEMFHY
–
30
–
mV
LIN Receiver
Input Hysteresis
LIN Wake-up Threshold
Unit
V
HIGH SIDE OUTPUT (HS)
Switch ON Resistance @ TJ = 25 °C with ILOAD = 1.0 A
High Side Over-current Shutdown
HALF-BRIDGE OUTPUTS (HB1:HB4)
Switch ON Resistance @ TJ = 25 °C with ILOAD = 1.0 A
Low Side Current Limitation @ TJ = 25°C
Current Limit 1 (CLS2 = 0, CLS1 = 1, CLS0 = 1)
Hysteresis for BEMF Detection
mΩ
mA
Low Side Current-to-Voltage Ratio (VADOUT [V]/IHB [A])
V/A
CSA = 1
RATIOH
7.0
12.0
14.0
CSA = 0
RATIOL
1.0
2.0
3.0
IHVDDOCT
24
30
40
mA
RATIOVSUP
4.8
5.1
5.35
–
STTOV
–
19
–
mV/°C
VT25
1.7
2.1
2.5
V
VSUP < 16.2 V
VHALL1
–
VSUP - 1.2
–
VSUP > 16.2 V
VHALL2
–
–
15
SWITCHABLE VDD OUTPUT (PH.D.)
Over-current Shutdown Threshold
VSUP DOWN-SCALER
Voltage Ratio (RATIOVSUP = VSUP /VADOUT)
INTERNAL DIE TEMPERATURE SENSOR
Voltage/Temperature Slope
Output Voltage @ 25 °C
HALL-EFFECT SENSOR INPUTS (H1:H3)
Output Voltage
V
908E625
8
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
All characteristics are for the analog chip only. Refer to the 68HC908EY16 specification for characteristics of the
microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40 °C ≤ TJ ≤ 125 °C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Threshold
IHSCT
6.9
8.8
11
Hysteresis
IHSCH
–
0.88
–
IHL
–
90
–
mA
Over-current Warning HP_OCF Flag Threshold]
VHPOCT
–
3.0
–
V
Dropout Voltage @ ILOAD = 15 mA
VHPDO
–
0.5
–
V
ICSPA1
570
670
770
CSSEL1 = 0, CSSEL0 = 0
NCSPA1-0
8.5
10
11.5
CSSEL1 = 0, CSSEL0 = 1
NCSPA1-1
28.5
30
31.5
CSSEL1 = 1, CSSEL0 = 0
NCSPA1-2
58.5
60
61.5
Sense Current
Output Current Limitation
Unit
mA
ANALOG INPUT (PA1)
μA
Current Source PA1
CSSEL1 = 1, CSSEL0 = 1
Selectable Scaling Factor Current Source PA1 (I(N) = ICSPA1* N)
%
908E625
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
All characteristics are for the analog chip only. Please refer to the specification for 68HC908EY16 for characteristics of the
microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40 °C ≤ TJ ≤ 125 °C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
LIN PHYSICAL LAYER
Propagation Delay (13), (14)
μs
t TXD-LIN-low
–
–
–
–
-2.0
-2.0
–
–
4.0
4.0
–
–
6.0
6.0
8.0
8.0
2.0
2.0
-1.0
-2.0
-3.0
1.0
2.0
3.0
SRS
-2.0
–
2.0
μs
t HPPD
–
1.0
–
μs
t OSC
–
40
–
μs
TJ < 25 °C
16
27
34
TJ ≥ 25 °C
16
22
28
TJ < 25 °C
8.0
13.5
17
TJ ≥ 25 °C
8.0
11
14
–
90
–
TXD Low to LIN Low
TXD High to LIN High
t TXD-LIN-high
LIN Low to RXD Low
t LIN-RXD-low
LIN High to RXD High
t LIN-RXD-
TXD Symmetry
RXD Symmetry
Output Falling Edge Slew Rate (13), (15)
high
t TXD-SYM
t RXD-SYM
SRF
80% to 20%
Output Rising Edge Slew Rate (13), (15)
V/μs
SRR
V/μs
20% to 80%, RBUS > 1.0 kΩ, CBUS < 10 nF
LIN Rise/Fall Slew Rate Symmetry (13), (15)
HALL-EFFECT SENSOR INPUTS (H1:H3)
Propagation Delay
AUTONOMOUS WATCHDOG (AWD)
AWD Oscillator Period
AWD Period Low = 512 t OSC
AWD Period High = 256 t OSC
AWD Cyclic Wake-up On Time
t AWDPH
ms
t AWDPL
t AWDHPON
ms
μs
Notes
13. All LIN characteristics are for initial LIN slew rate selection (20 kBaud) (SRS0:SRS1= 00).
14. See Figure 2.
15. See Figure 3.
908E625
10
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MICROCONTROLLER PARAMETRICS
MICROCONTROLLER PARAMETRICS
Table 5. Microcontroller Description
For a detailed microcontroller description, refer to the MC68HC908EY16 data sheet.
Module
Description
Core
High Performance HC08 Core with a Maximum Internal Bus Frequency of 8.0 MHz
Timer
Two 16-Bit Timers with Two Channels (TIM A and TIM B)
Flash
16 K Bytes
RAM
512 Bytes
ADC
10-Bit Analog-to-Digital Converter
SPI
SPI Module
ESCI
Standard Serial Communication Interface (SCI) Module
Bit-Time Measurement
Arbitration
Prescaler with Fine Baud Rate Adjustment
ICG
Internal Clock Generation Module (25% Accuracy with Trim Capability to 2%)
BEMF Counter
Special Counter for SMARTMOS™ BEMF Output
TIMING DIAGRAMS
t TXD-LIN-low
t
t TXD-LIN-high
tTx-LIN-high
Tx-LIN-low
TXD
Tx
TXD
LIN
LIN
Recessive State
0.9 VSUP
VSUP
0.9
Recessive State
0.7
VLIN
0.6 VSUP
0.4 VSUP
0.3
VLIN
0.1
SUP
0.1 V
VSUP
Dominant State
Rx
RXD
t LIN-RXD-low
t
LIN-Rx-low
ttLIN-RXD-high
LIN-Rx-high
Figure 4. LIN Timing Description
908E625
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
Δt Fall-time
Δt Rise-time
0.8
VSUP
0.8 VSUP
0.8 VSUP
VSUP
ΔV Fall
ΔV Rise
0.2 VSUP
VSUP
0.2
0.2VSUP
VSUP
0.2
Dominant State
SRF =
ΔV Fall
Δt Fall-time
SRR =
ΔV Rise
Δt Rise-time
Figure 5. LIN Slew Rate Description
ELECTRICAL PERFORMANCE CURVES
1.6
Forward Voltage (V)
1.4
1.2
TJ = 25°C
1.0
0.8
0.6
0.4
0.2
0.0
0.0
0.5
1.0
1.5
2.0
2.5
ILOAD (A)
3.0
3.5
4.0
4.5
5.0
H-Bridge Low Side
Figure 6. Free Wheel Diode Forward Voltage vs. ILOAD
908E625
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
250
Drop Out Voltage (mV)
200
TA = 125°C
150
100
TA = 25°C
50
TA = -40°C
0
0
5
10
15
20
25
ILoad (mA)
Figure 7. Dropout Voltage on HVDD vs. ILOAD
908E625
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 908E625 device was designed and developed as a
highly integrated and cost effective solution for automotive
and industrial applications. For automotive body electronics,
the 908E625 is well suited to perform complete mirror, door
lock, and light-levelling control all via a three-wire LIN bus.
This device combines an standard HC08 MCU core
(68HC908EY16) with flash memory together with a
SMARTMOS IC chip. The SMARTMO™ IC chip combines
power and control in one chip. Power switches are provided
on the SMARTMOS IC configured as half-bridge outputs with
one high side switch. Other ports are also provided; they
include Hall-effect sensor input ports, analog input ports, and
a selectable HVDD pin. An internal voltage regulator is
provided on the SMARTMOS IC chip, which provides power
to the MCU chip.
Also included in this device is a LIN physical layer, which
communicates using a single wire. This enables the device to
be compatible with three-wire bus systems, where one wire is
used for communication, one for battery, and the third for
ground.
FUNCTIONAL PIN DESCRIPTION
See Figure 1 for a graphic representation of the various
pins referred to in the following paragraphs. Also, see the pin
diagram on Figure 3 for a depiction of the pin locations on the
package.
PORT A I/O PINS (PTA0:4)
These pins are special-function, bidirectional I/O port pins
that are shared with other functional modules in the MCU.
PTA0:PTA4 are shared with the keyboard interrupt pins,
KBD0:KBD4.
The PTA5/SPSCK pin is not accessible in this device and
is internally connected to the SPI clock pin of the analog die.
The PTA6/SS pin is likewise not accessible.
For details refer to the 68HC908EY16 datasheet.
PORT B I/O PINS (PTB1, PTB3:7)
These pins are special function, bi-directional I/O port pins
that are shared with other functional modules in the MCU. All
pins are shared with the ADC module. The PTB6:PTB7 pins
are also shared with the Timer B module.
PTB0/AD0 is internally connected to the ADOUT pin of the
analog die, allowing diagnostic measurements to be
calculated; e.g., current recopy, VSUP, etc. The PTB2/AD2
pin is not accessible in this device.
For details refer to the 68HC908EY16 datasheet.
PORT D I/O PINS (PTD0:1)
PTD1/TACH1 and PTD0/TACH0/BEMF are special
function, bi-directional I/O port pins that can also be
programmed to be timer pins.
In step motor applications, the PTD0 pin should be
connected to the BEMF output of the analog die, to evaluate
the BEMF signal with a special BEMF module of the MCU.
PTD1 pin is recommended for use as an output pin for
generating the FGEN signal (PWM signal), if required by the
application.
PORT E I/O PIN (PTE1)
PTE1/RXD and PTE0/TXD are special function, bidirectional I/O port pins that can also be programmed to be
enhanced serial communication.
PTE0/TXD is internally connected to the TXD pin of the
analog die. The connection for the receiver must be done
externally.
EXTERNAL INTERRUPT PIN (IRQ)
The IRQ pin is an asynchronous external interrupt pin. This
pin contains an internal pull-up resistor that is always
activated, even when the IRQ pin is pulled LOW.
For details refer to the 68HC908EY16 datasheet.
PORT C I/O PINS (PTC2:4)
EXTERNAL RESET PIN (RST)
These pins are special function, bi-directional I/O port pins
that are shared with other functional modules in the MCU. For
example, PTC2:PTC4 are shared with the ICG module.
PTC0/MISO and PTC1/MOSI are not accessible in this
device and are internally connected to the MISO and MOSI
SPI pins of the analog die.
For details refer to the 68HC908EY16 datasheet.
A Logic [0] on the RST pin forces the MCU to a known
startup state. RST is bi-directional, allowing a reset of the
entire system. It is driven LOW when any internal reset
source is asserted.
This pin contains an internal pull-up resistor that is always
activated, even when the reset pin is pulled LOW.
CURRENT LIMITATION FREQUENCY INPUT PIN
(FGEN)
Input pin for the half-bridge current limitation and the high
side inrush current limiter PWM frequency. This input is not a
For details refer to the 68HC908EY16 datasheet.
908E625
14
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
real PWM input pin; it should just supply the period of the
PWM. The duty cycle will be generate automatically.
Important The recommended FGEN frequency should
be in the range of 0.1 kHz to 20 kHz.
BACK ELECTROMAGNETIC FORCE OUTPUT PIN
(BEMF)
This pin gives the user information about back
electromagnetic force (BEMF). This feature is mainly used in
step motor applications for detecting a stalled motor. In order
to evaluate this signal the pin must be directly connected to
pin PTD0/TACH0/BEMF.
RESET PIN (RST_A)
RST_A is the bi-directional reset pin of the analog die. It is
an open drain with pull-up resistor and must be connected to
the RST pin of the MCU.
INTERRUPT PIN (IRQ_A)
IRQ_A is the interrupt output pin of the analog die
indicating errors or wake-up events. It is an open drain with
pull-up resistor and must be connected to the IRQ pin of the
MCU.
POWER GROUND PINS (GND1 AND GND2)
GND1 and GND2 are device power ground connections.
Owing to the low ON-resistance and current requirements of
the half-bridge driver outputs and high side output driver,
multiple pins are provided.
GND1 and GND2 pins must be connected to get full chip
functionality.
HIGH SIDE OUTPUT PIN (HS)
The HS output pin is a low RDS(ON) high side switch. The
switch is protected against over-temperature and overcurrent. The output is capable of limiting the inrush current
with an automatic PWM generation using the FGEN module.
SWITCHABLE VDD OUTPUT PIN (HVDD)
The HVDD pin is a switchable VDD output for driving
resistive loads requiring a regulated 5.0 V supply; e.g., 3-pin
Hall-effect sensors. The output is short-circuit protected.
HALL-EFFECT SENSOR INPUT PINS (H1:H3)
The Hall-effect sensor input pins H1:H3 provide inputs for
Hall-effect sensors and switches.
+5.0 V VOLTAGE REGULATOR OUTPUT PIN (VDD)
SLAVE SELECT PIN (SS)
This pin is the SPI Slave Select pin for the analog chip. All
other SPI connections are done internally. SS must be
connected to PTB1 or any other logic I/O of the
microcontroller.
The VDD pin is needed to place an external capacitor to
stabilize the regulated output voltage. The VDD pin is
intended to supply the embedded microcontroller.
Important The VDD pin should not be used to supply
other loads; use the HVDD pin for this purpose. The VDD,
EVDD, VDDA, and VREFH pins must be connected together.
LIN BUS PIN (LIN)
The LIN pin represents the single-wire bus transmitter and
receiver. It is suited for automotive bus systems and is based
on the LIN bus specification.
ANALOG INPUT PIN (PA1)
HALF-BRIDGE OUTPUT PINS (HB1:HB4)
VOLTAGE REGULATOR GROUND PIN (VSS)
The 908E625 device includes power MOSFETs
configured as four half-bridge driver outputs. The HB1:HB4
outputs may be configured for step motor drivers, DC motor
drivers, or as high side and low-side switches.
The HB1:HB4 outputs are short-circuit and overtemperature protected, and they feature current recopy,
current limitation, and BEMF generation. Current limitation
and recopy are done on the low side MOSFETs.
The VSS pin is the ground pin for the connection of all nonpower ground connections (microcontroller and sensors).
Important VSS, EVSS, VSSA, and VREFL pins must be
connected together.
POWER SUPPLY PINS (VSUP1:VSUP3)
VSUP1:VSUP3 are device power supply pins. The
nominal input voltage is designed for operation from 12 V
systems. Owing to the low ON-resistance and current
requirements of the half-bridge driver outputs and high side
output driver, multiple VSUP pins are provided.
All VSUP pins must be connected to get full chip
functionality.
This pin is an analog input port with selectable current
source values.
LIN TRANSCEIVER OUTPUT PIN (RXD)
This pin is the output of LIN transceiver. The pin must be
connected to the microcontroller’s Enhanced Serial
Communications Interface (ESCI) module (RXD pin).
ADC REFERENCE PINS (VREFL AND VREFH)
VREFL and VREFH are the reference voltage pins for the
ADC. It is recommended that a high quality ceramic
decoupling capacitor be placed between these pins.
Important VREFH is the high reference supply for the
ADC and should be tied to the same potential as VDDA via
separate traces. VREFL is the low reference supply for the
908E625
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
ADC and should be tied to the same potential as VSS via
separate traces.
For details refer to the 68HC908EY16 datasheet.
ADC SUPPLY PINS (VDDA AND VSSA)
VDDA and VSSA are the power supply pins for the analogto-digital converter (ADC). It is recommended that a high
quality ceramic decoupling capacitor be placed between
these pins.
Important VDDA is the supply for the ADC and should be
tied to the same potential as EVDD via separate traces.
VSSA is the ground pin for the ADC and should be tied to the
same potential as EVSS via separate traces.
For details refer to the 68HC908EY16 datasheet.
MCU POWER SUPPLY PINS (EVDD AND EVSS)
Fast signal transitions on MCU pins place high, short
duration current demands on the power supply. To prevent
noise problems, take special care to provide power supply
bypassing at the MCU.
For details refer to the 68HC908EY16 datasheet.
TEST PIN (FLSVPP)
This pin is for test purposes only. This pin should be either
left open (not connected) or connected to GND.
EXPOSED PAD PIN
The exposed pad pin on the bottom side of the package
conducts heat from the chip to the PCB board. For thermal
performance the pad must be soldered to the PCB board. It
is recommended that the pad be connected to the ground
potential.
EVDD and EVSS are the power supply and ground pins.
The MCU operates from a single power supply.
908E625
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
INTERRUPTS
AUTONOMOUS WATCHDOG INTERRUPT (AWD)
The 908E625 has seven different interrupt sources as
described in the following paragraphs. The interrupts can be
disabled or enabled via the SPI. After reset all interrupts are
automatically disabled.
Refer to Autonomous Watchdog Autonomous Watchdog
(AWD) on page 36.
LOW VOLTAGE INTERRUPT
The low voltage interrupt (LVI) is related to the external
supply voltage, VSUP. If this voltage falls below the LVI
threshold, it will set the LVI flag. If the low voltage interrupt is
enabled, an interrupt will be initiated.
With LVI the H-Bridges (high side MOSFET only) and the
high side driver are switched off. All other modules are not
influenced by this interrupt.
During STOP mode the LVI circuitry is disabled.
LIN INTERRUPT
If the LINIE bit is set, a falling edge on the LIN pin will
generate an interrupt. During STOP mode this interrupt will
initiate a system wake-up.
HALL-EFFECT SENSOR INPUT PIN INTERRUPT
If the PHIE bit is set, the enabled Hall-effect sensor input
pins H1:H3 can generate an interrupt if a current above the
threshold is detected. During Stop mode this interrupt,
combined with the cyclic wake-up feature of the AWD, can
wake up the system. Refer to pin Hall-Effect Sensor Input
Pins (H1:H3).
HIGH VOLTAGE INTERRUPT
The high voltage interrupt (HVI) is related to the external
supply voltage, VSUP. If this voltage rises above the HVI
threshold, it will set the HVI flag. If the high voltage interrupt
is enabled, an interrupt will be initiated.
With HVI the H-Bridges (high side MOSFET only) and the
high side driver are switched off. All other modules are not
influenced by this interrupt.
During STOP mode the HVI circuitry is disabled.
HIGH TEMPERATURE INTERRUPT
The high temperature interrupt (HTI) is generated by the
on-chip temperature sensors. If the chip temperature is
above the HTI threshold, the HTI flag will be set. If the high
temperature interrupt is enabled, an interrupt will be initiated.
During STOP mode the HTI circuitry is disabled.
OVER-CURRENT INTERRUPT
If an over-current condition on a half-bridge occurs, the
high side or the HVDD output is detected and the OCIE bit is
set and an interrupt generated.
SYSTEM WAKE-UP
System wake-up can be initiated by any of four events:
• A falling edge on the LIN pin
• A wake-up signal from the AWD
• A Logic [1] at Hall-effect sensor input pin during cyclic
check via AWD
• An LVR condition
If one of these wake-up events occurs and the interrupt
mask bit for this event is set, the interrupt will wake-up the
microcontroller as well as the main voltage regulator (MREG)
(Figure 8).
908E625
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
MCU Die
Analog Die
From Reset
Initialize
Operate
SPI:
GS =1
(MREG off)
STOP MREG
STOP
Wait for Action
LIN
AWD
Hallport
IRQ
Interrupt?
Assert IRQ_A
SPI: Reason for
Interrupt
Start
MREG
Operate
MREG = Main Voltage
Regulator
Figure 8. STOP Mode/Wake-up Procedure
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
SERIAL SPI INTERFACE
• MOSI—Master-Out Slave-In
• MISO—Master-In Slave-Out
• SPSCK—Serial Clock
A complete data transfer via the SPI consists of 2 bytes.
The master sends address and data, slave system status,
and data of the selected address.
The SPI creates the communication link between the
microcontroller and the 908E625. The interface consists of
four pins. See Figure 9:
• SS —Slave Select
SS
Read/Write, Address, Parity
MOSI
R/W
A4
A3
A2
A1
A0
Data (Register write)
P
X
D7
D6
D5
System Status Register
MISO
S7
S6
S5
S4
S3
S2
D4
D3
D2
D1
D0
D1
D0
Data (Register read)
S1
S0
D7
D6
D5
D4
D3
D2
SPSCK
Rising edge of SPSCK
Change MISO/MOSI
Output
Falling edge of SPSCK
Sample MISO/MOSI
Input
Slave latch
register address
Slave latch
data
Figure 9. SPI Protocol
During the inactive phase of SS, the new data transfer is
PARITY P
prepared. The falling edge on the SS line indicates the start
The parity bit is equal to 0 if the number of 1 bits is an even
of a new data transfer and puts MISO in the low-impedance
number contained within R/ W, A4:A0. If the number of 1 bits
mode. The first valid data are moved to MISO with the rising
is odd, P equals 1. For example, if R/ W = 1, A4:A0 = 00001,
edge of SPSCK.
then P equals 0.
The MISO output changes data on a rising edge of
The parity bit is only evaluated during a write operation.
SPSCK. The MOSI input is sampled on a falling edge of
SPSCK. The data transfer is only valid if exactly 16 sample
BIT X
clock edges are present in the active phase of SS.
Not used.
After a write operation, the transmitted data is latched into
the register by the rising edge of SS. Register read data is
MASTER DATA BYTE
internally latched into the SPI at the time when the parity bit
Contains data to be written or no valid data during a read
is transferred. SS HIGH forces MISO to high impedance.
operation.
A4:A0
Contains the address of the desired register.
R/ W
Contains information about a read or a write operation.
• If R/ W = 1, the second byte of master contains no valid
information, slave just transmits back register data.
• If R/ W = 0, the master sends data to be written in the
second byte, slave sends concurrently contents of
selected register prior to write operation, write data is
latched in the SMARTMOS register on rising edge of
SS.
SLAVE STATUS BYTE
Contains the contents of the System Status Register ($0c)
independent of whether it is a write or read operation or which
register was selected.
SLAVE DATA BYTE
Contains the contents of selected register. During a write
operation it includes the register content prior to a write
operation.
908E625
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
SPI REGISTER OVERVIEW
Table 6 summarizes the SPI register addresses and the
bit names of each register.
Table 6. List of Registers
Addr
Register Name
R/W
$01
H-Bridge Output
(HBOUT)
R
$02
H-Bridge Control
(HBCTL)
W
$03
System Control
(SYSCTL)
W
$04
Interrupt Mask
(IMR)
$05
Interrupt Flag
(IFR)
W
$06
Reset Mask
(RMR)
W
$07
Analog Multiplexer
Configuration (ADMUX)
$08
Hall-Effect Sensor Input
Pin Control
(HACTL)
W
R
R
R
W
R
R
R
Bit
7
6
5
4
3
2
1
0
HB4_H
HB4_L
HB3_H
HB3_L
HB2_H
HB2_L
HB1_H
HB1_L
OFC_EN
CSA
0
0
0
CLS2
CLS1
CLS0
PSON
SRS1
SRS0
0
0
0
0
0
HPIE
LINIE
HTIE
LVIE
HVIE
0
HPF
LINF
HTF
LVF
HVF
0
0
0
0
0
0
0
0
0
SS3
0
0
0
0
TTEST
W
R
0
GS
OCIE
0
OCF
0
HVRE
HTRE
SS2
SS1
SS0
H3EN
H2EN
H1EN
0
W
$09
Hall-Effect Sensor Input
Pin Status
(HASTAT)
$0a
AWD Control
(AWDCTL)
W
$0b
Power Output
(POUT)
W
$0c
System Status
(SYSSTAT)
R
0
0
0
0
0
0
0
0
H3F
H2F
H1F
AWDRE
AWDIE
AWDCC
AWDF
AWDR
CSSEL0
CSEN1
CSEN0
HVDDON
HS_ON
LVF
HVF
W
R
R
R
W
AWDRST
0
HP_OCF
0
LINCL
CSSEL1
HVDD_OC
HS_OCF
F
HB_OCF
HTF
908E625
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
INTERRUPT FLAG REGISTER (IFR)
Register Name and Address: IFR - $05
Bits
Read
Write
Reset
7
6
5
4
3
2
0
HPF
LINF
HTF
LVF
HVF
0
0
0
0
0
0
1
0
OCF
0
condition is still present while writing a Logic [1] to HTF, the
writing has no effect. Therefore, a high temperature interrupt
cannot be lost due to inadvertent clearing of HTF. Reset
clears the HTF bit. Writing a Logic [0] to HTF has no effect.
• 1 = High temperature condition has occurred
• 0 = High temperature condition has not occurred
Low Voltage Flag Bit (LVF)
0
0
Hall-Effect Sensor Input Pin Flag Bit (HPF)
This read/write flag is set depending on Run/Stop mode.
RUN Mode
An interrupt will be generated when a state change on any
enabled Hall-effect sensor input pin is detected. Clear HPF
by writing a Logic [1] to HPF. Reset clears the HPF bit.
Writing a Logic [0] to HPF has no effect.
• 1 = State change on the hallflags detected
• 0 = No state change on the hallflags detected
STOP Mode
An interrupt will be generated when AWDCC is set and a
current above the threshold is detected on any enabled Halleffect sensor input pin. Clear HPF by writing a Logic [1] to
HPF. Reset clears the HPF bit. Writing a Logic [0] to HPF has
no effect.
• 1 = One or more of the selected Hall-effect sensor input
pins had been pulled HIGH
• 0 = None of the selected Hall-effect sensor input pins
has been pulled HIGH
LIN Flag Bit (LINF)
This read/write flag is set on the falling edge at the LIN
data line. Clear LINF by writing a Logic [1] to LINF. Reset
clears the LINF bit. Writing a Logic [0] to LINF has no effect.
• 1 = Falling edge on LIN data line has occurred
• 0 = Falling edge on LIN data line has not occurred since
last clear
High-Temperature Flag Bit (HTF)
This read/write flag is set on a low voltage condition. Clear
LVF by writing a Logic [1] to LVF. If a low voltage condition is
still present while writing a Logic [1] to LVF, the writing has no
effect. Therefore, a low voltage interrupt cannot be lost due
to inadvertent clearing of LVF. Reset clears the LVF bit.
Writing a Logic [0] to LVF has no effect.
• 1 = Low voltage condition has occurred
• 0 = Low voltage condition has not occurred
High Voltage Flag Bit (HVF)
This read/write flag is set on a high voltage condition.
Clear HVF by writing a Logic [1] to HVF. If high voltage
condition is still present while writing a Logic [1] to HVF, the
writing has no effect. Therefore, a high voltage interrupt
cannot be lost due to inadvertent clearing of HVF. Reset
clears the HVF bit. Writing a Logic [0] to HVF has no effect.
• 1 = High voltage condition has occurred
• 0 = High voltage condition has not occurred
Over-current Flag Bit (OCF)
This read-only flag is set on an over-current condition.
Reset clears the OCF bit. To clear this flag, write a Logic [1]
to the appropriate over-current flag in the SYSSTAT
Register. See Figure 10,illustrating the three signals
triggering the OCF.
• 1 = High current condition has occurred
• 0 = High current condition has not occurred
HVDD_OCF
HS_OCF
OCF
HB_OCF
Figure 10. Principal Implementation for OCF
This read/write flag is set on a high temperature condition.
Clear HTF by writing a Logic [1] to HTF. If a high temperature
908E625
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
INTERRUPT MASK REGISTER (IMR)
High Voltage Interrupt Enable Bit (HVIE)
Register Name and Address: IMR - $04
Bits
Read
Write
Reset
7
0
0
6
5
4
HPIE LINIE HTIE
0
0
0
3
LVIE
2
1
HVIE OCIE
0
0
0
0
This read/write bit enables CPU interrupts by the high
voltage flag, HVF. Reset clears the HVIE bit.
• 1 = Interrupt requests from HVF flag enabled
• 0 = Interrupt requests from HVF flag disabled
0
Over-current Interrupt Enable Bit (OCIE)
0
Hall-Effect Sensor Input Pin Interrupt Enable Bit (HPIE)
This read/write bit enables CPU interrupts by the Halleffect sensor input pin flag, HPF. Reset clears the HPIE bit.
• 1 = Interrupt requests from HPF flag enabled
• 0 = Interrupt requests from HPF flag disabled
This read/write bit enables CPU interrupts by the overcurrent flag, OCF. Reset clears the OCIE bit.
• 1 = Interrupt requests from OCF flag enabled
• 0 = Interrupt requests from OCF flag disabled
RESET
The 908E625 chip has four internal reset sources and one
external reset source, as explained in the paragraphs below.
Figure 11 depicts the internal reset sources.
LIN Line Interrupt Enable Bit (LINIE)
This read/write bit enables CPU interrupts by the LIN flag,
LINF. Reset clears the LINIE bit.
• 1 = Interrupt requests from LINF flag enabled
• 0 = Interrupt requests from LINF flag disabled
High Temperature Interrupt Enable Bit (HTIE)
This read/ write bit enables CPU interrupts by the high
temperature flag, HTF. Reset clears the HTIE bit.
• 1 = Interrupt requests from HTF flag enabled
• 0 = Interrupt requests from HTF flag disabled
Low Voltage Interrupt Enable Bit (LVIE)
This read/write bit enables CPU interrupts by the low
voltage flag, LVF. Reset clears the LVIE bit.
• 1 = Interrupt requests from LVF flag enabled
• 0 = Interrupt requests from LVF flag disabled
RESET INTERNAL SOURCES
Autonomous Watchdog
AWD modules generates a reset because of a timeout
(watchdog function).
High Temperature Reset
To prevent damage to the device, a reset will be initiated if
the temperature rises above a certain value. The reset is
maskable with bit HTRE in the reset mask register. After a
reset the high temperature reset is disabled.
Low Voltage Reset
The LVR is related to the internal VDD. In case the voltage
falls below a certain threshold, it will pull down the RST_A pin.
908E625
22
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
SPI REGISTERS
AWDRE Flag
AWD Reset
Sensor
VDD
HVRE Flag
High-Voltage
Reset Sensor
HTRE Flag
High-Temperature
Reset Sensor
RST_A
MONO
FLOP
Low-Voltage Reset
Figure 11. Internal Reset Routing
High-Voltage Reset
High Temperature Reset Test (TTEST)
The HVR is related to the external VSUP voltage. In case
the voltage is above a certain threshold, it will pull down the
RST_A pin. The reset is maskable with bit HVRE in the Reset
Mask Register. After a reset the high voltage reset is
disabled.
This read/write bit is for test purposes only. It decreases
the over-temperature shutdown limit for final test. Reset
clears the HTRE bit.
• 1 = Low temperature threshold enabled
• 0 = Low temperature threshold disabled
RESET EXTERNAL SOURCE
High Voltage Reset Enable Bit (HVRE)
This read/write bit enables resets on high voltage
conditions. Reset clears the HVRE bit.
• 1 = High voltage reset enabled
• 0 = High voltage reset disabled
External Reset Pin
The microcontroller has the capability of resetting the
SMARTMOS device by pulling down the RST pin.
RESET MASK REGISTER (RMR)
High Temperature Reset Enable Bit (HTRE)
Register Name and Address: RMR - $06
Bits
Read
Write
Reset
7
TTEST
0
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
1
0
This read/write bit enables resets on high temperature
conditions. Reset clears the HTRE bit.
• 1 = High temperature reset enabled
• 0 = High temperature reset disabled
HVRE HTRE
0
0
908E625
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
ANALOG DIE I/OS
Analog Multiplexer/ADOUT Pin
LIN Physical Layer
The ADOUT pin is the analog output interface to the ADC
of the MCU. See Figure 12. An analog multiplexer is used to
read seven internal diagnostic analog voltages.
The LIN bus pin provides a physical layer for single-wire
communication in automotive applications. The LIN physical
layer is designed to meet the LIN physical layer specification.
The LIN driver is a low side MOSFET with internal current
limitation and thermal shutdown. An internal pull-up resistor
with a serial diode structure is integrated, so no external pullup components are required for the application in a slave
node. The fall time from dominant to recessive and the rise
time from recessive to dominant is controlled. The symmetry
between both slew rate controls is guaranteed.
The LIN pin offers high susceptibility immunity level from
external disturbance, guaranteeing communication during
external disturbance.
The LIN transmitter circuitry is enabled by setting the
PSON bit in the System Control Register (SYSCTL). If the
transmitter works in the current limitation region, the LINCL
bit in the System Status Register (SYSSTAT) is set. Due to
excessive power dissipation in the transmitter, software is
advised to monitor this bit and turn the transmitter off
immediately.
TXD PIN
The TXD pin is the MCU interface to control the state of the
LIN transmitter (see Figure 1). When TXD is LOW, LIN output
is low (dominant state). When TXD is HIGH, the LIN output
MOSFET is turned off. The TXD pin has an internal pull-up
current source in order to set the LIN bus in recessive state
in the event, for instance, the microcontroller could not control
it during system power-up or power-down.
Current Recopy
The analog multiplexer is connected to the four low side
current sense circuits of the half-bridges. These sense
circuits offer a voltage proportional to the current through the
low side MOSFET. High or low resolution is selectable: 5.0 V/
2.5 A or 5.0 V/500 mA, respectively. Refer to Half-Bridge
Current Recopy on page 32.)
Analog Input PA1
The analog input PA1 is directly connected to the analog
multiplexer, permitting analog values from the periphery to be
read.
TEMPERATURE SENSOR
The 908E625 includes an on-chip temperature sensor.
This sensor offers a voltage that is proportional to the actual
chip junction temperature.
VSUP PRESCALER
The VSUP prescaler permits the reading or measurement
of the external supply voltage. The output of this voltage is
VSUP /RATIOVSUP.
The different internal diagnostic analog voltages can be
selected with the ADMUX Register.
ANALOG MULTIPLEXER CONFIGURATION
REGISTER (ADMUX)
RXD PIN
The RXD transceiver pin is the MCU interface, which
reports the state of the LIN bus voltage. LIN HIGH (recessive
state) is reported by a high level on RXD, LIN LOW (dominant
state) by a low level on RXD.
STOP MODE/WAKE-UP FEATURE
During STOP mode operation the transmitter of the
physical layer is disabled. The receiver pin is still active and
able to detect wake-up events on the LIN bus line.
If LIN interrupt is enabled (LINIE bit in the Interrupt Mask
Register is set), a falling edge on the LIN line causes an
interrupt. This interrupt switches on the main voltage
regulator and generates a system wake-up.
Register Name and Address: ADMUX - $07
Bits
7
6
5
4
Read
0
0
0
0
0
0
0
0
Write
Reset
3
2
1
0
SS3
SS2
SS1
SS0
0
0
0
0
SS3, SS2, SS1, and SS0—A/D Input Select Bits
These read/write bits select the input to the ADC in the
microcontroller according to Table 7. Reset clears SS3, SS2,
SS1, and SS0 bits.
908E625
24
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
ANALOG INPUT PA1
Table 7. Analog Multiplexer Configuration Register
SS3
SS2
SS1
SS0
Channel
0
0
0
0
Current Recopy HB1
0
0
0
1
Current Recopy HB2
0
0
1
0
Current Recopy HB3
0
0
1
1
Current Recopy HB4
0
1
0
0
VSUP Prescaler
0
1
0
1
Temperature Sensor
0
1
1
0
Not Used
0
1
1
1
PA1 Pin
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
The Analog input PA1 pin provides an input for reading
analog signals and is internally connected to the analog
multiplexer. It can be used for reading switches,
potentiometers or resistor values, etc.
ANALOG INPUT PA1 CURRENT SOURCE
The analog input PA1 has an additional selectable current
source. It enables the reading of switches, NTC, etc., without
the need of an additional supply line for the sensor illustrated
in Figure 12. With this feature it is also possible to read
multiple switches on one input.
Current source is enabled if the PSON bit in the System
Control Register (SYSCTL) and the CSEN bit in the Power
Output Register (POUT) is set.
Four different current source values can be selected with the CSSELx bits
shown in Table 8. This function ceases during STOP mode operation.
Table 8. PA1 Current Source Level Selection Bits
CSSEL1 CSSEL0
Not Used
Current Source Enable (typ.)
0
0
10%
0
1
30%
1
0
60%
1
1
100%
Source Selection Bits
VDD
SSx
3
CSSEL
Selectable
Current
Source
PSON
ADOUT
Analog
Multiplexer
CSEN
PA1
Analog Input PA1
NTC
Figure 12. Analog Input PA1 and Multiplexer
908E625
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
POWER OUTPUT REGISTER (POUT)
• 1 = Lamp driver enabled
• 0 = Lamp driver disabled
Hall-Effect Sensor Input Pins (H1:H3)
Register Name and Address: POUT - $0b
Bits
7
6
Read
0
0
5
4
3
CSSEL1 CSSEL0 CSEN
2
0
(16)
1
0
HVDDON HS_ON
Write
Reset
0
0
0
0
0
0
0
0
Notes
16. This bit must always be set to 0.
Current Source Select Bits (CSSEL0:CSSEL1)
These read/write bits select the current source values.
Reset clears the CSSEL0:CSSEL1 bits.
Current Source Enable Bit (CSEN)
This read/write bit enables the current source for PA1.
Reset clears the CSEN bit (Table 9).
Table 9. PA1 Current Source Enable Bit
CSEN
Current Source Enable
0
Current Source Off
1
Current Source On
HVDD On Bit (HVDDON)
This read/write bit enables HVDD output. Reset clears the
HVDDON bit.
• 1 = HVDD enabled
• 0 = HVDD disabled
Lamp Driver On Bit (HS_ON)
This read/write bit enables the Lamp driver. Reset clears
the HS_ON bit.
Function
The Hall-effect sensor input pins provide three inputs for
two-pin Hall-effect sensors for detecting stall and position or
reading Hall-effect sensor contact switches. The Hall-effect
sensor input pins are not influenced by the PSON bit in the
System Control Register.
Each pin of the Hall-effect sensor can be enabled by
setting the HxEN bit in the Hall-effect sensor input pin control
register (HACTL). If the pins are enabled, the Hall-effect
sensors are supplied with VSUP voltage and the sense
circuitry is working. An internal clamp circuity limits the supply
voltage to the sensor to 15 V. This sense circuitry monitors
the current to VSS. The result of this sense operation is given
by the HxF flags in the Hall-effect sensor input pin status
register (HASTAT).
The flag is set if the sensed current is higher than IHSCT.
To prevent noise on this flag, a hysteresis is implemented on
these pins.
After switching on the Hall-effect sensor input pins (HxEN
= 1), the Hall-effect sensors need some time to stabilize the
output. In RUN mode the software must wait at least 40 μs
between enabling the Hall-effect sensor and reading the hall
flag.
The Hall-effect sensor input pin works in an dynamic
output voltage range from VSUP down to 2.0 V. Below 2.0 V
the hallflags are not functional anymore. If the output voltage
is below a certain threshold, the Hall-effect sensor input pin
over-current flag (HP_OCF) in the system status register is
set.
Figures 13 through 15 illustrate the connections to the
Hall-effect input sensors.
908E625
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
HxEN
Two-Terminal Hall-Effect Sensor
Hx
Sense
Circuitry
HxF
GND
V
Figure 13. Hall-effect Sensor Input Pin Connected to Two Pin Hall-effect Sensor
HxEN
Sense
Circuitry
Hx
Rv
HxF
V
GND
Figure 14. Hall-effect Sensor Input Pin Connected to Local Switch
908E625
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Three-Terminal Hall-Effect Sensor
Vs
HxEN
Sense
Circuitry
Hx
Out
HxF
V
GND
GND
Figure 15. Hall-effect Sensor Input Pin Connected to Three Pin Hall-effect Sensor
Interrupts
CYCLIC WAKE-UP
The Hall-effect sensor input pins are interrupt capable.
How and when an interrupt occurs is dependent on the
operating mode, RUN or Stop.
The Hall-effect sensor inputs can be used to wake up the
system. This wake-up function is provided by the cyclic check
wake-up feature of the AWD (Autonomous Watchdog).
If the cyclic check wake-up feature is enabled (AWDCC bit
is set), the AWD switches on the enabled Hall-effect sensor
pins periodically. To ensure that the Hall-effect sensor current
is stabilized after switching on, the inputs are sensed after
~40 μs. If a 1 is detected (IHall sensor > IHSCT) and the
interrupt mask bit HPIE is set, an interrupt is performed. This
wakes up the MCU and starts the main voltage regulator.
The wake-up function via this input is available when all
three conditions exist:
• The two-pin Hall-effect sensor input is enabled
(HxEN = 1)
• The cyclic wake-up of the AWD is enabled (AWDCC =
1); see Figure 16
• The Hall-effect sensor input pin interrupt is enabled
(HPIE = 1)
RUN Mode
In RUN mode the Hall-effect sensor input pin interrupt flag
(HPF) will be set if a state change on the hallflags (HxF) is
detected. The interrupt is maskable with the HPIE bit in the
interrupt mask register. Before enabling the interrupt, the flag
should be cleared in order to prevent a wrong interrupt.
STOP Mode
In STOP mode the Hall-effect sensor input pins are
disabled independent of the state of the HxEN flags.
908E625
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
SPI:
AWDCC = 1
GS = 1
SPI Command
STOP
MREG
No
STOP
AWD
Timer Overflow?
Yes
No
Switch on
Selected Hallport
IRQ_A = 0
Start MREG
IRQ?
Yes
SPI:
Reason for Wakeup
Operate
Wait 40 µs
Yes
Assert IRQ_A
Hallport = 1
No
Switch off
Selected Hallport
MREG = Main Voltage
Regulator
Figure 16. Hall-effect Sensor Input Pin Cyclic Check Wake-up Feature
HALL-EFFECT SENSOR INPUT PIN CONTROL
REGISTER (HACTL)
HALL-EFFECT SENSOR INPUT PIN STATUS
REGISTER (HASTAT)
Register Name and Address: HACTL - $08
Bits
7
6
5
4
3
Read
0
0
0
0
0
Write
Reset
0
0
0
0
0
Register Name and Address: HASTAT - $09
2
1
0
H3EN
H2EN
H1EN
0
0
0
Bits
7
6
5
4
3
2
1
0
Read
0
0
0
0
0
H3F
H2F
H1F
0
0
0
0
0
0
0
0
Write
Reset
Hall-Effect Sensor Input Pin Enable Bits (H3EN:H1EN)
Hall-Effect Sensor Input Pin Flag Bits (H3F:H1F)
These read/write bits enable the Hall-effect sensor input
pins. Reset clears the H3EN:H1EN bits.
• 1 = Hall-effect sensor input pin Hx switched on and
sensed
• 0 = Hall-effect sensor input pin Hx disabled
These read-only flag bits reflect the input Hx while the Halleffect sensor input pin Hx is enabled (HxEN = 1). Reset
clears the H3F:H1F bits.
• 1 = Hall-effect sensor input pin current above threshold
• 0 = Hall-effect sensor input pin current below threshold
908E625
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
HALF-BRIDGES
Outputs HB1:HB4 provide four low-resistive half-bridge
output stages. The half-bridges can be used in H-Bridge, high
side, or low side configurations.
Reset clears all bits in the H-Bridge output register
(HBOUT) owing to the fact that all half-bridge outputs are
switched off.
HB1:HB4 output features:
• Short-circuit (over-current) protection on high side and
low side MOSFETs
• Current recopy feature (low side MOSFET)
• Over-temperature protection
• Over-voltage and under-voltage protection
• Current limitation feature (low side MOSFET)
VSUP
Control
On/Off
High Side Driver
Status
Charge Pump,
OVer-temperature Protection,
OVer-current Protection
BEMF
HBx
On/Off
Status
Current
Limit
Low Side Driver
Current Recopy,
Current Limitation,
OVer-current Protection
GND
Figure 17. Half-bridge Push-Pull Output Driver
HALF-BRIDGE CONTROL
Each output MOSFET can be controlled individually. The
general enable of the circuitry is done by setting PSON in the
system control register (SYSCTL). HBx_L and HBx_H form
one half-bridge. It is not possible to switch on both MOSFETs
in one half-bridge at the same time. If both bits are set, the
high-side MOSFET has a higher priority.
To avoid both MOSFETs (high side and low side) of one
half-bridge being on at the same time, a break-before-make
circuit exists. Switching the high side MOSFET on is inhibited
as long as the potential between gate and VSS is not below a
certain threshold. Switching the low side MOSFET on is
blocked as long as the potential between gate and source of
the high-side MOSFET did not fall below a certain threshold.
HALF-BRIDGE OUTPUT REGISTER (HBOUT)
Register Name and Address: HBOUT - $01
Bits
Read
Write
Reset
7
6
5
4
3
2
1
0
HB4_ HB4_ HB3_ HB3_ HB2_ HB2_ HB1_ HB1_
H
L
H
L
H
L
H
L
0
0
0
0
0
0
0
0
Low Side On/Off Bits (HBx_L)
These read/write bits turn on the low side MOSFETs.
Reset clears the HBx_L bits.
• 1 = Low side MOSFET turned on for half-bridge output x
• 0 = Low side MOSFET turned off for half-bridge output x
908E625
30
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
High Side On/Off Bits (HBx_H)
These read/write bits turn on the high side MOSFETs.
Reset clears the HBx_H bits.
• 1 = High side MOSFET turned on for half-bridge output
x
• 0 = High side MOSFET turned on for half-bridge output
x
HALF-BRIDGE CURRENT LIMITATION
Each low side MOSFET offers a current limit or constant
current feature. This features is realized by a pulse width
modulation on the low side MOSFET. The pulse width
modulation on the outputs is controlled by the FGEN input
and the load characteristics. The FGEN input provides the
PWM frequency, whereas the duty cycle is controlled by the
load characteristics.
The recommended frequency range for the FGEN and the
PWM is 0.1 kHz to 20 kHz.
Functionality
Each low side MOSFET switches off if a current above the
selected current limit was detected. The 908E625 offers five
different current limits. Refer to Table 10 for current limit
values. The low side MOSFET switches on again if a rising
edge on the FGEN input was detected (Figure 18).
H-Bridge low-side
MOSFET will be switched
off if select current limit is
reached.
Coil Current
H-Bridge low-side
MOSFET will be turned on
with each rising edge of
the FGEN input.
t
Half-Bridge
Low-Side Output
t
FGEN Input
(MCU PWM
Signal)
t
Minimum 50 μs
Figure 18. Half-bridge Current Limitation
908E625
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
OFFSET CHOPPING
If bit OFC_EN in the H-Bridge control register (HBCTL) is
set, HB1 and HB2 will continue to switch on the low side
MOSFETs with the rising edge of the FGEN signal and HB3
and HB4 will switch on the low side MOSFETs with the falling
edge on the FGEN input. In step motor applications this
feature allows the reduction of EMI due to a reduction of the
di/dt (Figure 19).
Coil1 Current
Coil2 Current
FGEN Input
(MCU PWM
Signal)
HB1
HB2
HB3
HB4
Coil1…..
Coil2…..
Current in
VSUP Line
Figure 19. Offset Chopping for Step Motor Control
HALF-BRIDGE CURRENT RECOPY
HALF-BRIDGE BEMF GENERATION
Each low side MOSFET has an additional sense output to
allow a current recopy feature. This sense source is internally
connected to a shunt resistor. The drop voltage is amplified
and switched to the analog multiplexer.
The factor for the current sense amplification can be
selected via bit CSA in the system control register.
• CSA = 1: Low resolution selected (500 mA
measurement range)
• CSA = 0: High resolution selected (2.5 A measurement
range)
The BEMF output is set to 1 if a recirculation current is
detected in any half-bridge. This recirculation current flows
via the two freewheeling diodes of the power MOSFETs. The
BEMF circuitry detects that and generates a HIGH on the
BEMF output as long as a recirculation current is detected.
This signal provides a flexible and reliable detection of stall in
step motor applications. For this the BEMF circuitry takes
advantage of the instability of the electrical and mechanical
behavior of a step motor when blocked. In addition the signal
can be used for open load detection (absence of this signal),
see Figure 20.
908E625
32
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Coil Current
Voltage on 1
1
BEMF Signal
Figure 20. BEMF Signal Generation
HALF-BRIDGE OVER-TEMPERATURE
PROTECTION
The half-bridge outputs provide an over-temperature prewarning with the HTF in the Interrupt Flag Register (IFR). In
order to protect the outputs against over-temperature, the
high temperature reset must be enabled. If this value is
reached, the part generates a reset and disables all power
outputs.
The over-voltage/under-voltage status flags are cleared
(and the outputs re-enabled) by writing a Logic [1] to the LVF/
HVF flags in the interrupt flag register or by reset. Clearing
this flag is useless as long as a high or low voltage condition
is present.
HALF-BRIDGE CONTROL REGISTER (HBCTL)
Register Name and Address: HBCTL - $02
HALF-BRIDGE OVER-CURRENT PROTECTION
The half-bridges are protected against short to GND, short
to VSUP, and load shorts.
In the event an over-current on the high side is detected,
the high side MOSFETs on all HB high side MOSFETs are
switched off automatically. In the event an over-current on the
low side is detected, all HB low side MOSFETs are switched
off automatically. In both cases the over-current status flag
HB_OCF in the system status register (SYSSTAT) is set.
The over-current status flag is cleared (and the outputs reenabled) by writing a Logic [1] to the HB_OCF flag in the
System status register or by reset.
HALF-BRIDGE OVER-VOLTAGE/UNDERVOLTAGE
The half-bridge outputs are protected against undervoltage and over-voltage conditions. This protection is done
by the low and high voltage interrupt circuitry. If one of these
flags (LVF, HVF) is set, the outputs are automatically
disabled.
Bits
Read
Write
Reset
7
6
OFC_EN
CSA
0
0
5
4
3
0
0
0
0
0
0
2
1
0
CLS2
CLS1
CLS0
0
0
0
H-Bridge Offset Chopping Enable Bit (OFC_EN)
This read/write bit enables offset chopping. Reset clears
the OFC_EN bit.
• 1 = Offset chopping enabled
• 0 = Offset chopping disabled
H-Bridges Current Sense Amplification Select Bit (CSA)
This read/write bit selects the current sense amplification
of the H-Bridges. Reset clears the CSA bit.
• 1 = Current sense amplification set for measuring 0.5 A.
• 0 = Current sense amplification set for measuring 2.5 A.
908E625
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
H-Bridge Current Limitation Selection Bits (CLS2:CLS0)
HIGH SIDE DRIVER
These read/write bits select the current limitation value
according to Figure 10. Reset clears the CLS2:CLS0 bits.
The high side output is a low-resistive high side switch
targeted for driving lamps. The high side is protected against
over-temperature. To limit the high inrush current of bulbs,
over-current protection circuitry is used to limit the current.
The output is enabled with bit PSON in the system control
register and can be switched on/off with bit HS_ON in the
power output register. Figure 21 depicts the high-side switch
circuitry and connection to external lamp.
Table 10. H-Bridge Current Limitation Value Selection
Bits
CLS2
CLS1
CLS0
Current Limit
0
0
0
0
0
1
0
1
0
0
1
1
55 mA (typ)
1
0
0
260 mA (typ)
1
0
1
370 mA (typ)
1
1
0
550 mA (typ)
1
1
1
740 mA (typ)
No Limit
HIGH-SIDE OVER-VOLTAGE/UNDER-VOLTAGE
PROTECTION
The high side output pin, HS, is protected against undervoltage/over-voltage conditions. This protection is done by
the low and high voltage interrupt circuitry. If one of these
flags (LVF, HVF) is set, the output is disabled.
The over-voltage/under-voltage status flags are cleared
and the output re-enabled by writing a Logic [1] to the LVF/
HVF flags in the interrupt flag register or by reset. Clearing
this flag is useless as long as a high or low voltage condition
is present.
VSUP
On/Off
Control
Status
Current
Limit
High Side Driver
Charge Pump,
OVer-current Protection,
Inrush Current Limiter
HS
Figure 21. High Side Circuitry
HIGH SIDE OVER-TEMPERATURE PROTECTION
The high side output provides an over-temperature prewarning with the HTF in the interrupt flag register. In order to
protect the output against over-temperature, the hightemperature reset must be enabled. If this value is reached,
the part generates a reset and disables all power outputs.
HIGH-SIDE OVER-CURRENT PROTECTION
The high side output is protected against over-current. In
the event over-current limit is or was reached, the output
automatically switches off and the over-current flag is set.
Due to the high inrush current of bulbs, a special feature of
the 908E625 prevents an over-current shutdown during this
inrush. If an PWM frequency is supplied to the FGEN output
during the switching on of a bulb, the inrush current is limited
to the over-current shutdown limit. This means if the current
reaches the over-current shutdown, the high side will be
switched off, but each rising edge on the FGEN input will
enable the driver again.
To distinguish between a shutdown due to an inrush
current or a real shutdown, the software must check if the
over-current status flag (HS_OCF) in the System Status
Register is set beyond a certain period of time. The overcurrent status flag is cleared by writing a Logic [1] to the
HS_OCF in the System Status Register, see Figure 22.
908E625
34
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
HS Current
HS Over-current Shutdown Threshold
t
FGEN Input
(MCU PWM
Signal)
t
Figure 22. Inrush Current Limiter on High Side Output
SWITCHABLE VDD OUTPUT (HVDD)
The HVDD pin is a switchable VDD output pin. It can be
used for driving external circuitry that requires a VDD voltage.
The output is enabled with bit PSON in the system control
register and can be switched on/off with bit HVDDON in the
power output register. Low or high voltage conditions (LVI/
HVI) have no influence on this circuitry.
HVDD OVER-TEMPERATURE PROTECTION
Over-temperature protection is enabled if the high
temperature reset is enabled.
HVDD OVER-CURRENT PROTECTION
The HVDD output is protected against over-current. In the
event the over-current limit is or was reached, the output
automatically switches off and the HVDD over-current flag in
the system status register is set.
SYSTEM CONTROL REGISTER (SYSCTL)
Register Name and Address: SYSCTL - $03
Bits
Read
Write
Reset
7
6
5
PSON
SRS1
SRS0
0
0
0
4
3
2
1
0
0
0
0
0
0
GS
0
0
0
0
0
Power Stages On Bit (PSON)
This read/write bit enables the power stages (half-bridges,
high side, LIN transmitter, Analog Input PA1 current sources,
and HVDD output). Reset clears the PSON bit.
• 1 = Power stages enabled.
• 0 = Power stages disabled.
LIN Slew Rate Selection Bits (SRS0:SRS1)
These read/write bits enable the user to select the
appropriate LIN slew rate for different baud rate
configurations as shown in Table 11.
The high speed slew rates are used, for example, for
programming via the LIN and are not intended for use in the
application.
908E625
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
HVDD_OCF bit. Writing a Logic [0] to HVDD_OCF has no
effect.
Table 11. LIN Slew Rate Selection Bits
SRS1
SRS0
LIN Slew Rate
0
0
Initial Slew Rate (20 kBaud)
0
1
Slow Slew Rate (10 kBaud)
1
0
High Speed II (8x)
1
1
High Speed I (4x)
•1 = Over-current condition on HVDD has occurred
•0 = No over-current condition on HVDD has occurred
High Side Over-current Flag Bit (HS_OCF)
Go to STOP Mode Bit (GS)
This write-only bit instructs the 908E625 to power down
and go into Stop mode. Reset or CPU interrupt requests clear
the GS bit.
• 1 = Power down and go into Stop mode
• 0 = Not in STOP mode
Register Name and Address: SYSSTAT - $0c
Read
Write
Reset
7
HP_
OCF
6
LINCL
0
0
5
4
HVDD
_OCF
HS_
OCF
0
0
3
2
LVF
HVF
0
0
1
HB_
OCF
0
0
HTF
0
Hall-Effect Sensor Input Pin Over-current Flag Bit
(HP_OCF)
This read/write flag is set on an over-current condition at
one of the Hall-effect sensor input pins. Clear HP_OCF and
enable the output by writing a Logic [1] to the HP_OCF flag.
Reset clears the HP_OCF bit. Writing a Logic [0] to HP_OCF
has no effect.
• 1 = Over-current condition on Hall-effect sensor input
pin has occurred
• 0 = No over-current condition on Hall-effect sensor input
pin has occurred
LIN Current Limitation Bit (LINCL)
This read-only bit is set if the LIN transmitter operates in
current limitation region. Due to excessive power dissipation
in the transmitter, software is advised to turn the transmitter
off immediately.
•1 = Transmitter operating in current limitation region
•0 = Transmitter not operating in current limitation region
HVDD Output Over-current Flag Bit (HVDD_OCF)
This read/write flag is set on an over-current condition at
the HVDD pin. Clear HVDD_OCF and enable the output by
writing a Logic [1] to the HVDD_OCF Flag. Reset clears the
WATCHDOG
Low Voltage Bit (LVF)
This read only bit is a copy of the LVF bit in the Interrupt
Flag Register.
• 1 = Low voltage condition has occurred
• 0 = No low voltage condition has occurred
SYSTEM STATUS REGISTER (SYSSTAT)
Bits
This read/write flag is set on an over-current condition at
the high side driver. Clear HS_OCF and enable the high side
driver by writing a Logic [1] to HS_OCF. Reset clears the
HS_OCF bit. Writing a Logic [0] to HS_OCF has no effect.
• 1 = Over-current condition on high side drivers has
occurred
• 0 = No over-current condition on high side drivers has
occurred
High Voltage Sensor Bit (HVF)
This read-only bit is a copy of the HVF bit in the Interrupt
Flag Register.
• 1 = High voltage condition has occurred
• 0 = No high voltage condition has occurred
H-Bridge Over-current Flag Bit (HB_OCF)
This read / write flag is set on an over-current condition at
the H-Bridges. Clear HB_OCF and enable the H-Bridge
driver by writing a Logic [1] to HB_OCF. Reset clears the
HB_OCF bit. Writing a Logic [0] to HB_OCF has no effect.
• 1 = Over-current condition on H-Bridges has occurred
• 0 = No over-current condition on H-Bridges has
occurred
Over-temperature Status Bit (HTF)
This read-only bit is a copy of the HTF bit in the Interrupt
Flag Register.
• 1 = Over-temperature condition has occurred
• 0 = No over-temperature condition has occurred
AUTONOMOUS WATCHDOG (AWD)
The Autonomous Watchdog module consists of three
functions:
• Watchdog function for the CPU in RUN mode
• Periodic interrupt function in STOP mode
• Cyclic wake-up function in STOP mode
The AWD is enabled if AWDIE, AWDRE, or AWDCC in the
AWDCTL Register is set. If these bits are cleared, the AWD
oscillator is disabled and the watchdog switched off.
The watchdog function is only available in RUN mode. On
setting the AWDRE bit, watchdog functionality in RUN mode
908E625
36
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
is activated. Once this function is enabled, it is not possible to
disable it via software.
If the timer reaches end value and AWDRE is set, a
system reset is initiated. Operations of the watchdog function
cease in STOP mode. Normal operation will be continued
when the system is back to RUN mode.
To prevent a watchdog reset, the watchdog timeout
counter must be reset before it reaches the end value. This is
done by a write to the AWDRST bit in the AWDCTL Register.
PERIODIC INTERRUPT
Periodic interrupt is only available in STOP mode. It is
enabled by setting the AWDIE bit in the AWDCTL Register. If
AWDIE is set, the AWD wakes up the system after a fixed
period of time. This time period can be selected with bit
AWDR in the AWDCTL Register.
The cyclic wake-up feature is only available in STOP
mode. If this feature is enabled, the selected Hall-effect
sensor input pins are switched on and sensed. If a “1” is
detected on one of these inputs and the interrupt for the Halleffect sensors is enabled, a system wake-up is performed.
(Switch on main voltage regulator and assert IRQ_A to the
microcontroller).
Register Name and Address: AWDCTL - $0a
Bits
7
6
5
Read
0
0
0
AWDRS
T
0
0
Autonomous Watchdog Interrupt Enable Bit (AWDIE)
This read/write bit enables CPU interrupts by the
Autonomous Watchdog timeout flag, AWFD. IRQ_A is only
asserted when the device is in STOP mode. Reset clears the
AWDIE bit.
• 1 = CPU interrupt requests from AWDF enabled
• 0 = CPU interrupt requests from AWDF disabled
0
This read/write bit enables the cyclic check of the two pin
Hall-effect sensor and the analog inputs. Reset clears the
AWDCC bit.
• 1 = Cyclic check of the Hall-effect sensor and analog
port
• 0 = No cyclic check of the Hall-effect sensor and analog
port
Autonomous Watchdog Timeout Flag Bit (AWDF)
AUTONOMOUS WATCHDOG CONTROL
REGISTER (AWDCTL)
Reset
This read/write bit enables resets on AWD timeouts. A
reset on the RST_A is only asserted when the device is in
RUN mode. AWDRE is one time setable (write once) after
each reset. Reset clears the AWDRE bit.
• 1 = Autonomous watchdog enabled
• 0 = Autonomous watchdog disabled
Autonomous Watchdog Cyclic Check (AWDCC)
CYCLIC WAKE-UP
Write
Autonomous Watchdog Reset Enable Bit (AWDRE)
4
3
2
1
0
AWDR
E
AWDI
E
AWDC
C
AWDF
AWD
R
0
0
0
0
0
This read/write flag is set when the Autonomous
Watchdog has timed out. Clear AWDF by writing a Logic [1]
to AWDF. Clearing AWDF also resets the AWD counter and
starts a new timeout period. Reset clears the AWDF bit.
Writing a Logic [0] to AWDF has no effect.
• 1 = AWD has timed out
• 0 = AWD has not yet timed out
Autonomous Watchdog Rate Bit (AWDR)
Autonomous Watchdog Reset Bit (AWDRST)
This write-only bit resets the Autonomous Watchdog
timeout period. AWDRST always reads 0. Reset clears
AWDRST bit.
• 1 = Reset AWD and restart timeout period
• 0 = No effect
This read/write bit selects the clock rate of the
Autonomous Watchdog. Reset clears the AWDR bit.
• 1 = Fast rate selected (10 ms)
• 0 = Slow rate selected (20 ms)
VOLTAGE REGULATOR
The 908E625 chip contains a low power, low drop voltage
regulator to provide internal power and external power for the
MCU. The on-chip regulator consist of two elements, the
main voltage regulator and the low voltage reset circuit.
The VDD regulator accepts a unregulated input supply and
provides a regulated VDD supply to all digital sections of the
device. The output of the regulator is also connected to the
VDD pin to provide the 5.0 V to the microcontroller.
RUN Mode
During RUN mode the main voltage regulator is on. It
provides a regulated supply to all digital sections.
908E625
Analog Integrated Circuit Device Data
Freescale Semiconductor
37
FUNCTIONAL DEVICE OPERATION
FACTORY TRIMMING AND CALIBRATION
STOP Mode
During STOP mode the STOP mode regulator supplies a
regulated output voltage. The STOP mode regulator has a
very limited output current capability. The output voltage will
be lower than the output voltage of the main voltage
regulator.
FACTORY TRIMMING AND CALIBRATION
To enhance the ease-of-use of the 908E625, various
parameters (e.g. ICG trim value) are stored in the flash
memory of the device. The following flash memory locations
are reserved for this purpose and might have a value different
from the empty (0xFF) state:
•0xFD80:0xFDDF Trim and Calibration Values
•0xFFFE:0xFFFF Reset Vector
In the event the application uses these parameters, one
has to take care not to erase or override these values. If these
parameters are not used, these flash locations can be erased
and otherwise used.
Trim Values
Below the usage of the trim values located in the flash
memory is explained
Internal Clock Generator (ICG) Trim Value
The internal clock generator (ICG) module is used to
create a stable clock source for the microcontroller without
using any external components. The untrimmed frequency of
the low frequency base clock (IBASE), will vary as much as
±25 percent due to process, temperature, and voltage
dependencies. To compensate this dependencies a ICG trim
values is located at address $FDC2. After trimming the ICG
is a range of typ. ±2% (±3% max.) at nominal conditions
(filtered (100 nF) and stabilized (4,7 μF) VDD = 5.0 V,
TAMBIENT~25 °C) and will vary over temperature and voltage
(VDD) as indicated in the 68HC908EY16 datasheet.
To trim the ICG this values has to be copied to the ICG
Trim Register ICGTR at address $38 of the MCU.
Important The value has to copied after every reset.
908E625
38
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
FACTORY TRIMMING AND CALIBRATION
TYPICAL APPLICATIONS
DEVELOPMENT SUPPORT
As the 908E625 has the MC68HC908EY16 MCU
embedded typically all the development tools available for
the MCU also apply for this device, however due to the fact
of the additional analog die circuitry and the nominal +12 V
supply voltage some additional items have to be considered:
• nominal 12 V rather than 5.0 V or 3.0 V supply
• high voltage VTST might be applied not only to IRQ pin,
but IRQ_A pin
For a detailed information on the MCU related
development support see the MC68HC908EY16 datasheet section development support.
The programming is principally possible at two stages in
the manufacturing process - first on chip level, before the IC
is soldered onto a pcb board and second after the IC is
soldered onto the pcb board.
Chip level programming
On Chip level the easiest way is to only power the MCU
with +5.0 V (see Figure 23) and not to provide the analog
chip with VSUP, in this setup all the analog pin should be left
open (e.g. VSUP[1:3]) and interconnections between MCU
and analog die have to be separated (e.g. IRQ - IRQ_A).
This mode is well described in the MC68HC908EY16
datasheet - section development support.
VSUP[1:3]
VDD
GND[1:2]
VSS
+5V
VREFH
VDDA
RST
EVDD
RST_A
+5V
1
1µF
+
4
GND
C1C2+
V+
+
5
RS232
DB-9
16
+
3
1µF
VCC
C1+
100nF
VTST
C2-
MAX232
V-
IRQ_A
1µF
7 T2OUT
3
8 R2IN
1µF
9.8304MHz CLOCK
6
+5V
+
CLK
PTB4/AD4
T2IN 10
6
10k
5
+5V
10k
DATA
PTA1/KBD1
PTA0/KBD0
10k
4
PTB3/AD3
3
2
10k
PTC4/OSC1
1µF
74HC125
5
VSSA
+
2
R2OUT 9
MM908E625
EVSS
15
74HC125
2
4.7µF
VREFL
IRQ
1
Figure 23. Normal Monitor Mode Circuit (MCU only)
Of course its also possible to supply the whole system with
Vsup (12 V) instead as described in Figure 24, page 40.
PCB level programming
If the IC is soldered onto the pcb board its typically not
possible to separately power the MCU with +5.0 V, the whole
system has to be powered up providing VSUP (see
Figure 24).
908E625
Analog Integrated Circuit Device Data
Freescale Semiconductor
39
TYPICAL APPLICATIONS
FACTORY TRIMMING AND CALIBRATION
VDD
VSUP
+
47µF
100nF
VSUP[1:3]
VDD
GND[1:2]
VSS
VREFH
VDDA
RST
EVDD
RST_A
VDD
1
C1+
VCC
+
1µF
+
3
4
C1-
GND
C2+
V+
+
1µF
5
RS232
DB-9
100nF
VTST
16
C2-
MAX232
V-
7 T2OUT
3
8 R2IN
VSSA
EVSS
15
1µF
+
2
9.8304MHz CLOCK
6
VDD
+
CLK
10k
PTC4/OSC1
PTB4/AD4
1µF
T2IN 10
6
74HC125
R2OUT 9
MM908E625
IRQ_A
1µF
10k
74HC125
2
4.7µF
VREFL
IRQ
10k
5
DATA
PTA1/KBD1
PTA0/KBD0
10k
4
PTB3/AD3
3
2
VDD
1
5
Figure 24. Normal Monitor Mode Circuit
Table 12 summarizes the possible configurations and the
necessary setups.
Table 12. Monitor Mode Signal Requirements and Options
Mode
IRQ RST
Normal
Monitor
Forced
Monitor
VTST
Reset
Vector
VDD
X
VDD
$FFFF
(blank)
VDD
Serial
Communication
Mode
Selection
PTA0
PTA1
PTB3
PTB4
1
0
0
1
1
0
X
VDD
VDD
not $FFFF
(not blank)
X
X
X
ICG
COP
OFF
disabled
disabled
9.8304
MHz
2.4576
MHz
9600
OFF
disabled
disabled
9.8304
MHz
2.4576
MHz
9600
ON
disabled
disabled
—
Nominal
1.6MHz
Nominal
6300
ON
enabled
enabled
—
Nominal
1.6MHz
Nominal
6300
X
GND
User
Communication Speed
Normal
Request
Baud
Bus
Timeout External
Clock Frequency Rate
X
Notes
1. PTA0 must have a pull-up resistor to VDD in monitor mode
2.
3.
4.
5.
External clock is a 4.9152 MHz, 9.8304 MHz or 19.6608 MHz canned oscillator on OCS1
Communication speed with external clock is depending on external clock value. Baud rate is bus frequency / 256
X = don’t care
VTST is a high voltage VDD + 3.5 V ≤ VTST ≤ VDD + 4.5 V
908E625
40
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
FACTORY TRIMMING AND CALIBRATION
EMC/EMI RECOMMENDATIONS
This paragraph gives some device specific
recommendations to improve EMC/EMI performance.
Further generic design recommendations can be e.g. found
on the Freescale web site www.freescale.com.
MCU digital supply pins (EVDD and EVSS)
VSUP pins (VSUP1:VSUP3)
Fast signal transitions on MCU pins place high, shortduration current demands on the power supply. To prevent
noise problems, take special care to provide power supply
bypassing at the MCU. It is recommended that a high quality
ceramic decoupling capacitor be placed between these pins.
Its recommended to place a high-quality ceramic
decoupling capacitor close to the VSUP pins to improve
EMC/EMI behavior.
MCU analog supply pins (VREFH, VDDA and VREFL,
VSSA)
To avoid noise on the analog supply pins its important to
take special care on the layout. The MCU digital and analog
supplies should be tied to the same potential via separate
traces and connected to the voltage regulator output.
Figure 25 and Figure 26 show the recommendations on
schematics and layout level and Table 13 indicates
recommended external components and layout
considerations.
LIN pin
For DPI (Direct Power Injection) and ESD (Electro Static
Discharge) its recommended to place a high quality ceramic
decoupling capacitor near the LIN pin. An additional varistor
will further increase the immunity against ESD. A ferrite in the
LIN line will suppress some of the noise induced.
Voltage regulator output pins (VDD and AGND)
Use a high quality ceramic decoupling capacitor to
stabilize the regulated voltage.
D1
VSUP
C1
+
C2
VSUP1
VDD
VSUP2
VSS
VSUP3
VREFH
VDDA
L1
LIN
LIN
EVDD
V1
C5
C3
MM908E625
C4
EVSS
VSSA
GND1
VREFL
GND2
Figure 25. EMC/EMI Recommendations
908E625
Analog Integrated Circuit Device Data
Freescale Semiconductor
41
TYPICAL APPLICATIONS
FACTORY TRIMMING AND CALIBRATION
1
54
2
53
3
52
4
51
5
50
49
7
VREFH
48
8
VDDA
47
9
EVDD
46
10
EVSS
45
11
VSSA
44
12
VREFL
43
13
14
42
NC
908E625
15
41
VSS
16
VDD
18
C5
V1
36
20
LIN
21
NC
22
NC
35
34
NC
23
GND
32
VSUP1
VSUP3
31
25
GND1
GND2
30
26
C1
33
24
27
VBAT
38
37
19
L1
C4
40
39
17
LIN
C3
6
29
VSUP2
28
C2
D1
Figure 26. PCB Layout Recommendations
.
Table 13. Component Value Recommendation
Component
Recommended Value(1)
D1
Comments / Signal routing
reverse battery protection
C1
Bulk Capacitor
C2
100nF, SMD Ceramic, Low ESR
Close (<5mm) to VSUP1, VSUP2 pins with good ground return
C3
100nF, SMD Ceramic, Low ESR
Close (<3mm) to digital supply pins (EVDD, EVSS) with good ground
return.
The positive analog (VREFH, VDDA) and the digital (EVDD) supply
should be connected right at the C3.
C4
4,7uF, SMD Ceramic, Low ESR
Bulk Capacitor
C5
180pF, SMD Ceramic, Low ESR
Close (<5.0 mm) to LIN pin.
Total Capacitance on LIN has to be below 220 pF.
(Ctotal = CLIN-Pin + C5 + CVaristor ~ 10 pF + 180 pF + 15 pF)
V1(2)
L1
(2)
Varistor Type TDK AVR-M1608C270MBAAB
Optional (close to LIN connector)
SMD Ferrite Bead Type TDK MMZ2012Y202B
Optional, (close to LIN connector)
Notes
1. Freescale does not assume liability, endorse, or want components from external manufactures that are referenced in circuit drawings
or tables. While Freescale offers component recommendations in this configuration, it is the customer’s responsibility to validate their
application.
2. Components are recommended to improve EMC and ESD performance.
908E625
42
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGING DIMENSIONS
PACKAGING
PACKAGING DIMENSIONS
Important: For the most current revision of the package, visit www.freescale.com and do a keyword search on the
98ARL10519D drawing number below. Dimensions shown are provided for reference ONLY.
EK SUFFIX (PB-FREE)
54-PIN
98ARL10519D
ISSUE D
908E625
Analog Integrated Circuit Device Data
Freescale Semiconductor
43
PACKAGING
PACKAGING DIMENSIONS
EK SUFFIX (PB-FREE)
54-PIN
98ARL10519D
ISSUE D
908E625
44
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGING DIMENSIONS
EK SUFFIX (PB-FREE)
54-PIN
98ARL10519D
ISSUE D
908E625
Analog Integrated Circuit Device Data
Freescale Semiconductor
45
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
ADDITIONAL DOCUMENTATION
908E625
THERMAL ADDENDUM (REV 2.0)
Introduction
This thermal addendum ia provided as a supplement to the MM908E625
technical data sheet. The addendum provides thermal performance information
that may be critical in the design and development of system applications. All
electrical, application and packaging information is provided in the data sheet.
54-PIN
SOICW-EP
Package and Thermal Considerations
This MM908E625 is a dual die package. There are two heat sources in the
package independently heating with P1 and P2. This results in two junction
temperatures, TJ1 and TJ2, and a thermal resistance matrix with RθJAmn.
For m, n = 1, RθJA11 is the thermal resistance from Junction 1 to the reference
temperature while only heat source 1 is heating with P1.
For m = 1, n = 2, RθJA12 is the thermal resistance from Junction 1 to the
reference temperature while heat source 2 is heating with P2. This applies to
RθJ21 and RθJ22, respectively.
TJ1
TJ2
=
RθJA11 RθJA12
RθJA21 RθJA22
.
P1
P2
The stated values are solely for a thermal performance comparison of one
package to another in a standardized environment. This methodology is not
meant to and will not predict the performance of a package in an applicationspecific environment. Stated values were obtained by measurement and
simulation according to the standards listed below.
EK SUFFIX (Pb-Free)
98ARL10519D
54-PIN SOICW-EP
Note For package dimensions, refer to
98ARL10519D.
Standards
Table 1. Thermal Performance Comparison
Thermal
Resistance
1 = Power Chip, 2 = Logic Chip [°C/W]
1.0
m = 1,
n=1
m = 1, n = 2
m = 2, n = 1
m = 2,
n=2
RθJAmn (1)(2)
23
20
24
RθJBmn (2)(3)
9.0
6.0
10
RθJAmn (1)(4)
52
47
52
RθJCmn (5)
1.0
0
2.0
Notes:
1. Per JEDEC JESD51-2 at natural convection, still air
condition.
2. 2s2p thermal test board per JEDEC JESD51-7and
JESD51-5.
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
4. Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
5. Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
1.0
0.2
0.2
* All measurements
are in millimeters
Soldermast
openings
54 Terminal SOIC-EP
0.65 mm Pitch
17.9 mm x 7.5 mm Body
10.3 mm x 5.1 mm Exposed Pad
Thermal vias
connected to top
buried plane
908E625
46
Analog Integrated Circuit Device Data
Freescale Semiconductor
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
PTB7/AD7/TBCH1
PTB6/AD6/TBCH0
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
PTB5/AD5
PTB4/AD4
PTB3/AD3
IRQ
RST
PTB1/AD1
PTD0/TACH0/BEMF
PTD1/TACH1
NC
FGEN
BEMF
RST_A
IRQ_A
SS
LIN
NC
NC
HB1
VSUP1
GND1
HB2
VSUP2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Exposed
Pad
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
A
PTA0/KBD0
PTA1/KBD1
PTA2/KBD2
FLSVPP
PTA3/KBD3
PTA4/KBD4
VREFH
VDDA
EVDD
EVSS
VSSA
VREFL
PTE1/RXD
RXD
VSS
PA1
VDD
H1
H2
H3
HVDD
NC
HB4
VSUP3
GND2
HB3
HS
908E625 Pin Connections
54-Pin SOICW-EP
0.65 mm Pitch
17.9 mm x 7.5 mm Body
10.3 mm x 5.1 mm Exposed Pad
Figure 27. Thermal Test Board
Device on Thermal Test Board
Material:
Outline:
Area A:
Ambient Conditions:
Single layer printed circuit board
FR4, 1.6 mm thickness
Cu traces, 0.07 mm thickness
80 mm x 100 mm board area,
including edge connector for thermal
testing
Cu heat-spreading areas on board
surface
Natural convection, still air
Table 14. Thermal Resistance Performance
Thermal
Resistance
RθJAmn
RθJSmn
Area A
(mm2)
1 = Power Chip, 2 = Logic Chip (°C/W)
m = 1,
n=1
m = 1, n = 2
m = 2, n = 1
m = 2,
n=2
0
53
48
53
300
39
34
38
600
35
30
34
0
21
16
20
300
15
11
15
600
14
9.0
13
RθJA is the thermal resistance between die junction and
ambient air.
RθJSmn is the thermal resistance between die junction and
the reference location on the board surface near a center
lead of the package.
This device is a dual die package. Index m indicates the
die that is heated. Index n refers to the number of the die
where the junction temperature is sensed.
908E625
Analog Integrated Circuit Device Data
Freescale Semiconductor
47
REVISION HISTORY
REVISION HISTORY
REVISION
7.0
8.0
9.0
10.0
DATE
9/2010
7/2011
DESCRIPTION OF CHANGES
•
Implemented Revision History page
•
Changed Peak Package Reflow Temperature During Reflow(7)(8) description.
•
Added note (8)
•
Changes to AWD Period Low = 512 tOSC and AWD Period High = 256 tOSC
•
Change to LIN Timing Description
•
Change to Stop Mode Output Voltage (Maximum Output Current 100 μA)
•
Added MM908E625ACEK and MM908E625ACPEK to the ordering information
•
Removed part numbers with DWB suffix
•
Updated Freescale form and style
•
Updated packaging information
10/2011
•
Change to LIN Timing Description
04/2012
•
Removed part number MM908E625ACEK.
•
Updated Freescale form and style
908E625
48
Analog Integrated Circuit Device Data
Freescale Semiconductor
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© 2012 Freescale Semiconductor, Inc.
Document Number: MM908E625
Rev 10
04/2012
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