ESD202-B1-CSP01005 Data Sheet (754 KB, EN)

Protection Device
TVS (Transient Voltage Suppressor)
ESD202-B1-CSP01005
Bi-directional, 5.5 V, 6.5 pF, 01005, RoHS and Halogen Free compliant
ESD202-B1-CSP01005
Data Sheet
Revision 1.4, 2016-04-07
Final
Power Management & Multimarket
Edition 2016-04-07
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2016 Infineon Technologies AG
All Rights Reserved.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com)
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
ESD202-B1-CSP01005
Product Overview
1
Product Overview
1.1
Features
•
ESD / transient protection of high speed data lines according to:
– IEC61000-4-2 (ESD): ±17 kV (air), ±15 kV (contact discharge)
– IEC61000-4-4 (EFT): ±2 kV / ±40 A(5/50 ns)
– IEC61000-4-5 (surge): ±3 A (8/20 µs)
Bi-directional working voltage up to: VRWM = ±5.5 V
Line capacitance: CL = 6.5 pF (typical) at f = 1 MHz
Clamping voltage: VCL = 13 V (typical) at ITLP = 16 A with RDYN = 0.2 Ω (typical)
Very low reverse current:. IR < 1 nA (typical)
Minimized clamping overshoot due to extremely low parasitic inductance
Small form factor SMD Size 01005 and low profile (0.43 mm x 0.23 mm x 0.15 mm)
Bi-directional and symmetric I/V characteristics for optimized design and assembly
Pb-free (RoHS compliant) and halogen free package
•
•
•
•
•
•
•
•
Guidelines for optimized PCB design and assembly process available [2]
1.2
•
•
Application Examples[3]
ESD Protection of highly susceptible IC/ASICs in audio, headset, human digital interfaces
Dedicated solution to boost space saving and high performance in miniaturized modern electronics
1.3
Product Description
a) Pin configuration
b) Schematic diagram
Configutation_Schematic_Diagram.vsd
Figure 1-1 Pin Configuration and Schematic Diagram
Table 1-1
Part Information
Type
Package
Configuration
Marking code
ESD202-B1-CSP01005
WLL-2-2
1 line, bi-directional
A1)
1) The device does not have any marking or date code on the device backside. The marking code is on pad side.
Final Data Sheet
3
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ESD202-B1-CSP01005
Maximum Ratings
2
Maximum Ratings
Table 2-1
Maximum Ratings at TA = 25 °C, unless otherwise specified 1)
Parameter
Symbol
Reverse working voltage
ESD discharge
contact
air
Values
±5.5
VRWM
2)
Unit
V
kV
VESD
±15
±17
Peak pulse power3)
PPK
36
W
Peak pulse current
IPP
±3
A
Operating temperature range
TOP
-55 to 125
°C
Storage temperature
Tstg
-65 to 150
°C
3)
1) Device is electrically symmetrical
2) VESD according to IEC61000-4-2 (R = 330 Ω, C = 150 pF discharge network)
3) Stress pulse: 8/20μs current waveform according to IEC61000-4-5
Attention: Stresses above the max. values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the integrated circuit.
3
Electrical Characteristics
$% & %'
&
%( &
&(
!" !! # Figure 3-1 Definitions of electrical characteristics
Final Data Sheet
4
Revision 1.4, 2016-04-07
ESD202-B1-CSP01005
Electrical Characteristics
Table 3-1
DC Characteristics at TA = 25 °C, unless otherwise specified 1)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note / Test Condition
Breakdown voltage
VBR
6
-
10
V
IBR = 1 mA
Reverse current
IR
-
<1
100
nA
VR = 5.5 V
Unit
Note / Test Condition
pF
VR = 0 V, f = 1 MHz
1) Device is electrically symmetrical
Table 3-2
AC Characteristics at TA = 25 °C, unless otherwise specified
Parameter
Symbol
Line capacitance
Table 3-3
CL
Values
Min.
Typ.
Max.
–
6.5
–
–
6.5
–
VR = 0 V, f = 1 GHz
ESD and Surge Characteristics at TA = 25 °C, unless otherwise specified1)
Parameter
Symbol
2)
Clamping voltage
VCL
3)
Clamping voltage
Dynamic resistance2)
RDYN
Values
Unit
Note / Test Condition
V
ITLP = 16 A, tp = 100 ns
Min.
Typ.
Max.
–
13
–
–
17
–
ITLP = 30 A, tp = 100 ns
–
9.5
–
IPP = 1 A, tp = 8/20 μs
–
12
–
IPP = 3 A, tp = 8/20 μs
–
0.2
–
Ω
tp = 100 ns
1) Device is electrically symmetrical
2) Please refer to Application Note AN210[1]. TLP parameter: Z0 = 50 Ω , tp = 100ns, tr = 0.6 ns.
3) Stress pulse: 8/20μs current waveform according to IEC61000-4-5
Final Data Sheet
5
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ESD202-B1-CSP01005
Typical Characteristics Diagrams
4
Typical Characteristics Diagrams
Typical characteristics diagrams at TA = 25°C, unless otherwise specified
10-3
-4
10
-5
10
10-6
10-7
-8
IR [A]
10
-9
10
10-10
10-11
10-12
-13
10
-14
10
-6
-4
-2
0
VR [V]
2
4
6
Figure 4-1 Reverse leakage current: IR = f(VR)
10
9
8
CL [pF]
7
6
1 GHz
5
4
1 MHz
3
2
1
0
-3
-2.5
-2
-1.5
-1
-0.5
0
0.5
VR [V]
1
1.5
2
2.5
3
Figure 4-2 Line capacitance: CL = f(VR), f = 1 MHz
Final Data Sheet
6
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ESD202-B1-CSP01005
Typical Characteristics Diagrams
50
Scope: 6 GHz, 20 GS/s
VCL-max-peak = 28 V
25
VCL [V]
VCL-30ns-peak = 12 V
0
-25
-50
0
50
100
150
200
tp [ns]
250
300
350
400
450
Figure 4-3 Clamping voltage (ESD): VCL = f(t), 8 kV positive pulse
25
Scope: 6 GHz, 20 GS/s
VCL [V]
0
VCL-max-peak = -28 V
-25
VCL-30ns-peak = -11 V
-50
-50
0
50
100
150
200
tp [ns]
250
300
350
400
450
Figure 4-4 Clamping voltage (ESD): VCL = f(t), 8 kV negative pulse
Final Data Sheet
7
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ESD202-B1-CSP01005
Typical Characteristics Diagrams
50
Scope: 6 GHz, 20 GS/s
VCL-max-peak = 41 V
25
VCL [V]
VCL-30ns-peak = 15 V
0
-25
-50
0
50
100
150
200
tp [ns]
250
300
350
400
450
Figure 4-5 Clamping voltage (ESD): VCL = f(t), 15 kV positive pulse
25
Scope: 6 GHz, 20 GS/s
VCL [V]
0
VCL-max-peak = -41 V
-25
VCL-30ns-peak = -14 V
-50
-50
0
50
100
150
200
tp [ns]
250
300
350
400
450
Figure 4-6 Clamping voltage (ESD): VCL = f(t), 15 kV negative pulse
Final Data Sheet
8
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ESD202-B1-CSP01005
Typical Characteristics Diagrams
30
15
ESD202-B1-CSP01005
RDYN
25
12.5
20
10
15
7.5
10
5
5
2.5
0
0
-5
-2.5
-10
-5
-15
-7.5
Equivalent VIEC [kV]
ITLP [A]
RDYN = 0.2 Ω
RDYN = 0.2 Ω
-20
-10
-25
-12.5
-30
-20
-15
-10
-5
0
5
10
15
-15
20
VTLP [V]
Figure 4-7 Clamping voltage (TLP): ITLP = f(VTLP) [1]
Final Data Sheet
9
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ESD202-B1-CSP01005
Typical Characteristics Diagrams
3.5
3
2.5
2
1.5
1
IPP [A]
0.5
0
-0.5
-1
-1.5
-2
-2.5
-3
-3.5
-12
-10
-8
-6
-4
-2
0
2
VCL [V]
4
6
8
10
12
Figure 4-8 Clamping voltage (Surge): IPP = f(VCL)[1]
Final Data Sheet
10
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ESD202-B1-CSP01005
Typical Characteristics Diagrams
0
Insertion Loss (|S21|) [dB]
1
2
3
4
5
6
7
8
9
10
10-2
ESD202-B1-CSP01005
0.1
1
Frequency [GHz]
10
Figure 4-9 Insertion loss vs. frequency in a 50 Ω system
Final Data Sheet
11
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ESD202-B1-CSP01005
Package Information
5
Package Information
5.1
WLL-2-2
Top view
Bottom view
0.15 ±0.01
0.23 ±0.03
0.28
(0.15)
0.43 ±0.03
2
0.13 ±0.02
1
0.2 ±0.02
SG-WLL-2-2-PO V01
Figure 5-1 WLL-2-2: Package (dimension in mm)
Copper
Solder mask
0.3
0.3
0.15
0.23
0.15
0.23
Stencil apertures
SG-WLL-2-2-FP V01
Figure 5-2 WLL-2-2 Footprint (dimension in mm) Recommendation for Printed Circuit Board Assembly[2]
8
0.5
0.2
2
0.2
0.28
SG-WLL-2-2-TP V01
Figure 5-3 WLL-2-2: Packing (dimension in mm)
Marking on pad-side
Type code
Type code
1
1
1
1
SG-WLL-2-2-MK V02
Figure 5-4 WLL-2-2: Marking example Table 1-1 “Part Information” on Page 3
Final Data Sheet
12
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ESD202-B1-CSP01005
References
References
[1]
Infineon AG - Application Note AN210: Effective ESD Protection design at System Level Using VF-TLP
Characterization Methodology
[2]
Infineon AG - Recommendation for Printed Circuit Board Assembly of Infineon WLL Packages
http://www.infineon.com/dgdl/?fileId=db3a304344f7b4f9014503db540027c0 [3]
Infineon AG - Application Note AN392: TVS Diodes in ChipScalePackage reduce size and save cost
Final Data Sheet
8
Revision 1.4, 2016-04-07
ESD202-B1-CSP01005
Revision History: Rev.1.3, 2016-02-05
Page or Item
Subjects (major changes since previous revision)
Revision 1.4, 2016-04-07
6
Update of Figure 4-2
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Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of
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Last Trademarks Update 2010-10-26
Final Data Sheet
9
Revision 1.4, 2016-04-07
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Published by Infineon Technologies AG
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