FR-DSU3 PGA401P Evaluation Board for the DSU-FR20/30 Emulator Product Specifications * Some of these specifications are undetermined because of product developments. Specifications may change in the future. * This Specifications Manual also serves as design specifications. FR-DSU3 PGA401P EVALUATION BOARD FOR THE DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS Contents 1. Application .............................................................................................4 2. Composition of the Product..................................................................5 3. Composition of the System ..................................................................6 4. Machine External Appearance..............................................................7 4.1 Machine External Appearance..................................................................... 7 4.2 Usage of the Evaluation Board .................................................................... 8 5. General Specifications ..........................................................................9 6. Function Specifications .............................................................................................10 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 Function Specifications................................................................................ 10 Composition of the Main Components......................................................... 11 Evaluation Pin Assignment.......................................................................... 12 DSU Connector Pin Assignment.................................................................. 12 Header I/F Connector Pin Assignment ........................................................ 13 SSRAM Specifications ................................................................................ 15 FLASH Specifications.................................................................................. 15 SRAM Specifications................................................................................... 15 7. Detailed Specifications..........................................................................16 7.1 7.2 7.3 7.4 7.5 7.6 Block Drawing ............................................................................................. 16 Trace Memory Block.................................................................................... 18 User Memory Block ..................................................................................... 19 Processing of the Reset Pin ........................................................................ 22 Power Supply Unit....................................................................................... 22 Other Peripheral Blocks............................................................................... 23 8. AC Characteristics.................................................................................24 8.1 8.2 8.3 8.4 8.5 8.6 Trace Memory Read Timing ........................................................................ 24 Trace Memory Write Timing......................................................................... 26 FLASH Read Timing.................................................................................... 27 FLASH Write Timing.................................................................................... 28 SRAM Read Timing..................................................................................... 29 SRAM Write Timing ..................................................................................... 30 9 Control Items...........................................................................................31 9.1 Power ON and Power OFF Order................................................................ 31 9.2 Control Items............................................................................................... 32 2 FR-DSU3 PGA401P EVALUATION BOARD FOR THE DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS Figures Figure 1 Composition of the System .................................................................................6 Figure 2 External Appearance of the Evaluation Board ....................................................7 Figure 3 Header I/F Cable Connections ...........................................................................7 Figure 4 Example 1 of Evaluation Board Usage ................................................................8 Figure 5 Example 2 of Evaluation Board Usage ................................................................8 Figure 6 shows the Block Drawing of the Evaluation Board...............................................16 Figure 7 Wiring of the Trace Memory and Evaluation Chip................................................18 Figure 8 User Memory Block ............................................................................................19 Figure 9 CS and CLK Switcher Block................................................................................21 Figure 10 Processing of the Reset Pin..............................................................................22 Figure 11 Power Supply Unit ............................................................................................22 Figure 12 Other Peripheral Blocks ....................................................................................23 Figure 13 Trace Memory Read Timing..............................................................................22 Figure 14 Trace Memory Write Timing ..............................................................................26 Figure 15 FLASH Read Timing .........................................................................................27 Figure 16 FLASH Write Timing .........................................................................................28 Figure 17 SRAM Read Timing ..........................................................................................29 Figure 18 SRAM Write Timing ..........................................................................................30 Tables Table 1 General Specifications .........................................................................................9 Table 2 Evaluation Board Function Specifications .............................................................10 Table 3 Composition of the Main Component....................................................................11 Table 4 Header I/F Connector 1 Pin Assignment...............................................................13 Table 5 Header I/F Connector 2 Pin Assignment...............................................................14 Table 6 SSRAM Specifications .........................................................................................15 Table 7 FLASH Specifications...........................................................................................15 Table 8 SRAM Specifications............................................................................................15 Table 9 CS and CLK Switcher Block Pin Names and Functions ........................................20 Table 10 Control Board.....................................................................................................32 3 FR-DSU3 PGA401P EVALUATION BOARD FOR THE DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS 1. Application This manual applies to the product specifications and design specifications for the DSU-FR20/30 Emulator MB2197-01 (called Emulator below) FRDSU3 PGA401P Evaluation Board (called evaluation board below). The objective MCU of this product is MB91V360. 4 FR-DSU3 PGA401P EVALUATION BOARD FOR THE DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS 2. Composition of the Product The following shows the composition of the product. FR-DSU3 PGA401P Evaluation Board (Package Number: MB2197-1XX) Evaluation Board Header I/F Cable (Standard: 5 cm) × 2 Pcs. Header I/F Cable (Long: 20 cm) × 2 Pcs. Hardware Manual Note: The Header I/F Cable (Long) is not normally used. l Parts Sold Separately • QFP208P Header for the MB2197-110 Package Number: MB2197-1XX • Evaluation Chip Package Number: MB91V360 • QFP208PIC Socket Package Number: NQPACK208SD * • QFP208PIC Socket Cover Package Number: HQPACK208SD * • Emulator for the DSU-FR20/30 Package Number: MB2197-01 In this manual, we call the "MB2197-1XX QFP208P Header" a "Header Board." This product functions as an emulation adapter for the evaluation chip by combining with a Header Board that conforms to the objective MCU. Refer to the QFP208P Header for MB2197-1XX Product Specifications Manual for details concerning the Header Board. The QFP208 Header for MB2197-1XX conforms to MB91F361 (QFP-208). * Attached to the QFP208P Header for MB2197-1XX. 5 FR-DSU3 PGA401P EVALUATION BOARD FOR THE DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS 3. Composition of the System The following shows the composition of the Evaluation Board system. Personal Computer External Power Supply +5 V RS232C Cable or LAN Cable DSU-FR20 DSU Emulator DSU Cable (MB2197 01) DSU Connector MB91V360 Evaluation Board Header I/F Cable (× 2 Pcs. Standard or Long) Header Board Header I/F Connector (2 For Each Board) QFP208P Header for MB2197-1XX User Board Figure 1 Composition of the System Notes: 1. Refer to the "DSU-FR20/30 Emulator MB2197-01 Hardware Manual" for details concerning the DSU-FR20/30 Emulator. 2. Refer to the "QFP208P Header for MB2197-1XX Product Specifications Manual" for details concerning the Header Board. 3. The Header Board is connected to the specified MCU socket on the user board. Refer to the "Header Board Product Specification Manual" for details concerning the specific MCU socket. 6 FR-DSU3 PGA401P EVALUATION BOARD FOR THE DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS 4. Machine External Appearance 4.1 Machine External Appearance Figure 2 shows the external appearance of the Evaluation Board. Figure 3 shows the Header I/F Cable connections. Board Suspension Hole Header I/F Cable x 2. (Standard: 5 cm or Long: 20 cm) IC Socket for Oscillator DSU Connector Monitor Pin Short Socket IC Socket for Evaluation Chip To Header Board Trace Memory Trace Memory Trace Memory Header I/F Connector 2 (Established on Back Side) SRAM FLASH Connector for External Power Supply Evaluation Board Header I/F Connector 1 (Established on Back Side) An Insulation Board is mounted on the backside. Board Suspension Hole Figure 2 External Appearance of the Evaluation Board Evaluation Board Header Board Header I/F Cable Figure 3 Header I/F Cable Connections 7 Insulation Board FR-DSU3 PGA401P EVALUATION BOARD FOR THE DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS 4.2 Usage of the Evaluation Board Figure 4 and Figure 5 show examples of the usage of the Evaluation Board. Header Board Evaluation Board The Header Board is fastened to the specified IC socket on the User Board MCU. Insulation Board User Board Figure 4 Example 1 of Evaluation Board Usage Suspend the Evaluation Board using a string or the equivalent. Evaluation Board Fasten the DSU Cable to the Evaluation Board using tape or the equivalent. Header Board User Board Figure 5 Example 2 of Evaluation Board Usage 8 FR-DSU3 PGA401P EVALUATION BOARD FOR THE DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS 5. General Specifications Table 1 shows the general specifications of the Evaluation Board. Item Content Remarks Product Name PGA401P Evaluation Board for FR-DSU3 Power Supply 1 VCC (Evaluation Chip 5 V (Depends on Evaluation Chip Rating) *1 5 V ± 5% and VCC2 ≥ VCC1 Current Value Not Decided. *2 Operating Temperature and Storing 0º to 35ºC (When Operating), -20º to 70ºC Operating Humidity Temperature (When Stored) and Storing Humidity Operating Temperature and Storing 30% to 80% (When Operating), 30% to 90% Operating Humidity Temperature (When Stored) and Storing Humidity Power Supply) Power Supply 2 VCC (Evaluation Board Power Supply) External Dimension Weight Evaluation Board Evaluation Board Header I/F Cable Cable Length 5 cm (Standard) Header I/F Cable (Long) Cable Length 20 cm Evaluation Board Evaluation Board Table 1 General Specifications *1. This is supplied from the User Board via the Header Board. This is used as the Evaluation Chip VDD Terminal and the Buffer IC Power Supply. We will design so that the product will operate under 3.3 V. That will allow for tentative usage of the MB91V300 which runs under 3.3 V operating specifications. However, we do not guarantee the product will run under 3.3 V at the product level. *2. This supplies a stable power supply from an external source. This power supply creates the 3.3 V of power (VCC3) for the circuits in the Evaluation Board. 9 FR-DSU3 PGA401P EVALUATION BOARD FOR THE DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS 6. Function Specifications 6.1 Function Specifications Table 2 shows the Evaluation Board function specifications. Item Content DSU Connector This is used in conjunction with the QFP208 Header for MB2197-1XX and functions as the MB91V360 adapter. Header I/F Connector Remarks 3 SSRAM (64 K words × 32 bit) are mounted onto the board as the Trace Memory for FR-DSU3. Trace Memory User Subrogate Memory FLASH x 2 (256 K word × 32 bit) SRAM x 2 (256 K word × 32 bit) are mounted. This uses a Short Plug to switch the CLK (2 System) Signal between the signals from the User Board and the adapter. CLK (2 Switcher Systems) Signal This uses an oscillator as the power supply of the CLK signal on the User Board to supply the CLK signal from the User Board. You need to connect an oscillator to the oscillator IC socket located on the Evaluation Board to supply the CLK signal from the Evaluation Board. CS Signal Switcher This uses a Short Plug to switch the output destination of the Evaluation Chip CSOX to CS7X signal to the User Board FLASH and SRAM. C Pin Control This uses a Short Plug to add a capacitor to the VCC3/C on the Evaluation Board. The Low Path Filter is mounted onto the Evaluation Board. This uses a Short Plug to switch to the User Board. Low Path Filter An IC Socket is mounted. Tracer Switcher Power Supply The Short Plug switches the Tracer power supply to VCC1 when the VCC1 power supply is 3 V. Table 2 Evaluation Board Function Specifications 10 FR-DSU3 PGA401P EVALUATION BOARD FOR THE DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS 6.2 Composition of the Main Components Table 3 shows the composition of the main components. Item Evaluation Chip DSU Connector Content Remarks Package Number: MB91V360 PGA401 Pin (Fujitsu) × 1 * 30 Pin FPC Connector (Right Angle) × 1 Package Number: FH10A-30S-1SH (Hirose Electric) PGA401 Pin IC Socket × 1 IC Socket Package Number: 2401-1335-00-3302 (Sumitomo 3M) Header I/F Cable Connector Evaluation Board 100 Pin SMT Type Connector (Straight) × 2 Package Number: FX2-100P-1.27SVL (Hirose Electric) FLASH Package Number: MBM29LV400T-10PFTN (Fujitsu) × 2 SRAM Package Number: TC55V16256FT-12 (Toshiba) × 2 Package Number: HD74LVC244AFP (Hitachi) × 3 Buffer IC TC74LVXC3245FS (Toshiba) × 4 Trace Memory Package Number: MT58LC64K32D9LG-11 (Micron) 3 Pin Short Plug (3 x 4 Rows) × 6 Short Plug Package Number: FFC-12NSM1 (Honda Tsushin) IC Socket for CLK Power Connector Header I/F Cable Supply 300 MIL 8 Pin IC Socket x 3 Package Number: FCN-064M008-H/3A (Fujitsu) Package Number: ML-70B2P (Sato Parts) Header for 100 Pin Socket Type Bracket Cable × 2 Cable Header Package Number: FX2BA-100S - 1.27 R (Hirose Electric) Table 3 Composition of the Main Component * The Evaluation Chip is sold separately. Also, refer to the Evaluation Chip Data Sheet for details concerning the Evaluation Chip specifications. 11 FR-DSU3 PGA401P EVALUATION BOARD FOR THE DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS 6.3 Evaluation Pin Assignment Refer to the MB91V360 Data Sheet for details on the Evaluation Pin assignment. 6.4 DSU Connector Pin Assignment Refer to the DSU-FR20/30 Emulation Hardware Manual for details on the DSU Connector Pin assignment. 12 FR-DSU3 PGA401P EVALUATION BOARD FOR THE DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS 6.5 Header I/F Connector Pin Assignment Tables 4 and 5 show the pin assignments of the Header I/F Connectors 1 and 2. Also, the numbers of the pins in the following tables match the pin numbers in the Connector Data Sheet. Connector A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 MB91V360 MB91F361 189 76 81 190 134 248 72 70 68 66 135 249 36 303 86 138 250 195 38 251 39 40 139 89 140 254 91 199 255 92 356 256 144 357 310 258 203 93 204 260 45 148 95 206 62 60 58 56 54 50 48 46 44 42 40 38 36 34 32 30 28 24 22 20 18 16 14 12 10 8 6 4 2 208 206 204 202 200 47 2 150 48 151 49 263 196 194 192 190 188 186 184 Pin name VSS DA1 AVSS AN6 AN4 AN2 AN0 AVCC DACK0 AN15 AN13 AN11 AN9 CS3X CS1X AH/BOOT ALE WR3X WR1X RDX BGRNTX CS6X CS4X A19 A17 A15 A13 A11 A9 A7 A5 A3 A1 D31 D29 D27 D25 D23 D21 D19 D17 D15 VDD D13 D11 D9 D7 D5 D3 D1 Connector B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 MB91V360 132 246 133 247 34 82 300 84 193 85 302 136 37 351 137 194 87 252 304 88 305 196 43 142 307 143 44 308 200 309 257 201 202 146 259 147 312 94 205 1 46 MB91F361 77 75 73 71 69 67 65 63 61 59 57 55 53 49 47 45 43 41 39 37 35 33 31 29 27 23 21 19 17 15 13 11 9 7 5 3 1 207 205 203 201 261 313 149 262 96 207 3 264 197 195 193 191 189 187 185 183 Table 4 Header I/F Connector 1 Pin Assignment 13 Pin name ALARM DA0 AN7 AN5 AN3 AN1 AVRH DEOP0 DREQ0 AN14 AN12 AN10 AN8 CS2X CS0X CLK AS WR2X WR0X BRQ RDY CS5X A20 A18 A16 A14 A12 A10 A8 A6 A4 A2 A0 D30 D28 D26 D24 D22 D20 D18 D16 VSS D14 D12 D10 D8 D6 D4 D2 D0 FR-DSU3 PGA401P EVALUATION BOARD FOR THE DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS Connector M B 9 1 V 3 6 0 M B 9 1 F 3 6 1 P i n n a m e Connector M B 9 1 V 3 6 0 M B 9 1 F 3 6 1 A1 58 130 SOT4 B1 109 129 A2 165 128 SDA B2 221 127 A3 61 126 SGO B3 59 125 A4 325 124 CPO B4 164 121 A5 163 122 X1A B5 29 119 A6 291 120 X1 B6 126 117 A7 VDDX B7 30 115 A8 292 116 MONCLK B8 239 113 A9 182 114 HSTX B9 293 111 A10 31 112 MD1 B10 183 109 A11 VSS B11 128 107 A12 78 108 OUT2 B12 32 105 A13 184 106 OUT0 B13 129 103 A14 240 104 IN2 B14 294 101 A15 79 102 IN0 B15 130 99 A16 185 100 INT6 B16 33 97 A17 241 98 INT4 B17 295 95 A18 80 96 INT2 B18 A19 344 94 INT0 B19 186 91 A20 VDD B20 296 89 A21 242 90 LED6 B21 243 87 A22 131 88 LED4 B22 187 85 A23 345 86 LED2 B23 297 83 A24 346 84 LED0 B24 245 81 A25 188 8 2C P U T E S T X B25 A26 298 80 ATGX B26 A27 VDD B27 315 179 A28 99 180 P W M 2 M 3 B28 153 177 A29 98 178 P W M 1 M 3 B29 152 175 A30 HVDD B30 209 173 A31 51 174 P W M 2 P 2 B31 52 169 A32 210 172 P W M 1 P 2 B32 53 167 A33 7 170 P W M 2 M 1 B33 154 165 A34 8 168 P W M 1 M 1 B34 211 163 A35 101 164 P W M 2 P 0 B35 A36 9 162 P W M 1 P 0 B36 102 159 A37 10 160 VDD int. B37 156 157 A38 VSS B38 103 155 A39 212 156 SIN2 B39 157 153 A40 55 154 SIN1 B40 269 151 A41 104 152 SIN0 B41 270 149 A42 320 150 TX2 B42 215 147 A43 105 148 TX1 B43 A44 321 146 TX0 B44 159 143 A45 322 142 OCPA6 B45 160 141 A46 217 140 OCPA4 B46 272 139 A47 106 138 OCPA2 B47 161 137 A48 218 136 OCPA0 B48 107 135 A49 57 134 SOT3 B49 219 133 A50 12 132 SCK4 B50 108 131 Table 5 Header I/F Connector 2 Pin Assignment 14 Pin name SCL SGA VCI X0A X0 SELCLK INITX MD2 MD0 OUT3 OUT1 IN3 IN1 INT7 INT5 INT3 INT1 VSS LED7 LED5 LED3 LED1 LTESTX TESTX VDD HVSS PWM2P3 PWM1P3 PWM2M2 PWM1M2 PWM2P1 PWM1P1 PWM2M0 PWM1M0 HVSS VCC3/C SOT2 SOT1 SOT0 RX2 RX1 RX0 VSS OCPA7 OCPA5 OCPA3 OCPA1 SCK3 SIN3 SIN4 FR-DSU3 PGA401P EVALUATION BOARD FOR THE DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS 6.6 SSRAM Specifications Table 6 shows the specifications of the SSRAM. Item Content Package Number MT58LC64K32D9LG11 Manufacturer Micron Corporation Capacity 64 K Words Bus Width 32 bits Power Voltage Supply Access Time Remarks 3.3 V ( +10/ -5%) 7 ns Table 6 SSRAM Specifications 6.7 FLASH Specifications Table 7 shows the FLASH specifications. Item Content Package Number MBM29LV400T-10PFTN Manufacturer Fujitsu Capacity 64 K Words Bus Width 16 bits Power Voltage Supply Access Time Content 3.3 V ( +10/ -5%) 100 ns Table 7 FLASH Specifications 6.8 SRAM Specifications Table 8 shows the SRAM specifications. Item Content Package Number TC55V16256FT-12 Manufacturer Toshiba Capacity 256 K Words Bus Width 16 bits Power Supply Voltage 3.3 V ( +10/ -5%) Access Time 12 ns Table 8 SRAM Specifications 15 Content FR-DSU3 PGA401P EVALUATION BOARD FOR THE DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS 7. Detailed Specifications The values of the resistors, etc. will be determined after function evaluations because some chip specifications have not yet been determined. 7.1 Block Drawing Figure 7 shows the Block Drawing of the Evaluation Board. Evaluation Board FLASH Bus for Trace Trace Memory Memory Header I/F Block SRAM Evaluation Chip User Bus Trace Memory Block CLK xCS Switcher Header I/F Connector × 2 Xx User Memory Block To Header Board Emulator Bus Switcher Block DSU Connector Block DSU Connector Power Supply Unit Power Supply Connector Figure 6. shows the Block Drawing of the Evaluation Board. 16 FR-DSU3 PGA401P EVALUATION BOARD FOR THE DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS The details concerning the Trace Block, User Memory Block, Switcher Block and Evaluation Chip Reset Pin are explained on the following pages. The DSU Block is wired directly to all Evaluation Chips and Header I/F connector pins, excluding the DSU connector's *RSTIN Pin. See 7.4 for details concerning the processing of the *RSTIN Pin. The Header I/F Block is wired directly to all Evaluation Chips and Header I/F connector pins, excluding the Header I/F Connector's CS0X to CS6X, X0, X1, X0A, X1A and INITX Pins. See 7.3 for details concerning the processing of the CS0X to CS6X, X0, X1, X0A, X1A and INITX Pins. See 7.4 for details concerning the processing of the INITX Pin. See 7.6 for details concerning the processing of the C Pin and Low Path Filter. 17 FR-DSU3 PGA401P EVALUATION BOARD FOR THE DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS 7.2 Trace Memory Block Figure 7 shows the wiring of the Trace Memory and the Evaluation Chip. (The Trace Memory Power Supply is VCCT.) VCCT VCCT MT58LC64K32D9LG-11 VDD3 TCLK TDT [31:00] TAD[15:00] TDT[31:00] 16 16 TCE1X TADSCX TWRX TOEX CLK DQ[31:0] CE2 xCE2 A[15:0] xBWE xCE xADSC xGW xOE xBW[4:1] xADSP MODE ZZ xADV 4 MB91V360 MT58LC64K32D9LG-11 TDT[63:32 ] 16 CLK DQ[31:0] CS2 xCE2 A[15:0] xCE xBWE 4 xBW[4:1] xADSC xADSP xGW xOE MODE ZZ xADV MT58LC64K32D9LG-11 TDT [68:64] 16 CLK DQ[4:0] A[15:0] xCE CE2 xCE2 xBWE xBW[4:1] xADSC xADSP xGW xOE MODE ZZ DQ[31:5] xADV Figure 7 Wiring of the Trace Memory and Evaluation Chip 18 4 FR-DSU3 PGA401P EVALUATION BOARD FOR THE DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS 7.3 User Memory Block Figure 8 shows the wiring of the User Memory Block. Also, Table 9 and Figure 9 show the functions of the CLK and CS Switcher Blocks. VCC1 VCC1 MB91V360 VCC3 VCC3 TC74LVXC MA[19:2] MD[31:16] xMRD xMW xFCS 3245×4 VDD B D[31:0] A DIR xG A[19:2] RDX WR3X WR2X HD74LVC244 ×4 WR1X WR0X MA[19:2] MD[15:0] xMRD xMWR2 xFCS CS7x-CSOX X1 X0 xG X1A A0A PALLV 22V10-7 XMRD xMWR3 xMWR2 xMWR1 xMWR0 xFCS xSCS X0A X1A xSWR xSBE0 xSBE1 xSBE2 xSBE3 xEXG EXDIR X0 X1 CS7X-CS0X xFLCS xSRCS xUCS6-0 MA[19:2] MD[31:16] xMRD xSWR xSBE0 xSBE1 10 KΩ A[17:0] D[15:0] RDX WR CS MBM29LV400T -10PFTN A[17:0] D[15:0] RDX WR CS TC55V16256 FT-12 A[17:0] D[15:0] RDX WR UB LB CS 10 KΩ 10 KΩ Header I/F Connector MA[19:2] MD[15:0] xMRD xSWR xSBE2 xSBE3 UX1 UX0 UX1A UX0A CS,CLK Switcher Block MBM29LV40 0T-10PFTN xSWR = xMWR3 + xMWR1 + xMWR1 + xMWR0 xSBE3 = xSCS (xMRD + xMWR3); xSBE2 = xSCS (xMRD + xMWR2); xSBE1 = xSCS (xMRD + xMWR1); xSBE0 = xSCS (xMRD + xMWR0); EXDIR = !xMRD; PALLV22V10-7 Logic Type XEXG = (xFCS + xSCS) (xMRD + xMWR3 + xMWR2 + xMWR1 + xMWR0) Figure 8 User Memory Block 19 TC55V16256 FT-12 A[17:0] D[15:0] RDX WR UB LB CS FR-DSU3 PGA401P EVALUATION BOARD FOR THE DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS Function CS Signal Input FLASH Chip Select Signal Input xSRCS SRAM Chip Select Signal Input xUCS6 to 0 User Chip Select Input UX0,UX1 CLK Signal Input from the User Board UX0A,UX1A SUBCLK Signal Input from the User Board X0,X1 The CLK signals from the Evaluation Board and from the User Board are supplied to the Evaluation Chip. Use a Short Plug to switch signals. X0A,X1A The SUBCLK signals from the Evaluation Board and from the User Board are supplied to the Evaluation Chip. Use a Short Plug to switch signals. Table 9 CS and CLK Switcher Block Pin Names and Functions 20 DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS VCC1 VCC1 10 K 10 K VCC1 10 K xFLCS EVA SRAM FLASH xCS7 xUCS6-xUCS0 USER EVA FLASH SRAM xCS6-xCS0 USER EVA IC Socket UX0 22 pF 3MHz X0 USER EVA USER EVA 22 pF UX1 X1 IC Socket UX0A 33 pF 32.768kHz X0A USER EVA UX1A X1A Figure 9 CS and CLK Switcher Block 21 33 pF FR-DSU3 PGA401P EVALUATION BOARD FOR THE DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS 7.4 Processing of the Reset Pin Figure 10 shows the processing of the Reset Pin. MV91V360 Header I/F Connector DSU Connector (User Board) INITX RST RSTX xRSTI RST INIT LVC14 × 2 Figure 10 Processing of the Reset Pin 7.5 Power Supply Unit Figure 11 shows the Power Supply Unit. VCC1 External Power Supply Connector +5 V VCC3 EK14 LT1529CT-3.3 (VCC2) 47uF O I + SEN XSTB GND 47uF + GND 100K V360 VCC (VCCT) T V300 GND Figure 11 Power Supply Unit 22 FR-DSU3 PGA401P EVALUATION BOARD FOR THE DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS 7.6 Other Peripheral Blocks The following shows the C Pin (VCC3/C) and Low Path Filter (CPO and VCO) circuits. The Short Plug switches the C Pin ON and OFF. The Short Plug switches the Low Path Filter between the User Board and the Evaluation Board. C VCC3/C VCC3/C OPEN 0.1uF EVA USER CPO CPO EVA USER VCO VCO RA RB CP MB91V360 IC Socket ICƒ\ƒPƒbƒg Header I/F ƒwƒbƒ_I/F Connector ƒRƒlƒNƒ^ (User) (USER) Figure 12 Other Peripheral Blocks The Low Path Filter is mounted onto the IC Socket and tuning is possible. (When this is not going to be used, the Low Path Filter will not be mounted.) 23 FR-DSU3 PGA401P EVALUATION BOARD FOR THE DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS 8. AC Characteristics Because the AC Specifications have not yet been determined, Fujitsu will rewrite them when MB91V360AC has been disclosed. 8.1 Trace Memory Read Timing Figure 13 shows the TCLK 64 MHz Trace Memory Read Timing tCYC CLK tss tCL tCH tHS TADSCX tSA tHA TAD[15:0] ADDRESS TWRX TCE1X TOEX ttCHSV TDT[68:0] ttCHSV DATA Figure 13 Trace Memory Read Timing 24 FR-DSU3 PGA401P EVALUATION BOARD FOR THE DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS Value Symbol Calculated Value Meaning Units Min Max Min Max tCYC Cycle Time 15 -- 15.6 -- ns tCH TCLK H Width 5 -- 5 -- ns tCL TCLK L Width 5 -- 5 -- ns tSA Address Setup Time 2.5 -- 2.8 -- ns tHA Address Hold Time 0.5 -- 59.6 -- ns tSS Address Status Setup Time 2.5 -- 2.8 -- ns tHS Address Status Hold Time 0.5 -- 59.6 -- ns ttCHSV Data Setup Time 15 -- 17.4 -- ns ttCHSX Data Hold Time 0 -- 31.2 -- ns 25 FR-DSU3 PGA401P EVALUATION BOARD FOR THE DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS 8.2 Trace Memory Write Timing Figure 14 shows the TCLK 64 MHz Trace Memory Write Timing CLK tSS tHS TADSCX tSA tHA ADDRESS TAD [15:0] tSW tHW TWRX tSC tHC TCE1X TOEX tSD tHD TDT[68:0] Figure 14 Trace Memory Write Timing Symbol Meaning tSA Meaning Calculated Value Units Min Max Min Max Address Setup Time 2.5 -- 2.8 -- ns tHA Address Hold Time 0.5 -- 12.8 -- ns tSS Address Status Setup Time 2.5 -- 2.8 -- ns tHS Address Status Hold Time 0.5 -- 12.8 -- ns tSD Data Setup Time 2.5 -- 2.8 -- ns tHD Data Hold Time 0.5 -- 12.8 -- ns tSW TWRX Setup Time 2.5 -- 2.8 -- ns tHW TWRX Hold Time 0.5 -- 12.8 -- ns tSC TCE1X Setup Time 2.5 -- 2.8 -- ns tHC TCE1X Hold Time 0.5 -- 12.8 -- ns 26 FR-DSU3 PGA401P EVALUATION BOARD FOR THE DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS 8.3 FLASH Read Timing There are 3 Wait Accesses when read accessing FLASH. (When CLK = 32 kHz) Figure 15 shows the FLASH Read Timing. CLK 15 ns A[17:0] 15 ns CS0X 6 ns 102.5to116ns RDX ts th D[31:0] Value Symbol Calculated Value Meaning min max min max Units ts Data Setup Time for ↑ R 10 -- 17.1 -- ns th Data Hold Time for ↑ R 0 -- 1 -- ns Figure 15 FLASH Read Timing ts, shown in the figure above, changes due to the Clock Frequency (Cycle Time) or the Wait Count. The relationships between the ts calculation value, cycle time and the Wait Count are shown below. ω: Wait Count; τ: Cycle Count (ω + 1.5) τ +133.5 = ts ≥ 10................(1) Insert the following to complete the above formula. Block Frequency Count Minimum 11.2 MHz (Cycle Time 89.2 ns): Minimum 1 Wait Block Frequency Count Minimum 18.7 MHz (Cycle Time 53.4 ns): Minimum 2 Waits Block Frequency Count Minimum 26.2 MHz (Cycle Time 38.1 ns): Minimum 3 Waits 27 FR-DSU3 PGA401P EVALUATION BOARD FOR THE DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS 8.4 FLASH Write Timing There are 3 Wait Accesses when write accessing FLASH. (When CLK = 32 kHz) Figure 16 shows the FLASH Write Timing. CLK 16.5 to 22ns A[17:0] 16.5 to 22ns CS0X 7.5 to 14ns WR0X 2 to 16.5ns th ts D[31:0] Figure 16 FLASH Write Timing Value Symbol Calculated Value Meaning min max min max Units ts Data Setup Time for ↑ W 50 -- 102 -- ns th Data Hold Time for ↑ W 0 -- 1 -- ns 28 FR-DSU3 PGA401P EVALUATION BOARD FOR THE DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS 8.5 SRAM Read Timing There is 1 Wait Access when read accessing the SRAM. Figure 17 shows the SRAM Read Timing. CLK 15 ns A[17:0] 15 ns CS0X 6 ns RDX 9.5 to 29.5ns th ts D[31:0] Figure 17 SRAM Read Timing Value Symbol Calculated Value Meaning min max min max Units ts Data Setup Time for ↑ R 10 -- 34.5 -- ns th Data Hold Time for ↑ R 0 -- 1 -- ns ts, shown in the figure above, changes due to the Clock Frequency (Cycle Time) or the Wait Count. The relationships between the ts calculation value, cycle time and the Wait Count are shown below. ω: Wait Count; τ: Cycle Count (ω + 1) τ -28 = ts ≥ 10 ........................ (1) Insert the following to complete the above formula. Block Frequency Count Minimum 26.3 MHz (Cycle Time 38 ns): Minimum 1 Wait 29 FR-DSU3 PGA401P EVALUATION BOARD FOR THE DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS 8.6 SRAM Write Timing There are 1 Wait Accesses when write accessing SRAM. Figure 18 shows the SRAM Write Timing. CLK 16.5 to 23ns A[17:0] 16.5 to 23ns CS0X 8.5 to 22.5ns WR0X 2 to 16.5ns th ts D[31:0] Value Symbol Calculated Value Meaning min max min max Units ts Data Setup Time for ↑ W 7 -- 32 -- ns th Data Hold Time for ↑ W 0 -- 1 -- ns Figure 18 SRAM Write Timing 30 FR-DSU3 PGA401P EVALUATION BOARD FOR THE DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS 9. Control Items 9.1 Power ON and Power OFF Order The following shows the order for turning ON the system power supply when using the Evaluation Board. Turn ON the Emulator Power Supply. Turn ON the Evaluation Board Power Supply (External Power Supply). Turn ON the User Board Power Supply. The following shows the order for turning OFF the system power supply when using the Evaluation Board. Turn OFF the User Board Power Supply. Turn OFF the Evaluation Board Power Supply (External Power Supply). Turn OFF the Emulator Power Supply. 31 FR-DSU3 PGA401P EVALUATION BOARD FOR THE DSU-FR20/30 EMULATOR PRODUCT SPECIFICATIONS 9.2 Control Items The following shows the control items when using the Evaluation Board. IC Socket for Specific MCU 1 Sockets must always be mounted for the MCU on the User Board when using an Evaluation Board. Use the specified IC Socket. Resetting the Evaluation Chip. 2 The Emulator controls the Evaluation Chip INITX pin. Reset is input from the User System via the Emulator instead of being directly input to the Evaluation Chip. For that reason, reset timing is delayed several clocks by the reset timing of the User System. Also, the Emulator Reset Command resets only the Evaluation Chip. It does not reset the User System. Supplying a CLK Signal from the User Board. 3 Use an oscillator to supply power for the CLK signal on the User Board when supplying CLK signals from the User Board to the Evaluation Chip. Using a Header I/F Cable (Long). 4 It is possible to use this cable when there the MCU Clock frequency is low or when there is extremely little chance of putting a load on the User Pins. Normally, use the standard cable. Using User Memory An External Bus is possible only when there is a 32 Bit Bus width. It is not possible when using 8 or 16 bit widths. 5 However, it is possible to drive the D23-0 when FLASH or SRAM have entered Mode Fetch. Memory will correctly fetch the mode data. All Data Bus are driven regardless of access size when reading both FLASH and SRAM. You can access words or half-words when FLASH is in the Write mode. You can access words, half-words and bytes when SRAM is in the Write mode. Neither FLASH nor SRAM support DMA by an external Bus Master. Selecting Chips 6 You cannot use the User Board when you are using the User Board on the Evaluation Board of CS6X to CS0X. Only 1 FLASH and SRAM can be set in the User Memory of CS7X to CS0X. Table 10 Control Board 32