HT16LK24v110.pdf

HT16LK24
RAM Mapping 67×4/63×8
LCD Driver with Key Scan
Feature
Applications
• Logic Operating Voltage:1.8V ~ 5.5V
• Leisure products
• LCD Operating Voltage (VLCD):2.4V ~ 6.0V
• Games
• Internal 32kHz RC oscillator
• Telephone display
• Duty:1/1 (static), 1/2, 1/3, 1/4 or 1/8; Bias: 1/1 (static), 1/2, 1/3 or 1/4
• Audio Combo display
• Internal LCD bias generation with voltage-follower
buffers
• Kitchen Appliance display
• Video Player display
• Measurement equipment display
• External VLCD pin to supply LCD operating voltage
• Household appliance
• Integrated regulator to adjust LCD operating voltage:
3.0V, 3.2V, 3.3V, 3.4V, 4.4V, 4.5V, 4.6V, 5.0V
• Consumer electronics
• Four Selectable LCD frame frequencies: 64Hz,
85.3Hz, 128Hz or 170.6Hz
General Description
• Integrated LED driver up to 12 channels
The HT16LK24 device is a memory mapping and
multi-function LCD controller driver. The Display
segments of the device may be 67 patterns for 1/1
duty display, 134 patterns for 1/2 duty display, 201
patterns for 1/3 duty display, 268 patterns for 1/4 duty
display or 504 patterns for 1/8 duty display. It can also
support LED drive outputs on certain Segment pins
with up to 128 levels luminance PWM control. The
key scan circuitry which can be organized into a 4×12
matrix is also integrated in this device. The software
configuration feature of the HT16LK24 device makes
it suitable for multiple LCD applications including
LCD modules and display subsystems. The HT16LK24
device communicates with most microprocessors/
microcontrollers via a two-wire bidirectional I2C-bus or
a three-wire SPI interface.
• Support key scan function with up to 4×12 key
matrix
• Support up to 128 levels PWM luminance control
• Support I2C-bus or SPI 3-wire serial interface
• Up to 63×8 bits RAM for display data storage
• Display patterns:
– 1/1 duty: up to 67×1 patterns
– 1/2 duty: up to 67×2 patterns
– 1/3 duty: up to 67×3 patterns
– 1/4 duty: up to 67×4 patterns
– 1/8 duty: up to 63×8 patterns
• Support three driver output modes: Segment/COM,
LED or Key Scan
• Versatile blinking modes: off, 0.5Hz, 1Hz, 2Hz
• R/W address auto increment
• Support Power Save Mode for low power consumption
• Manufactured in silicon gate CMOS process
• Package Type: 64LQFP and 80LQFP packages
Rev. 1.10
1
March 18, 2014
HT16LK24
Block Diagram
RSTB
VDD Voltage supported range
Power_on
reset
VDD
COM0
8
VSS
Display RAM
COM3
SDA/DIO
SCL/CLK
COM4/SEG0
I2C or 3-wire
Controller
Internal
RC
Oscillator
Timing generator
Column
/Segment
driver
output
CSB
8
IFS
Key data RAM
COM7/SEG3
SEG4
INT
VE bit
VLCD
regulator
VOP
R
SEG50
－
OP2
＋
R
－
OP1
＋
R
－
OP0
＋
R
LCD bias generator
LCD
Voltage
Selector
SEG51/KSL15
Segment
/LED driver
Output and
keyscan
circuit
SEG52/KSL14
SEG65/KSL1
SEG66/KSL0
VLCD Voltage supported range
Rev. 1.10
2
March 18, 2014
HT16LK24
Pin Assignment
S
S
S
S
S
E G 5
E G 5
E G 5
E G 5
E G 5
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
2 /K S
3 /K S
4 /K S
5 /K S
6 /K S
5 7 /K
5 8 /K
5 9 /K
6 0 /K
6 1 /K
6 2 /K
6 3 /K
6 4 /K
6 5 /K
6 6 /K
L 1
L 1
L 1
L 1
L 1
S L
S L
S L
S L
S L
S L
S L
S L
S L
S L
V S
S
4
3
2
1
0
9
8
4 /S
5 /S
6 /S
7 /S
7
C O M
C O M
C O M
C O M
C
6
C
5
C
4
C
V
3
R
2
1
0
S C L
S D A
IF S
IN T
C S B
/C L K
/D IO
S T B
V D D
L C D
O M 0
O M 1
O M 2
O M 3
E G 0
E G 1
E G 2
E G 3
6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
5 1 /K S L 1 5
5 0
4 9
4 8
4 7
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S
S
S
S
3 1
3 0
S
S
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 5
1 4
1 3
1 2
E G 5
E G 5
E G 5
E G 5
E G 5
E G 5
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E
1 /K S
2 /K S
3 /K S
4 /K S
5 /K S
6 /K S
5 7 /K
5 8 /K
5 9 /K
6 0 /K
6 1 /K
6 2 /K
6 3 /K
6 4 /K
6 5 /K
6 6 /K
G 5 0
L 1 5
L 1 4
L 1 3
L 1 2
L 1 1
L 1 0
S L 9
S L 8
S L 7
S L 6
S L 5
S L 4
S L 3
S L 2
S L 1
S L 0
V S S
IF S
IN T
C O
C O
C O
C O
C
S C L /C
S D A /D
R S
V
V L
C O
C O
C O
C O
M 4 /S E
M 5 /S E
M 6 /S E
M 7 /S E
S E
S E
S E
S E
S E
S E
S B
L K
IO
T B
D D
C D
M 0
M 1
M 2
M 3
G 0
G 1
G 2
G 3
G 4
G 5
G 6
G 7
G 8
G 9
8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 6 9 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1
1
2
6 0
5 9
3
5 8
4
5 7
5
5 6
6
5 5
7
5 4
8
5 3
9
5 2
1 0
1 1
1 2
5 1
4 0
4 9
1 3
4 8
1 4
4 7
1 5
4 6
1 6
4 5
1 7
4 4
1 8
4 3
1 9
2 0
4 2
2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0
4 1
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
4 9
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
3 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
3
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
1 0
Rev. 1.10
March 18, 2014
HT16LK24
Pin Description
Pin Name
Type
Description
Serial Data Input/Output pin
Serial Data (SDA) Input/Output for 2-wire I2C interface is an NMOS open drain
structure.
Serial Data (DIO) Input/Output for 3-wire SPI interface is a CMOS input/output
structure.
SDA/DIO
I/O
SCL/CLK
I
Serial Clock Input pin
Serial Clock (SCL) for 2-wire I2C interface.
Serial Clock (CLK) for 3-wire SPI interface
CSB
I
SPI Chip Select pin
This pin is active low and only available for 3-wire SPI interface. When the I2C
interface is used, this pin is not used and must be connected to VDD.
IFS
I
Communication interface select pin
This pin is used to select the communication interface. When this pin is
connected to VDD, the device communicates with MCU or microprocessors
via a 2-wire I2C interface. When this pin is connected to VSS, the device
communicates with MCU or microprocessors using a 3-wire SPI interface.
INT
O
Interrupt signal output pin
After a power-on or reset condition occurs, the INT pin is in a high level. The INT
output polarity can be changed by configuring the POL bit in the key scan control
command via the I2C or SPI interface.
COM0~COM3
O
LCD Common outputs.
COM4/SEG0~
COM7/SEG3
O
LCD Common/Segment multiplexed driver outputs
SEG4~SEG50
O
LCD Segment outputs.
SEG51/KSL15~
SEG66/KSL0
O
LCD Segment / Key input / Key Scan output / LED output pins
These pins are LCD segment pins after a power on or reset condition. When
the KSLn pins are configured as other shared functional pins except segment
outputs, the LED outputs has higher priority than the Key Scan outputs followed
by the Key inputs. After the KSLn pin-shared functions are determined by
configuring the corresponding L, KX and KY fields in the shared-pin configuration
command, the rest pins then are used as the LCD segment outputs.
RSTB
I
Reset input pin
This pin is active low and used to initialize all the internal registers and the
commands pin.
VDD
—
Positive power supply.
VSS
—
Negative power supply, ground.
VLCD
—
LCD power supply pin
Rev. 1.10
4
March 18, 2014
HT16LK24
Approximate Internal Connections
SCL, SDA (for Schmitt trigger type)
COM0~COM7; SEG0~SEG50
DIO (for Schmitt trigger type)
VDD
VDD
VLCD
VSS
VLCD
VSS
VSS
VSS
IFS, RSTB
CSB, CLK (for Schmitt trigger type)
INT
VDD
VDD
VDD
VSS
VSS
VSS
SEG51_KSL15~SEG66_KSL0
VLCD
VSS
VLCD
VSS
VLCD
Ky
VSS
VLCD
KSx
VSS
LEDn
VSS
Ky: Key input
KSx: Key Scan output
Rev. 1.10
5
March 18, 2014
HT16LK24
Absolute Maximum Ratings
Supply Voltage ............................VSS-0.3V to VSS+6.6V
Storage Temperature ........................... -55°C to 150°C
Input Voltage ............................ VSS-0.3V to VDD+0.3V
Operating Temperature.......................... -40°C to 85°C
Total LED Driver Output Current (Ta=25°C)....132mA
Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings"
may cause substantial damage to the device. Functional operation of this device at other conditions beyond
those listed in the specification is not implied and prolonged exposure to extreme conditions may affect
device reliability.
Timing Diagrams
I2C Interface Timing
SDA
tBUF
tSU:DAT
tf
tHD:STA
tr
tLOW
tSP
SCL
tHD:STA
tHD:DAT
S
tSU:STA
tHIGH
tAA
tSU:STO
S
P
Sr
SDA
OUT
SPI Timing
tCSW
90%
90%
VDD
CSB
10%
10%
tSYS
tCSL
tCSH
90%
CLK
90%
tCW
10%
tDS
90%
90%
90%
VSS
VDD
tCW
10%
10%
10%
VSS
tHS
VDD
90%
DIO
(INPUT )
10%
10%
tPD
VSS
tPD
90%
90%
VDD
DIO
(OUTPUT )
10%
Rev. 1.10
10%
6
VSS
March 18, 2014
HT16LK24
Reset Timing
80%
tSR
0.9V
VDD
tRSON
0.9V
tPOF
tRW
50
%
50%
RSTB
Data
transfer
50%
50%
tRSOFF
tRSOFF
tRSOFF
50%
50%
50%
Note: 1. If the conditions of Reset timing are not satisfied in power ON/OFF sequence, the internal Power on Reset
(POR) circuit will not operate normally.
2. If the VDD drops lower than the minimum operating voltage during operating, the conditions of Power on
Reset timing must also be satisfied. That is the VDD drop to 0.9V and keep at 0.9V for 10ms (min.) before
rising to the normal operating voltage.
3. Data transfers on the I2C-bus or SPI 3-wire serial bus should at least be delayed for 1ms after the poweron sequence to ensure that the reset operation is complete.
D.C. Characteristics
Symbol
Parameter
VSS= 0V, VDD= 1.8V to 5.5V, Ta= -40°C to +85°C
Test Condition
VDD
Condition
—
VDD
Operating Voltage
—
VLCD
LCD Operating Voltage
—
VIH
Input High Voltage
—
CSB, CLK, DIO, RSTB
VIL
Input Low Voltage
—
IIL
Input Leakage Current
—
IOH
High Level Output Current
—
3.3V
IDD
Operating Current
3.3V
5.0V
ILCD1
Rev. 1.10
Operating Current
—
1.8
—
5.5
V
6
V
—
VDD
V
CSB, CLK, DIO, RSTB
0
—
0.3VDD
V
VIN=VSS or VDD
-1
—
1
μA
-2
—
—
mA
-6
—
—
mA
-12
—
—
mA
3
—
—
mA
6
—
—
mA
9
—
—
mA
—
1
3
μA
—
2
6
μA
—
4
12
μA
—
10
20
μA
VOH=0.9VDD for DIO pin
VOL=0.4V for SDA/DIO pin
5.0V
2.0V
Unit
—
2.0V
Low Level Output Current
Max.
2.4
5.0V
IOL
Typ.
0.7VDD
2.0V
3.3V
Min.
No load, fLCD=64Hz, 1/3bias,
LCD display on, Internal system
oscillator on, VLCD pin input voltage =5V,
Disable integrated regulator,
LED and Key scan
No load, fLCD=64Hz, 1/3bias,
LCD display on, Internal system
oscillator on, current mode is set to low
current 2, VLCD pin input voltage =5V.
Disable integrated regulator,
LED and Key scan
7
March 18, 2014
HT16LK24
Symbol
ILCD2
Parameter
Operating Current
Standby Current for VDD
ISTB1
Test Condition
Standby Current for VLCD
Regulator Output
LCD Common Sink
Current
IOL1
LCD Common Source
Current
IOH1
LCD Segment Sink
Current
IOL2
Unit
—
25
40
μA
—
—
1
μA
—
—
2
μA
—
—
1
μA
—
—
2
μA
VLCD pin input voltage =5.5V,
Regulator output is set to 4.5V,
Ta =-40~85°C
4.35
4.5
4.65
V
VLCD pin input voltage =5.5V,
Regulator output is set to 4.5V,
Ta =25°C
4.42
4.5
4.58
V
VLCD=3.3V, VOL=0.33V,
Disable integrated regulator
250
400
—
μA
VLCD=5V, VOL=0.5V
Disable integrated regulator
500
800
—
μA
VLCD=3.3V, VOH=2.97V,
Disable integrated regulator
-140
-230
—
μA
VLCD=5V, VOH=4.5V,
Disable integrated regulator
-300
-500
—
μA
VLCD=3.3V, VOL=0.33V,
Disable integrated regulator
250
400
—
μA
VLCD=5V, VOL=0.5V,
Disable integrated regulator
500
800
—
μA
VLCD=3.3V, VOH=2.97V,
Disable integrated regulator
-140
-230
—
μA
VLCD=5V, VOH=4.5V,
Disable integrated regulator
-300
-500
—
μA
VLCD=3.3V, VOL= 1V,
10
—
—
mA
VLCD=5.0V, VOL= 2V,
20
—
—
mA
VLCD=3.3V, VOL= 1V,
-2.5
—
—
mA
VLCD=5.0V, VOL= 2V,
-5
—
—
mA
220
—
—
KΩ
—
3.3V
3.3V
—
—
—
—
LCD Segment Source
Current
—
IOL3
LED Sink Current
—
IOH3
Key Scan Output Source
Current
—
RPL
Input Pull-low Resistor
—
IOH2
Max.
No load, fLCD=64Hz, 1/3bias,
LCD display on, Internal system
oscillator on, current mode is set to low
current 2, VLCD pin input voltage =5.5V,
Regulator output is set to 5V, disable
keyscan and LED
5.0V
Vreg
Typ.
Condition
5.0V
ISTB2
Min.
VDD
No load, 1/3bias, LCD display off,
Internal system oscillator off, VLCD pin
input voltage =5V, Disable integrated
regulator, LED and Key scan
No load, 1/3bias, LCD display off,
Internal system oscillator off, VLCD pin
input voltage =5V, Disable integrated
regulator, LED and Key scan
Key0~Key15 are pressed, Disable
regulator
Note: 1. Please use the integrated regulator when the Regulator output voltage is less than (VLCD – 0.5V).
2. If the 12 LED outputs are all turned on at the same time, the total current consumption of the LED drivers
can not be greater than 120mA.
Rev. 1.10
8
March 18, 2014
HT16LK24
A.C. Characteristics
Symbol
Parameter
Ta= -40°C to +85°C
Test Condition
Condition
VDD
Frame frequency = 68.3Hz
fLCD1
fLCD2
fLCD3
fLCD4
fLCD5
fLCD6
fPWM1
fPWM2
fPWM3
LCD Frame Frequency
(1/3 duty)
3.3V
Ta=25°C
Ta=25°C
61
68.3
75.1
91
100.2
Frame frequency = 136.5Hz
122.5 136.5 150.2
Frame frequency = 182Hz
164
182
200.3
Frame frequency = 68.3Hz
54.5
68.3
88.6
72.0
91
118.5
145
182
237
Frame frequency = 68.3Hz
48
—
68.3
62.5
—
91
95.5
—
136.5
Frame frequency = 182Hz
125.5
—
182
Frame frequency = 64Hz
57.6
64
70.4
Frame frequency = 85.3Hz
76
85.3
94
Frame frequency = 128Hz
115.2
128
140.8
Frame frequency = 170.6Hz
152
170.6
188
Frame frequency = 64Hz
51.2
64
83
68
85.3
111
102.4
128
166
Frame frequency = 170.6Hz
136
170.6
222
Frame frequency = 64Hz
45
—
64
59
—
85.3
90
—
128
Frame frequency = 170.6Hz
118
—
170.6
PWM frequency = 85.3Hz
76
85.3
94
PWM frequency = 128Hz
115.2
128
140.8
152
170.6
188
LCD Frame Frequency 1.8V~ Ta=-40°C Frame frequency = 85.3Hz
(1/4 duty)
2.5V
~ 85°C Frame frequency = 128Hz
LED Output PWM
Frequency (1/4 duty)
LED Output PWM
Frequency (1/4 duty)
3.3V
Ta=25°C
PWM frequency = 170.6Hz
PWM frequency = 256Hz
230.4
256
281.6
PWM frequency = 85.3Hz
68
85.3
111
102.4
128
166
136
170.6
222
PWM frequency = 256Hz
204.8
256
332
PWM frequency = 85.3Hz
59
—
85.3
2.5V~ Ta=-40°C PWM frequency = 128Hz
5.5V
~ 85°C PWM frequency = 170.6Hz
1.8V~ Ta=-40°C PWM frequency = 128Hz
2.5V
~ 85°C PWM frequency = 170.6Hz
90
—
128
118
—
170.6
180
—
256
6.8
8
9.2
2.5V~ Ta=-40°C~85°C,
5.5V Key scan pulse width = 2ms
5.6
8
10.4
1.8V~ Ta=-40°C~85°C,
2.5V Key scan pulse width = 2ms
7.2
—
12
PWM frequency = 256Hz
3.3V
tKCT
Rev. 1.10
Key Scan Cycle Time
109.2 136.5 177.1
Frame frequency = 182Hz
LCD Frame Frequency 2.5V~ Ta=-40°C Frame frequency = 85.3Hz
(1/4 duty)
5.5V
~ 85°C Frame frequency = 128Hz
LED Output PWM
Frequency (1/4 duty)
Max.
81.5
LCD Frame Frequency 1.8V~ Ta=-40°C Frame frequency = 91Hz
(1/3 duty)
2.5V
~ 85°C Frame frequency = 136.5Hz
3.3V
Typ.
Frame frequency = 91Hz
LCD Frame Frequency 2.5V~ Ta=-40°C Frame frequency = 91Hz
(1/3 duty)
5.5V
~ 85°C Frame frequency = 136.5Hz
LCD Frame Frequency
(1/4 duty)
Min.
Ta=25°C, Key scan pulse width = 2ms
9
Unit
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
ms
March 18, 2014
HT16LK24
Symbol
Test Condition
Parameter
Min.
Typ.
Max.
1.7
2
2.3
2.5V~ Ta=-40°C~85°C,
5.5V Key scan pulse width = 2ms
1.4
2
2.6
1.8V~ Ta=-40°C~85°C,
2.5V Key scan pulse width = 2ms
1.8
—
3.0
0.05
—
—
V/ms
Condition
VDD
3.3V
tKPW
Key Scan Pulse Width
Ta=25°C, Key scan pulse width = 2ms
Unit
ms
tSR
VDD Slew Rate
—
tPOF
VDD OFF Times
—
VDD drop down to 0.9V
10
—
—
ms
—
When RSTB signal is externally input
from a microcontroller, etc.
250
—
—
ns
—
100
—
ms
400
—
—
ns
1
—
—
ms
tRSON
RSTB Input Time
—
R=100KΩ and C=0.1μF
(see application circuit)
tRW
RSTB Pulse Width
—
When RSTB signal is externally input
from a microcontroller etc.
tRSOFF
Wait Time for Data
Transfers
—
2-wire I2C-bus or 3-wire SPI bus
I2C Interface Characteristics
Unless otherwise specified, VSS=0 V, VDD=1.8V to 5.5V, Ta= -40°C to +85°C
Symbol
Parameter
VDD=1.8V to
5.5V
VDD=3.0V to
5.5V
Min.
Max.
Min.
Max.
—
—
100
—
400
kHz
Condition
Unit
fSCL
Clock Frequency
tBUF
Bus Free Time
Time in which the bus must be free
before a new transmission can start
4.7
—
1.3
—
μs
tHD: STA
Start Condition Hold Time
After this period, the first clock pulse
is generated
4
—
0.6
—
μs
tLOW
SCL Low Time
—
4.7
—
1.3
—
μs
tHIGH
SCL High Time
—
4
—
0.6
—
μs
tSU: STA
Start Condition Setup Time
4.7
—
0.6
—
μs
tHD: DAT
Data Hold Time
—
0
—
0
—
ns
tSU: DAT
Data Setup Time
—
250
—
100
—
ns
tR
SDA and SCL Rise Time
Note
—
1
—
0.3
μs
tF
SDA and SCL Fall Time
Note
—
0.3
—
0.3
μs
tSU: STO
Stop Condition Set-up Time
—
4
—
0.6
—
μs
tAA
Output Valid from Clock
—
—
3.5
—
0.9
μs
tSP
Input Filter Time Constant
(SDA and SCL Pins)
—
20
—
20
ns
Only relevant for repeated START
condition.
Noise suppression time
Note: These parameters are periodically sampled but not 100% tested.
Rev. 1.10
10
March 18, 2014
HT16LK24
A.C. Characteristics – SPI Interface
Unless otherwise specified, VSS=0V, VDD=1.8V to 5.5V, Ta= -40°C to +85°C
Symbol
Parameter
tSYS
Clock cycle time
tCW
Clock Pulse Width
Test Condition
Min.
Typ.
Max.
Unit
For write data
250
—
—
ns
For read data
1000
—
—
ns
For write data
50
—
—
ns
For read data
400
—
—
ns
VDD
—
—
Condition
tDS
Data Setup Time
—
For write data
50
—
—
ns
tDH
Data Hold Time
—
For write data
50
—
—
ns
tCSW
"H" CSB Pulse Width
—
50
—
—
ns
50
—
—
ns
tCSL
CSB Setup Time (CSB↓ — CLK↑)
—
tCSH
CS Hold Time (CLK↑ — CSB↑)
—
tPD
DATA Output Delay Time
(CLK — DIO)
—
—
For write data
For read data
—
CO=15pF
tPD=10% to 90%
tPD=90% to 10%
400
—
—
ns
2
—
—
μs
—
—
350
ns
Note: fLCD= 1/tLCD
Rev. 1.10
11
March 18, 2014
HT16LK24
Functional Description
The contents of the RAM data are directly mapped
to the LCD data. The first RAM column corresponds
to the segments operated with respect to COM0. In
multiplexed LCD applications the segment data of the
second, third and fourth column of the display RAM
are time-multiplexed with COM1, COM2 and COM3
respectively. The LCD display duty can be 1/4 or 1/8
determined by a Duty bit contained in the Drive Mode
Command. The following diagram is a data transfer
format for I2C or SPI interface.
Power-On Reset
When the power is applied, the device is initialized
by an internal power-on reset circuit. The status of the
internal circuits after initialization is as follows:
• All common outputs are set to VLCD.
• All segment outputs are set to VLCD.
• The drive mode 1/4 duty output and 1/3 bias is
selected.
MSB
LSB
• The System Oscillator and the LCD bias generator
are off state.
LCD
• LCD Display is off state.
LCD Display data transfer format for I2C or SPI bus
• Integrated regulator is disabled.
D6
D5
D4
D3
D2
D1
D0
Display Mode
• Key scan pulse width is set to 2 ms and INT output
is set to a high level.
• 1/1, 1/2, 1/3, 1/4 duty
When the Duty2 bit is set to 0, the drive mode can
be selected as 1/1, 1/2, 1/3 or 1/4 duty using the
Duty1 and Duty0 bits and the LCD RAM map is
implemented as the following table shown. This
default display mode is 1/4 duty after a reset.
• The Segment/Key scan/LED shared pin is set as
the Segment pin.
• The LCD driving mode is set to the normal current
mode.
• Frame Frequency is set to 64Hz.
• 1/8 duty
When the Duty2 bit is set to 1, the drive mode is
selected as 63 segments by 8 commons and the
LCD RAM map is implemented as the following
table shown.
• Blinking function is switched off.
Reset Function
When the RSTB pin is pulled to a low level, a
reset operation is executed and it will initialize all
functions. The status of the internal circuits after
initialization is as follows:
System Oscillator
The timing for the internal logic and the LCD drive
signals are generated by an internal oscillator. The
System Clock frequency (fSYS) determines the LCD
frame frequency. During initial system power on the
System Oscillator will be in the stop state.
• All common outputs are set to VLCD.
• All segment outputs are set to VLCD.
• The drive mode 1/4 duty output and 1/3 bias is
selected.
• The System Oscillator and the LCD bias generator
are off state.
LCD Bias Generator
The LCD supply power can come from the external
VLCD pin or the internal regulator output voltage
determined using the Internal Voltage Adjustment
(IVA) setting command. The device provides an
external VLCD pin and also integrates an internal
regulator. The LCD voltage may be temperature
compensated externally through the Voltage supply to
the VLCD pin. The internal regulator can also provide
the LCD operating voltage. Therefore, the full-scale
LCD voltage (VOP) is obtained from (VLCD – VSS) or
(Vreg – VSS).
• LCD Display is off state.
• Integrated regulator is disabled.
• The Segment/Key scan/LED shared pin is set as
the Segment pin.
• The LCD driving mode is set to the normal current
mode.
• Frame Frequency is set to 64Hz.
• Blinking function is switched off
Display Memory – RAM Structure
Fractional LCD biasing voltages, known as 1/1, 1/2,
1/3 or 1/4 bias voltage, are obtained from an internal
voltage divider of four series resistors connected
between VOP and VSS. The resistors can be switched
out of circuits to provide a 1/2, 1/3 or 1/4 bias voltage
level configuration.
The display RAM is static 63 x 8-bits RAM which
stores the LCD data. Logic "1" in the RAM bit-map
indicates the "on" state of the corresponding LCD
segment; similarly, logic 0 indicates the ‘off’ state.
Rev. 1.10
D7
12
March 18, 2014
HT16LK24
Output
COM3
COM2
COM1
COM0
Output
COM3
COM2
COM1
COM0
Address
SEG1
SEG0
00H
SEG3
SEG2
01H
SEG5
SEG4
02H
↓
↓
↓
↓
↓
↓
SEG65
↓
↓
↓
↓
SEG64
20H
SEG66
D7
D6
D5
↓
21H
D4
D3
D2
D1
D0
Data
RAM mapping of 67x4 display mode – 1/1, 1/2, 1/3 and 1/4 duty
Output
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
Address
SEG4
00H
SEG5
01H
SEG6
02H
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
D7
D6
D5
D4
D3
D2
D1
D0
Data
SEG66
3EH
RAM mapping of 63x8 display mode – 1/8 duty
LCD Drive Mode Waveforms
• When the LCD drive mode is selected as 1/1 duty and 1/1 bias (static), the waveform and LCD display is shown
as follows:
tLCD
State1
State1
(on)
(on)
VLCD
VLCD
COM0
COM0
LCD segment
LCD segment
State2
State2
(off)
(off)
VSS
VSS
VLCD
VLCD
SEG n
SEG n
VSS
VSS
VLCD
VLCD
SEG n+1
SEG n+1
VSS
VSS
VLCD
VLCD
SEG n+2
SEG n+2
VSS
VSS
VLCD
VLCD
SEG n+3
SEG n+3
VSS
VSS
Waveforms for 1/1 duty drive mode with 1/1 bias (VOP=VLCD-VSS)
Note: 1. tLCD=1/ fLCD
2. The unused COM1~3 outputs must be left open-circuit and the outputs are pulled to a high level (VLCD).
Rev. 1.10
13
March 18, 2014
HT16LK24
• When the LCD drive mode is selected as 1/2 duty and 1/2 bias, the waveform and LCD display is shown as
follows:
tLCD
State1
State1
(on)
(on)
VLCD
VLCD
COM0 VLCD- Vop/2
COM0 VLCD- Vop/2
LCD segment
LCD segment
VSS
VSS
State1
State1
(off)
(off)
VLCD
VLCD
COM1
COM1
VLCD- Vop/2
VLCD- Vop/2
VSS
VSS
VLCD
VLCD
SEG n VLCD- Vop/2
SEG n VLCD- Vop/2
VSS
VSS
VLCD
VLCD
SEG n+1 VLCD- Vop/2
SEG n+1 VLCD- Vop/2
VSS
VSS
VLCD
VLCD
SEG n+2 VLCD- Vop/2
SEG n+2 VLCD- Vop/2
VSS
VSS
VLCD
VLCD
SEG n+3 VLCD- Vop/2
SEG n+3 VLCD- Vop/2
VSS
VSS
Waveforms for 1/2 duty drive mode with 1/2 bias (VOP=VLCD-VSS)
Note: 1. tLCD=1/ fLCD
2.The unused COM2~3 outputs must be left open-circuit and the outputs are pulled to a high level (VLCD).
Rev. 1.10
14
March 18, 2014
HT16LK24
• When the LCD drive mode is selected as 1/2 duty and 1/3 bias, the waveform and LCD display is shown as
follows:
tLCD
State1
State1
(on)
(on)
VLCD
VLCD
COM0
COM0
VLCD- Vop/3
VLCD- Vop/3
VLCD- 2Vop/3
VLCD- 2Vop/3
LCD segment
LCD segment
VSS
VSS
State1
State1
(off)
(off)
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
COM1 VLCD- 2Vop/3
COM1 VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n
SEG n VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n+1
SEG n+1VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n+2
SEG n+2VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n+3
SEG n+3VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
Waveforms for 1/2 duty drive mode with 1/3 bias (VOP=VLCD-VSS)
Note: 1. tLCD=1/ fLCD
2. The unused COM2~3 outputs must be left open-circuit and the outputs are pulled to a high level (VLCD).
Rev. 1.10
15
March 18, 2014
HT16LK24
• When the LCD drive mode is selected as 1/3 duty and 1/3 bias, the waveform and LCD display is shown as
follows:
tLCD
State1
State1
(on)
(on)
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
COM0
COM0 VLCD- 2Vop/3
LCD segment
LCD segment
VLCD- 2Vop/3
VSS
VSS
State1
State1
(off)
(off)
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
COM1 VLCD- 2Vop/3
COM1 VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
COM2
COM2
VLCD- Vop/3
VLCD- Vop/3
VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n
VLCD2Vop/3
SEG n
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n+1
SEG n+1VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n+2
SEG n+2VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n+3
SEG n+3VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
Waveforms for 1/3 duty drive mode with 1/3 bias (VOP=VLCD-VSS)
Note: 1. tLCD=1/ fLCD
2. The unused COM3 output must be left open-circuit and the output is pulled to a high level (VLCD).
Rev. 1.10
16
March 18, 2014
HT16LK24
• When the LCD drive mode is selected as 1/4 duty and 1/3 bias, the waveform and LCD display is shown as
follows:
tLCD
LCD segment
LCD segment
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
COM0
COM0 VLCD- 2Vop/3
VLCD- 2Vop/3
State1
State1
(on)
(on)
VSS
VSS
VLCD
VLCD
COM1
COM1
State2
State2
(off)
(off)
VLCD- Vop/3
VLCD- Vop/3
VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
COM2
COM2
VLCD- Vop/3
VLCD- Vop/3
VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
COM3
COM3
VLCD- Vop/3
VLCD- Vop/3
VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n
SEG n VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n+1
SEG n+1 VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n+2
SEG n+2 VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n+3
SEG n+3VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
Waveforms for 1/4 duty drive mode with 1/3 bias (VOP=VLCD-VSS)
Note: tLCD=1/ fLCD
Rev. 1.10
17
March 18, 2014
HT16LK24
• When the LCD drive mode is selected as 1/8 duty and 1/4 bias, the waveform and LCD display is shown as
follows:
tLCD
LCD segment
LCD segment
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
VLCD- 2Vop/4
COM0
VLCD- 2Vop/4
COM0
State1
State1
(on)
(on)
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
State2
State2
(off)
(off)
VLCD- Vop/4
VLCD- Vop/4
VLCD- 2Vop/4
COM1
VLCD- 2Vop/4
COM1
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
VLCD- 2Vop/4
COM2
COM2
VLCD- 2Vop/4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
VLCD- 2Vop/4
COM3
VLCD- 2Vop/4
COM3
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
VLCD- 2Vop/4
COM4
COM4
VLCD- 2Vop/4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
VLCD- 2Vop/4
COM5
COM5
VLCD- 2Vop/4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
VLCD- 2Vop/4
COM6
COM6
VLCD- 2Vop/4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
VLCD- 2Vop/4
COM7
COM7
VLCD- 2Vop/4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
SEG n
SEG n
VLCD- 2Vop/4
VLCD- 2Vop/4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
SEG n+1
VLCD- 2Vop/4
SEG n+1
VLCD- 2Vop/4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
SEG n+2
VLCD- 2Vop/4
SEG n+2
VLCD- 2Vop/4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
SEG n+3
VLCD- 2Vop/4
SEG n+3
VLCD- 2Vop/4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
Waveforms for 1/8 duty drive mode with 1/4 bias (VOP=VLCD-VSS)
Note: tLCD=1/ fLCD
Rev. 1.10
18
March 18, 2014
HT16LK24
Segment Driver Outputs
Frame Frequency
The LCD drive section includes up to 67 segment outputs
which should be connected directly to the LCD panel.
The segment output signals are generated in accordance
with the multiplexed column signals and with the data
resident in the display latch. The unused segment
outputs should be left open-circuit.
The H T16LK 24 device provides four frame
frequencies selected with Frame Frequency command
known as 64Hz, 85.3Hz, 128Hz and 170.6Hz
respectively.
Column Driver Outputs
The device provides up to 12 LED output driving
pins with 128-level PWM luminance control. The
LED pins are NMOS-structured output pins. The Data
for the LED output is contained in the LED output
control command, starting from the most significant
bit. When a written data bit for a LED pin is set to 1,
the corresponding driving LED lights up while the
LED is switched off when the written data bit is 0.
The LED data is transferred from the MSB first via
I2C or SPI interface.
LED Function
The LCD drive section includes 4 column outputs
COM0~COM3 or 8 column outputs COM0~COM7
which should be connected directly to the LCD panel.
The column output signals are generated in accordance
with the selected LCD drive mode. The unused
column outputs should be left open-circuit if less than
4 or 8 column outputs are required.
Address Pointer
MSB
The addressing mechanism for the display RAM is
implemented using the address pointer. This allows
the loading of an individual display data byte, or a
series of display data bytes, into any location of the
display RAM. The sequence commences with the initialization of the address pointer by the Display Data
Input command.
LED output2 command
Blinking frequency (Hz)
Blink off
1
2
Rev. 1.10
2
1
3
0.5
x
x
x
LED11 LED10 LED9 LED8
The luminance of each lighted LED output pin can
be programmable individually using the LED PWM
luminance control command after the relevant LED
PWM function is enabled. When the PWM function
enable bit, PWENx, is set to 1, the corresponding
PWM function will be enabled. Otherwise, the LED
PWM luminance function will be disabled if the
PWENx bit is cleared to 0.
The device contains versatile blinking capabilities.
The whole display can be blinked at frequencies
selected by the Blinking Frequency command. The
blinking frequency is a subdivided ratio of the system
frequency. The ratio between the system oscillator
and blinking frequencies depends on the blinking
mode in which the device is operating, as shown in
the following table:
0
x
LED Display data transfer format for I2C or SPI bus
Blinking Function
Blinking Mode
LSB
LED output1 command LED7 LED6 LED5 LED4 LED3 LED2 LED1 LED0
The dimming values contained in the LED PWM
luminance control command is used to determine the
low pulse on the corresponding LED output pin as the
diagram shown.
The LED pins are pin-shared with the LCD segment
together with key scan matrix pins and can be
configured using the KX, KY and L fields in the SEG/
KSL shared pin configuration command. The LED
output function has the priority than the key scan
matrix and LCD segment output and the LED output
number is determined by configuring the "L" field in
the shared pin configuration command.
19
March 18, 2014
HT16LK24
fPWM
PWENx bit
Dimming Value
1/128
LEDx pin output at
dimming value=1/128
2/128
3/128
4/128
126/128 127//128 128/128
5/128
Hi-Z
Dimming Value
VSS
Hi-Z
LEDx pin output at
dimming value=2/128
VSS
Hi-Z
LEDx pin output at
dimming value=3/128
VSS
Hi-Z
LEDx pin output at
dimming value=4/128
VSS
Hi-Z
LEDx pin output at
dimming value=5/128
VSS
Hi-Z
LEDx pin output at
dimming value=126/128
VSS
Hi-Z
LEDx pin output at
dimming value=127/128
VSS
Hi-Z
LEDx pin output at
dimming value=128/128
VSS
LED output with PWM luminance control
Note: 1. The LEDx pin data stored in the LED output control command is set to 1.
2. The notation "Hi-Z" in the diagram means that the LEDx pin is in an open-drain status.
LED output
number set
L3
L2
L1
Segment/key scan/LED Shared pin
L0
Seg51/ Seg52/ Seg53/ Seg54/ Seg55/ Seg56/ Seg57/ Seg58/ Seg59/ Seg60/ Seg61/ Seg62/ Seg63/ Seg64/ Seg65/ Seg66/
KSL15 KSL14 KSL13 KSL12 KSL11 KSL10 KSL9
KSL8
KSL7
KSL6
KSL5
KSL4
KSL3
KSL2
KSL1
KSL0
0
0
0
0
Seg51
Seg52
Seg53
Seg54
Seg55
Seg56
Seg57
Seg58
Seg59
Seg60
Seg61
Seg62
Seg63
Seg64
Seg65
Seg66
0
0
0
1
Seg51
Seg52
Seg53
Seg54
Seg55
Seg56
Seg57
Seg58
Seg59
Seg60
Seg61
Seg62
Seg63
Seg64
Seg65
LED0
0
0
1
0
Seg51
Seg52
Seg53
Seg54
Seg55
Seg56
Seg57
Seg58
Seg59
Seg60
Seg61
Seg62
Seg63
Seg64
LED1
LED0
0
0
1
1
Seg51
Seg52
Seg53
Seg54
Seg55
Seg56
Seg57
Seg58
Seg59
Seg60
Seg61
Seg62
Seg63
LED2
LED1
LED0
0
1
0
0
Seg51
Seg52
Seg53
Seg54
Seg55
Seg56
Seg57
Seg58
Seg59
Seg60
Seg61
Seg62
LED3
LED2
LED1
LED0
0
1
0
1
Seg51
Seg52
Seg53
Seg54
Seg55
Seg56
Seg57
Seg58
Seg59
Seg60
Seg61
LED4
LED3
LED2
LED1
LED0
0
1
1
0
Seg51
Seg52
Seg53
Seg54
Seg55
Seg56
Seg57
Seg58
Seg59
Seg60
LED5
LED4
LED3
LED2
LED1
LED0
0
1
1
1
Seg51
Seg52
Seg53
Seg54
Seg55
Seg56
Seg57
Seg58
Seg59
LED6
LED5
LED4
LED3
LED2
LED1
LED0
1
0
0
0
Seg51
Seg52
Seg53
Seg54
Seg55
Seg56
Seg57
Seg58
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
1
0
0
1
Seg51
Seg52
Seg53
Seg54
Seg55
Seg56
Seg57
LED8
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
1
0
1
0
Seg51
Seg52
Seg53
Seg54
Seg55
Seg56
LED9
LED8
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
1
0
1
1
Seg51
Seg52
Seg53
Seg54
Seg55
LED10
LED9
LED8
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
1
1
0
0
Seg51
Seg52
Seg53
Seg54
LED11
LED10
LED9
LED8
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
Rev. 1.10
20
March 18, 2014
HT16LK24
Key Scan Function
The device provides 16 keys which can be used to construct the key matrix for key scan function. These keys
can be configured as key inputs or key scan outputs using the KX and KY fields in the shared pins configuration
command. For example, if there are four keys, KS3~KS0, set as key scan outputs, the maximum key matrix will
contain 12x4 keys. The maximum key matrix can be 12x4, 13x3, 14x2 or 15x1 keys with different key scan
output number. However, if there is no key configured as key scan outputs, there are up to 16 key inputs which are
externally connected to VLCD voltage.
The key scan circuitry sequentially outputs a high pulse on the key scan output pins, KS0~KS3. The key scan
output pulse width, tKPW, can be programmable by configuring the KF field in the key scan control command. The
key scan circuitry detects the key press at the tail of the key scan output pulse. The key press de-bounce time is
1~2 key scan cycles. That means that the available key press time duration must be equal to or greater than the key
debounce time. Therefore, the valid key will be detected twice consecutively.
Press key
KS0
Hi-Z
KS1
∫∫
t KPW
Hi-Z
Hi-Z
Hi-Z
KS2
Release key
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1st keyscan cycle(tKCT)
Hi-Z
Hi-Z
Hi-Z
Hi-Z
KS3
Hi-Z
Hi-Z
Hi-Z
∫∫
Hi-Z
Hi-Z
Hi-Z
∫∫
Hi-Z
∫∫
Hi-Z
2nd keyscan cycle(tKCT)
INT pin
(active low)
∫∫
INT pin
(active high)
∫∫
After all the key data has been read:
1. Clears the key data RAM
2. The INT flag bit is set to "0”
3. The INT pin goes to low when "POL”bit is set to“1”
4. The INT pin goes to high when "POL”bit is set to“0”
1. The key data is updated
2. The state of INT output is changed
3. INT flag is set to “1”
Four key scan outputs – KS0~KS3
Press key
KS0
KS1
KS2
Hi-Z
Release key
∫∫
tKPW
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1st keyscan cycle(tKCT)
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
∫∫
Hi-Z
∫∫
Hi-Z
2nd keyscan cycle(tKCT)
INT pin
(active low)
∫∫
INT pin
(active high)
1. The key data is updated
2. The state of INT output is changed
3. INT flag is set to “1”
∫∫
After all the key data has been read:
1. Clears the key data RAM
2. The INT flag bit is set to "0”
3. The INT pin goes to low when "POL”bit is set to“1”
4. The INT pin goes to high when "POL”bit is set to“0”
Three key scan outputs – KS0~KS2
Rev. 1.10
21
March 18, 2014
HT16LK24
Press key
KS0
Hi-Z
KS1
tKPW
Hi-Z
Release key
∫∫
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1st keyscan cycle(tKCT)
Hi-Z
Hi-Z
Hi-Z
Hi-Z
∫∫
2nd keyscan cycle(tKCT)
INT pin
(active low)
∫∫
INT pin
(active high)
∫∫
After all the key data has been read:
1. Clears the key data RAM
2. The INT flag bit is set to "0”
3. The INT pin goes to low when "POL”bit is set to“1”
4. The INT pin goes to high when "POL”bit is set to“0”
1. The key data is updated
2. The state of INT output is changed
3. INT flag is set to “1”
Two key scan outputs – KS0~KS1
Press key
KS0
Hi-Z
tKPW
Release key
∫∫
Hi-Z
Hi-Z
1st keyscan cycle(tKCT)
Hi-Z
Hi-Z
2nd keyscan cycle(tKCT)
INT pin
(active low)
∫∫
INT pin
(active high)
∫∫
After all the key data has been read:
1. Clears the key data RAM
2. The INT flag bit is set to "0”
3. The INT pin goes to low when "POL”bit is set to“1”
4. The INT pin goes to high when "POL”bit is set to“0”
1. The key data is updated
2. The state of INT output is changed
3. INT flag is set to “1”
One key scan output – KS0
Press key
Release key
VLCD
K0~K15
∫∫
1~2 keyscan cycle(tkct)
INT pin
(active low)
∫∫
INT pin
(active high)
1. The key data is updated
2. The state of INT output is changed
3. INT flag is set to “1”
VSS
∫∫
When after the all key data has been read:
1. Clears the key data RAM.
2. The INT flag bit is set to"0”
3.The INT pin goes to low when "POL”bit is set to “1”
4.The INT pin goes to high when "POL”bit is set to “0”
Key inputs – K0~K15
Rev. 1.10
22
March 18, 2014
HT16LK24
Ghost Key for Key Matrix
The Key scan circuitry can detect multiple pressed keys. However, the ghost keys may be generated when multiple
keys are pressed. If three or more than three keys are pressed and the pressed keys are lined in an "L" shape,
the ghost keys will be generated. As the accompanying diagram shows, the key on the 4th corner which forms a
rectangle together with other three pressed keys will be the ghost key and be recognized as a pressed key no matter
the relevant external key is pressed or not. Attentions must be paid to avoid from ghost keys in multiple key press
applications.
Ghost Key
Pressed Key
KS0
KS1
KS2
KS3
K0
K1
K2
Ghost Key
Pressed Key
KS0
KS1
KS2
KS3
K0
Rev. 1.10
K1
K2
23
K3
March 18, 2014
HT16LK24
Key Scan Interrupt Function
The device provides two ways to indicate the interrupt occurrence for key scan function.
• Hardware signal
When the valid key press is detected, the interrupt will be generated and the INT pin will change state from its
inactive state to active state. The polarity of the INT output pin can be changed by configuring the POL bit in
the Key scan control command via the I2C or SPI interface. When the POL bit is set to 1, the INT pin is active
high while the INT pin is active low if the POL bit is cleared to 0. After the key data has been read, all the key
data will be cleared to 0 and the INT pin returns to an inactive state.
• Software indicator
When the valid key press is detected, the interrupt flag will be set to 1 and can be read using the I2C or SPI
interface. After the key data has been read, all the key data will be cleared to 0 and the interrupt flag will also be
cleared to 0. The INT interrupt flag is stored in the register bit 0 and is set and cleared by hardware.
Press key
KS(n)
1st keyscan cycle
2nd keyscan cycle
3rd keyscan cycle
INT flag
INT pin
(active low)
INT pin
(active high)
Press KEY1 and KEY2
1st keyscan cycle
Keyscan
2nd keyscan cycle
3rd keyscan cycle
Press KEY3
4th keyscan cycle
Press KEY4
5th keyscan cycle
6th keyscan cycle
Release key
7th keyscan cycle
Keyscan period
INT flag
INT pin
(active low)
INT pin
(active high)
1. The key data is updated
2. State of INT output is changed
3. INT flag is set to “1”
Rev. 1.10
24
When all the key data has been read:
1. The key data is cleared to“0”
2. INT flag is set to "0”
3. INT pin goes to low when "POL” bit is set to “1”
4. INT pin goes to high when "POL” bit is ise to “0”
March 18, 2014
HT16LK24
Key Data Memory Structure
• The Key data RAM is a read-only memory and is organized into 16x4 bits which stores the key data detected
by the key scan circuitry. Each key data corresponds to one key in the key matrix.
• The key data byte in the corresponding address will be cleared after the data byte is read and therefore, the
successive key press can be identified again. If the key data byte is not read, the pressed key data will be
successively recorded when other keys are pressed.
• The key data RAM address will be incremented automatically when the key data is read continuously. The
address will be wrapped around to the start address 0x00H when the key data RAM read operation is executed
successively and the RAM address is greater than the maximum available address 0x07H. It is strongly
recommended to read the whole key data from the start address 0x00H sequentially via the I2C or 3-wiredSPI
interface.
Output K15 K14 K13 K12 K11 K10 K9
K8 Addr.
K7
K6
K5
K4
K3
K2
K1
K0
Addr.
KS0
01H
00H
KS1
03H
02H
KS2
05H
04H
KS3
07H
06H
D7
D6
D5
D4
D3
D2
D1
D0
Data
D7
D6
D5
D4
D3
D2
D1
D0
Data
Standby Mode
The standby mode is selected by setting the "S" bit in the system mode setting command to "0". It is strongly recommended that the LCD display is first switched off before the standby mode command is setup. Otherwise, the
LCD display will be turned on automatically when the device standby mode is released.
When the device enters the standby mode by setting "S" bit in the system mode setting command to "0", the status
in standby mode is shown as below:
• System Oscillator LCD display and key scan will be in the off state.
• All key data RAM and INT flag are cleared to "0" until the standby mode is released.
• The INT pin output is set to high when the ‘POL ’ bit in the Key scan control command is set to ‘0’.
• The INT pin output is set to low when the ‘POL’ bit in the Key scan control command is set to ‘1’.
• If the PWENx bit in the LED output control command is set to "0", the status of the corresponding LEDx output
pin will not be changed after entering standby mode where "x" means 0~11.
• If the PWENx bit in the LED output control command is set to "1", the status of the corresponding LEDx output
pin will be turned off after entering standby mode where "x" means 0~11.
• The K0~K15 pin are set as inputs.
• The KS0~KS3 pins are set to high.
• All common outputs and segment outputs are set to a high level of a VLCD voltage.
Rev. 1.10
25
March 18, 2014
HT16LK24
Wake-up Function
The device can be woken up by a valid key press or setting the "S" bit in the system mode setting command to"1".
When the device is woken up from the standby mode, the status after wakeup is shown as below:
• The System Oscillator restarts.
• The key scan will be performed.
• The LED PWM function will be performed and the LEDx output will be lighted up after wakeup if the PWENx
bit is set to 1 and the LEDx data value is set to 1 before entering the standby mode. Otherwise, the LEDx output
is always turned off where "x" means 0~11. The relationship between the LED output status and LED PWM
function at different modes is shown as below:
PWM function System OSC
PWEN bit
S bit
0
1→0→1
1
1→0→1
LED output status
LED PWM function
Normal mode→Standby mode→
Wake up mode/ Normal mode
Normal mode→Standby mode→
Wake up mode/ Normal mode
off→off→off
off→off→off
on→on→on
off→off→off
on→off→on
on→off→on
• The relationship between the wake-up and pressing key is shown as below:
Press key
Any key
Press key
Invalid key
Valid key
Press key
Release key
≥ (tKCT+tKPW)
Valid key
Release key
≥ (tKCT+tKPW)
Release key
< tKCT
INT flag or INT pin output
(When the act bit of Frame/INT
setting command is set to “1”)
Key data are updated
Key data are updated
Read key data command
set by MCU
When after the key data has been
read,Clears the key data RAM.
When the key data has been read,
the key data RAM will be cleared.
Standby mode command
set by MCU
Wake-up
Normal active status
Normal active status
HT16LK24 operation status
Standby status
• As the following diagram shown, if the KS3-K0 key is kept in a pressed state before entering the standby mode,
the device can not be woken up by the KS0-K0, KS1-K0 and KS2-K0 key presses.
These keys can not wake-up IC
keep pressing the key
KS0
KS1
KS2
KS3
K0
Rev. 1.10
K1
K2
26
March 18, 2014
HT16LK24
I2C Serial Interface
I2C Operation
The device supports I2C serial interface. The I2C bus is for bidirectional, two-line communication between
different ICs or modules. The two lines are a serial data line, SDA, and a serial clock line, SCL. Both lines are
connected to the positive supply via pull-up resistors with a typical value of 4.7KΩ. When the bus is free, both
lines are high. Devices connected to the bus must have open-drain or open-collector outputs to implement a wiredor function. Data transfer is initiated only when the bus is not busy.
Data Validity
The data on the SDA line must be stable during the high period of the serial clock. The high or low state of the
data line can only change when the clock signal on the SCL line is Low as shown in the diagram.
SDA
SCL
Change of data
allowed
Data line stable;
Data valid
START and STOP Conditions
• A high to low transition on the SDA line while SCL is high defines a START condition.
• A low to high transition on the SDA line while SCL is high defines a STOP condition.
• START and STOP conditions are always generated by the master. The bus is considered to be busy after the
START condition. The bus is considered to be free again a certain time after the STOP condition.
• The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In some respects, the
START(S) and repeated START (Sr) conditions are functionally identical.
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
Byte Format
Every byte put on the SDA line must be 8-bit long. The number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit,
MSB, first.
P
SDA
Sr
SCL
Rev. 1.10
S
or
Sr
1
2
7
8
9
ACK
27
1
2
3-8
9
ACK
P
or
Sr
March 18, 2014
HT16LK24
Acknowledge
• Each bytes of eight bits is followed by one acknowledge bit. This Acknowledge bit is a low level placed on the
bus by the receiver. The master generates an extra acknowledge related clock pulse.
• A slave receiver which is addressed must generate an Acknowledge, ACK, after the reception of each byte.
• The device that acknowledges must pull down the SDA line during the acknowledge clock pulse so that it
remains stable low during the high period of this clock pulse.
• A master receiver must signal an end of data to the slave by generating a not-acknowledge, NACK, bit on the
last byte that has been clocked out of the slave. In this case, the master receiver must leave the data line high
during the 9th pulse to not acknowledge. The master will generate a STOP or repeated START condition.
Data Output
by Transmitter
not acknowledge
Data Outptu
by Receiver
acknowledge
SCL From
Master
1
S
2
7
8
START
condition
9
clock pulse for
acknowledgement
Slave Addressing
• The slave address byte is the first byte received following the START condition form the master device. The
first seven bits of the first byte make up the slave address. The eighth bit defines a read or write operation to be
performed. When the R/W bit is "1", then a read operation is selected. A "0" selects a write operation.
• TheHT16LK24 address bits are "0111101". When an address byte is sent, the device compares the first seven
bits after the START condition. If they match, the device outputs an Acknowledge on the SDA line.
Slave Address
MSB
0
Rev. 1.10
LSB
1
1
1
1
28
0
1
R/W
March 18, 2014
HT16LK24
I2C Interface Write Operation
Byte Write Operation
• Single Command Type
A Single Command write operation requires a START condition, a slave address with an R/W bit, a command
byte and a STOP condition for a single command write operation.
Slave Address
S
0
1
1
1
1
Command byte
0
1
0
P
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
Write ACK
ACK
1st
I2C Single Command Type Write Operation
• Compound Command Type
A Compound Command write operation requires a START condition, a slave address with an R/W bit, a
command byte, up to two command setting bytes and a STOP condition for a compound command write
operation.
Slave Address
S
0
1
1
1
1
0
1
0
Command byte
Command setting
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
Write ACK
ACK
1st
P
ACK
2nd
2
I C Compound Command Type Write Operation – One Command Setting Byte
Command byte
Command setting 1
Command setting 2
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
Slave Address
S
0
1
1
1
1
0
1
0
Writer ACK
ACK
1st
ACK
2nd
P
ACK
3rd
2
I C Compound Command Type Write Operation – Two Command Setting Bytes
• Single Display RAM Data Byte
A single display RAM data byte write operation requires a START condition, a slave address with an R/W bit, a
display data input command byte, a valid Register Address byte, a Data byte and a STOP condition.
Slave Address
S
0
1
1
1
1
Command byte
0
1
0
1
Write ACK
0
0
0
0
1st
0
Register Address byte
0
0
X
ACK
X
A5
A4
A3
2nd
A2
Data byte
A1
A0
D7
ACK
D6
D5
D4
D3
D2
D1
D0
P
ACK
2
I C Display RAM Single Data Byte Write Operation
Rev. 1.10
29
March 18, 2014
HT16LK24
Display RAM Page Write Operation
After a START condition the slave address with the R/W bit is placed on the bus followed with a display data input
command byte and the specified display RAM Register Address of which the contents are written to the internal
address pointer. The data to be written to the memory will be transmitted next and then the internal address pointer will
be incremented by 1 to indicate the next memory address location after the reception of an acknowledge clock pulse.
After the internal address point reaches the maximum memory address, the address pointer will be reset to 00H.
Duty
Maximum Memory Address
1/1, 1/2, 1/3, 1/4
21H
1/8
3EH
Slave Address
S
0
1
1
1
1
Command byte
0
1
0
Write
1
0
0
D6
D5
D4
D3
0
0
Register Address byte
0
0
X
X
A5
1st
A4
A3
D1
D0
D7
1st data
A1
A0
ACK
ACK
Data byte
D2
A2
2nd
ACK
Data byte
D7
0
D6
D5
D4
D3
Data byte
D2
D1
D0
D7
D6
D5
2nd data
D4
D3
Nth data
ACK
ACK
ACK
D2
D1
P
D0
ACK
2
I C Interface N Bytes Display RAM Data Write Operation
Rev. 1.10
30
March 18, 2014
HT16LK24
I2C Interface Read Operation – Display RAM, Key Data and INT flag
In this mode, the master reads the device data after setting the slave address. Following the R/W bit (="0") is an
acknowledge bit, a command byte and the register address byte which is written to the internal address pointer.
After the start address of the Read Operation has been configured, another START condition and the slave
address transferred on the bus followed by the R/W bit (="1"). Then the MSB of the data which was addressed is
transmitted first on the I2C bus. The address pointer is only incremented by 1 after the reception of an acknowledge
clock. That means that if the device is configured to transmit the data at the address of AN+1, the master will read
and acknowledge the transferred new data byte and the address pointer is incremented to AN+2. After the internal
address pointer reaches the maximum memory address, the address pointer will be reset to 00H.
This cycle of reading consecutive addresses will continue until the master sends a STOP condition.
Slave Address
S
0
1
1
1
Command byte
1
0
1
0
1
Write
Slave Address
S
0
1
1
1
0
0
0
0
Register Address byte
0
0
0
0
1
1
D7
D6
D5
A5
A4
D4
A3
A2
A1
P
A0
2nd
ACK
ACK
Data byte
D3
D2
D1
D0
D7
D6
D5
D4
1st data
Read
X
1st
ACK
Data byte
1
X
Data byte
D3
D2
D1
D0
D7
D6
D5
D4
2nd data
ACK
D3
D2
D1
D0
Nth data
ACK
ACK
P
NACK
ACK
I2C Interface N Bytes Display RAM Data Read Operation
Command byte
Slave Address
S
0
1
1
1
1
0
1
0
1
Write
0
1
1
1
1
0
0
0
Register Address byte
0
0
0
X
1
1
D7
Read
D6
X
X
D5
D4
X
A2
A1
P
A0
2nd
ACK
ACK
Data byte
0
X
1st
ACK
Device Address
S
1
D3
Data byte
D2
D1
D0
D7
D6
D5
1st data
D4
D3
Data byte
D2
D1
D0
D7
D6
D5
2nd data
ACK
D4
D3
8th data
ACK
ACK
D2
D1
D0
P
NACK
ACK
2
I C Interface Key Data Read Operation
Slave Address
S
0
1
1
1
Command byte
1
0
1
0
1
Write
1
1
0
0
Register Address byte
0
0
0
0
1
1
0
0
0
1st
ACK
1
0
0
ACK
1
0
P
0
2nd
Device Address
S
0
ACK
Data byte
0
1
1
0
0
0
0
0
0
0
INT
flag
INT flag register data
Read ACK
P
NACK
2
I C Interface INT Flag Read Operation
Rev. 1.10
31
March 18, 2014
HT16LK24
SPI Serial Interface
SPI Operation
The device also includes a 3-wire SPI serial interface. The SPI operations are described as follows:
• The CSB pin is used to activate the data transfer. When the CSB pin is at a high level, the SPI operation will be
reset and stopped. If the CSB pin changes state from high to low, data transmission will start.
• The data is transferred from the MSB of each byte and is shifted into the shift register during each CLK rising
edge.
• The input data is automatically latched into the internal register for each 8-bit input data after the CSB signal
goes low.
• For read operations, the MCU should assert a high pulse on the CSB pin to change the data transfer direction
from input mode to output mode on the DIO pin after sending the command byte and the setting values. If the
MCU sets the CSB signal to a high level again after receiving the output data, the data direction on the DIO pin
will be changed into input mode and the read operation will end.
• For a read operation, the data is output on the DIO pin at the CLK falling edge.
• For display RAM data read/write operations using the SPI interface, the read/write control bit is contained in
the Display Data Input Command. Refer to the Display Data Input Command description for more details.
SPI Interface Write Operation
Byte Write Operation
• Single Command Type
A Single Command write operation is activated by the CSB signal going low. The 8-bit command byte is shifted
from the MSB into the shift register at each CLK rising edge.
CSB
CLK
Command byte
DIO
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
SPI Single Command Type Write Operation
• Compound Command Type
For a compound command, an 8-bit command byte is first shifted into the shift register followed by an 8-bit
command setting. Note that the CLK high pulse width, after the command byte has been shifted in, must remain
at this level for at least 2μs after which the command setting data can be consecutively shifted in.
CSB
2µs(min)
CLK
DIO
Command byte
Command setting
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SPI Compound Command Type Write Operation – One Command Setting Byte
Rev. 1.10
32
March 18, 2014
HT16LK24
CSB
2µs(min)
CLK
DIO
2µs(min)
Command byte
Command setting 1
Command setting 2
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
2nd
3rd
Write
1st
SPI Compound Command Type Write Operation – Two Command Setting Bytes
• Single Display RAM Data Byte
The single display RAM data write operation consists of a display data input (write) command, a register
address and a write data byte.
CSB
2µs(min)
2µs(min)
CLK
Display Data Input command byte
1
DIO
0
0
0
0
0
0
0
Data byte
Register Address byte
X
X
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SPI Single Display RAM Data Byte Write Operation
Display RAM Page Write Operation
The display RAM Page write operation consists of a display data write command, a register address of which the
contents are written to the internal address pointer followed by N bytes of written data. The data to be written to
the memory will be transmitted next and then the internal address pointer will be automatically incremented by
1 to indicate the next memory address location. After the internal address point reaches the maximum memory
address, the address pointer will be reset to 00H.
Duty
Maximum Memory Address
1/1, 1/2, 1/3, 1/4
21H
1/8
3EH
CSB
CLK
2μs(min)
2μs(min)
Display Data Input Command byte
DIO
1
0
0
0
0
0
0
2μs(min)
Data byte
Register Address byte
0
X
X
A5
A4
A3
A2
2μs(min)
A1
A0
D7
D6
D5
D4
D3
2μs(min)
Data byte
D2
D1
D0
1st data
D7
D6
D5
D4
D3
2nd data
Data byte
D2
D1
D0
D7
3rd
data
Data byte
D0
(N-1)th
data
D7
D6
D5
D4
D3
D2
D1
D0
Nth data
SPI Interface N Bytes Display RAM Data Write Operation
Rev. 1.10
33
March 18, 2014
HT16LK24
SPI Interface Read Operation – Display RAM, Key Data and INT Flag
In this mode, the master reads the HT16LK24 data after sending the Display Data Input command when the CSB
pin changes state from high to low. Following the read/write control bit, which is contained in the Display Data
Input command, is the register address byte which is written to the internal address pointer. After the start address
of the Read Operation has been configured, another CSB high pulse is placed on the bus and then the MSB of the
data which was addressed is transmitted first on the SPI bus. The address pointer is only incremented by 1 after the
reception of each data byte. That means that if the device is configured to transmit the data at the address of AN+1,
the master will read the transferred data byte and the address pointer is incremented to AN+2. After the internal
address pointer reaches the maximum memory address, the address pointer will be reset to 00H.
This cycle of reading consecutive addresses will continue until the master pulls the CSB line to a high level to
terminate the data transfer.
CSB
CLK
2μs(min)
2μs(min)
Display data Input command byte
DIO
1
0
0
0
0
0
0
1
X
X
A5
A4
A3
A2
2μs(min)
Data byte
Register Address byte
A1
A0
D7
D6
D5
D4
D3
2μs(min)
Data byte
D2
D1
D0
D7
D6
D5
1st data
D4
D3
Data byte
D2
D1
D0
Data byte
D7
D0
3rd
data
2nd data
D7
D6
D5
(N-1)th
data
D4
D3
D2
D1
D0
Nth data
SPI Interface N Bytes Display RAM Data Read Operation
CSB
2µs(min)
2µs(min)
CLK
Key data input command byte
DIO
1
1
0
0
0
1st
0
0
1
X
X
X
X
Read
X
A2
2µs(min)
Key data byte
Register Address byte
A1
D7
A0
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D7
D0
Key data byte
D0
(n-1)th
data
3rd
data
2nd data
1st data
2nd
2µs(min)
Key data byte
Key data byte
D7
D6
D5
D4
D3
D2
D1
D0
8th data
SPI Interface Key Data Read Operation
CSB
2µs(min)
CLK
INT flag input command byte
DIO
1
1
1
0
0
1st
0
0
INT flag register
Register Address byte
1
Read
0
0
0
0
0
2nd
0
0
0
0
0
0
0
0
0
0
INT
flag
1st data
SPI Interface INT Flag Read Operation
Rev. 1.10
34
March 18, 2014
HT16LK24
Command Summary
Software Reset Command
This command is used to initialize the device.
Function
Byte
(MSB)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Soft Reset Command
1st
1
0
1
0
1
0
1
(LSB)
Note
Bit0
0
—
R/W
Def
W
—
Note:
• When this software reset command is executed, all the command registers are initialized to the default values.
• After the reset command is executed, the device will experience an internal initialization for 1ms.
• Normal operation can be executed after the device initialization is complete.
• During the initialization period, no commands can be executed.
• If the programmed command is not defined, the function will not be affected.
The status of the internal circuits after initialization is as follows:
• All segment/common outputs are set to VLCD.
• The drive mode 1/4 duty output and 1/3 bias is selected.
• The System Oscillator and the LCD bias generator are in an off state.
• The LCD Display is in an off state and the integrated regulator is disabled.
• The key scan function is disabled.
• The INT pin is set to a high level.
• The operation mode is set to normal mode.
• The Segment/KEY/LED shared pin is setup as a Segment pin.
• The Frame Frequency is set to 64Hz.
• The blinking function is switched off
Rev. 1.10
35
March 18, 2014
HT16LK24
Display Data Input Command
This command is used to access the display data by the MCU to the memory MAP of the device.
Function
Byte
Display Data Input/
output Command
1st
Address pointer
2nd
(MSB)
(LSB)
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1
Bit7
Bit0
1
0
0
0
0
0
0
Note
R/W Def
0
Write operation
W
—
R
—
W
00H
1
0
0
0
0
0
0
1
Read operation for 3-wire
SPI interface used only.
X
X
A5
A4
A3
A2
A1
A0
Display data start address
of memory map
Note:
Duty
Maximum Memory Address
1/1, 1/2, 1/3, 1/4
21H
1/8
3EH
• Power on status: the address is set to 00H
• If the programmed command is not defined, the function will not be affected.
Key Data Input Command
This command is used to access the key data by the MCU to the memory MAP of the device.
Function
Byte
Key Data
access
Command
1st
Address pointer
2nd
(MSB)
(LSB)
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1
Bit7
Bit0
Note
R/W Def
1
1
0
0
0
0
0
0
Write operation
W
—
1
1
0
0
0
0
0
1
Read operation for 3-wire
SPI interface used only.
R
—
X
X
X
X
X
A2
A1
A0
Key data start address of
memory map
W
00H
Note:
• Power on status: the address is set to 00H
• If the programmed command is not defined, the function will not be affected.
INT Flag Access Command
This command is used to access the INT flag by the MCU to the memory MAP of the device.
Function
Byte
INT flag
access Command
1st
Address pointer
2nd
(MSB)
(LSB)
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1
Bit7
Bit0
Note
R/W Def
1
1
1
0
0
0
0
0
Write operation
W
—
1
1
1
0
0
0
0
1
Read operation for 3-wire
SPI interface used only.
R
—
0
0
0
0
0
0
0
0
INT flag register address,
read only.
W
00H
Note:
• Power on status: the address is set to 00H
• If the programmed command is not defined, the function will not be affected.
Rev. 1.10
36
March 18, 2014
HT16LK24
Drive Mode Command
Byte
(MSB)
Bit7
Bit6
Bit5
Bit4
Drive mode setting
command
1st
1
0
0
0
0
0
Duty, Bias and
pin-shared setting
2nd
X
Duty0
X
X
Function
Duty2 Duty1
Bit3 Bit2
Bit1
(LSB)
Bit0
Note
R/W
Def
1
0
—
W
—
—
W
32H
Bias1 Bias0
Note:
Bias1
Bias0
LCD Bias
0
0
1/1 bias
0
1
1/2 bias
1
0
1/3 bias (default)
1
1
1/4 bias
Duty2
Duty1
Duty0
LCD Duty
0
0
0
1/1 duty
0
0
1
1/2 duty
0
1
0
1/3 duty
0
1
1
1/4 duty (default)
1
x
x
1/8 duty
• Power on status: The drive mode 1/4 duty output and 1/3 bias is selected and also the segment output pins are selected.
• If the programmed command is not defined, the function will not be affected.
System Mode Command
This command controls the internal system oscillator on/off and display on/off.
(MSB)
Bit6
Bit7
Function
Byte
System mode setting
command
1st
1
System oscillator and
Display on/off Setting
2nd
X
Bit5
Bit4
Bit3
Bit2
Bit1
(LSB)
Bit0
Note
R/W
Def
0
0
0
0
1
0
0
—
W
—
X
X
X
X
X
S
E
—
W
00H
Note:
Bit
S
E
Internal System oscillator
LCD Display
off
0
X
off
1
0
on
off
1
1
on
on
• Power on status: Display off and disable the internal system oscillator.
• If the programmed command is not defined, the function will not be affected.
Rev. 1.10
37
March 18, 2014
HT16LK24
Frame/PWM Frequency Setting Command
This command is used to select the LCD display frame frequency, the PWM frequency and the PWM level setting.
Function
Byte
(MSB)
Bit6
Bit7
Bit5
Bit4
Bit3
Bit2
Bit1
(LSB)
Bit0
Note
R/W Def
Frequency
command
1st
1
0
0
0
0
1
1
0
—
W
—
Frequency setting
2nd
X
PWS
X
PF1
PF0
X
F1
F0
—
W
02H
Note:
Bit [1:0]
LCD Frame Frequency
F1, F0
1/1, 1/2, 1/4, 1/8 duty
00
85.3 Hz
91 Hz
01
170.6 Hz
182 Hz
10
64 Hz (default)
68.3 Hz (default)
11
128 Hz
136.5 Hz
Bit [4:3]
PF1, PF0
1/3 duty
PWM Frequency (fPWM)
00
85.3 Hz
01
128 Hz
10
170.6 Hz
11
256 Hz
PWS
PWM step selection
0
64
1
128
Note:
If the LED driver is used for back light application, it is suggested to set the PWM frequency as the following
table shown to avoid from the display flicker. If the LED driver is not used for back light application, there is no
limitation for the PWM frequency selection.
Frame Frequency
PWM Frequency
PWM step= 64 steps
PWM step =128 steps
64Hz
85.3 Hz or170.6Hz
85.3 Hz or170.6Hz
85.3Hz
128Hz or 256Hz
128Hz or 256Hz
128Hz
170.6Hz
invalid
170.6 Hz
256 Hz
invalid
• Power on status: LCD Frame frequency is set to 64Hz and PWM frequency is set to 85.3Hz.
• If the programmed command is not defined, the function will not be affected.
Rev. 1.10
38
March 18, 2014
HT16LK24
Blinking Frequency Command
This command defines the blinking frequency of the display modes.
(MSB)
Bit6 Bit5 Bit4 Bit3 Bit2
Bit7
Function
Byte
Blinking Frequency
command
1st
1
0
0
0
1
Blinking Frequency
setting
2nd
X
X
X
X
X
Bit1
(LSB)
Bit0
Note
R/W
Def
0
0
0
—
W
—
X
BK1
BK0
—
W
00H
Note:
Bit
Blinking Frequency
BK1
BK0
0
0
Blinking off (default)
0
1
2Hz
1
0
1Hz
1
1
0.5Hz
• Power on status: Blinking function is switched off.
• If the programmed command is not defined, the function will not be affected.
Internal Voltage Adjustment (IVA) Setting Command
The internal voltage (VLCD) adjustment can provide eight kinds of regulator voltage adjustment options by setting
the LCD operating voltage adjustment command.
Function
(MSB)
(LSB)
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1
Bit7
Bit0
Byte
Note
R/W
Def
Internal Voltage
Adjustment (IVA) Setting
1st
1
0
0
0
1
0
1
0
—
W
—
Internal Voltage Adjust
control
2nd
X
X
X
VE
X
V2
V1
V0
—
W
00H
Note:
VE
Regulator adjustment
0
Off - bias voltage is supplied from VLCD pin (default)
1
On - bias voltage is supplied from the internal regulator
V2
V1
V0
Regulator output voltage (V)
0
0
0
3.0V
0
0
1
3.2V
0
1
0
3.3V
0
1
1
3.4V
1
0
0
4.4V
1
0
1
4.5V
1
1
0
4.6V
1
1
1
5.0V
• Power on status: disable the internal regulator.
• When the VLCD voltage is lower than 3.5V, it is recommended to disable the internal regulator so that the
VLCD voltage is directly connected to the internal Bias voltage generator.
• Caution: use the internal regulator when the "Regulator output voltage < VLCD -0.5V "
• If the programmed command is not defined, the function will not be affected.
Rev. 1.10
39
March 18, 2014
HT16LK24
LED Output1 Control Command
This command defines the LED0~LED7 data and control the corresponding LED PWM dimming function.
Function
LED output1
control
Byte
(MSB)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
(LSB)
Bit0
1st
1
0
0
1
0
1
0
0
LEDn PWM
2nd
enable control
LED0~LED7
output data
PWEN7 PWEN6 PWEN5 PWEN4 PWEN3 PWEN2 PWEN1 PWEN0
3rd
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
Note R/W Def
—
W
—
—
W
00H
—
W
00H
PWENn
LEDn PWM
Function Control
Note
0
Off
The LED output status will not be changed by System oscillator
and LCD display On/Off control setting.
1
On
The LED output will be switched off when the device enters the
standby mode and turned on again after it is woken up.
LEDn
LEDn Data
0
0 – LEDn is switched off
1
1 – LEDn is turned on
Note:
• "n" ranges from 0~7
• Power on reset status: All LED output pins are set to a high level with a voltage of VLCD.
• The LED and PWM registers and latches are cleared after a new configuration is written into the KX, KY and
L fields in the SEG/KSL shared pin configuration setting command.
• If the programmed command is not defined, the function will not be affected.
Rev. 1.10
40
March 18, 2014
HT16LK24
LED Output2 Control Command
This command defines the LED8~LED11 data and control the corresponding LED PWM dimming function.
Byte
(MSB)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
(LSB)
Bit0
Note
LED output2
control
1st
1
0
0
1
0
1
1
0
—
W
—
LEDn PWM
enable control
2nd
x
x
x
x
—
W
00H
LED8~LED11
output data
3rd
x
x
x
x
—
W
00H
Function
PWEN11 PWEN10 PWEN9 PWEN8
LED11
LED10
LED9
LED8
PWENn
LEDn PWM
Function Control
0
Off
The LED output status will not be changed by System
oscillator and LCD display On/Off control setting.
1
On
The LED output will be switched off when the device enters
the standby mode and turned on again after it is woken up.
R/W Def
Note
LEDn
LEDn Data
0
0 – LEDn is switched off
1
1 – LEDn is turned on
Note:
• "n" ranges from 8~11
• Power on reset status: All LED output pins are set to a high level with a voltage of VLCD.
• The LED and PWM registers and latches are cleared after a new configuration is written into the KX, KY and
L fields in the SEG/KSL shared pin configuration setting command.
• If the programmed command is not defined, the function will not be affected.
Rev. 1.10
41
March 18, 2014
HT16LK24
SEG/KSL Shared Pin Configuration Command
This command defines the segment, Key input, Key scan output and LED pin number on the shared pins. It is
recommended that the SEG/KSL shared pin configuration should be changed when the LCD display is switched
off. Otherwise, the unpredictable results will occur.
Function
Byte
(MSB)
(LSB)
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1
Bit7
Bit0
Shared pin
configuration
1st
1
0
0
0
1
1
1
0
LED pin number
setting
2nd
x
x
x
x
L3
L2
L1
L0
Key input and Key
scan output pin
number setting
3rd
KX2
KX1 KX0 KY4 KY3 KY2 KY1
KY0
Note
R/W Def
—
W
—
L: LED pin setting
W
00H
KX: Key output setting
KY: Key input setting
W
00H
L [3:0]
LED pin number (NLED)
LED Pin Configuration Descriptions
0000
0
No LED pin selected
0001
1
LED0 selected
0010
2
LED0~LED1 selected
0011
3
LED0~LED2 selected
0100
4
LED0~LED3 selected
0101
5
LED0~LED4 selected
0110
6
LED0~LED5 selected
0111
7
LED0~LED6 selected
1000
8
LED0~LED7 selected
1001
9
LED0~LED8 selected
1010
10
LED0~LED9 selected
1011
11
LED0~LED10 selected
1100~1111
12
LED0~LED11 selected
KX [2:0]
Key Scan output pin
number (NKS)
Key Scan Pin (KS) Configuration Descriptions
000
0
No KS pin selected
001
1
KS0 selected
010
2
KS0~KS1 selected
011
3
KS0~KS2 selected
100~111
4
KS0~KS3 selected
Rev. 1.10
42
March 18, 2014
HT16LK24
KY [4:0]
Key input pin number
(NK)
Key input Pin (K) Configuration Descriptions
00000
0
No Key input selected
00001
1
1 Key input selected
00010
2
2 Key input selected
00011
3
3 Key input selected
00100
4
4 Key input selected
00101
5
5 Key input selected
00110
6
6 Key input selected
00111
7
7 Key input selected
01000
8
8 Key input selected
01001
9
9 Key input selected
01010
10
10 Key input selected
01011
11
11 Key input selected
01100
12
12 Key input selected
01101
13
13 Key input selected
01110
14
14 Key input selected
01111
15
15 Key input selected
10000~11111
16
16 Key input selected
Note:
• The maximum SEG/KSL shared pin number is 16, i.e., (NLED+NKS+NK+NSEG) = 16.
NSEG: Segment pin number, up to 16.
NK: Key input pin number, up to 16.
NKS: Key scan output pin number, up to 4.
NLED: LED output pin number, up to 12.
• The pin-shared function priority: LED > Key Scan output > Key input > Segment output.
• The LED data and Key data are cleared and INT output is changed to its inactive level after a new configuration
is written into the KX, KY or L field in the SEG/KSL shared pin configuration setting command.
• Power on reset status: The shared pin is set as a segment output pin.
• If the programmed command is not defined, the function will not be affected
Rev. 1.10
43
March 18, 2014
HT16LK24
• SEG/KSL Shared Pin Configuration example:
Shared pins Configuration
setting
Key Input/Output
number setting
SEG / KSL Shared pins
LED
number
setting
Seg51_ Seg52_ Seg53_ Seg54_ Seg55_ Seg56_ Seg57_ Seg58_ Seg59_ Seg60_ Seg61_ Seg62_ Seg63_ Seg64_ Seg65_ Seg66_
KSL15 KSL14 KSL13 KSL12 KSL11 KSL10
KSL9
KSL8
KSL7
KSL6
KSL5
KSL4
KSL3
KSL2
KSL1
KSL0
KX
[2:0]
KY
[4:0]
L [3:0]
000b
00000b
0000b
Seg51
Seg52
Seg53
Seg54
Seg55
Seg56
Seg57
Seg58
Seg59
Seg60
Seg61
Seg62
Seg63
Seg64
Seg65
Seg66
000b
00000b
0001b
Seg51
Seg52
Seg53
Seg54
Seg55
Seg56
Seg57
Seg58
Seg59
Seg60
Seg61
Seg62
Seg63
Seg64
Seg65
LED0
000b
00000b
0010b
Seg51
Seg52
Seg53
Seg54
Seg55
Seg56
Seg57
Seg58
Seg59
Seg60
Seg61
Seg62
Seg63
Seg64
LED1
LED0
000b
00000b
0011b
Seg51
Seg52
Seg53
Seg54
Seg55
Seg56
Seg57
Seg58
Seg59
Seg60
Seg61
Seg62
Seg63
LED2
LED1
LED0
000b
00000b
0100b
Seg51
Seg52
Seg53
Seg54
Seg55
Seg56
Seg57
Seg58
Seg59
Seg60
Seg61
Seg62
LED3
LED2
LED1
LED0
000b
00000b
0101b
Seg51
Seg52
Seg53
Seg54
Seg55
Seg56
Seg57
Seg58
Seg59
Seg60
Seg61
LED4
LED3
LED2
LED1
LED0
000b
00000b
0110b
Seg51
Seg52
Seg53
Seg54
Seg55
Seg56
Seg57
Seg58
Seg59
Seg60
LED5
LED4
LED3
LED2
LED1
LED0
000b
00000b
0111b
Seg51
Seg52
Seg53
Seg54
Seg55
Seg56
Seg57
Seg58
Seg59
LED6
LED5
LED4
LED3
LED2
LED1
LED0
000b
00000b
1000b
Seg51
Seg52
Seg53
Seg54
Seg55
Seg56
Seg57
Seg58
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
000b
00000b
1001b
Seg51
Seg52
Seg53
Seg54
Seg55
Seg56
Seg57
LED8
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
000b
00000b
1010b
Seg51
Seg52
Seg53
Seg54
Seg55
Seg56
LED9
LED8
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
000b
00000b
1011b
Seg51
Seg52
Seg53
Seg54
Seg55
LED10
LED9
LED8
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
000b
00000b
1100b
Seg51
Seg52
Seg53
Seg54
LED11
LED10
LED9
LED8
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
100b
00100b
0100b
Seg51
Seg52
Seg53
Seg54
K11
K10
K9
K8
KS3
KS2
KS1
KS0
LED3
LED2
LED1
LED0
100b
01000b
0100b
K15
K14
K13
K12
K11
K10
K9
K8
KS3
KS2
KS1
KS0
LED3
LED2
LED1
LED0
000b
01100b
0100b
K15
K14
K13
K12
K11
K10
K9
K8
K7
K6
K5
K4
LED3
LED2
LED1
LED0
001b
00111b
1000b
K15
K14
K13
K12
K11
K10
K9
KS0
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
010b
00110b
1000b
K15
K14
K13
K12
K11
K10
KS1
KS0
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
011b
00101b
1000b
K15
K14
K13
K12
K11
KS2
KS1
KS0
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
100b
00100b
1000b
K15
K14
K13
K12
KS3
KS2
KS1
KS0
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
000b
01000b
1000b
K15
K14
K13
K12
K11
K10
K9
K8
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
001b
00011b
1100b
K15
K14
K13
KS0
LED11
LED10
LED9
LED8
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
010b
00010b
1100b
K15
K14
KS1
KS0
LED11
LED10
LED9
LED8
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
011b
00001b
1100b
K15
KS2
KS1
KS0
LED11
LED10
LED9
LED8
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
000b
00100b
1100b
K15
K14
K13
K12
LED11
LED10
LED9
LED8
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
001b
01111b
0000b
K15
K14
K13
K12
K11
K10
K9
K8
K7
K6
K5
K4
K3
K2
K1
KS0
010b
01110b
0000b
K15
K14
K13
K12
K11
K10
K9
K8
K7
K6
K5
K4
K3
K2
KS1
KS0
011b
01101b
0000b
K15
K14
K13
K12
K11
K10
K9
K8
K7
K6
K5
K4
K3
KS2
KS1
KS0
100b
01100b
0000b
K15
K14
K13
K12
K11
K10
K9
K8
K7
K6
K5
K4
KS3
KS2
KS1
KS0
100b
00100b
0000b
Seg51
Seg52
Seg53
Seg54
Seg55
Seg56
Seg57
Seg58
K7
K6
K5
K4
KS3
KS2
KS1
KS0
000b
01000b
0000b
Seg51
Seg52
Seg53
Seg54
Seg55
Seg56
Seg57
Seg58
K7
K6
K5
K4
K3
K2
K1
K0
000b
10000b
0000b
K15
K14
K13
K12
K11
K10
K9
K8
K7
K6
K5
K4
K3
K2
K1
K0
Rev. 1.10
44
March 18, 2014
HT16LK24
Key Scan Control Command
This command defines the INT pin polarity and Key scan pulse width.
Byte
(MSB)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
(LSB)
Bit0
Note
R/W
Def
Key scan control
command
1st
1
0
0
1
0
0
0
0
—
W
—
Key scan pulse
setting
2nd
POL
x
x
x
x
x
KF1
KF0
—
W
01H
Function
The KF field is used to define the Key scan pulse width.
KF1
KF0
Key Scan Pulse Width (tKPW)
Key Scan Cycle (tKCT)
Key Press De-bounce Time (tKCT)
0
0
1 ms
4 ms
4 ms ~ 8 ms
0
1
2 ms
8 ms
8 ms ~ 16 ms
1
0
3 ms
12 ms
12 ms ~ 16 ms
1
1
4 ms
16 ms
16 ms ~ 32 ms
The POL bit is used to define the INT output pin polarity.
POL
INT Output Pin Polarity
0
Active Low
1
Active High
Note:
• Power on reset status: The key scan pulse width is set to 2 ms and the INT output level is set to high.
• If the programmed command is not defined, the function will not be affected.
Rev. 1.10
45
March 18, 2014
HT16LK24
LED PWM Luminance Control Command
This command is used to select the LED output pin and define the corresponding LED PWM luminance duty.
Byte
(MSB)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
(LSB)
Bit0
LED PWM
Luminance control
command
1st
1
0
0
1
0
0
1
0
—
W
—
LED PWM output
selection
2nd
x
x
x
x
LS3
LS2
LS1
LS0
—
W
00H
PWM dimming value
3rd
x
—
W
00H
Function
Note R/W Def
PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0
The LS field is used to select the LED output pin with the PWM luminance function as the relevant PWM
function is enabled.
LS [3:0]
LED Output Selected
0000
LED0
0001
LED1
0010
LED2
0011
LED3
0100
LED4
0101
LED5
0110
LED6
0111
LED7
1000
LED8
1001
LED9
1010
LED10
1011
LED11
1100~1111
Invalid
The PWM field is used to define the selected LED output PWM dimming value.
PWM [6:0]
Dimming Values
Note
0000000
1/128
Lowest LED luminance.
0000001
2/128
—
0000010
3/128
—
0000011
4/128
—
0000100
5/128
—
:
:
:
:
:
:
:
:
:
0111101
62/128
—
0111110
63/128
—
0111111
64/128
Highest LED luminance for 64-step PWM setting.
1000000
65/128
—
1000001
66/128
—
:
:
:
:
:
:
:
:
:
1111100
125/128
1111101
126/128
1111110
127/128
1111111
128/128
Rev. 1.10
Highest LED luminance for 128-step PWM setting.
46
March 18, 2014
HT16LK24
If the PWM dimming level is set as 64 steps, the PWM6 bit has no effect on changing the PWM dimming value.
fPWM
PWEN0~11 bits
Dimming Value
1/128
LED pin output at
dimming value=1/128
2/128
3/128
4/128
126/128 127//128 128/128
5/128
Hi-Z
Dimming Value
VSS
Hi-Z
LED pin output at
dimming value=2/128
VSS
Hi-Z
LED pin output at
dimming value=3/128
VSS
Hi-Z
LED pin output at
dimming value=4/128
VSS
Hi-Z
LED pin output at
dimming value=5/128
VSS
Hi-Z
LED pin output at
dimming value=126/128
VSS
Hi-Z
LED pin output at
dimming value=127/128
VSS
Hi-Z
LED pin output at
dimming value=128/128
VSS
128-step PWM Dimming level
fPWM
PWEN0~11 bits
Dimming Value
LED pin output at
dimming value=1/64
1/64
2/64
3/64
4/64
62/64
5/64
63/64
64/64
Hi-Z
Dimming Value
VSS
Hi-Z
LED pin output at
dimming value=2/64
VSS
Hi-Z
LED pin output at
dimming value=3/64
VSS
Hi-Z
LED pin output at
dimming value=4/64
VSS
Hi-Z
LED pin output at
dimming value=5/64
VSS
Hi-Z
LED pin output at
dimming value=62/64
VSS
Hi-Z
LED pin output at
dimming value=63/64
VSS
Hi-Z
LED pin output at
dimming value=64/64
VSS
64-step PWM Dimming level
Note: 1. The LED0~LED11 data bits in the LED output control command are set to 1 in the above diagram.
2. The "Hi-Z" notation means that the relevant LED pin is in an NMOS open-drain status.
Note:
• Power on reset status: The dimming value is set to 00H.
• If the programmed command is not defined, the function will not be affected.
Rev. 1.10
47
March 18, 2014
HT16LK24
LCD Driving Current Control Command
This command is used to Select the Current mode according to the characteristics of the LCD panel for achieving
high display quality.
Byte
(MSB)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
(LSB)
Bit0
Note
LCD driving current
control
1st
1
0
0
1
1
0
0
0
—
W
—
Current mode select
2nd
0
0
0
0
0
P2
P1
P0
—
W
01H
Function
R/W Def
The P field is used to select the LCD charge current.
P [2:0]
Current mode
Current consumption (ILCD1)
000
High current
X 1.8
001
Normal current
X 1.0 (default)
010
Low current 1
X 0.67
011
Low current 2
X 0.50
Note:
• Power on reset status: normal current mode.
• If the programmed command is not defined, the function will not be affected.
Rev. 1.10
48
March 18, 2014
HT16LK24
Operation Flow Chart
Access procedures are illustrated below using flowcharts.
Initialization
Power On
Soft reset setting
Internal LCD bias and duty setting
LCD blinking frequency setting
Segment / KEY/ LED shared pin setting
Internal Voltage Adjustment setting
LCD current mode setting
LCD frame frequency
LED PWM frequency and step setting
LED PWM channel select and
PWM dimming value setting
Keyscan pulse width set and
Active level of INT output pin setting
Next processing
Rev. 1.10
49
March 18, 2014
HT16LK24
Display Data Write (Address Setting)
Start
Address setting
Display RAM data write
Display on and enable
internal system clock
Next processing
Rev. 1.10
50
March 18, 2014
HT16LK24
Key Data Read
Start
INT pin active=?
Or
INT flag bit =1?
no
Yes
Read all key data RAM
INT flag bit is set to “0”
INT pin returns to inactive state
and the key data is cleared to 0
Next processing
Rev. 1.10
51
March 18, 2014
HT16LK24
Standby Mode Setting
Start
Send Display off
command
(E bit is set to "0")
Send initial status
command again
Standby mode
no
S bit is set to "1" ?
or Key is pressed?
yes
Wake-up IC
Next processing
Rev. 1.10
52
March 18, 2014
HT16LK24
Application Circuit
(1) The SEG/KSL shared pin configuration is 16 segment outputs.
Shared Pins
Configuration Setting
Command
Duty
KX[2:0] KY[4:0] L[3:0]
1/1
000b
00000b 0000b
Key Circuit
Output
(KS)
Input
(K)
none
none
LED
Output
COM
Output
SEG
Output
none
COM0
SEG0~66
LCD panel
COM
Output
SEG
Output
COM0
SEG0~66
1/2
none
none
none
COM0~1
SEG0~66
COM0~1
SEG0~66
1/3
none
none
none
COM0~2
SEG0~66
COM0~2
SEG0~66
1/4
none
none
none
COM0~3
SEG0~66
COM0~3
SEG0~66
1/8
none
none
none
COM0~7
SEG4~66
COM0~7
SEG0~62
• The RSTB pin is connected to a MCU
2
VLCD
VLCD
VLCD
COM
0.1uF
SEG
VDD
VLCD
VDD
LCD panel
SEG
VDD
VDD
0.1uF
4.7KΩ
COM
0.1uF
LCD panel
0.1uF
4.7KΩ
VDD
VDD
VDD
CSB
CSB
SCL/CLK
SCL/CLK
SDA/DIO
SDA/DIO
INT
INT
RSTB
RSTB
VSS
VSS
VSS
VSS
VSS
VSS
IFS
VDD
IFS
VSS
• RSTB pin is connected to external resistor and capacitor.
2
VLCD
VLCD
VLCD
COM
0.1uF
SEG
VDD
VLCD
VDD
0.1uF
4.7KΩ
LCD panel
SEG
VDD
VDD
COM
0.1uF
LCD panel
0.1uF
4.7KΩ
VDD
VDD
VDD
CSB
CSB
SCL/CLK
SCL/CLK
SDA/DIO
SDA/DIO
INT
VDD
100KΩ
VSS
INT
VDD
RSTB
VSS
0.1uF
VSS
IFS
RSTB
0.1uF
VSS
VSS
VDD
100KΩ
VSS
VSS
IFS
Note: If only the internal power on reset circuit is used, the RSTB pin must be connected to VDD.
Rev. 1.10
53
March 18, 2014
HT16LK24
(2) The SEG/KSL shared pin configuration is 12 segment outputs and 4 LED outputs.
Shared pins
Configuration setting
command
Key circuit
Duty
00000b
0100b
COM
output
SEG
output
Output
(KS)
Input
(K)
1/1
none
none
LED0~3
COM0
1/2
none
none
LED0~3
COM0~1
1/3
none
none
LED0~3
1/4
none
none
LED0~3
1/8
none
none
LED0~3
KX[2:0] KY[4:0] L[3:0]
000b
LED
output
LCD panel
COM
output
SEG
output
SEG0~62
COM0
SEG0~62
SEG0~62
COM0~1
SEG0~62
COM0~2
SEG0~62
COM0~2
SEG0~62
COM0~3
SEG0~62
COM0~3
SEG0~62
COM0~7
SEG4~62
COM0~7
SEG0~58
• The RSTB pin is connected to a MCU.
2
VLCD
VLCD
VLCD
COM
0.1uF
SEG
VDD
VLCD
VDD
LCD panel
SEG
VDD
VDD
0.1uF
0.1uF
4.7KΩ
COM
0.1uF
LCD panel
4.7KΩ
VDD
VDD
VDD
CSB
CSB
SCL/CLK
SDA/DIO
SDA/DIO
INT
INT
RSTB
VSS
SCL/CLK
LED3
VSS
VSS
VDD
IFS
RSTB
VSS
LED2
VLCD
LED1
VSS
LED0
RLED*4
LED3
LED2
VSS
IFS
VSS
LED*4
VLCD
LED1
LED0
RLED*4
LED*4
• The RSTB pin is connected to external resistor and capacitor.
2
VLCD
VLCD
VLCD
COM
0.1uF
SEG
VDD
VLCD
VDD
0.1uF
4.7KΩ
LCD panel
SEG
VDD
VDD
COM
0.1uF
LCD panel
0.1uF
4.7KΩ
VDD
VDD
VDD
CSB
CSB
SCL/CLK
SCL/CLK
SDA/DIO
SDA/DIO
INT
VDD
100KΩ
LED3
0.1uF
VSS
VSS
VSS
VDD
INT
VDD
RSTB
IFS
100KΩ
VLCD
VSS
VSS
LED1
LED0
RLED*4
VSS
LED*4
LED3
0.1uF
VSS
LED2
RSTB
IFS
LED2
VLCD
LED1
LED0
RLED*4 LED*4
Note: If only the internal power on reset circuit is used, the RSTB pin must be connected to VDD.
Rev. 1.10
54
March 18, 2014
HT16LK24
(3) The SEG/KSL shared pin configuration is 4 segment outputs, 4 LED outputs, 4 key scan outputs and 4 key inputs.
Shared Pins
Configuration Setting
Command
KX[2:0] KY[4:0]
100b
00100b
Key Circuit
Duty
COM
Output
SEG
Output
Output
(KS)
Input
(K)
1/1
KS0~3
K8~11
LED0~3
COM0
1/2
KS0~3
K8~11
LED0~3
1/3
KS0~3
K8~11
1/4
KS0~3
1/8
KS0~3
L[3:0]
0100b
LED
Output
LCD Panel
COM
Output
SEG
Output
SEG0~54
COM0
SEG0~54
COM0~1
SEG0~54
COM0~1
SEG0~54
LED0~3
COM0~2
SEG0~54
COM0~2
SEG0~54
K8~11
LED0~3
COM0~3
SEG0~54
COM0~3
SEG0~54
K8~11
LED0~3
COM0~7
SEG4~54
COM0~7
SEG0~50
• The RSTB pin is connected to a MCU.
I2C Interface:
SPI 3-wire Interface:
VLCD
VLCD
VLCD
COM
0.1uF
SEG
VDD
VLCD
VDD
4.7KΩ
VDD
0.1uF
4.7KΩ
VDD
HT16LK24
HT16LK24
K11
K10
K9
K8
CSB
SCL/CLK
VDD
SCL/CLK
=
RSTB
VSS
MCU
RSTB
VSS
LED2
VSS
KS3
KS2
KS1
KS0
INT
LED3
VSS
=
SDA/DIO
KS3
KS2
KS1
KS0
INT
K11
K10
K9
K8
CSB
SDA/DIO
MCU
LCD panel
SEG
VDD
0.1uF
VDD
COM
0.1uF
LCD panel
LED3
VSS
VLCD
LED2
VSS
LED1
VDD
LED0
IFS
VLCD
LED1
RLED*4
LED0
IFS
VSS
LED*4
RLED*4
LED*4
• The RSTB pin is connected to external resistor and capacitor.
I2C Interface:
SPI 3-wire Interface:
VLCD
VLCD
VLCD
COM
0.1uF
SEG
VDD
VLCD
VDD
4.7KΩ
VDD
0.1uF
HT16LK24
4.7KΩ
VDD
CSB
SCL/CLK
HT16LK24
K11
K10
K9
K8
INT
VDD
100KΩ
VSS
RSTB
VDD
CSB
SCL/CLK
=
SDA/DIO
MCU
INT
VDD
VSS
VDD
IFS
100KΩ
VSS
LED2
VLCD
LED*4
=
KS3
KS2
KS1
KS0
LED3
LED2
VSS
VSS
RLED*4
RSTB
0.1uF
VSS
LED1
LED0
K11
K10
K9
K8
SDA/DIO
MCU
KS3
KS2
KS1
KS0
LED3
0.1uF
VSS
LCD panel
SEG
VDD
0.1uF
VDD
COM
0.1uF
LCD panel
IFS
VLCD
LED1
LED0
RLED*4
LED*4
Note: If only the internal power on reset circuit is used, the RSTB pin must be connected to VDD.
Rev. 1.10
55
March 18, 2014
HT16LK24
(4) The SEG/KSL shared pin configuration is 4 LED outputs, 4 key scan outputs and 8 key inputs.
Shared pins
Configuration setting
command
KX[2:0] KY[4:0]
100b
01000b
Key circuit
Duty
COM
output
SEG
output
COM0
SEG0~50
LCD panel
Output
(KS)
Input
(K)
1/1
KS0~3
K8~K15
LED0~3
1/2
KS0~3
K8~K15
LED0~3
COM0~1 SEG0~50 COM0~1 SEG0~50
1/3
KS0~3
K8~K15
LED0~3
COM0~2 SEG0~50 COM0~2 SEG0~50
1/4
KS0~3
K8~K15
LED0~3
COM0~3 SEG0~50 COM0~3 SEG0~50
1/8
KS0~3
K8~K15
LED0~3
COM0~7 SEG4~50 COM0~7 SEG0~46
L[3:0]
0100b
LED
output
COM
output
SEG
output
COM0
SEG0~50
• The RSTB pin is connected to a MCU.
I2C Interface:
SPI 3-wire Interface:
VLCD
VLCD
VLCD
COM
0.1uF
SEG
VDD
4.7KΩ
VDD
VDD
HT16LK24
CSB
SCL/CLK
K15
K14
K13
K12
K11
K10
K9
K8
INT
RSTB
VSS
LCD panel
VDD
0.1uF
HT16LK24
VDD
CSB
SCL/CLK
=
SDA/DIO
MCU
VSS
VDD
IFS
KS3
KS2
KS1
KS0
INT
RSTB
VSS
=
KS3
KS2
KS1
KS0
LED3
LED2
VLCD
VSS
VSS
LED1
LED0
K15
K14
K13
K12
K11
K10
K9
K8
SDA/DIO
MCU
LED3
VSS
COM
SEG
VDD
VDD
0.1uF
4.7KΩ
VLCD
0.1uF
LCD panel
IFS
VSS
RLED*4
LED2
VLCD
LED1
LED0
LED*4
RLED*4
LED*4
• The RSTB pin is connected to external resistor and capacitor.
I2C Interface:
SPI 3-wire Interface:
VLCD
VLCD
VLCD
COM
0.1uF
SEG
VDD
4.7KΩ
VDD
VDD
HT16LK24
CSB
SCL/CLK
K15
K14
K13
K12
K11
K10
K9
K8
INT
VDD
100KΩ
VSS
HT16LK24
VDD
CSB
SCL/CLK
INT
VDD
LED3
VSS
IFS
100KΩ
VSS
VLCD
LED*4
LED3
LED2
VSS
VSS
RLED*4
=
KS3
KS2
KS1
KS0
RSTB
0.1uF
VSS
LED1
LED0
K15
K14
K13
K12
K11
K10
K9
K8
SDA/DIO
MCU
KS3
KS2
KS1
KS0
LED2
VDD
VDD
RSTB
0.1uF
VSS
LCD panel
0.1uF
=
SDA/DIO
MCU
COM
SEG
VDD
VDD
0.1uF
4.7KΩ
VLCD
0.1uF
LCD panel
IFS
VLCD
LED1
LED0
RLED*4
LED*4
Note: If only the internal power on reset circuit is used, the RSTB pin must be connected to VDD.
Rev. 1.10
56
March 18, 2014
HT16LK24
(5) The SEG/KSL shared pin configuration is 4 LED outputs and 12 key inputs.
Shared pins
Configuration setting
command
KX[2:0] KY[4:0]
000b
Key circuit
Duty
0100b
COM
output
SEG
output
Output
(KS)
Input
(K)
1/1
none
K4~K15
LED0~3
COM0
1/2
none
K4~K15
LED0~3
1/3
none
K4~K15
1/4
none
1/8
none
L[3:0]
01100b
LED
output
LCD panel
COM
output
SEG
output
SEG0~50
COM0
SEG0~50
COM0~1
SEG0~50
COM0~1
SEG0~50
LED0~3
COM0~2
SEG0~50
COM0~2
SEG0~50
K4~K15
LED0~3
COM0~3
SEG0~50
COM0~3
SEG0~50
K4~K15
LED0~3
COM0~7
SEG4~50
COM0~7
SEG0~46
• The RSTB pin is connected to a MCU.
I2C Interface:
SPI 3-wire Interface:
VLCD
VLCD
VLCD
COM
0.1uF
SEG
VDD
4.7KΩ
VDD
VDD
HT16LK24
CSB
SCL/CLK
SDA/DIO
MCU
K15
K14
K13
K12
K11
K10
K9
K8
K7
K6
K5
K4
RSTB
VSS
VSS
IFS
VDD
VDD
HT16LK24
VDD
CSB
SCL/CLK
SDA/DIO
MCU
K15
K14
K13
K12
K11
K10
K9
K8
K7
K6
K5
K4
=
INT
=
VLCD
LED3
RSTB
VSS
LED2
VSS
LCD panel
0.1uF
INT
COM
SEG
VDD
VDD
0.1uF
4.7KΩ
VLCD
0.1uF
LCD panel
LED2
VSS
VSS
LED1
IFS
VSS
LED0
RLED*4
VLCD
LED3
LED1
LED0
LED*4
RLED*4
LED*4
• The RSTB pin is connected to external resistor and capacitor.
I2C Interface:
SPI 3-wire Interface:
VLCD
VLCD
VLCD
COM
0.1uF
VLCD
LCD panel
SEG
VDD
SEG
VDD
VDD
0.1uF
4.7KΩ
4.7KΩ
VDD
VDD
HT16LK24
CSB
SCL/CLK
SDA/DIO
MCU
K15
K14
K13
K12
K11
K10
K9
K8
K7
K6
K5
K4
VDD
0.1uF
HT16LK24
VDD
CSB
SCL/CLK
SDA/DIO
MCU
INT
VDD
100KΩ
VSS
VDD
RSTB
VLCD
LED3
LED2
VSS
VSS
VDD
IFS
K15
K14
K13
K12
K11
K10
K9
K8
K7
K6
K5
K4
INT
=
0.1uF
COM
0.1uF
LCD panel
100KΩ
VSS
LED2
VSS
RLED*4
VSS
VSS
LED*4
VLCD
LED3
0.1uF
LED1
LED0
=
RSTB
IFS
LED1
LED0
RLED*4
LED*4
Note: If only the internal power on reset circuit is used, the RSTB pin must be connected to VDD.
Rev. 1.10
57
March 18, 2014
HT16LK24
(6) The SEG/KSL shared pin configuration is 8 segment outputs and 8 LED outputs.
Shared pins
Configuration setting
command
KX[2:0] KY[4:0]
000b
00000b
Key circuit
Duty
COM
output
SEG
output
Output
(KS)
Input
(K)
1/1
none
none
LED0~7
COM0
1/2
none
none
LED0~7
1/3
none
none
1/4
none
1/8
none
L[3:0]
1000b
LED
output
LCD panel
COM
output
SEG
output
SEG0~58
COM0
SEG0~58
COM0~1
SEG0~58
COM0~1
SEG0~58
LED0~7
COM0~2
SEG0~58
COM0~2
SEG0~58
none
LED0~7
COM0~3
SEG0~58
COM0~3
SEG0~58
none
LED0~7
COM0~7
SEG4~58
COM0~7
SEG0~54
• The RSTB pin is connected to a MCU.
I2C Interface:
SPI 3-wire Interface:
VLCD
VLCD
VLCD
COM
0.1uF
SEG
VDD
VLCD
VDD
4.7KΩ
VDD
0.1uF
4.7KΩ
VDD
HT16LK24
HT16LK24
VDD
CSB
CSB
SCL/CLK
SDA/DIO
MCU
LED7
SCL/CLK
LED7
LED6
SDA/DIO
LED6
MCU
LED5
INT
RSTB
LED5
INT
LED4
VSS
LCD panel
SEG
VDD
0.1uF
VDD
COM
0.1uF
LCD panel
LED4
VLCD
LED3
RSTB
VSS
LED2
VSS
LED0
IFS
VDD
LED2
VSS
LED1
VSS
VLCD
LED3
RLED*8
LED1
VSS
LED*8
LED0
IFS
VSS
RLED*8
LED*8
• The RSTB pin is connected to external resistor and capacitor.
I2C Interface:
SPI 3-wire Interface:
VLCD
VLCD
VLCD
COM
0.1uF
SEG
VDD
VLCD
VDD
4.7KΩ
VDD
0.1uF
4.7KΩ
VDD
HT16LK24
HT16LK24
VDD
CSB
CSB
SCL/CLK
LED7
SDA/DIO
MCU
INT
VDD
100KΩ
VSS
LED6
MCU
LED5
RSTB
VDD
VLCD
LED3
VSS
VDD
IFS
LED6
100KΩ
LED5
LED4
RSTB
VLCD
LED3
LED2
VSS
LED1
LED0
LED7
SDA/DIO
0.1uF
LED2
VSS
SCL/CLK
INT
LED4
0.1uF
VSS
LCD panel
SEG
VDD
0.1uF
VDD
COM
0.1uF
LCD panel
RLED*8
VSS
VSS
LED*8
IFS
LED1
LED0
RLED*8
LED*8
Note: If only the internal power on reset circuit is used, the RSTB pin must be connected to VDD.
Rev. 1.10
58
March 18, 2014
HT16LK24
(7) The SEG/KSL shared pin configuration is 8 LED outputs, 4 key scan outputs and 4 key inputs.
Shared pins
Configuration setting
command
KX[2:0] KY[4:0]
100b
Key circuit
Duty
1000b
COM
output
SEG
output
Output
(KS)
Input
(K)
1/1
KS0~3
K12~15
LED0~7
COM0
1/2
KS0~3
K12~15
LED0~7
1/3
KS0~3
K12~15
1/4
KS0~3
1/8
KS0~3
L[3:0]
00100b
LED
output
LCD panel
COM
output
SEG
output
SEG0~50
COM0
SEG0~50
COM0~1
SEG0~50
COM0~1
SEG0~50
LED0~7
COM0~2
SEG0~50
COM0~2
SEG0~50
K12~15
LED0~7
COM0~3
SEG0~50
COM0~3
SEG0~50
K12~15
LED0~7
COM0~7
SEG4~50
COM0~7
SEG0~46
• The RSTB pin is connected to a MCU.
I2C Interface:
SPI 3-wire Interface:
COM
VLCD
VLCD
0.1uF
VDD
VDD
0.1uF
4.7KΩ
4.7KΩ
VDD
VDD
SCL/CLK
SDA/DIO
MCU
VLCD
SEG
0.1uF
VDD
K15
K14
K13
K12
HT16LK24
CSB
COM
VLCD
LCD panel
HT16LK24
VDD
KS3
KS2
KS1
KS0
CSB
SCL/CLK
LED7
SDA/DIO
MCU
LED6
INT
K15
K14
K13
K12
VDD
0.1uF
=
RSTB
VSS
VLCD
RSTB
VSS
LED4
VLCD
LED3
VSS
VSS
LED2
IFS
VDD
LED7
LED5
LED4
LED3
VSS
=
KS3
KS2
KS1
KS0
LED6
INT
LED5
VSS
LCD panel
SEG
LED2
IFS
VSS
LED1
LED1
LED0
LED0
RLED*8
RLED*8
LED*8
LED*8
• The RSTB pin is connected to external resistor and capacitor.
I2C Interface:
SPI 3-wire Interface:
COM
VLCD
VLCD
0.1uF
VDD
VDD
0.1uF
4.7KΩ
4.7KΩ
VDD
VDD
SCL/CLK
SDA/DIO
MCU
INT
VDD
VSS
100KΩ
RSTB
VSS
VSS
VDD
0.1uF
VDD
K15
K14
K13
K12
=
IFS
HT16LK24
VDD
KS3
KS2
KS1
KS0
CSB
SCL/CLK
LED7
SDA/DIO
MCU
INT
LED6
VDD
LED5
VLCD
LED3
LED2
VSS
LED0
100KΩ
RSTB
=
KS3
KS2
KS1
KS0
LED7
LED6
LED5
LED4
0.1uF
VLCD
LED3
VSS
VSS
VSS
LED1
LCD panel
SEG
K15
K14
K13
K12
VDD
0.1uF
LED4
0.1uF
VLCD
SEG
HT16LK24
CSB
COM
VLCD
LCD panel
IFS
LED2
LED1
LED0
RLED*8
RLED*8
LED*8
LED*8
Note: If only the internal power on reset circuit is used, the RSTB pin must be connected to VDD.
Rev. 1.10
59
March 18, 2014
HT16LK24
(8) The SEG/KSL shared pin configuration is 8 LED outputs and 8 key inputs.
Shared pins
Configuration setting
command
Key circuit
Duty
01000b
1000b
COM
output
SEG
output
Output
(KS)
Input
(K)
1/1
none
K8~15
LED0~7
COM0
1/2
none
K8~15
LED0~7
1/3
none
K8~15
1/4
none
1/8
none
KX[2:0] KY[4:0] L[3:0]
000b
LED
output
LCD panel
COM
output
SEG
output
SEG0~50
COM0
SEG0~50
COM0~1
SEG0~50
COM0~1
SEG0~50
LED0~7
COM0~2
SEG0~50
COM0~2
SEG0~50
K8~15
LED0~7
COM0~3
SEG0~50
COM0~3
SEG0~50
K8~15
LED0~7
COM0~7
SEG4~50
COM0~7
SEG0~46
• The RSTB pin is connected to a MCU.
I2C Interface:
SPI 3-wire Interface:
COM
VLCD
VLCD
0.1uF
VDD
VDD
0.1uF
4.7KΩ
4.7KΩ
VDD
VDD
HT16LK24
CSB
SDA/DIO
INT
RSTB
VSS
0.1uF
VDD
K15
K14
K13
K12
K11
K10
K9
K8
VSS
IFS
VDD
VDD
0.1uF
K15
K14
K13
K12
K11
K10
K9
K8
LED7
SDA/DIO
MCU
LED6
INT
LED5
LED4
RSTB
VSS
VLCD
LED7
LED6
LED5
LED4
LED3
VSS
LED2
=
SCL/CLK
VLCD
VSS
LED1
IFS
VSS
RLED*8
LCD panel
SEG
CSB
=
LED0
HT16LK24
VDD
LED3
VSS
VLCD
SEG
SCL/CLK
MCU
COM
VLCD
LCD panel
LED*8
LED2
LED1
LED0
RLED*8
LED*8
• The RSTB pin is connected to external resistor and capacitor.
I2C Interface:
SPI 3-wire Interface:
COM
VLCD
VLCD
0.1uF
VDD
VDD
0.1uF
4.7KΩ
4.7KΩ
VDD
VDD
HT16LK24
CSB
VDD
100KΩ
INT
LED6
0.1uF
VSS
IFS
VDD
0.1uF
K15
K14
K13
K12
K11
K10
K9
K8
CSB
MCU
VDD
LED4
100KΩ
LED7
INT
LED6
RSTB
0.1uF
VSS
LED2
LED1
VLCD
LED5
LED4
LED3
VSS
VSS
LED*8
=
SDA/DIO
VSS
RLED*8
LCD panel
SEG
SCL/CLK
VLCD
LED5
LED0
HT16LK24
VDD
LED3
VSS
VDD
VDD
=
LED7
RSTB
0.1uF
K15
K14
K13
K12
K11
K10
K9
K8
SDA/DIO
VSS
VLCD
SEG
SCL/CLK
MCU
COM
VLCD
LCD panel
IFS
LED2
LED1
LED0
RLED*8
LED*8
Note: If only the internal power on reset circuit is used, the RSTB pin must be connected to VDD.
Rev. 1.10
60
March 18, 2014
HT16LK24
(9) The SEG/KSL shared pin configuration is 4 key scan outputs and 12 key inputs.
Shared pins
Configuration setting
command
KX[2:0] KY[4:0]
100b
Key circuit
Duty
0000b
COM
output
SEG
output
Output
(KS)
Input
(K)
1/1
KS0~3
K4~15
none
COM0
1/2
KS0~3
K4~15
none
1/3
KS0~3
K4~15
1/4
KS0~3
1/8
KS0~3
L[3:0]
01100b
LED
output
LCD panel
COM
output
SEG
output
SEG0~50
COM0
SEG0~50
COM0~1
SEG0~50
COM0~1
SEG0~50
none
COM0~2
SEG0~50
COM0~2
SEG0~50
K4~15
none
COM0~3
SEG0~50
COM0~3
SEG0~50
K4~15
none
COM0~7
SEG4~50
COM0~7
SEG0~46
• The RSTB pin is connected to a MCU.
VLCD
I2C Interface:
SPI 3-wire Interface:
VLCD
VLCD
COM
0.1uF
SEG
VDD
4.7KΩ
4.7KΩ
VDD
HT16LK24
CSB
SCL/CLK
MCU
SDA/DIO
INT
K15
K14
K13
K12
K11
K10
K9
K8
K7
K6
K5
K4
RSTB
VSS
VSS
VSS
IFS
VDD
COM
LCD panel
SEG
VDD
VDD
0.1uF
VDD
VLCD
0.1uF
LCD panel
VDD
0.1uF
HT16LK24
VDD
CSB
SCL/CLK
MCU
SDA/DIO
INT
RSTB
VSS
=
VSS
VSS
KS3
KS2
KS1
KS0
K15
K14
K13
K12
K11
K10
K9
K8
K7
K6
K5
K4
IFS
VSS
=
KS3
KS2
KS1
KS0
• The RSTB pin is connected to external resistor and capacitor.
VLCD
I2C Interface:
SPI 3-wire Interface:
VLCD
VLCD
COM
0.1uF
SEG
VDD
4.7KΩ
4.7KΩ
VDD
HT16LK24
CSB
SCL/CLK
MCU
SDA/DIO
VDD
VSS
100KΩ
INT
K15
K14
K13
K12
K11
K10
K9
K8
K7
K6
K5
K4
VDD
VDD
IFS
HT16LK24
VDD
CSB
SCL/CLK
MCU
SDA/DIO
INT
VDD
100KΩ
K15
K14
K13
K12
K11
K10
K9
K8
K7
K6
K5
K4
RSTB
VSS
=
VSS
LCD panel
0.1uF
RSTB
0.1uF
VSS
COM
SEG
VDD
VDD
0.1uF
VDD
VLCD
0.1uF
LCD panel
=
0.1uF
VSS
KS3
KS2
KS1
KS0
VSS
VSS
IFS
KS3
KS2
KS1
KS0
Note: If only the internal power on reset circuit is used, the RSTB pin must be connected to VDD.
Rev. 1.10
61
March 18, 2014
HT16LK24
(10) The SEG/KSL shared pin configuration is 16 key inputs.
Shared pins
Configuration setting
command
KX[2:0] KY[4:0]
000b
10000b
Key circuit
Duty
COM
output
SEG
output
Output
(KS)
Input
(K)
1/1
none
K0~15
none
COM0
1/2
none
K0~15
none
1/3
none
K0~15
1/4
none
1/8
none
L[3:0]
0000b
LED
output
LCD panel
COM
output
SEG
output
SEG0~50
COM0
SEG0~50
COM0~1
SEG0~50
COM0~1
SEG0~50
none
COM0~2
SEG0~50
COM0~2
SEG0~50
K0~15
none
COM0~3
SEG0~50
COM0~3
SEG0~50
K0~15
none
COM0~7
SEG4~50
COM0~7
SEG0~46
• The RSTB pin is connected to a MCU.
I2C Interface:
SPI 3-wire Interface:
VLCD
VLCD
VLCD
COM
0.1uF
SEG
VDD
VDD
VDD
CSB
SCL/CLK
SDA/DIO
MCU
INT
RSTB
VSS
VSS
VSS
0.1uF
VLCD
HT16LK24
VDD
K0
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
K13
K14
K15
CSB
SCL/CLK
SDA/DIO
MCU
INT
RSTB
VSS
VSS
VSS
=
IFS
VDD
LCD panel
VDD
VLCD
HT16LK24
4.7KΩ
COM
SEG
VDD
VDD
0.1uF
4.7KΩ
VLCD
0.1uF
LCD panel
K0
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
K13
K14
K15
=
IFS
VSS
• The RSTB pin is connected to external resistor and capacitor.
2
VLCD
VLCD
VLCD
COM
0.1uF
SEG
VDD
COM
LCD panel
SEG
VDD
VDD
VDD
VLCD
0.1uF
4.7KΩ
VLCD
0.1uF
LCD panel
0.1uF
VLCD
4.7KΩ
VDD
VDD
CSB
SCL/CLK
SDA/DIO
VDD
INT
100KΩ
VSS
RSTB
0.1uF
VSS
VSS
VDD
IFS
VDD
K0
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
K13
K14
K15
CSB
SCL/CLK
SDA/DIO
INT
VDD
100KΩ
VSS
0.1uF
VSS
=
RSTB
VSS
VSS
K0
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
K13
K14
K15
=
IFS
Note: If only the internal power on reset circuit is used, the RSTB pin must be connected to VDD.
Rev. 1.10
62
March 18, 2014
HT16LK24
Package Information
Note that the package information provided here is for consultation purposes only. As this information may be
updated at regular intervals users are reminded to consult the Holtek website for the latest version of the package
information.
Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be
transferred to the relevant website page.
• Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications)
• Packing Meterials Information
• Carton information
Rev. 1.10
63
March 18, 2014
HT16LK24
64-pin LQFP (7mm × 7mm) Outline Dimensions
Symbol
Nom.
Max.
A
—
0.354 BSC
—
B
—
0.276 BSC
—
C
—
0.354 BSC
—
D
—
0.276 BSC
—
E
—
0.016 BSC
—
F
0.005
0.007
0.009
G
0.053
0.055
0.057
H
—
—
0.063
I
0.002
—
0.006
J
0.018
0.024
0.030
K
0.004
—
0.008
α
0°
—
7°
Symbol
Rev. 1.10
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
—
9.00 BSC
—
B
—
7.00 BSC
—
C
—
9.00 BSC
—
D
—
7.00 BSC
—
E
—
0.40 BSC
—
F
0.13
0.18
0.23
G
1.35
1.40
1.45
H
—
—
1.60
I
0.05
—
0.15
J
0.45
0.60
0.75
K
0.09
—
0.20
α
0°
—
7°
64
March 18, 2014
HT16LK24
80-pin LQFP (10mm × 10mm) Outline Dimensions
Symbol
Nom.
Max.
A
―
0.472 BSC
―
B
―
0.394 BSC
―
C
―
0.472 BSC
―
D
―
0.394 BSC
―
E
―
0.016 BSC
―
F
0.007
0.009
0.011
G
0.053
0.055
0.057
H
―
―
0.063
I
0.002
―
0.006
J
0.018
0.024
0.030
K
0.004
―
0.008
α
0°
―
7°
Symbol
Rev. 1.10
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
—
12.00 BSC
—
B
—
10.00 BSC
—
C
—
12.00 BSC
—
D
—
10.00 BSC
—
E
―
0.40 BSC
―
F
0.13
0.18
0.23
G
1.35
1.4
1.45
H
―
―
1.60
I
0.05
—
0.15
J
0.45
0.60
0.75
K
0.09
―
0.20
α
0°
―
7°
65
March 18, 2014
HT16LK24
Copyright© 2014 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time
of publication. However, Holtek assumes no responsibility arising from the use of
the specifications described. The applications mentioned herein are used solely
for the purpose of illustration and Holtek makes no warranty or representation that
such applications will be suitable without further modification, nor recommends
the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical
components in life support devices or systems. Holtek reserves the right to alter
its products without prior notification. For the most up-to-date information, please
visit our web site at http://www.holtek.com.
Rev. 1.10
66
March 18, 2014