8161Z183236B

GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
• User-configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
• Fully pin-compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 2.5 V or 3.3 V +10%/–10% core power supply
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ pin for automatic power-down
• JEDEC-standard 100-lead TQFP and 165-bump FP-BGA
packages
• RoHS-compliant 100-lead TQFP and 165-bump BGA
packages available
The GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
may be configured by the user to operate in Pipeline or Flow
Through mode. Operating as a pipelined synchronous device,
in addition to the rising-edge-triggered registers that capture
input signals, the device incorporates a rising-edge-triggered
output register. For read cycles, pipelined SRAM output data is
temporarily stored by the edge triggered output register during
the access cycle and then released to the output drivers at the
next rising edge of clock.
De
sig
Functional Description
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
ct
Features
250 MHz–150 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
n—
Di
sco
nt
inu
ed
Pr
od
u
100-Pin TQFP & 165-Bump BGA
Commercial Temp
Industrial Temp
me
nd
ed
for
Ne
w
The GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
is an 18Mbit Synchronous Static SRAM. GSI's NBT SRAMs,
like ZBT, NtRAM, NoBL or other pipelined read/double late
write or flow through read/single late write SRAMs, allow
utilization of all available bus bandwidth by eliminating the
need to insert deselect cycles when the device is switched from
read to write cycles.
The GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
is implemented with GSI's high performance CMOS
technology and is available in JEDEC-standard 100-pin TQFP
and 165-bump FP-BGA packages.
Re
co
m
Parameter Synopsis
No
t
Pipeline
3-1-1-1
Rev: 1.05a 10/2009
Flow Through
2-1-1-1
-250
-200
-150
Unit
tKQ
tCycle
2.5
4.0
3.0
5.0
3.8
6.7
ns
ns
Curr (x18)
Curr (x32/x36)
295
345
245
285
200
225
mA
mA
tKQ
tCycle
5.5
5.5
6.5
6.5
7.5
7.5
ns
ns
Curr (x18)
Curr (x32/x36)
225
255
200
220
185
205
mA
mA
1/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
A
A
E1
E2
NC
NC
BB
BA
E3
VDD
VSS
CK
W
CKE
G
ADV
A
A
A
A
GS8161Z18BT Pinout (Package T)
NC
NC
NC
Rev: 1.05a 10/2009
Ne
w
me
nd
ed
for
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA5
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
A
A
A
A1
A0
TMS
TDI
VSS
VDD
TDO
TCK
A
A
A
A
A
A
A
Re
co
LBO
m
A
No
t
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
FT
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
De
sig
VDDQ
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
1M x 18
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
2/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
A
A
E1
E2
BD
BC
BB
BA
E3
VDD
VSS
CK
W
CKE
G
ADV
A
A
A
A
GS8161Z36BT Pinout (Package T)
Rev: 1.05a 10/2009
Ne
w
me
nd
ed
for
DQPB
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
DQPA
A
A
A
A1
A0
TMS
TDI
VSS
VDD
TDO
TCK
A
A
A
A
A
A
A
Re
co
LBO
m
A
No
t
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
FT
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
512K x 36
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
De
sig
DQPC
DQC
DQC
VDDQ
3/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Type
Description
A 0, A 1
In
Burst Address Inputs; Preload the burst counter
A
In
Address Inputs
CK
In
BA
In
Byte Write signal for data inputs DQA1–DQA9; active low
BB
In
Byte Write signal for data inputs DQB1–DQB9; active low
BC
In
Byte Write signal for data inputs DQC1–DQC9; active low
BD
In
Byte Write signal for data inputs DQD1–DQD9; active low
W
In
Write Enable; active low
E1
In
E2
In
Chip Enable—Active High. For self decoded depth expansion
E3
In
Chip Enable—Active Low. For self decoded depth expansion
G
In
Output Enable; active low
ADV
In
CKE
In
NC
—
DQA, DQPA
I/O
DQB, DQPB
I/O
DQC, DQPC
I/O
DQD, DQPD
I/O
ZZ
In
FT
In
LBO
In
MCH
—
TMS
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
Symbol
Re
co
m
100-Pin TQFP Pin Descriptions
Clock Input Signal
Chip Enable; active low
De
sig
Advance/Load; Burst address counter control pin
No Connect
Byte A Data Input and Output pins
Byte B Data Input and Output pins
Byte C Data Input and Output pins
Byte D Data Input and Output pins
Power down control; active high
Pipeline/Flow Through Mode Control; active low
Linear Burst Order; active low.
Must Connect High (165 BGA only)
Scan Test Mode Select
No
t
me
nd
ed
for
Ne
w
Clock Input Buffer Enable; active low
Rev: 1.05a 10/2009
4/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
100-Pin TQFP Pin Descriptions
Type
Description
Scan Test Data In
TDO
Scan Test Data Out
TCK
Scan Test Clock
I
TDI
I
TDO
O
TCK
I
VDD
In
VSS
In
VDDQ
In
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Core power supply
Ground
Output driver power supply
No
t
Re
co
m
me
nd
ed
for
Ne
w
De
sig
TMS
n—
Di
sco
nt
inu
ed
Pr
od
u
TDI
ct
Symbol
Rev: 1.05a 10/2009
5/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
2
3
4
5
6
7
8
9
10
11
A
NC
A
E1
BB
NC
E3
CKE
ADV
A
A
A
A
B
NC
A
E2
NC
BA
CK
W
G
A
A
NC
B
C
NC
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
DQPA
C
D
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
D
E
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
E
F
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
F
G
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
G
H
FT
MCH
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ
H
J
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
J
K
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
K
L
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
L
M
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
M
N
DQPB
NC
P
NC
NC
R
LBO
NC
me
nd
ed
for
Ne
w
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
1
De
sig
165 Bump BGA—x18 Commom I/O—Top View (Package D)
VSS
NC
NC
NC
VSS
VDDQ
NC
NC
N
A
A
TDI
A1
TDO
A
A
A
NC
P
A
A
TMS
A0
TCK
A
A
A
A
R
Re
co
m
VDDQ
No
t
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.05a 10/2009
6/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
165 Bump BGA—x32 Common I/O—Top View (Package D)
2
3
4
5
6
7
8
9
10
11
A
NC
A
E1
BC
BB
E3
CKE
ADV
A
A
NC
B
NC
A
E2
BD
BA
CK
W
G
A
A
C
NC
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
D
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
E
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
F
DQC
DQC
VDDQ
VDD
VSS
VSS
G
DQC
DQC
VDDQ
VDD
VSS
H
FT
MCH
NC
VDD
J
DQD
DQD
VDDQ
K
DQD
DQD
L
DQD
M
A
B
NC
NC
C
VDDQ
DQB
DQB
D
VDD
VDDQ
DQB
DQB
E
VSS
VDD
VDDQ
DQB
DQB
F
VSS
VSS
VDD
VDDQ
DQB
DQB
G
VSS
VSS
VSS
VDD
NC
NC
ZZ
H
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
J
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
K
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
L
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
M
N
NC
NC
P
NC
NC
R
LBO
NC
me
nd
ed
for
Ne
w
n—
Di
sco
nt
inu
ed
Pr
od
u
NC
De
sig
ct
1
VSS
NC
NC
NC
VSS
VDDQ
NC
NC
N
A
A
TDI
A1
TDO
A
A
A
NC
P
A
A
TMS
A0
TCK
A
A
A
A
R
Re
co
m
VDDQ
No
t
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.05a 10/2009
7/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
165 Bump BGA—x36 Common I/O—Top View (Package D)
2
3
4
5
6
7
8
9
10
11
A
NC
A
E1
BC
BB
E3
CKE
ADV
A
A
NC
B
NC
A
E2
BD
BA
CK
W
G
A
A
C
DQPC
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
D
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
E
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
F
DQC
DQC
VDDQ
VDD
VSS
VSS
G
DQC
DQC
VDDQ
VDD
VSS
H
FT
MCH
NC
VDD
J
DQD
DQD
VDDQ
K
DQD
DQD
L
DQD
M
A
B
NC
DQPB
C
VDDQ
DQB
DQB
D
VDD
VDDQ
DQB
DQB
E
VSS
VDD
VDDQ
DQB
DQB
F
VSS
VSS
VDD
VDDQ
DQB
DQB
G
VSS
VSS
VSS
VDD
NC
NC
ZZ
H
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
J
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
K
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
L
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
M
N
DQPD
NC
P
NC
NC
R
LBO
NC
me
nd
ed
for
Ne
w
n—
Di
sco
nt
inu
ed
Pr
od
u
NC
De
sig
ct
1
VSS
NC
NC
NC
VSS
VDDQ
NC
DQPA
N
A
A
TDI
A1
TDO
A
A
A
NC
P
A
A
TMS
A0
TCK
A
A
A
A
R
Re
co
m
VDDQ
No
t
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.05a 10/2009
8/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
GS8161Z18/32/36BD 165-Bump BGA Pin Description
Type
Description
A 0, A 1
I
Address field LSBs and Address Counter Preset Inputs
A
I
Address Inputs
DQA
DQB
DQC
DQD
I/O
BA , BB , BC , BD
I
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
NC
—
No Connect
CK
I
CKE
I
Clock Input Buffer Enable; active low
W
I
Write Enable; active low
E1
I
E3
I
E2
I
G
I
ADV
I
ZZ
I
FT
I
LBO
I
TMS
I
TDI
I
TDO
O
TCK
I
MCH
—
VDD
I
VSS
I
VDDQ
I
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
Symbol
Data Input and Output pins
Clock Input Signal; active high
Chip Enable; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
De
sig
Burst address counter advance enable; active high
Sleep mode control; active high
Flow Through or Pipeline mode; active low
me
nd
ed
for
Ne
w
Linear Burst Order mode; active low
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Must Connect High
Core power supply
I/O and Core Ground
No
t
Re
co
m
Output driver power supply
Rev: 1.05a 10/2009
9/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
Rev: 1.05a 10/2009
W
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
10/38
G
CKE
CK
E3
E2
E1
BD
BC
BB
BA
ADV
No
LBO
t
A0–An
K
K
Q
K
SA1
SA0
Control Logic
Data Coherency
Read, Write and
Match
Register 1
Write Address
K
18
SA1’
SA0’
Write Drivers
Sense Amps
K
K
D
Q
K
FT
Write Data
Register 1
Write Data
Register 2
n—
Di
sco
nt
inu
ed
Pr
od
u
Memory
Array
De
sig
FT
Ne
w
Register 2
Write Address
Burst
Counter
me
nd
ed
for
Re
co
m
K
D
ct
DQa–DQn
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
GS8161Z18/32/36B NBT SRAM Functional Block Diagram
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Functional Details
ct
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
W
BA
BB
BC
BD
Read
H
X
X
X
X
Write Byte “a”
L
L
H
H
H
Write Byte “b”
L
H
L
H
H
Write Byte “c”
L
H
H
L
H
Write Byte “d”
L
H
H
H
L
Write all Bytes
L
L
L
L
L
Write Abort/NOP
L
H
H
H
De
sig
Function
n—
Di
sco
nt
inu
ed
Pr
od
u
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2 and E3). Deassertion of any one of the Enable
inputs will deactivate the device.
H
me
nd
ed
for
Ne
w
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Re
co
m
Write operation occurs when the RAM is selected, CKE is asserted low, and the write input is sampled low at the rising edge of
clock. The Byte Write Enable inputs (BA, BB, BC & BD) determine which bytes will be written. All or none may be activated. A
write cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.
No
t
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use
of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new
address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Rev: 1.05a 10/2009
11/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Synchronous Truth Table
Type Address CK CKE ADV W Bx E1 E2 E3 G ZZ
External
L-H
L
Read Cycle, Continue Burst
B
Next
L-H
L
NOP/Read, Begin Burst
R
External
L-H
L
Dummy Read, Continue Burst
B
Next
L-H
L
Write Cycle, Begin Burst
W
External
L-H
L
Write Abort, Begin Burst
D
None
L-H
L
Write Cycle, Continue Burst
B
Next
L-H
L
Write Abort, Continue Burst
B
Next
L-H
L
Deselect Cycle, Power Down
D
None
L-H
L
Deselect Cycle, Power Down
D
None
L-H
L
Deselect Cycle, Power Down
D
None
L-H
L
Deselect Cycle, Continue
D
None
L-H
None
X
Current
L-H
Clock Edge Ignore, Stall
H
X
L
H
L
L
L
Q
Notes
H
X
X
X
X
X
L
L
Q
1,10
L
H
X
L
H
L
H
L
High-Z
2
H
X
X
X
X
X
H
L
High-Z
1,2,10
L
L
L
L
H
L
X
L
D
3
L
L
H
L
H
L
X
L
High-Z
1
H
X
L
X
X
X
X
L
D
1,3,10
H
X
H
X
X
X
X
L
High-Z 1,2,3,10
L
X
X
H
X
X
X
L
High-Z
L
X
X
X
X
H
X
L
High-Z
L
X
X
X
L
X
X
L
High-Z
Ne
w
Sleep Mode
L
ct
R
DQ
De
sig
Read Cycle, Begin Burst
n—
Di
sco
nt
inu
ed
Pr
od
u
Operation
L
H
X
X
X
X
X
X
L
High-Z
X
X
X
X
X
X
X
X
H
High-Z
H
X
X
X
X
X
X
X
L
-
1
4
No
t
Re
co
m
me
nd
ed
for
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect cycle is executed first.
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W
pin is sampled low but no Byte Write pins are active so no write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during
write cycles.
4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write
signals are Low
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
Rev: 1.05a 10/2009
12/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Pipelined and Flow Through Read Write Control State Diagram
D
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
B
Deselect
R
D
R
D
W
New Read
W
B
R
W
R
ƒ Transition
Current State (n)
No
t
Command
Re
co
m
Clock (CK)
Ne
w
2. W, R, B, and D represent input command
codes as indicated in the Synchronous Truth Table.
n+1
ƒ
Current State
D
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
Next State (n+1)
n
B
Notes:
me
nd
ed
for
Input Command Code
W
Burst Write
De
sig
Burst Read
D
Key
New Write
R
B
B
W
n+2
ƒ
n+3
ƒ
ƒ
Next State
Current State and Next State Definition for Pipelined and Flow Through Read/Write Control State Diagram
Rev: 1.05a 10/2009
13/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Pipeline Mode Data I/O State Diagram
R
High Z
(Data In)
D
R B
Intermediate
Data Out
(Q Valid)
W
D
Intermediate
Intermediate
W
Intermediate
ct
B W
n—
Di
sco
nt
inu
ed
Pr
od
u
Intermediate
R
High Z
B
D
Key
Ne
w
Input Command Code
ƒ Transition
Transition
Intermediate State (N+1)
me
nd
ed
for
Current State (n)
n
Next State (n+2)
n+1
Notes:
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
n+2
n+3
Command
ƒ
ƒ
ƒ
No
t
Re
co
m
Clock (CK)
De
sig
Intermediate
Current State
Intermediate
State
Next State
ƒ
Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
Rev: 1.05a 10/2009
14/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Flow Through Mode Data I/O State Diagram
R B
R
High Z
(Data In)
Data Out
(Q Valid)
n—
Di
sco
nt
inu
ed
Pr
od
u
W
ct
B W
D
D
W
R
High Z
B
Key
Ne
w
Input Command Code
ƒ Transition
Current State (n)
me
nd
ed
for
Re
co
m
Command
n+1
ƒ
Current State
Notes:
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Next State (n+1)
n
Clock (CK)
De
sig
D
n+2
ƒ
n+3
ƒ
ƒ
Next State
No
t
Current State and Next State Definition for: Pipeline and Flow through Read Write Control State Diagram
Rev: 1.05a 10/2009
15/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
Pin Name
Burst Order Control
LBO
Output Register Control
FT
Power Down Control
ZZ
Single/Dual Cycle Deselect Control
SCD
FLXDrive Output Impedance Control
me
nd
ed
for
9th Bit Enable
De
sig
Mode Name
Ne
w
Mode Pin Functions
ZQ
PE
State
Function
L
Linear Burst
H
Interleaved Burst
L
Flow Through
H or NC
Pipeline
L or NC
Active
H
Standby, IDD = ISB
L
Dual Cycle Deselect
H or NC
Single Cycle Deselect
L
High Drive (Low Impedance)
H or NC
Low Drive (High Impedance)
L or NC
Activate DQPx I/Os (x18/x3672 mode)
H
Deactivate DQPx I/Os (x16/x3272 mode)
No
t
Re
co
m
Note:
There is a are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so thosethis input pins can be
unconnected and the chip will operate in the default states as specified in the above tables.
Rev: 1.05a 10/2009
16/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
1st address
00
01
10
11
2nd address
01
10
11
00
2nd address
01
00
11
10
3rd address
10
11
00
01
3rd address
10
11
00
01
4th address
11
00
01
10
4th address
11
10
01
00
n—
Di
sco
nt
inu
ed
Pr
od
u
1st address
ct
A[1:0] A[1:0] A[1:0] A[1:0]
Note:
The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
No
t
Re
co
m
me
nd
ed
for
Ne
w
De
sig
Note:
The burst counter wraps to initial state on the 5th clock.
Rev: 1.05a 10/2009
17/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
ct


Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
n—
Di
sco
nt
inu
ed
Pr
od
u
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
tKH
tKC
tKL
CK
tZZR
tZZS
tZZH
De
sig
ZZ
No
t
Re
co
m
me
nd
ed
for
Ne
w
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipelinemode via the FT signal found
on Pin 14. Not all vendors offer this option, however most mark Pin 14 as VDD or VDDQ on pipelined parts and VSS on flow
through parts. GSI NBT SRAMs are fully compatible with these sockets.
Rev: 1.05a 10/2009
18/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Absolute Maximum Ratings
(All voltages reference to VSS)
Description
Value
Unit
VDD
Voltage on VDD Pins
–0.5 to 4.6
V
VDDQ
Voltage in VDDQ Pins
–0.5 to 4.6
VI/O
Voltage on I/O Pins
VIN
Voltage on Other Input Pins
IIN
Input Current on Any Pin
IOUT
Output Current on Any I/O Pin
PD
Package Power Dissipation
TSTG
Storage Temperature
TBIAS
Temperature Under Bias
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
Symbol
V
–0.5 to VDDQ +0.5
V
–0.5 to VDD +0.5
V
+/–20
mA
+/–20
mA
1.5
W
–55 to 125
o
–55 to 125
o
C
C
De
sig
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Parameter
Symbol
Min.
Typ.
Max.
Unit
3.3 V Supply Voltage
Ne
w
Power Supply Voltage Ranges
VDD3
3.0
3.3
3.6
V
VDD2
2.3
2.5
2.7
V
me
nd
ed
for
2.5 V Supply Voltage
3.3 V VDDQ I/O Supply Voltage
VDDQ3
3.0
3.3
3.6
V
2.5 V VDDQ I/O Supply Voltage
VDDQ2
2.3
2.5
2.7
V
Notes
No
t
Re
co
m
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+1.5 V maximum, with a pulse width not to exceed 50% tKC.
Rev: 1.05a 10/2009
19/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Symbol
Min.
Typ.
Max.
Unit
Notes
VDD Input High Voltage
VIH
2.0
—
VDD + 0.3
V
1
VDD Input Low Voltage
VIL
–0.3
—
0.8
V
1
VDDQ I/O Input High Voltage
VIHQ
2.0
—
VDDQ + 0.3
V
1,3
VDDQ I/O Input Low Voltage
VILQ
–0.3
—
0.8
V
1,3
n—
Di
sco
nt
inu
ed
Pr
od
u
Parameter
ct
VDDQ3 Range Logic Levels
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+1.5 V maximum, with a pulse width not to exceed 50% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Parameter
Symbol
Typ.
Max.
Unit
Notes
VDD Input High Voltage
VIH
0.6*VDD
—
VDD + 0.3
V
1
VDD Input Low Voltage
VIL
–0.3
—
0.3*VDD
V
1
VDDQ I/O Input High Voltage
VIHQ
0.6*VDD
—
VDDQ + 0.3
V
1,3
VDDQ I/O Input Low Voltage
–0.3
—
0.3*VDD
V
1,3
De
sig
Min.
Ne
w
VDDQ2 Range Logic Levels
VILQ
me
nd
ed
for
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+1.5 V maximum, with a pulse width not to exceed 50% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Recommended Operating Temperatures
Symbol
Min.
Typ.
Max.
Unit
Notes
Ambient Temperature (Commercial Range Versions)
TA
0
25
70
C
2
Ambient Temperature (Industrial Range Versions)
TA
–40
25
85
C
2
Re
co
m
Parameter
No
t
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+1.5 V maximum, with a pulse width not to exceed 50% tKC.
Rev: 1.05a 10/2009
20/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
50% tKC
VDD +1.5 V
VSS
n—
Di
sco
nt
inu
ed
Pr
od
u
50%
ct
50%
VDD
VSS – 2.0 V
50% tKC
VIL
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 2.5 V)
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
Input Capacitance
CIN
VIN = 0 V
4
5
pF
Input/Output Capacitance
CI/O
VOUT = 0 V
6
7
pF
AC Test Conditions
Conditions
Input high level
VDD – 0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
VDD/2
Output load
me
nd
ed
for
Output reference level
Ne
w
Parameter
De
sig
Note:
These parameters are sample tested.
VDDQ/2
Fig. 1
Output Load 1
DQ
No
t
Re
co
m
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
50
30pF*
VDDQ/2
* Distributed Test Jig Capacitance
Rev: 1.05a 10/2009
21/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
DC Electrical Characteristics
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
IIL
VIN = 0 to VDD
–1 uA
1 uA
ZZ Input Current
IIN1
VDD  VIN  VIH
0 V VIN VIH
FT Input Current
IIN2
Output Leakage Current
ct
Parameter
1 uA
100 uA
VDD  VIN  VIL
0 V VIN VIL
–100 uA
–1 uA
1 uA
1 uA
IOL
Output Disable, VOUT = 0 to VDD
–1 uA
1 uA
Output High Voltage
VOH2
IOH = –8 mA, VDDQ = 2.375 V
1.7 V
—
Output High Voltage
VOH3
IOH = –8 mA, VDDQ = 3.135 V
2.4 V
—
Output Low Voltage
VOL
IOL = 8 mA
—
0.4 V
No
t
Re
co
m
me
nd
ed
for
Ne
w
De
sig
n—
Di
sco
nt
inu
ed
Pr
od
u
–1 uA
–1 uA
Rev: 1.05a 10/2009
22/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Operating Currents
-250
Device Selected;
All other inputs
VIH or VIL
Output open
Operating
Current
Symbol
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
Pipeline
IDD
IDDQ
305
40
315
40
255
30
265
30
205
20
215
20
mA
Flow Through
IDD
IDDQ
235
20
245
20
205
15
215
15
190
15
200
15
mA
Pipeline
IDD
IDDQ
275
20
285
20
230
15
240
15
185
15
195
15
mA
Flow Through
IDD
IDDQ
215
10
225
10
190
10
200
10
175
10
185
10
mA
Pipeline
ISB
40
50
40
50
40
50
mA
Flow Through
ISB
40
50
40
50
40
50
mA
Pipeline
IDD
85
90
75
80
60
65
mA
Flow Through
IDD
60
65
50
55
50
55
mA
Mode
(x32/
x36)
(x18)
Standby
Current
ZZ VDD – 0.2 V
Deselect
Current
Device Deselected;
All other inputs
VIH or  VIL
—
—
ct
Test Conditions
-150
–40
to
85°C
n—
Di
sco
nt
inu
ed
Pr
od
u
Parameter
-200
0
to
70°C
Unit
No
t
Re
co
m
me
nd
ed
for
Ne
w
De
sig
Notes:
1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation.
2. All parameters listed are worst case scenario.
Rev: 1.05a 10/2009
23/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
AC Electrical Characteristics
Clock to Output Valid
tKQ
Clock to Output Invalid
tKQX
Clock to Output in Low-Z
tLZ1
Setup time
tS
Hold time
tH
Clock Cycle Time
tKC
Clock to Output Valid
tKQ
Clock to Output Invalid
tKQX
1
Clock to Output in Low-Z
tLZ
Setup time
tS
Hold time
tH
Clock HIGH Time
tKH
-150
Min
Max
Min
Max
Min
Max
4.0
—
5.0
—
ct
tKC
-200
6.7
—
n—
Di
sco
nt
inu
ed
Pr
od
u
Clock Cycle Time
-250
Unit
ns
—
2.5
—
3.0
—
3.8
ns
1.5
—
1.5
—
1.5
—
ns
1.5
—
1.5
—
1.5
—
ns
1.2
—
1.4
—
1.5
—
ns
0.2
—
0.4
—
0.5
—
ns
5.5
—
6.5
—
7.5
—
ns
—
5.5
—
6.5
—
7.5
ns
2.0
—
2.0
—
2.0
—
ns
2.0
—
2.0
—
2.0
—
ns
1.5
—
1.5
—
1.5
—
ns
0.5
—
0.5
—
0.5
—
ns
1.3
—
1.3
—
1.5
—
ns
1.5
—
1.5
—
1.7
—
ns
De
sig
Flow Through
Symbol
1.5
2.5
1.5
3.0
1.5
3.0
ns
Clock LOW Time
tKL
Clock to Output in
High-Z
tHZ1
G to Output Valid
tOE
—
2.5
—
3.0
—
3.8
ns
G to output in Low-Z
tOLZ1
0
—
0
—
0
—
ns
G to output in High-Z
ZZ setup time
tOHZ1
me
nd
ed
for
ZZ hold time
Ne
w
Pipeline
Parameter
ZZ recovery
—
2.5
—
3.0
—
3.8
ns
2
5
—
5
—
5
—
ns
2
1
—
1
—
1
—
ns
tZZR
20
—
20
—
20
—
ns
tZZS
tZZH
No
t
Re
co
m
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.05a 10/2009
24/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Pipeline Mode Timing (NBT)
Write A
Write B
Write B+1
Read C
Cont
Read D
Write E
Read F
Write G
Deselect
tKL
tKH
tKC
ct
CK
n—
Di
sco
nt
inu
ed
Pr
od
u
tH
tS
CKE
tH
tS
E*
tH
tS
ADV
tH
tS
W
tH
tS
Bn
tH
tS
A
A0–An
B
C
D
tS
D(A)
F
D(B)
D(B+1)
G
tHZ
tKQX
Q(C)
Q(D)
D(E)
Q(F)
D(G)
tOLZ
tOHZ
tOE
Ne
w
DQa–DQd
E
tLZ
tKQ
De
sig
tH
G
No
t
Re
co
m
me
nd
ed
for
*Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1
Rev: 1.05a 10/2009
25/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Flow Through Mode Timing (NBT)
Write A
Write B
Write B+1
Read C
Cont
Read D
Write E
Read F
Write G
tKL
tKH
tKC
tH
tS
CKE
tH
tS
E*
tH
tS
ADV
tH
tS
W
tH
tS
Bn
tH
A0–An
B
C
tH
tS
D(A)
D(B)
D(B+1)
Ne
w
DQ
D
tKQ
tLZ
G
E
F
tKQX
De
sig
tS
A
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
CK
tHZ
Q(C)
Q(D)
G
tKQ
tLZ
D(E)
tKQX
Q(F)
D(G)
tOLZ
tOE
tOHZ
JTAG Port Operation
me
nd
ed
for
*Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1
Re
co
m
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output
drivers are powered by VDDQ.
No
t
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
Rev: 1.05a 10/2009
26/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
JTAG Pin Descriptions
Pin Name
I/O
Description
TCK
Test Clock
In
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TMS
Test Mode Select
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
In
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
Test Data In
TDO
Test Data Out
n—
Di
sco
nt
inu
ed
Pr
od
u
TDI
ct
Pin
Output that is active depending on the state of the TAP state machine. Output changes in
Out response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
JTAG Port Registers
Ne
w
De
sig
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
me
nd
ed
for
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
No
t
Re
co
m
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
Rev: 1.05a 10/2009
27/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
·
·
·
·
·
·
·
n—
Di
sco
nt
inu
ed
Pr
od
u
·
ct
JTAG TAP Block Diagram
Boundary Scan Register
·
1
·
·
108
0
0
Bypass Register
2 1 0
Instruction Register
TDI
TDO
ID Code Register
·
· ··
2 1 0
De
sig
31 30 29
Control Signals
TMS
Test Access Port (TAP) Controller
Ne
w
TCK
No
t
Die
Revision
Code
Re
co
m
ID Register Contents
GSI Technology
JEDEC Vendor
ID Code
I/O
Configuration
Not Used
Presence Register
me
nd
ed
for
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Bit #
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
x36
X
X
x32
X
x18
x16
X
X
0
0
0
X
1
0
0
1
0
0
0
0
1
0
0
0
0
0 0 1 1 0 1 1 0 0 1
1
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0 0 1 1 0 1 1 0 0 1
1
X
X
X
X
0
0
0
X
1
0
0
1
0
0
0
0
1
0
1
0
0
0 0 1 1 0 1 1 0 0 1
1
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0 0 1 1 0 1 1 0 0 1
1
Rev: 1.05a 10/2009
28/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Tap Controller Instruction Set
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
0
Run Test Idle
1
Select DR
1
Select IR
0
0
1
De
sig
Shift DR
Ne
w
1
me
nd
ed
for
1
0
Shift IR
0
1
1
Exit1 DR
0
Exit1 IR
0
0
Pause DR
1
Exit2 DR
1
Update DR
1
Capture IR
0
0
Pause IR
1
Exit2 IR
0
1
0
0
Update IR
1
0
No
t
Re
co
m
1
Capture DR
0
1
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.
Rev: 1.05a 10/2009
29/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
De
sig
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.

Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated.
Ne
w
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
me
nd
ed
for
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
RFU
No
t
Re
co
m
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
Rev: 1.05a 10/2009
30/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
JTAG TAP Instruction Set Summary
Code
Description
Notes
EXTEST
000
Places the Boundary Scan Register between TDI and TDO.
1
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
1, 2
SAMPLE-Z
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
1
RFU
011
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
SAMPLE/
PRELOAD
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
1
GSI
101
GSI private instruction.
1
RFU
110
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
Instruction
1
No
t
Re
co
m
me
nd
ed
for
Ne
w
De
sig
BYPASS
111
Places Bypass Register between TDI and TDO.
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
1
Rev: 1.05a 10/2009
31/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
JTAG Port Recommended Operating Conditions and DC Characteristics
Symbol
Min.
Max.
Unit Notes
3.3 V Test Port Input High Voltage
VIHJ3
2.0
VDD3 +0.3
V
1
3.3 V Test Port Input Low Voltage
VILJ3
–0.3
0.8
V
1
2.5 V Test Port Input High Voltage
VIHJ2
0.6 * VDD2
VDD2 +0.3
V
1
VILJ2
–0.3
0.3 * VDD2
V
1
IINHJ
–300
1
uA
2
IINLJ
–1
100
uA
3
IOLJ
–1
1
uA
4
VOHJ
1.7
—
V
5, 6
VOLJ
—
0.4
V
5, 7
VOHJC
VDDQ – 100 mV
—
V
5, 8
VOLJC
—
100 mV
V
5, 9
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
Parameter
2.5 V Test Port Input Low Voltage
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
Test Port Output High Voltage
Test Port Output Low Voltage
Test Port Output CMOS High
Test Port Output CMOS Low
me
nd
ed
for
Ne
w
De
sig
Notes:
1. Input Under/overshoot voltage must be –2 V > Vi < VDDn +1.5 V maximum, with a pulse width not to exceed 50% tTKC.
2. VILJ  VIN VDDn
3. 0 V VIN VILJn
4. Output Disable, VOUT = 0 to VDDn
5. The TDO output driver is served by the VDDQ supply.
6. IOHJ = –4 mA
7. IOLJ = + 4 mA
8. IOHJC = –100 uA
9. IOHJC = +100 uA
JTAG Port AC Test Conditions
Parameter
Input high level
Input low level
Re
co
m
Input slew rate
Conditions
VDD – 0.2 V
JTAG Port AC Test Load
DQ
0.2 V
50
1 V/ns
Input reference level
VDDQ/2
Output reference level
VDDQ/2
30pF*
VDDQ/2
* Distributed Test Jig Capacitance
No
t
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
Rev: 1.05a 10/2009
32/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
JTAG Port Timing Diagram
tTKC
tTKH
tTKL
TCK
tTH
tTS
TMS
tTKQ
TDO
tTH
tTS
Parallel SRAM input
JTAG Port AC Electrical Characteristics
Symbol
Min
Max
TCK Cycle Time
tTKC
50
—
TCK Low to TDO Valid
tTKQ
—
TCK High Pulse Width
tTKH
20
TCK Low Pulse Width
tTKL
20
TDI & TMS Set Up Time
tTS
TDI & TMS Hold Time
tTH
Unit
ns
De
sig
Parameter
n—
Di
sco
nt
inu
ed
Pr
od
u
tTH
tTS
ct
TDI
ns
—
ns
—
ns
10
—
ns
10
—
ns
me
nd
ed
for
Ne
w
20
No
t
Re
co
m
Boundary Scan (BSDL Files)
For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications
Engineering Department at: [email protected]
Rev: 1.05a 10/2009
33/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
TQFP Package Drawing (Package T)
A1
Standoff
0.05
0.10
0.15
A2
Body Thickness
1.35
1.40
1.45
b
Lead Width
0.20
0.30
0.40
c
Lead Thickness
0.09
—
0.20
D
Terminal Dimension
21.9
22.0
22.1
D1
Package Body
19.9
20.0
20.1
E
Terminal Dimension
15.9
16.0
16.1
E1
Package Body
13.9
14.0
14.1
e
Lead Pitch
—
0.65
—
L
Foot Length
0.45
0.60
0.75
L1
Lead Length
—
1.00
—
Y
Coplanarity

Lead Angle
n—
Di
sco
nt
inu
ed
Pr
od
u
Min. Nom. Max
e
b
A2
Y
De
sig
A1
0.10
0
—
7
E1
E
No
t
Re
co
m
me
nd
ed
for
Ne
w
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
D
D1
Description
c
Pin 1
Symbol
L1

ct
L
Rev: 1.05a 10/2009
34/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Package Dimensions—165-Bump FPBGA (Package D)
A1 CORNER
TOP VIEW
BOTTOM VIEW
Ø0.10 M C
Ø0.25 M C A B
Ø0.40~0.60 (165x)
ct
1 2 3 4 5 6 7 8 9 10 11
A1 CORNER
14.0
1.0
1.0
10.0
13±0.05
0.20(4x)
No
t
Re
co
m
0.36~0.46
1.40 MAX.
SEATING PLANE
C
B
1.0
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
me
nd
ed
for
0.15 C
Ne
w
A
De
sig
15±0.05
1.0
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
n—
Di
sco
nt
inu
ed
Pr
od
u
11 10 9 8 7 6 5 4 3 2 1
Rev: 1.05a 10/2009
35/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Ordering Information for GSI Synchronous Burst RAMs
TA3
250/5.5
C
TQFP
200/6.5
C
TQFP
150/7.5
C
RoHS-compliant TQFP
250/5.5
C
RoHS-compliant TQFP
200/6.5
C
RoHS-compliant TQFP
150/7.5
C
165 BGA
250/5.5
C
165 BGA
200/6.5
C
165 BGA
150/7.5
C
165 BGA
250/5.5
C
165 BGA
200/6.5
C
165 BGA
150/7.5
C
RoHS-compliant 165 BGA
250/5.5
C
RoHS-compliant 165 BGA
200/6.5
C
Pipeline/Flow Through
RoHS-compliant 165 BGA
150/7.5
C
GS8161Z32BGD-250
Pipeline/Flow Through
RoHS-compliant 165 BGA
250/5.5
C
512K x 32
GS8161Z32BGD-200
Pipeline/Flow Through
RoHS-compliant 165 BGA
200/6.5
C
512K x 32
GS8161Z32BGD-150
Pipeline/Flow Through
RoHS-compliant 165 BGA
150/7.5
C
512K x 36
GS8161Z36BT-250
Pipeline/Flow Through
TQFP
250/5.5
C
512K x 36
GS8161Z36BT-200
Pipeline/Flow Through
TQFP
200/6.5
C
512K x 36
GS8161Z36BT-150
Pipeline/Flow Through
TQFP
150/7.5
C
512K x 36
GS8161Z36BGT-250
Pipeline/Flow Through
RoHS-compliant TQFP
250/5.5
C
512K x 36
GS8161Z36BGT-200
Pipeline/Flow Through
RoHS-compliant TQFP
200/6.5
C
512K x 36
GS8161Z36BGT-150
Pipeline/Flow Through
RoHS-compliant TQFP
150/7.5
C
512K x 36
GS8161Z36BD-250
Pipeline/Flow Through
165 BGA
250/5.5
C
512K x 36
GS8161Z36BD-200
Pipeline/Flow Through
165 BGA
200/6.5
C
512K x 36
GS8161Z36BD-150
Pipeline/Flow Through
165 BGA
150/7.5
C
512K x 36
GS8161Z36BGD-250
Pipeline/Flow Through
RoHS-compliant 165 BGA
250/5.5
C
Type
Package
1M x 18
GS8161Z18BT-250
Pipeline/Flow Through
TQFP
1M x 18
GS8161Z18BT-200
Pipeline/Flow Through
1M x 18
GS8161Z18BT-150
Pipeline/Flow Through
1M x 18
GS8161Z18BGT-250
Pipeline/Flow Through
1M x 18
GS8161Z18BGT-200
Pipeline/Flow Through
1M x 18
GS8161Z18BGT-150
Pipeline/Flow Through
1M x 18
GS8161Z18BD-250
Pipeline/Flow Through
1M x 18
GS8161Z18BD-200
Pipeline/Flow Through
1M x 18
GS8161Z18BD-150
Pipeline/Flow Through
512K x 32
GS8161Z32BD-250
Pipeline/Flow Through
512K x 32
GS8161Z32BD-200
Pipeline/Flow Through
512K x 32
GS8161Z32BD-150
Pipeline/Flow Through
1M x 18
GS8161Z18BGD-250
Pipeline/Flow Through
1M x 18
GS8161Z18BGD-200
Pipeline/Flow Through
1M x 18
GS8161Z18BGD-150
512K x 32
De
sig
Ne
w
me
nd
ed
for
Re
co
m
n—
Di
sco
nt
inu
ed
Pr
od
u
Part Number1
ct
Speed2
(MHz/ns)
Org
No
t
512K x 36
GS8161Z36BGD-200
Pipeline/Flow Through
RoHS-compliant 165 BGA
200/6.5
C
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number.
1. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
3. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.05a 10/2009
36/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Ordering Information for GSI Synchronous Burst RAMs (Continued)
Part Number1
Type
Package
Speed2
(MHz/ns)
TA3
512K x 36
GS8161Z36BGD-150
Pipeline/Flow Through
RoHS-compliant 165 BGA
150/7.5
C
1M x 18
GS8161Z18BT-250I
Pipeline/Flow Through
TQFP
250/5.5
I
1M x 18
GS8161Z18BT-200I
Pipeline/Flow Through
TQFP
200/6.5
I
1M x 18
GS8161Z18BT-150I
Pipeline/Flow Through
TQFP
150/7.5
I
1M x 18
GS8161Z18BGT-250I
Pipeline/Flow Through
RoHS-compliant TQFP
250/5.5
I
1M x 18
GS8161Z18BGT-200I
Pipeline/Flow Through
RoHS-compliant TQFP
200/6.5
I
1M x 18
GS8161Z18BGT-150I
Pipeline/Flow Through
RoHS-compliant TQFP
150/7.5
I
1M x 18
GS8161Z18BD-250I
Pipeline/Flow Through
165 BGA
250/5.5
I
1M x 18
GS8161Z18BD-200I
Pipeline/Flow Through
165 BGA
200/6.5
I
1M x 18
GS8161Z18BD-150I
Pipeline/Flow Through
165 BGA
150/7.5
I
512K x 32
GS8161Z32BD-250I
Pipeline/Flow Through
165 BGA
250/5.5
I
512K x 32
GS8161Z32BD-200I
Pipeline/Flow Through
165 BGA
200/6.5
I
512K x 32
GS8161Z32BD-150I
Pipeline/Flow Through
165 BGA
150/7.5
I
1M x 18
GS8161Z18BGD-250I
Pipeline/Flow Through
RoHS-compliant 165 BGA
250/5.5
I
1M x 18
GS8161Z18BGD-200I
Pipeline/Flow Through
RoHS-compliant 165 BGA
200/6.5
I
1M x 18
GS8161Z18BGD-150I
Pipeline/Flow Through
RoHS-compliant 165 BGA
150/7.5
I
512K x 32
GS8161Z32BGD-250I
Pipeline/Flow Through
RoHS-compliant 165 BGA
250/5.5
I
512K x 32
GS8161Z32BGD-200I
Pipeline/Flow Through
RoHS-compliant 165 BGA
200/6.5
I
512K x 32
GS8161Z32BGD-150I
Pipeline/Flow Through
RoHS-compliant 165 BGA
150/7.5
I
512K x 36
GS8161Z36BT-250I
Pipeline/Flow Through
TQFP
250/5.5
I
512K x 36
GS8161Z36BT-200I
Pipeline/Flow Through
TQFP
200/6.5
I
512K x 36
GS8161Z36BT-150I
Pipeline/Flow Through
TQFP
150/7.5
I
512K x 36
GS8161Z36BGT-250I
Pipeline/Flow Through
RoHS-compliant TQFP
300/5.3
I
512K x 36
GS8161Z36BGT-200I
Pipeline/Flow Through
RoHS-compliant TQFP
200/6.5
I
512K x 36
GS8161Z36BGT-150I
Pipeline/Flow Through
RoHS-compliant TQFP
150/7.5
I
512K x 36
GS8161Z36BD-250I
Pipeline/Flow Through
165 BGA
250/5.5
I
512K x 36
GS8161Z36BD-200I
Pipeline/Flow Through
165 BGA
200/6.5
I
512K x 36
GS8161Z36BD-150I
Pipeline/Flow Through
165 BGA
150/7.5
I
512K x 36
GS8161Z36BGD-250I
Pipeline/Flow Through
RoHS-compliant 165 BGA
250/5.5
I
512K x 36
GS8161Z36BGD-200I
Pipeline/Flow Through
RoHS-compliant 165 BGA
200/6.5
I
n—
Di
sco
nt
inu
ed
Pr
od
u
De
sig
Ne
w
me
nd
ed
for
Re
co
m
ct
Org
No
t
512K x 36
GS8161Z36BGD-150I
Pipeline/Flow Through
RoHS-compliant 165 BGA
150/7.5
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number.
1. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
3. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.05a 10/2009
37/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
18Mb Sync SRAM Data Sheet Revision History
Types of Changes
Format or Content
Page;Revisions;Reason
• Creation of new datasheet
8161ZxxB_r1
ct
DS/DateRev. Code: Old;
New
• Updated overshoot/undershoot information
Content
8161ZxxB_r1_01;
8161ZxxB_r1_02
Content
• Added 300 MHz speed bin
• Added Pb-free information for 165 BGA
8161ZxxB_r1_02;
8161ZxxB_r1_03
Content
• Removed 300 MHz speed bin
• Changed Pb-free to RoHS-compliant
• Added Status column to Ordering Information table
• Rev1.03a: updated coplanarity for 165 BGA mechanical, removed
Status column from Ordering Information table.
8161ZxxB_r1_03;
8161ZxxB_r1_04
Content
8161ZxxB_r1_04;
8161ZxxB_r1_05
Content
n—
Di
sco
nt
inu
ed
Pr
od
u
8161ZxxB_r1;
8161ZxxB_r1_01
• Added MCH to Pin Description table
No
t
Re
co
m
me
nd
ed
for
Ne
w
De
sig
• Updated to MP Status
• Rev.1.05a: Updated Pin Description to include DQPn designation
Rev: 1.05a 10/2009
38/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
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