Data Sheet

NX3L4053-Q100
Triple low-ohmic single-pole double-throw analog switch
Rev. 1 — 18 April 2013
Product data sheet
1. General description
The NX3L4053-Q100 is a triple low-ohmic single-pole double-throw analog switch,
suitable for use as an analog or digital multiplexer/demultiplexer. Each switch has a digital
select input (nS), two independent inputs/outputs (nY0 and nY1) and a common
input/output (nZ). All three switches share an enable input (E). A digital enable pin E is
common to all switches. When E is HIGH, the switches are turned off.
Schmitt trigger action at the digital inputs makes the circuit tolerant to slower input rise and
fall times. Low threshold digital inputs allow this device to be driven by 1.8 V logic levels in
3.3 V applications without significant increase in supply current ICC. This makes it possible
for the NX3L4053-Q100 to switch 4.3 V signals with a 1.8 V digital controller, eliminating
the need for logic level translation. The NX3L4053-Q100 allows signals with amplitude up
to VCC to be transmitted from nZ to nY0 or nY1; or from nY0 or nY1 to nZ. Its low ON
resistance (0.5 ) and flatness (0.13 ) ensures minimal attenuation and distortion of
transmitted signals.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +85 C and from 40 C to +125 C
 Wide supply voltage range from 1.4 V to 4.3 V
 Very low ON resistance (peak):
 1.8  (typical) at VCC = 1.4 V
 1.0  (typical) at VCC = 1.65 V
 0.6  (typical) at VCC = 2.3 V
 0.6  (typical) at VCC = 2.7 V
0.5  (typical) at VCC = 4.3 V
 Break-before-make switching
 High noise immunity
 ESD protection:
 MIL-STD-883, method 3015 Class 3A exceeds 4000 V
 HBM JESD22-A114F Class 3A exceeds 4000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
 CDM AEC-Q100-011 revision B exceeds 1000 V
 IEC61000-4-2 contact discharge exceeds 6000 V for switch ports
 CMOS low-power consumption
 Latch-up performance exceeds 100 mA per JESD 78 Class II Level A
NX3L4053-Q100
NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch




1.8 V control logic at VCC = 3.6 V
Control input accepts voltages above supply voltage
Very low supply current, even when input is below VCC
High current handling capability (350 mA continuous current under 3.3 V supply)
3. Applications






Cell phone
PDA
Portable media player
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
40 C to +125 C
HXQFN16
plastic thermal enhanced extremely thin quad flat SOT1039-2
package; no leads; 16 terminals; body 3  3  0.5
mm
NX3L4053PW-Q100 40 C to +125 C
TSSOP16
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
NX3L4053HR-Q100
Version
5. Marking
Table 2.
Marking codes
Type number
Marking code
NX3L4053HR-Q100
M43
NX3L4053PW-Q100
X3L4053
NX3L4053_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 18 April 2013
© NXP B.V. 2013. All rights reserved.
2 of 22
NX3L4053-Q100
NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch
6. Functional diagram
VCC
16
13
1S
2S
11
1S
1Y0
12
10
2S
1Y1
13
9
3S
1Z
14
2Y0
2
2Y1
1
2Z
6
E
3S
1Y1
11
10
12
9
1Y0
14
1Z
1
DECODER
LOGIC
2Y1
2
2Y0
15
3Y0
5
3Y1
3
3Z
15
2Z
3
4
3Y1
001aal735
E
5
6
3Y0
4
3Z
8
GND
Pin numbers are shown for TSSOP16 package only.
Fig 1.
Logic symbol
001aal736
Pin numbers are shown for TSSOP16 package only.
Fig 2.
Logic diagram
7. Pinning information
7.1 Pinning
1;/4
$"%
"&'
<
9&&
<
=
<
=
=
<
<
<
(
6
QF
6
*1'
1;/4
DDD
Fig 3.
Pin configuration SOT1039-2 (HXQFN16)
NX3L4053_Q100
Product data sheet
6
DDD
!"#
Fig 4.
Pin configuration SOT403-1 (TSSOP16)
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NX3L4053-Q100
NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch
7.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
SOT1039-2
SOT403-1
E
4
6
enable input (active LOW)
n.c.
5
7
not connected
GND
6
8
ground (0 V)
1S, 2S, 3S
9, 8, 7
11, 10 ,9
select input
1Y0, 2Y0, 3Y0
10, 16, 3
12, 2, 5
independent input or output
1Y1, 2Y1, 3Y1
11, 15, 1
13, 1, 3
independent input or output
1Z , 2Z, 3Z
12, 13, 2
14, 15, 4
independent output or input
VCC
14
16
supply voltage
8. Functional description
Table 4.
Function table
Inputs
Channel on
E
nS
L
L
nY0 to nZ
L
H
nY1 to nZ
H
X
switches off
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
9. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
VI
input voltage
VSW
switch voltage
IIK
input clamping current
ISK
switch clamping current
VI < 0.5 V or VI > VCC + 0.5 V
ISW
switch current
VSW > 0.5 V or VSW < VCC + 0.5 V;
source or sink current
VSW > 0.5 V or VSW < VCC + 0.5 V;
pulsed at 1 ms duration, < 10 % duty cycle;
peak current
Tstg
Conditions
nS and E
VI < 0.5 V
storage temperature
NX3L4053_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 18 April 2013
Min
Max
Unit
0.5
+4.6
V
[1]
0.5
+4.6
V
[2]
0.5
VCC + 0.5 V
50
-
mA
-
50
mA
-
350
mA
-
500
mA
65
+150
C
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NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch
Table 5.
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Ptot
total power dissipation
Tamb = 40 C to +125 C
Min
Max
Unit
HXQFN16
[3]
-
250
mW
TSSOP16
[4]
-
500
mW
[1]
The minimum input voltage rating may be exceeded if the input current rating is observed.
[2]
The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed but may not
exceed 4.6 V.
[3]
For HXQFN16 package: above 135 C the value of Ptot derates linearly with 16.9 mW/K.
[4]
For TSSOP16 package: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
10. Recommended operating conditions
Table 6.
Recommended operating conditions
Symbol Parameter
VCC
supply voltage
VI
input voltage
VSW
Conditions
nS and E
[1]
switch voltage
Tamb
ambient temperature
t/V
input transition rise and fall rate
[1]
nS and E; VCC = 1.4 V to 4.3 V
Min
Max
Unit
1.4
4.3
V
0
4.3
V
0
VCC
V
40
+125
C
-
200
ns/V
To avoid sinking GND current from terminal nZ when switch current flows in terminal nYn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no GND current flows from terminal nYn. In this case, there is
no limit for the voltage drop across the switch.
11. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground 0 V).
Symbol Parameter
VIH
VIL
II
HIGH-level
input voltage
LOW-level
input voltage
input leakage
current
NX3L4053_Q100
Product data sheet
Tamb = 25 C
Conditions
Tamb = 40 C to +125 C
Unit
Min
Typ
Max
Min
Max
Max
(85 C) (125 C)
VCC = 1.4 V to 1.6 V
0.9
-
-
0.9
-
-
V
VCC = 1.65 V to 1.95 V
0.9
-
-
0.9
-
-
V
VCC = 2.3 V to 2.7 V
1.1
-
-
1.1
-
-
V
VCC = 2.7 V to 3.6 V
1.3
-
-
1.3
-
-
V
VCC = 3.6 V to 4.3 V
1.4
-
-
1.4
-
-
V
VCC = 1.4 V to 1.6 V
-
-
0.3
-
0.3
0.3
V
VCC = 1.65 V to 1.95 V
-
-
0.4
-
0.4
0.3
V
VCC = 2.3 V to 2.7 V
-
-
0.4
-
0.4
0.4
V
VCC = 2.7 V to 3.6 V
-
-
0.5
-
0.5
0.5
V
VCC = 3.6 V to 4.3 V
-
-
0.6
-
0.6
0.6
V
nS and E;
VI = GND to 4.3 V;
VCC = 1.4 V to 4.3 V
-
-
-
-
0.5
1
A
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Triple low-ohmic single-pole double-throw analog switch
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground 0 V).
Symbol Parameter
IS(OFF)
IS(ON)
ICC
ICC
OFF-state
leakage
current
ON-state
leakage
current
Tamb = 25 C
Conditions
Tamb = 40 C to +125 C
Unit
Min
Typ
Max
Min
Max
Max
(85 C) (125 C)
VCC = 1.4 V to 3.6 V
-
-
5
-
50
500
nA
VCC = 3.6 V to 4.3 V
-
-
10
-
50
500
nA
VCC = 1.4 V to 3.6 V
-
-
5
-
50
500
nA
VCC = 3.6 V to 4.3 V
-
-
10
-
50
500
nA
VCC = 3.6 V
-
-
100
-
500
5000
nA
VCC = 4.3 V
nY0 and nY1 port;
see Figure 5
nZ port;
VCC = 1.4 V to 3.6 V;
see Figure 6
supply current VI = VCC or GND;
VSW = GND or VCC
-
-
150
-
800
6000
nA
additional
VSW = GND or VCC
supply current
VI = 2.6 V; VCC = 4.3 V
-
2.0
4.0
-
7
7
A
VI = 2.6 V; VCC = 3.6 V
-
0.35
0.7
-
1
1
A
VI = 1.8 V; VCC = 4.3 V
-
7.0
10.0
-
15
15
A
VI = 1.8 V; VCC = 3.6 V
-
2.5
4.0
-
5
5
A
VI = 1.8 V; VCC = 2.5 V
-
50
200
-
300
500
nA
-
1.0
-
-
-
-
pF
CI
input
capacitance
nS and E
CS(OFF)
OFF-state
capacitance
-
35
-
-
-
-
pF
CS(ON)
ON-state
capacitance
-
130
-
-
-
-
pF
11.1 Test circuits
VCC
VIL or VIH
nS
nY0 1
nZ
nY1 2
switch
nS
E
1
VIL
VIH
2
VIH
VIH
switch
IS
E
GND
VIH
VI
VO
001aal739
VI = 0.3 V or VCC  0.3 V; VO = VCC  0.3 V or 0.3 V.
Fig 5.
Test circuit for measuring OFF-state leakage current
NX3L4053_Q100
Product data sheet
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NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch
VCC
VIL or VIH
nS
nY0 1
nZ
nY1 2
switch
nS
E
1
VIL
VIL
2
VIH
VIL
switch
IS
E
GND
VIL
VI
VO
001aal740
VI = 0.3 V or VCC  0.3 V; VO = VCC  0.3 V or 0.3 V.
Fig 6.
Test circuit for measuring ON-state leakage current
11.2 ON resistance
Table 8.
ON resistance[1]
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 8 to Figure 14.
Symbol
Parameter
RON(peak) ON resistance
(peak)
Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit
Conditions
Min
Typ[2]
Max
Min
Max
VCC = 1.4 V
-
1.8
3.8
-
4.2

VCC = 1.65 V
-
1.0
1.7
-
1.8

VCC = 2.3 V
-
0.6
0.9
-
1.0

VCC = 2.7 V
-
0.6
0.80
-
1.0

-
0.5
0.80
-
1.0

VCC = 1.4 V; VSW = 0.4 V
-
0.23
0.38
-
0.38

VCC = 1.65 V; VSW = 0.5 V
-
0.23
0.28
-
0.38

VCC = 2.3 V; VSW = 0.7 V
-
0.12
0.15
-
0.18

VCC = 2.7 V; VSW = 0.8 V
-
0.12
0.15
-
0.18

VCC = 4.3 V; VSW = 0.8 V
-
0.12
0.15
-
0.18

VCC = 1.4 V
-
1.0
3.3
-
3.6

VCC = 1.65 V
-
0.5
1.2
-
1.3

VCC = 2.3 V
-
0.15
0.3
-
0.35

VCC = 2.7 V
-
0.13
0.3
-
0.35

VCC = 4.3 V
-
0.2
0.4
-
0.45

VI = GND to VCC;
ISW = 100 mA; see Figure 7
VCC = 4.3 V
RON
RON(flat)
ON resistance
mismatch
between
channels
ON resistance
(flatness)
[3]
VI = GND to VCC;
ISW = 100 mA
[4]
VI = GND to VCC;
ISW = 100 mA
[1]
For NX3L4053PW-Q100 (TSSOP16 package), all ON resistance values are up to 0.05  higher.
[2]
Typical values are measured at Tamb = 25 C.
[3]
Measured at identical VCC, temperature and input voltage.
[4]
Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and
temperature.
NX3L4053_Q100
Product data sheet
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Rev. 1 — 18 April 2013
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NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch
11.3 ON resistance test circuit and graphs
001aag564
1.6
RON
(Ω)
1.2
(1)
V
VCC
VIL or VIH
VSW
nS
nY0 1
nZ
nY1 2
switch
switch
nS
E
1
VIL
VIL
2
VIH
VIL
0.8
(2)
(3)
(4)
0.4
(5)
(6)
E
GND
VIL
VI
ISW
0
0
1
2
RON = VSW / ISW.
3
4
5
VI (V)
001aal741
(1) VCC = 1.5 V.
(2) VCC = 1.8 V.
(3) VCC = 2.5 V.
(4) VCC = 2.7 V.
(5) VCC = 3.3 V.
(6) VCC = 4.3 V.
Measured at Tamb = 25 C.
Fig 7.
Test circuit for measuring ON resistance
NX3L4053_Q100
Product data sheet
Fig 8.
Typical ON resistance as a function of input
voltage
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Triple low-ohmic single-pole double-throw analog switch
001aag565
1.6
001aag566
1.0
RON
(Ω)
RON
(Ω)
0.8
1.2
(1)
(2)
(3)
(4)
0.6
(1)
(2)
(3)
(4)
0.8
0.4
0.4
0.2
0
0
0
1
2
3
0
1
2
VI (V)
(1) Tamb = 125 C.
(1) Tamb = 125 C.
(2) Tamb = 85 C.
(2) Tamb = 85 C.
(3) Tamb = 25 C.
(3) Tamb = 25 C.
(4) Tamb = 40 C.
(4) Tamb = 40 C.
Fig 9.
ON resistance as a function of input voltage;
VCC = 1.5 V
001aag567
1.0
3
VI (V)
Fig 10. ON resistance as a function of input voltage;
VCC = 1.8 V
001aag568
1.0
RON
(Ω)
RON
(Ω)
0.8
0.8
0.6
0.6
(1)
(2)
(3)
(4)
0.4
0.4
0.2
0.2
0
(1)
(2)
(3)
(4)
0
0
1
2
3
0
VI (V)
(1) Tamb = 125 C.
(2) Tamb = 85 C.
(2) Tamb = 85 C.
(3) Tamb = 25 C.
(3) Tamb = 25 C.
(4) Tamb = 40 C.
(4) Tamb = 40 C.
Fig 11. ON resistance as a function of input voltage;
VCC = 2.5 V
Product data sheet
2
3
VI (V)
(1) Tamb = 125 C.
NX3L4053_Q100
1
Fig 12. ON resistance as a function of input voltage;
VCC = 2.7 V
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Triple low-ohmic single-pole double-throw analog switch
001aag569
1.0
001aaj896
1.0
RON
(Ω)
RON
(Ω)
0.8
0.8
0.6
0.6
(1)
(2)
(3)
(4)
0.4
(1)
(2)
(3)
(4)
0.4
0.2
0.2
0
0
0
1
2
3
4
0
1
2
3
4
VI (V)
5
VI (V)
(1) Tamb = 125 C.
(1) Tamb = 125 C.
(2) Tamb = 85 C.
(2) Tamb = 85 C.
(3) Tamb = 25 C.
(3) Tamb = 25 C.
(4) Tamb = 40 C.
(4) Tamb = 40 C.
Fig 13. ON resistance as a function of input voltage;
VCC = 3.3 V
Fig 14. ON resistance as a function of input voltage;
VCC = 4.3 V
12. Dynamic characteristics
Table 9.
Dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 17.
Symbol Parameter
ten
tdis
enable time
disable time
Tamb = 25 C
Conditions
Product data sheet
Unit
Min
Max
Min
Max
(85 C)
Max
(125 C)
VCC = 1.4 V to 1.6 V
-
49
90
-
120
120
ns
VCC = 1.65 V to 1.95 V
-
35
70
-
80
90
ns
VCC = 2.3 V to 2.7 V
-
23
45
-
50
55
ns
VCC = 2.7 V to 3.6 V
-
21
40
-
45
50
ns
VCC = 3.6 V to 4.3 V
-
21
40
-
45
50
ns
-
32
70
-
80
90
ns
E, nS to nZ or nYn;
see Figure 15
E, nS to nZ or nYn;
see Figure 15
VCC = 1.4 V to 1.6 V
NX3L4053_Q100
Tamb = 40 C to +125 C
Typ[1]
VCC = 1.65 V to 1.95 V
-
17
55
-
60
65
ns
VCC = 2.3 V to 2.7 V
-
11
25
-
30
35
ns
VCC = 2.7 V to 3.6 V
-
8
20
-
25
30
ns
VCC = 3.6 V to 4.3 V
-
8
20
-
25
30
ns
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NX3L4053-Q100
NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch
Table 9.
Dynamic characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 17.
Symbol Parameter
tb-m
Tamb = 25 C
Conditions
Tamb = 40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
(85 C)
Max
(125 C)
-
19
-
9
-
-
ns
VCC = 1.65 V to 1.95 V
-
17
-
7
-
-
ns
VCC = 2.3 V to 2.7 V
-
13
-
4
-
-
ns
VCC = 2.7 V to 3.6 V
-
10
-
3
-
-
ns
VCC = 3.6 V to 4.3 V
-
9
-
2
-
-
ns
[2]
break-before-make see Figure 16
time
VCC = 1.4 V to 1.6 V
[1]
Typical values are measured at Tamb = 25 C and VCC = 1.5 V, 1.8 V, 2.5 V, 3.3 V and 4.3 V respectively.
[2]
Break-before-make guaranteed by design.
12.1 Waveform and test circuits
VI
VM
VM
nS, E input
GND
ten
tdis
VOH
VX
output
OFF to HIGH
HIGH to OFF
VX
GND
tdis
VOH
ten
VX
output
HIGH to OFF
OFF to HIGH
VX
001aal742
GND
Measurement points are given in Table 10.
Logic level: VOH is typical output voltage level that occurs with the output load.
Fig 15. Enable and disable times
Table 10.
Measurement points
Supply voltage
Input
Output
VCC
VM
VX
1.4 V to 4.3 V
0.5VCC
0.9VOH
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Triple low-ohmic single-pole double-throw analog switch
VCC
nS
nY0
nZ
nY1
E
VIL
G
VI
V
VO
RL
CL
VEXT = 1.5 V
GND
001aal743
a. Test circuit
VI
0.5VI
0.9VO
0.9VO
VO
tb-m
001aag572
b. Input and output measurement points
Fig 16. Test circuit for measuring break-before-make timing
VCC
nS
nY0 1
nZ
nY1 2
switch
E
VIL
G
VI
V
VO
RL
CL
VEXT = 1.5 V
GND
001aal744
Test data is given in Table 11.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
VEXT = External voltage for measuring switching times.
VI may be connected to nS or E.
Fig 17. Test circuit for measuring switching times
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Triple low-ohmic single-pole double-throw analog switch
Table 11.
Test data
Supply voltage
Input
Load
VCC
VI
tr, tf
CL
RL
1.4 V to 4.3 V
VCC
 2.5 ns
35 pF
50 
12.2 Additional dynamic characteristics
Table 12. Additional dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); VI = GND or VCC (unless otherwise
specified); tr = tf  2.5 ns; Tamb = 25 C.
Symbol Parameter
Conditions
THD
fi = 20 Hz to 20 kHz; RL = 32 ; see Figure 18
total harmonic
distortion
Min
-
0.15
-
%
-
0.10
-
%
VCC = 2.3 V; VI = 1.5 V (p-p)
-
0.02
-
%
VCC = 2.7 V; VI = 2 V (p-p)
-
0.02
-
%
-
0.02
-
%
-
60
-
MHz
-
90
-
dB
-
0.2
-
V
-
0.3
-
V
-
90
-
dB
VCC = 1.5 V
-
3
-
pC
VCC = 1.8 V
-
4
-
pC
VCC = 4.3 V; VI = 2 V (p-p)
iso
isolation (OFF-state)
fi = 100 kHz; RL = 50 ; see Figure 20
Vct
crosstalk voltage
between digital inputs and switch;
fi = 1 MHz; CL = 50 pF; RL = 50 ; see Figure 21
[1]
VCC = 1.4 V to 4.3 V
[1]
VCC = 1.4 V to 4.3 V
VCC = 1.4 V to 3.6 V
VCC = 3.6 V to 4.3 V
crosstalk
between switches;
fi = 100 kHz; RL = 50 ; see Figure 22
VCC = 1.4 V to 4.3 V
charge injection
Qinj
[1]
Unit
VCC = 1.4 V; VI = 1 V (p-p)
RL = 50 ; see Figure 19
Xtalk
Max
VCC = 1.65 V; VI = 1.2 V (p-p)
3 dB frequency
response
f(3dB)
Typ
[1]
[1]
fi = 1 MHz; CL = 0.1 nF; RL = 1 M; Vgen = 0 V;
Rgen = 0 ; see Figure 23
VCC = 2.5 V
-
6
-
pC
VCC = 3.3 V
-
9
-
pC
VCC = 4.3 V
-
15
-
pC
fi is biased at 0.5VCC.
NX3L4053_Q100
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Triple low-ohmic single-pole double-throw analog switch
12.3 Test circuits
VCC
VIL or VIH
0.5VCC
nS
nY0 1
nZ
nY1 2
RL
switch
switch
nS
E
1
VIL
VIL
2
VIH
VIL
E
VIL
fi
D
GND
001aal745
Fig 18. Test circuit for measuring total harmonic distortion
VCC
VIL or VIH
0.5VCC
nS
nY0 1
nZ
nY1 2
RL
switch
switch
nS
E
1
VIL
VIL
2
VIH
VIL
E
VIL
fi
dB
GND
001aal746
To obtain 0 dBm level at input, adjust fi voltage. Increase fi frequency until dB meter reads 3 dB.
Fig 19. Test circuit for measuring the frequency response when channel is in ON-state
0.5VCC
VCC
0.5VCC
RL
RL
nS
VIL or VIH
nY0 1
switch
nZ
switch
nS
E
1
VIH
VIH
2
VIL
VIH
nY1 2
E
VIH
fi
dB
GND
001aal747
To obtain 0 dBm level at input, adjust fi voltage.
Fig 20. Test circuit for measuring isolation (OFF-state)
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NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch
VCC
VIL or VIH
VI
G
logic
input
E
nS
nY0
nZ
nY1
RL
RL
0.5VCC
0.5VCC
CL
V
VO
001aal748
a. Test circuit
logic input
(nS, E)
off
on
off
VO
Vct
001aal749
b. Input and output pulse definitions
Fig 21. Test circuit for measuring crosstalk voltage between digital inputs and switch
VCC
0.5VCC 0.5VCC
RL
VIL or VIH
nS
nY0
nZ
nY1
RL
E
VIH
fi
dB
GND
001aal750
Fig 22. Test circuit for measuring crosstalk between switches
NX3L4053_Q100
Product data sheet
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NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch
VCC
nS
nY0 1
nZ
nY1 2
switch
E
Rgen
VIL
G
VI
V
VO
RL
CL
Vgen
GND
001aal751
a. Test circuit
logic input
(nS, E)
off
on
off
VO
VO
001aal752
b. Input and output pulse definitions
Definition: Qinj = VO  CL.
VO = output voltage variation.
Rgen = generator resistance.
Vgen = generator voltage.
VI may be connected to nS or E.
Fig 23. Test circuit for measuring charge injection
NX3L4053_Q100
Product data sheet
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Triple low-ohmic single-pole double-throw analog switch
13. Package outline
HXQFN16: plastic thermal enhanced extremely thin quad flat package; no leads;
16 terminals; body 3 x 3 x 0.5 mm
A
B
D
SOT1039-2
terminal 1
index area
E
A
A1
c
detail X
e1
1/2 e
e
5
8
C
C A B
C
v
w
b
y1 C
y
L
4
9
e
e2
Eh
1/2 e
12
1
terminal 1
index area
16
X
13
Dh
0
1
Dimensions
Unit
max
nom
min
mm
2 mm
scale
A
0.5
A1
b
c
D
0.05 0.35
3.1
0.30 0.127 3.0
0.00 0.25
2.9
Dh
E
Eh
e
e1
e2
L
v
1.95
1.85
1.75
3.1
3.0
2.9
1.95
1.85
1.75
0.5
1.5
1.5
0.40
0.35
0.30
0.1
w
y
0.05 0.05
y1
0.1
sot1039-2_po
References
Outline
version
IEC
SOT1039-2
---
JEDEC
JEITA
---
European
projection
Issue date
10-07-29
11-03-30
Fig 24. Package outline SOT1039-2 (HXQFN16)
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Product data sheet
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NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
E
D
A
X
c
y
HE
v M A
Z
9
16
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
8
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT403-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Fig 25. Package outline SOT403-1 (TSSOP16)
NX3L4053_Q100
Product data sheet
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Triple low-ohmic single-pole double-throw analog switch
14. Abbreviations
Table 13.
Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal-Oxide Semiconductor
ESD
ElectroStatic Discharge
HBM
Human Body Model
MIL
Military
MM
Machine Model
PDA
Personal Digital Assistant
15. Revision history
Table 14.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
NX3L4053_Q100 v.1
20130418
Product data sheet
-
-
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Product data sheet
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Triple low-ohmic single-pole double-throw analog switch
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
NX3L4053_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 18 April 2013
© NXP B.V. 2013. All rights reserved.
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Triple low-ohmic single-pole double-throw analog switch
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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Triple low-ohmic single-pole double-throw analog switch
18. Contents
1
2
3
4
5
6
7
7.1
7.2
8
9
10
11
11.1
11.2
11.3
12
12.1
12.2
12.3
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ON resistance test circuit and graphs. . . . . . . . 8
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Waveform and test circuits . . . . . . . . . . . . . . . 11
Additional dynamic characteristics . . . . . . . . . 13
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19
Legal information. . . . . . . . . . . . . . . . . . . . . . . 20
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Contact information. . . . . . . . . . . . . . . . . . . . . 21
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 18 April 2013
Document identifier: NX3L4053_Q100