Data Sheet

HEF4053B-Q100
Triple single-pole double-throw analog switch
Rev. 2 — 11 September 2014
Product data sheet
1. General description
The HEF4053B-Q100 is a triple single-pole double-throw (SPDT) analog switch, suitable
for use as an analog or digital multiplexer/demultiplexer. Each switch has a digital select
input (Sn), two independent inputs/outputs (nY0 and nY1) and a common input/output
(nZ). All three switches share an enable input (E). A HIGH on E causes all switches into
the high-impedance OFF-state, independent of Sn.
VDD and VSS are the supply voltage connections for the digital control inputs (Sn and E).
The VDD to VSS range is 3 V to 15 V. The analog inputs/outputs (nY0, nY1 and nZ) can
swing between VDD as a positive limit and VEE as a negative limit. VDD  VEE may not
exceed 15 V. Unused inputs must be connected to VDD, VSS, or another input. For
operation as a digital multiplexer/demultiplexer, VEE is connected to VSS (typically
ground). VEE and VSS are the supply voltage connections for the switches.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +85 C and from 40 C to +125 C
 Fully static operation
 5 V, 10 V, and 15 V parametric ratings
 Standardized symmetrical output characteristics
 ESD protection:
 MIL-STD-883, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
 Complies with JEDEC standard JESD 13-B
3. Applications
 Analog multiplexing and demultiplexing
 Digital multiplexing and demultiplexing
 Signal gating
HEF4053B-Q100
NXP Semiconductors
Triple single-pole double-throw analog switch
4. Ordering information
Table 1.
Ordering information
All types operate from 40 C to +125 C.
Type number
Package
HEF4053BT-Q100
Name
Description
Version
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
HEF4053BTT-Q100 TSSOP16
5. Functional diagram
E
6
VDD
16
13 1Y1
S1 11
LOGIC
LEVEL
CONVERSION
DECODER
12 1Y0
14 1Z
1 2Y1
S2 10
6
<
6
<
6
=
<
<
=
<
<
=
LOGIC
LEVEL
CONVERSION
2 2Y0
15 2Z
3 3Y1
S3 9
LOGIC
LEVEL
CONVERSION
5 3Y0
4 3Z
(
8
VSS
DDH
Fig 1.
Logic symbol
HEF4053B_Q100
Product data sheet
Fig 2.
7
VEE
001aae124
Functional diagram
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Rev. 2 — 11 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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HEF4053B-Q100
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Triple single-pole double-throw analog switch
nZ
nY1
Sn
LEVEL
CONVERTER
nY0
E
LEVEL
CONVERTER
to other multiplexers/demultiplexers
001aae645
Fig 3.
Logic diagram (one multiplexer/demultiplexer)
nYn
VDD
VEE
from decoder
and enable logic
Fig 4.
VDD
nZ
001aae644
Schematic diagram (one switch)
6. Pinning information
6.1 Pinning
+()%4
<
9''
<
=
<
=
=
<
<
<
(
6
9((
6
966
+()%4
6
<
9''
<
=
<
=
=
<
<
<
(
6
9((
6
966
DDD
Fig 5.
Pin configuration for SOT109-1 (SO16)
HEF4053B_Q100
Product data sheet
6
DDD
Fig 6.
Pin configuration for SOT403-1 (TSSOP16)
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Rev. 2 — 11 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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NXP Semiconductors
Triple single-pole double-throw analog switch
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
E
6
enable input (active LOW)
VEE
7
supply voltage
VSS
8
ground supply voltage
S1, S2, S3
11, 10, 9
select input
1Y0, 2Y0, 3Y0
12, 2, 5
independent input or output
1Y1, 2Y1, 3Y1
13, 1, 3
independent input or output
1Z, 2Z, 3Z
14, 15, 4
independent output or input
VDD
16
supply voltage
7. Functional description
Table 3.
Function table [1]
Inputs
Channel on
E
Sn
L
L
nY0 to nZ
L
H
nY1 to nZ
H
X
switches OFF
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol
Parameter
VDD
supply voltage
Conditions
[1]
Min
Max
Unit
0.5
+18
V
18
+0.5
V
-
10
mA
VEE
supply voltage
referenced to VDD
IIK
input clamping current
pins Sn and E;
VI < 0.5 V or VI > VDD + 0.5 V
VI
input voltage
0.5
VDD + 0.5
V
II/O
input/output current
-
10
mA
IDD
supply current
-
50
mA
Tstg
storage temperature
65
+150
C
Tamb
ambient temperature
40
+125
C
HEF4053B_Q100
Product data sheet
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Rev. 2 — 11 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
4 of 19
HEF4053B-Q100
NXP Semiconductors
Triple single-pole double-throw analog switch
Table 4.
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol
Ptot
P
[1]
[2]
Parameter
Conditions
total power dissipation
Tamb = 40 C to +125 C
power dissipation
Min
Max
Unit
SO16 package
-
500
mW
TSSOP16 package
-
500
mW
-
100
mW
[2]
per output
To avoid drawing VDD current out of terminal Z, when switch current flows into terminals nYn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal Z, no VDD current will flow out of terminals nYn, and in this case
there is no limit for the voltage drop across the switch, but the voltages at nYn and Z may not exceed VDD or VEE.
For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
For TSSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C.
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
Conditions
see Figure 7
VDD
supply voltage
VI
input voltage
Tamb
ambient temperature
t/V
input transition rise and fall
rate
Min
Typ
Max
Unit
3
-
15
V
0
-
VDD
V
in free air
40
-
+125
C
VDD = 5 V
-
-
3.75
s/V
VDD = 10 V
-
-
0.5
s/V
VDD = 15 V
-
-
0.08
s/V
001aae646
15
VDD − VSS
(V)
10
operating area
5
0
0
Fig 7.
5
10
VDD − VEE (V)
15
Operating area as a function of the supply voltages
HEF4053B_Q100
Product data sheet
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Rev. 2 — 11 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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HEF4053B-Q100
NXP Semiconductors
Triple single-pole double-throw analog switch
10. Static characteristics
Table 6.
Static characteristics
VSS = VEE = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter
Conditions
Tamb = 40 C Tamb = 25 C
VDD
Min
VIH
VIL
HIGH-level
input voltage
LOW-level
input voltage
II
input leakage
current
IS(OFF)
OFF-state
leakage
current
IO < 1 A
CI
Max
Min
Max
Min
Max
5V
3.5
-
3.5
-
3.5
-
3.5
-
V
7.0
-
7.0
-
7.0
-
7.0
-
V
15 V
11.0
-
11.0
-
11.0
-
11.0
-
V
5V
-
1.5
-
1.5
-
1.5
-
1.5
V
10 V
-
3.0
-
3.0
-
3.0
-
3.0
V
15 V
-
4.0
-
4.0
-
4.0
-
4.0
V
15 V
-
0.1
-
0.1
-
1.0
-
1.0
A
Z port;
15 V
all channels OFF;
see Figure 8
-
-
-
1000
-
-
-
-
nA
15 V
-
-
-
200
-
-
-
-
nA
5V
-
5
-
5
-
150
-
150
A
10 V
-
10
-
10
-
300
-
300
A
15 V
-
20
-
20
-
600
-
600
A
-
-
-
-
7.5
-
-
-
-
pF
IO < 1 A
supply current IO = 0 A
input
capacitance
Min
10 V
Y port;
per channel;
see Figure 9
IDD
Max
Tamb = 85 C Tamb = 125 C Unit
Sn, E inputs
10.1 Test circuits
VDD
VDD or VSS
IS
S1 to S3
nY0
1
nZ
nY1
2
switch
E
VSS = VEE
VDD
VI
VO
001aaj900
Fig 8.
Test circuit for measuring OFF-state leakage current Z port
HEF4053B_Q100
Product data sheet
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Rev. 2 — 11 September 2014
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6 of 19
HEF4053B-Q100
NXP Semiconductors
Triple single-pole double-throw analog switch
VDD
VDD or VSS
S1 to S3
nY0
1
nZ
nY1
2
switch
IS
E
VSS = VEE
VSS
VO
VI
001aaj901
Fig 9.
Test circuit for measuring OFF-state leakage current nYn port
10.2 ON resistance
Table 7.
ON resistance
Tamb = 25 C; ISW = 200 A; VSS = VEE = 0 V.
Symbol
Parameter
Conditions
VDD  VEE
Typ
Max
Unit
RON(peak)
ON resistance (peak)
VI = 0 V to VDD  VEE;
see Figure 10 and Figure 11
5V
350
2500

10 V
80
245

15 V
60
175

5V
115
340

10 V
50
160

15 V
40
115

RON(rail)
ON resistance (rail)
VI = 0 V; see Figure 10 and Figure 11
VI = VDD  VEE;
see Figure 10 and Figure 11
RON
ON resistance mismatch
between channels
VI = 0 V to VDD  VEE; see Figure 10
5V
120
365

10 V
65
200

15 V
50
155

5V
25
-

10 V
10
-

15 V
5
-

10.2.1 ON resistance waveform and test circuit
V
VSW
VDD
VDD or VSS
S1 to S3
nY0
1
nZ
nY1
2
switch
E
VSS = VEE
VSS
ISW
VI
001aaj902
RON = VSW / ISW.
Fig 10. Test circuit for measuring RON
HEF4053B_Q100
Product data sheet
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Rev. 2 — 11 September 2014
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HEF4053B-Q100
NXP Semiconductors
Triple single-pole double-throw analog switch
DDH
521
ȍ
9'' 9
9
9
9,9
Fig 11. Typical RON as a function of input voltage
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Tamb = 25 C; VSS = VEE = 0 V; for test circuit see Figure 15.
Symbol
Parameter
tPHL
HIGH to LOW propagation delay nYn, nZ to nZ, nYn; see Figure 12
Conditions
Sn to nYn, nZ; see Figure 13
tPLH
LOW to HIGH propagation delay nYn, nZ to nZ, nYn; see Figure 12
Sn to nYn, nZ; see Figure 13
tPHZ
tPZH
tPLZ
HIGH to OFF-state
propagation delay
OFF-state to HIGH
propagation delay
LOW to OFF-state
propagation delay
HEF4053B_Q100
Product data sheet
E to nYn, nZ; see Figure 14
E to nYn, nZ; see Figure 14
E to nYn, nZ; see Figure 14
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Rev. 2 — 11 September 2014
VDD
Typ
Max
Unit
5V
10
20
ns
10 V
5
10
ns
15 V
5
10
ns
5V
200
400
ns
10 V
85
170
ns
15 V
65
130
ns
5V
15
30
ns
10 V
5
10
ns
15 V
5
10
ns
5V
275
555
ns
10 V
100
200
ns
15 V
65
130
ns
5V
200
400
ns
10 V
115
230
ns
15 V
110
220
ns
5V
260
525
ns
10 V
95
190
ns
15 V
65
130
ns
5V
200
400
ns
10 V
120
245
ns
15 V
110
215
ns
© NXP Semiconductors N.V. 2014. All rights reserved.
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HEF4053B-Q100
NXP Semiconductors
Triple single-pole double-throw analog switch
Table 8.
Dynamic characteristics …continued
Tamb = 25 C; VSS = VEE = 0 V; for test circuit see Figure 15.
Symbol
Parameter
Conditions
VDD
Typ
Max
Unit
tPZL
OFF-state to LOW
propagation delay
E to nYn, nZ; see Figure 14
5V
280
565
ns
10 V
105
205
ns
15 V
70
140
ns
11.1 Waveforms and test circuit
VDD
nYn or nZ
input
VM
VDD
Sn input
VEE
tPLH
tPLH
VO
nZ or nYn
output
VM
VSS
tPHL
tPHL
VO
90 %
nYn or nZ
output
VM
10 %
VEE
VEE
switch OFF
switch ON
001aac290
switch OFF
001aac291
Measurement points are given in Table 9.
Measurement points are given in Table 9.
Fig 12. nYn, nZ to nZ, nYn propagation delays
Fig 13. Sn to nYn, nZ propagation delays
VDD
E input
VM
VSS
tPLZ
nYn or nZ output
LOW-to-OFF
OFF-to-LOW
tPZL
VO
90 %
10 %
VEE
tPHZ
VO
tPZH
90 %
nYn or nZ output
HIGH-to-OFF
OFF-to-HIGH
10 %
VEE
switch ON
switch OFF
switch ON
001aac292
Measurement points are given in Table 9.
Fig 14. Enable and disable times
Table 9.
Measurement points
Supply voltage
Input
Output
VDD
VM
VM
5 V to 15 V
0.5VDD
0.5VDD
HEF4053B_Q100
Product data sheet
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Rev. 2 — 11 September 2014
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HEF4053B-Q100
NXP Semiconductors
Triple single-pole double-throw analog switch
tW
VI
negative
pulse
0V
90 %
VM
10 %
tf
tr
tr
tf
VI
positive
pulse
0V
VM
10 %
90 %
VM
VM
tW
VDD
VDD VI
PULSE
GENERATOR
VI
VO
RL
S1
open
DUT
RT
CL
VSS
VEE
001aaj903
Test data is given in Table 10.
Definitions:
DUT = Device Under Test.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including test jig and probe.
RL = Load resistance.
Fig 15. Test circuit for measuring switching times
Table 10.
Test data
Input
nYn, nZ
Load
Sn and E
tr, tf
VDD or VEE VDD or VSS  20 ns
[1]
S1 position
VM
CL
RL
tPHL[1]
0.5VDD
50 pF
10 k
VDD or VEE VEE
tPLH
tPZH, tPHZ tPZL, tPLZ other
VEE
VDD
VEE
For nYn to nZ or nZ to nYn propagation delays use VEE. For Sn to nYn or nZ propagation delays use VDD.
HEF4053B_Q100
Product data sheet
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Rev. 2 — 11 September 2014
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Triple single-pole double-throw analog switch
11.2 Additional dynamic parameters
Table 11. Additional dynamic characteristics
VSS = VEE = 0 V; Tamb = 25 C.
Symbol
Parameter
THD
Conditions
total harmonic distortion
3 dB frequency response
f(3dB)
VDD
Typ
Max
Unit
see Figure 16; RL = 10 k; CL = 15 pF; 5 V
channel ON; VI = 0.5VDD (p-p);
10 V
fi = 1 kHz
15 V
[1]
0.25
-
%
[1]
0.04
-
%
[1]
0.04
-
%
see Figure 17; RL = 1 k; CL = 5 pF;
channel ON; VI = 0.5VDD (p-p)
5V
[1]
13
-
MHz
10 V
[1]
40
-
MHz
70
-
50
15 V
[1]
iso
isolation (OFF-state)
see Figure 18; fi = 1 MHz; RL = 1 k;
CL = 5 pF; channel OFF;
VI = 0.5VDD (p-p)
10 V
[1]
Vct
crosstalk voltage
digital inputs to switch; see Figure 19;
RL = 10 k; CL = 15 pF;
E or Sn = VDD (square-wave)
10 V
Xtalk
crosstalk
between switches; see Figure 20;
fi = 1 MHz; RL = 1 k;
VI = 0.5VDD (p-p)
10 V
[1]
50
[1]
MHz
-
dB
-
mV
50
-
dB
fi is biased at 0.5 VDD; VI = 0.5VDD (p-p).
Table 12. Dynamic power dissipation PD
PD can be calculated from the formulas shown; VEE = VSS = 0 V; tr = tf  20 ns; Tamb = 25 C.
Symbol
Parameter
dynamic power
dissipation
PD
VDD
Typical formula for PD (W)
where:
5V
PD = 2500  fi + (fo  CL)  VDD
10 V
PD = 11500  fi + (fo  CL) 
15 V
PD = 29000  fi + (fo  CL)  VDD2
2
fi = input frequency in MHz;
VDD2
fo = output frequency in MHz;
CL = output load capacitance in pF;
VDD = supply voltage in V;
(CL  fo) = sum of the outputs.
11.2.1 Test circuits
VDD
VDD or VSS
VDD
S1 to S3
nY0
1
nZ
nY1
2
VDD or VSS
switch
S1 to S3
nY0
1
nZ
nY1
2
E
E
VSS = VEE
VSS
RL
CL
D
RL
CL
dB
fi
001aaj904
Fig 16. Test circuit for measuring total harmonic
distortion
Product data sheet
VSS = VEE
VSS
fi
HEF4053B_Q100
switch
001aaj905
Fig 17. Test circuit for measuring frequency response
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Rev. 2 — 11 September 2014
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11 of 19
HEF4053B-Q100
NXP Semiconductors
Triple single-pole double-throw analog switch
VDD
VDD or VSS
S1 to S3
nY0
1
nZ
nY1
2
switch
E
VSS = VEE
VSS
RL
CL
dB
fi
001aaj906
Fig 18. Test circuit for measuring isolation (OFF-state)
9''
9''
5/
9''
6WR6
Q<
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5/
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966 9((
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9
92
DDM
a. Test circuit
ORJLF
LQSXW6Q(
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RQ
RII
92
9FW
DDM
b. Input and output pulse definitions
Fig 19. Test circuit for measuring crosstalk voltage between digital inputs and switch
HEF4053B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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HEF4053B-Q100
NXP Semiconductors
Triple single-pole double-throw analog switch
VDD
VDD
VDD or VSS
S1 to S3
nY0
nZ
nY1
VDD or VSS
S1 to S3
nY0
nZ
nY1
E
E
VSS = VEE
VSS
RL
VO
RL
VSS = VEE
VSS
VI
RL
VI
VO
001aaj909
a. Switch closed condition
RL
001aaj910
b. Switch open condition
Fig 20. Test circuit for measuring crosstalk between switches
HEF4053B_Q100
Product data sheet
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Rev. 2 — 11 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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HEF4053B-Q100
NXP Semiconductors
Triple single-pole double-throw analog switch
12. Package outline
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Fig 21. Package outline SOT109-1 (SO16)
HEF4053B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
14 of 19
HEF4053B-Q100
NXP Semiconductors
Triple single-pole double-throw analog switch
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Fig 22. Package outline SOT403-1 (TSSOP16)
HEF4053B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
15 of 19
HEF4053B-Q100
NXP Semiconductors
Triple single-pole double-throw analog switch
13. Abbreviations
Table 13.
Abbreviations
Acronym
Description
HBM
Human Body Model
ESD
ElectroStatic Discharge
MM
Machine Model
MIL
Military
14. Revision history
Table 14.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
HEF4053B_Q100 v.2
20140911
Product data sheet
-
HEF4053B_Q100 v.1
-
-
Modifications:
HEF4053B_Q100 v.1
HEF4053B_Q100
Product data sheet
•
Figure 19: Test circuit modified
20130222
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
16 of 19
HEF4053B-Q100
NXP Semiconductors
Triple single-pole double-throw analog switch
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
HEF4053B_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
17 of 19
HEF4053B-Q100
NXP Semiconductors
Triple single-pole double-throw analog switch
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
HEF4053B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
18 of 19
NXP Semiconductors
HEF4053B-Q100
Triple single-pole double-throw analog switch
17. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
10.1
10.2
10.2.1
11
11.1
11.2
11.2.1
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ON resistance waveform and test circuit . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms and test circuit . . . . . . . . . . . . . . . . 9
Additional dynamic parameters . . . . . . . . . . . 11
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 September 2014
Document identifier: HEF4053B_Q100