A1356 Datasheet

A1356
High Precision Linear Hall-Effect Sensor IC
With an Open Drain Pulse Width Modulated Output
Features and Benefits
Description
▪ Simultaneous programming of PWM carrier frequency,
quiescent duty cycle, and sensitivity; for system
optimization
▪ Factory programmed sensitivity temperature coefficient
and quiescent duty cycle drift
▪ Programmability at end-of-line
▪ Pulse width modulated (PWM) output provides increased
noise immunity compared to an analog output
▪ Precise recoverability after temperature cycling
• Output duty cycle clamps provide short circuit diagnostic
capabilities
▪ Optional 50% duty cycle calibration test mode at device
power up
▪ Wide ambient temperature range: –40°C to 150°C
▪ Resistant to mechanical stress
▪ Advanced chopper stabilization circuits and differential
signal path design lead to very low output offset levels
▪ Proprietary on-chip filters provide high output resolution
▪ Wide power supply operating range: 4.5 to 18 V
The A1356 device is a high precision, programmable open
drain Hall-effect linear sensor IC with a pulse width modulated
(PWM) output. The duty cycle (D) of the PWM output signal
is proportional to an applied magnetic field. The A1356 device
converts an analog signal from its internal Hall element to
a digitally encoded PWM output signal. The coupled noise
immunity of the digitally encoded PWM output is far superior
to the noise immunity of an analog output signal.
The BiCMOS, monolithic circuit inside of the A1356 integrates
a Hall element, precision temperature-compensating circuitry
to reduce the intrinsic sensitivity and offset drift of the Hall
element, a small-signal high-gain amplifier, proprietary
dynamic offset cancellation circuits, and PWM conversion
circuitry. The dynamic offset cancellation circuits reduce
the residual offset voltage of the Hall element. Hall element
offset is normally caused by device overmolding, temperature
dependencies, and thermal stress. The high frequency offset
cancellation (chopping) clock allows for a greater sampling
rate, which increases the accuracy of the output signal and
results in faster signal processing capability.
Package: 3-pin SIP (suffix KB)
The A1356 sensor is provided in a lead (Pb) free 3-pin single
inline package (KB suffix), with 100% matte tin leadframe
plating.
Not to scale
Functional Block Diagram
PWM Carrier
Generation
VCC/
Programming
Regulator
PWM
Frequency Trim
1
2
2
1
Chopper
Switches
Amp
Signal
Recovery
Sensitivity
Trim
Signal
Conditioning
Temperature
Compensation
% Duty
Cycle
PWMOUT
% Duty Cycle
Temperature
Coefficient
GND
A1356-DS
High Precision Linear Hall-Effect Sensor IC
With an Open Drain Pulse Width Modulated Output
A1356
Selection Guide
Part Number
Packing*
A1356LKB-T
500 pieces per bag
A1356LKBTN-T
4000 pieces per 13-in. reel
*Contact Allegro™ for additional packing options
Absolute Maximum Ratings
Characteristic
Symbol
Notes
Rating
Unit
Supply Voltage
VCC
28
V
Reverse Supply Voltage
VRCC
–18
V
Output Voltage
VOUT
24
V
Reverse Output Voltage
VROUT
–0.5
V
25
mA
Output Current
IOUTSINK
Reverse Output Current
IOUT
Operating Ambient Temperature
TA
Maximum Junction Temperature
TJ(max)
Storage Temperature
Tstg
Internal current limiting is intended to protect
the device from output short circuits, but is not
intended for continuous operation
VOUT > –0.5 V, TA = 25°C
–50
mA
L temperature range
–40 to 150
ºC
165
ºC
VCC = 0 V
–65 to 170
ºC
Pin-out Diagram
Terminal List Table
Number
1
2
Name
Function
1
VCC
Input power supply; use bypass capacitor to connect to ground; also
used for programming
2
GND
Ground
3
PWMOUT
Open drain pulse width modulated output signal
3
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
High Precision Linear Hall-Effect Sensor IC
With an Open Drain Pulse Width Modulated Output
A1356
OPERATING CHARACTERISTICS Valid over full operating temperature range, TA , VCC = 4.5 to 18 V, CBYPASS = 0.1 μF, unless
otherwise noted
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Electrical Characteristics
Supply Voltage
VCC
4.5
–
18
V
Supply Current
ICC
–
6
10
mA
Supply Zener Clamp Voltage
ICC = 18 mA, TA = 25ºC, t < 5 min
28
–
–
V
Power On Time1,2,3
tPO
fpwm = 2 kHz
–
–
4
ms
Internal Bandwidth
BWi
Small signal –3 dB, 100 G(P-P) magnetic input
signal
–
400
–
Hz
TA = 25°C
–
200
–
kHz
IOUTSINK ≤ 20 mA, PWMOUT transistor on
–
–
0.6
V
Chopping Frequency4
VZsupply
fC
Output Characteristics
PWMOUT Saturation Voltage
VSAT
IOUTSINK ≤ 10 mA, PWMOUT transistor on
–
–
0.5
V
PWMOUT Current Limit
ILIMIT
RL = 0 Ω
30
60
80
mA
PWMOUT Leakage Current
ILEAK
VCC = 3.2 V, 0 V ≤ PWMOUT ≤ 24 V, PWMOUT
transistor off
–
0.1
10
μA
PWMOUT Zener Clamp Voltage
VZOUT
IOUTSINK = ILIMIT , TA = 25ºC
28
–
–
V
tr
R = 2 kΩ, C = 20 pF
–
3
–
μs
tf
R= 2 kΩ, C = 20 pF
–
3
–
μs
1.5
–
ms
2
ms
PWMOUT Rise
Time2,3
PWMOUT Fall Time2,3
Maximum Propagation
Delay2,3
Response Time2,3
(External)3
tpd(max)
tRESPONSE
–
Impulse magnetic field of 300 G, fpwm = 2 kHz
–
–
RL
PWMOUT to VCC
2040
–
–
Ω
Load Capacitance (External)3
CL
PWMOUT to GND
–
–
10
nF
Duty Cycle Jitter2,3,5
JD
Measured over 1000 output PWM clock periods,
3 sigma values, Sens = 60 m% / G
–
–
±0.090
%D
DCLP(HIGH)
90
–
95
%D
DCLP(LOW)
5
–
10
%D
Load Resistance
Clamp Duty Cycle3
Pre-Programming Target6
Pre-Programming Quiescent Duty Cycle
Output
D(Q)PRE
B = 0 G, TA = 25°C
–
52
–
%D
Pre-Programming Sensitivity
SensPRE
TA = 25°C
–
20
–
(m% D)/G
Pre-Programming PWM Output Carrier
Frequency
fPWMPRE
TA = 25°C
–
2.8
–
kHz
Initial Quiescent Duty Cycle Output
D(Q)init
TA = 25°C
–
D(Q)PRE
–
%D
Guaranteed Quiescent Duty Cycle
Output Range7
D(Q)
TA = 25°C
40
–
60
%D
–
9
–
bit
Quiescent Duty Cycle Programming
Quiescent Duty Cycle Output
Programming Bits
Average Quiescent Duty Cycle Output
Step Size8,9
StepD(Q)
TA = 25°C
0.085
0.100
0.115
%D
Quiescent Duty Cycle Output
Programming Resolution10
ErrPGD(Q)
TA = 25°C
–
StepD(Q)
× ±0. 5
–
%D
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
High Precision Linear Hall-Effect Sensor IC
With an Open Drain Pulse Width Modulated Output
A1356
OPERATING CHARACTERISTICS (continued) Valid over full operating temperature range, TA , VCC = 4.5 to 18 V,
CBYPASS = 0.1 μF, unless otherwise noted
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Sensitivity Programming
Initial Sensitivity
Guaranteed Sensitivity Range
Sensinit
TA = 25°C
–
SensPRE
–
(% D)/G
SensLOW
TA = 25°C
45
–
75
(m% D)/G
Sensitivity Programming Bits
Average Sensitivity Step Size8,9
StepSENS(low) TA = 25°C
Sensitivity Programming Resolution10
ErrPGSENS
TA = 25°C
–
8
–
bit
150
300
450
(μ% D)/G
–
(μ% D)/G
–
StepSENS
× ±0. 5
Carrier Frequency Programming
Initial Carrier Frequency
Carrier Frequency Programming Range
fPWMinit
TA = 25°C
–
fPWMPRE
–
Hz
fPWM
TA = 25°C
1.8
2
2.2
kHz
–
4
–
bit
114
140
Hz
–
Hz
Carrier Frequency Programming Bits
Average Carrier Frequency Step
Size8,9
Carrier Frequency Programming
Resolution10
StepfPWM
ErrPGfPWM
TA = 25°C
90
TA = 25°C
–
StepfPWM
× ±0. 5
Calibration Test Mode
Calibration Test Mode Duration3
tCAL
fPWM = 2 kHz
45
50
55
ms
Output Duty Cycle During Calibration
Mode3
DCAL
TA = 25°C
49
50
51
%D
–
1
–
bit
Lock Bit Programming
Overall Programming Lock Bit
LOCK
Factory Programmed Sensitivity Temperature Coefficient And Drift Characteristics
Sensitivity Temperature Coefficient11
SensTC
TA = 150°C
–
0.03
–
%/°C
Sensitivity Drift Through Temperature
Range12
ΔSensTC
TA = 150°C
–
< ±3
–
%
Sensitivity Drift Due to Package
Hysteresis2
ΔSensPKG TA = 150°C, after temperature cycling
–
< ±1
–
%
TA = 150°C
–
0
–
(% D)/°C
Sens = SensPRE, TA = 150°C
–
< ±0.35
–
%D
Factory Programmed Duty Cycle Drift
Duty Cycle Temperature Coefficient11
Quiescent Duty Cycle Drift Through
Temperature Range
DTC
ΔD(Q)
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
High Precision Linear Hall-Effect Sensor IC
With an Open Drain Pulse Width Modulated Output
A1356
OPERATING CHARACTERISTICS (continued) Valid over full operating temperature range, TA , VCC = 4.5 to 18 V,
CBYPASS = 0.1 μF, unless otherwise noted
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
LinERR
–
–
±3.0
%
SymERR
–
–
±1.5
%
Error Components
Linearity Sensitivity Error2,3
Symmetry Sensitivity Error2,3
1After
powering on the device, output of device needs time to reach valid magnetic response with a valid PWM output.
Characteristic Definitions section.
3Guarenteed by design only. Characterized but not tested in production.
4f varies up to approximately ± 20% over the full operating ambient temperature range, T , and process.
C
A
5Jitter is dependent on the sensitivity of the device.
6Raw device characteristic values before any programming.
7D (max) is the value available with all programming fuses blown (maximum programming code set). The D
(Q)
(Q) range is the total range from D(Q)(min)
up to and including D(Q)(max). See Characteristic Definitions section.
8Step size is larger than required, in order to provide for manufacturing spread. See Characteristic Definitions section.
9Non-ideal behavior in the programming DAC can cause the step size at each significant bit rollover code to be greater than twice the maximum
specified value of StepD(Q) , StepSENS , or StepfPWM .
10Overall programming value accuracy. See Characteristic Definitions section.
11Programmed at 150°C and calculated relative to 25°C.
12Sensitivity drift from expected value at T after programming SENS . See Characteristic Definitions section.
A
TC
2See
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
High Precision Linear Hall-Effect Sensor IC
With an Open Drain Pulse Width Modulated Output
A1356
Characteristic Performance
Average Supply Current versus Temperature
Average Supply Current versus Supply Voltage
10.0
10.0
9.0
9.0
8.0
8.0
7.0
VCC (V)
6.0
4.5
5.0
12
24
4.0
ICC(AV) (mA)
ICC(AV) (mA)
7.0
3.0
2.0
1.0
1.0
0
20
40
60
25
150
4.0
2.0
-60 -40 -20
-40
5.0
3.0
0
TA (°C)
6.0
0
80 100 120 140 160
4
9
14
19
24
TA (°C)
VCC (V)
Average PWMOut Saturation Voltage versus Temperature
Isink = 10 mA
Average PWMOut Saturation Voltage versus Supply Voltage
Isink = 10 mA
0.30
0.30
0.25
0.25
VCC (V)
4.5
0.15
12
18
0.20
VSAT (V)
VSAT (V)
0.20
0.10
0.05
0.05
0
20
40 60
TA (°C)
4
80 100 120 140 160
0.30
0.25
0.25
VCC (V)
4.5
0.15
12
18
0.05
0.05
60
TA (°C)
80 100 120 140 160
TA (°C)
-40
0.10
40
24
0.15
0.10
20
19
0.20
VSAT (V)
0.20
0
14
Average PWMOut Saturation Voltage versus Supply Voltage
Isink = 20 mA
0.30
-60 -40 -20
9
VCC v(V)
Average PWMOut Saturation Voltage versus Temperature
Isink = 20 mA
VSAT (V)
25
150
0
-60 -40 -20
0
-40
0.15
0.10
0
TA (°C)
25
150
0
4
9
14
19
24
VCC (V)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
High Precision Linear Hall-Effect Sensor IC
With an Open Drain Pulse Width Modulated Output
A1356
Average Pre-Programming QDC Output versus Temperature
Average Pre-Programming Sensitivity versus Temperature
60
24
58
22
56
Sens (m%D/G)
D(Q) (%)
54
52
50
48
46
20
18
16
14
44
12
42
10
40
-50
0
50
100
150
-50
200
0
50
150
200
Pre-Programming Clamp Duty Cycle versus Temperature
Average Pre-Programming PWM Output Carrier Frequency
versus Temperature
3.00
100
2.95
90
DCLP(HIGH)
80
2.90
70
2.85
DCLP(D%)
fPWMPRE (kHz)
100
TA (°C)
TA (°C)
2.80
2.75
60
50
40
30
2.70
20
2.65
DCLP(LOW)
10
2.60
0
-50
0
50
100
TA (°C)
150
200
-50
0
50
100
150
200
TA (°C)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
High Precision Linear Hall-Effect Sensor IC
With an Open Drain Pulse Width Modulated Output
A1356
Characteristic Definitions
Power-On Time When the supply is ramped to its operating
voltage, the device requires a finite time to power its internal
components before supplying a valid PWM output duty-cycle.
Power-On Time, tPO, is defined as the time it takes for the output
voltage to settle within ±10% of its steady state value after the
power supply has reached its minimum specified operating voltage, VCC(min). (See figure 1.)
Propagation Delay Traveling time of signal from input Hall
plate to output stage of device. (See figure 2.)
Response Time The time interval between a) when the applied
magnetic field reaches 90% of its final value, and b) when the
sensor IC reaches 90% of its output corresponding to the applied
magnetic field. (See figure 2.)
Average Quiescent Duty Cycle Output Step Size The
average quiescent duty cycle output step size for a single device
is determined using the following calculation:
StepD(Q) =
D(Q)(max) – D(Q)(min)
,
2n –1
where:
n is the number of available programming bits in the trim range,
2n–1 is the value of programming steps in the range,
D(Q)(max) is the maximum reached quiescent duty cycle, and
D(Q)(min) is minimum reached quiescent duty cycle.
PWM Rise Time The time elapsed between 10% and 90% of
the rising signal value when output switches from low to high
states.
0.5 ms
Applied Magnetic
Field, B
PWM Fall Time The time elapsed between 90% and 10% of the
falling signal value when output switches from high to low states.
Time
Quiescent Duty Cycle In the quiescent state (no significant
magnetic field: B = 0 G), the output duty cycle, D(Q), equals a
specific programmed duty cycle throughout the entire operating
ranges of VCC and ambient temperature, TA.
Guaranteed Quiescent Duty Cycle Output Range The
Quiescent Duty Cycle Output, D(Q), can be programmed around
its nominal value of 50% D, within the Guaranteed Quiescent
Duty Cycle Range limits: D(Q)(min) and D(Q)(max). The available
guaranteed programming range for D(Q) falls within the distributions of the minimum and the maximum programming code for
setting D(Q). (See figure 3.)
V+
(1)
Output
Propagation
Delay
Response
Time
Figure 2. Definitions of Propagation Delay and Response Time
VCC
Guaranteed D(Q)
Programming
Range
A1356
Output
VCC(min)
First valid duty cycle
tPO
Time
Min Code D(Q)
Distribution
D(Q)(min)
Figure 1. Definition of Power-On Time
Max Code D(Q)
Distribution
Initial D(Q)
Distribution
D(Q)(max)
Figure 3. Definition of Guaranteed Quiescent Voltage Output Range
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
High Precision Linear Hall-Effect Sensor IC
With an Open Drain Pulse Width Modulated Output
A1356
Quiescent Duty Cycle Output Programming Resolution
The programming resolution for any device is half of its programming step size. Therefore, the typical programming resolution will be:
ErrPGD(Q)(typ) = 0.5 × StepD(Q)(typ)
.
(2)
Quiescent Duty Cycle Output Drift through Temperature Range Due to internal component tolerances and thermal
considerations, the quiescent Duty Cycle Temperature Coefficient, DTC(Q), may drift from its nominal value over the operating ambient temperature, TA. For purposes of specification, the
Quiescent Duty Cycle Output Drift Through Temperature Range,
∆D(Q) (% D), is defined as:
∆D(Q) = D(Q)(TA) – D(Q)(25°C)
,
(3)
where D(Q)(TA) is the quiescent duty cycle measured at TA and is
D(Q)(25°C) quiescent duty cycle measured at 25°C.
Sensitivity The presence of a south polarity magnetic field,
perpendicular to the branded surface of the package face,
increases the output duty cycle from its quiescent value toward
the maximum duty cycle limit. The amount of the output duty
cycle increase is proportional to the magnitude of the magnetic
field applied. Conversely, the application of a north polarity
field decreases the output duty cycle from its quiescent value.
This proportionality is specified as the magnetic sensitivity,
Sens ((% D)/G), of the device, and it is defined for bipolar
devices as:
D(BPOS) – D(BNEG)
Sens =
,
(4)
BPOS – BNEG
and for unipolar devices as:
D(BPOS) – D(Q)
Sens =
BPOS
,
(5)
where BPOS and BNEG are two magnetic fields with opposite
polarities.
Guaranteed Sensitivity Range The magnetic sensitivity,
Sens, can be programmed around its nominal value within the
sensitivity range limits: Sens(min) and Sens(max). Refer to the
Guaranteed Quiescent Duty Cycle Output Range section for a
conceptual explanation of how value distributions and ranges are
related.
Average Sensitivity Step Size Refer to the Average Quiescent Duty Cycle Output Step Size section for a conceptual
explanation.
Sensitivity Programming Resolution Refer to the Quiescent Duty Cycle Output Programming Resolution section for a
conceptual explanation.
Carrier Frequency Target The PWM output signal Carrier
Frequency Programming Range, fPWM, can be programmed to its
nominal value of 2 kHz.
Average Carrier Frequency Step Size Refer to the Average
Quiescent Duty Cycle Output Step Size section for a conceptual
explanation.
Carrier Frequency Programming Resolution Refer to the
Quiescent Duty Cycle Output Programming Resolution section
for a conceptual explanation.
Sensitivity Temperature Coefficient Device sensitivity
changes as temperature changes, with respect to its programmed
sensitivity temperature coefficient, SENSTC. SENSTC is programmed at 150°C, and calculated relative to the nominal
sensitivity programming temperature of 25°C. SENSTC (%/°C) is
defined as:
 1 
SensT2 – SensT1

SensTC = 
100% 
×
SensT1
 T2–T1

,
(6)
where T1 is the nominal Sens programming temperature of
25°C, and T2 is the programming temperature of 150°C. The
expected value of Sens over the full ambient temperature range,
SensEXPECTED(TA), is defined as:
SensEXPECTED(TA) =
SensT1× [100% +SensTC (TA –T1)]
100 %
.
(7)
SensEXPECTED (TA) should be calculated using the actual measured
values of SensT1 and SENSTC rather than programming target
values.
Sensitivity Drift Through Temperature Range Second order sensitivity temperature coefficient effects cause the
magnetic sensitivity, Sens, to drift from its expected value over
the operating ambient temperature range, TA. For purposes of
specification, the Sensitivity Drift Through Temperature Range,
∆SensTC , is defined as:
∆SensTC =
SensTA – SensEXPECTED(TA)
SensEXPECTED(TA)
× 100% .
(8)
Sensitivity Drift Due to Package Hysteresis Package
stress and relaxation can cause the device sensitivity at TA = 25°C
to change during and after temperature cycling.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
High Precision Linear Hall-Effect Sensor IC
With an Open Drain Pulse Width Modulated Output
A1356
For purposes of specification, the Sensitivity Drift Due to Package Hysteresis, ∆SensPKG, is defined as:
∆SensPKG =
Sens(25°C)2 – Sens(25°C)1
× 100%
Sens(25°C)1
,
(9)
where Sens(25°C)1 is the programmed value of sensitivity at TA =
25°C, and Sens(25°C)2 is the value of sensitivity at TA = 25°C,
after temperature cycling TA up to 150°C, down to –40°C, and
back to up 25°C.
Linearity Sensitivity Error The A1356 is designed to provide
a linear output in response to a ramping applied magnetic field.
Consider two magnetic fields, B1 and B2. Ideally, the sensitivity
of a device is the same for both fields, for a given supply voltage
and temperature. Linearity error is present when there is a difference between the sensitivities measured at B1 and B2.
Linearity Error is calculated separately for the positive
(LinERRPOS) and negative (LinERRNEG ) applied magnetic fields.
Linearity error (%) is measured and defined as:
 SensBPOS2 
 × 100%
LinERRPOS = 1–
 SensBPOS1 
,
 SensBNEG2
 × 100%
LinERRNEG = 1–
 SensBNEG1
,
(10)
where:
2 × BPOS1 and BNEG2 = 2 × BNEG1.
Then:
LinERR = max( LinERRPOS , LinERRNEG)
.
(11)
and BPOSx and BNEGx are positive and negative magnetic fields,
with respect to the quiescent duty cycle output such that BPOS2 =
(12)
Note that unipolar devices only have positive linearity error
(LINERRPOS).
Symmetry Sensitivity Error The magnetic sensitivity of
A1356 device is constant for any two applied magnetic fields
of equal magnitude and opposite polarities. Symmetry error,
SymERR (%), is measured and defined as:
 SensBPOS 
 × 100% ,
SymERR = 1–
(13)
 SensBNEG 
where SensBx is as defined in equation 11, and BPOS and BNEG
are positive and negative magnetic fields such that |BPOS| =
|BNEG|. Note that the symmetry error specification is only valid
for bipolar devices.
Jitter The duty cycle of the PWM output may vary slightly over
time despite the presence of a constant applied magnetic field and
a constant carrier frequency for the PWM signal. This phenomenon is known as jitter, and is defined as:
JDC = ±
|D(Bx) – D(Q)|
SensBx =
Bx
.
DB(max) – DB(min)
2
,
(14)
where DB(max) and DB(min) are the maximum and minimum
duty cycles at a constant applied magnetic field, B, measured
over 1000 PWM clock periods with a constant applied magnetic
field. JD is given in % D.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
High Precision Linear Hall-Effect Sensor IC
With an Open Drain Pulse Width Modulated Output
A1356
Typical Application Drawing
V+
1
VCC
A1356
PWMOUT
CBYPASS
0.1 μF
RPU
3
CL
GND
2
Chopper Stabilization Technique
When using Hall-effect technology, a limiting factor for
switchpoint accuracy is the small signal voltage developed across
the Hall element. This voltage is disproportionally small relative
to the offset that can be produced at the output of the Hall sensor IC. This makes it difficult to process the signal while maintaining an accurate, reliable output over the specified operating
temperature and voltage ranges. Chopper stabilization is a unique
approach used to minimize Hall offset on the chip. Allegro
employs a patented technique to remove key sources of the output drift induced by thermal and mechanical stresses. This offset
reduction technique is based on a signal modulation-demodulation process. The undesired offset signal is separated from the
magnetic field-induced signal in the frequency domain, through
modulation. The subsequent demodulation acts as a modulation
process for the offset, causing the magnetic field-induced signal
to recover its original spectrum at base band, while the DC offset
becomes a high-frequency signal. The magnetic-sourced signal
then can pass through a low-pass filter, while the modulated DC
offset is suppressed. In addition to the removal of the thermal and
stress related offset, this novel technique also reduces the amount
of thermal noise in the Hall sensor IC while completely removing
the modulated residue resulting from the chopper operation. The
chopper stabilization technique uses a high-frequency sampling
clock. For the demodulation process, a sample-and-hold technique is used. This high-frequency operation allows a greater
sampling rate, which results in higher accuracy and faster signalprocessing capability. This approach desensitizes the chip to the
effects of thermal and mechanical stresses, and produces devices
that have extremely stable quiescent Hall output voltages and
precise recoverability after temperature cycling. This technique
is made possible through the use of a BiCMOS process, which
allows the use of low-offset, low-noise amplifiers in combination
with high-density logic integration and sample-and-hold circuits.
Regulator
Clock/Logic
Hall Element
Amp
Anti-Aliasing
LP Filter
Tuned
Filter
Chopper Stabilization Technique
Allegro MicroSystems, LLC
115 Northeast Cutoff
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11
High Precision Linear Hall-Effect Sensor IC
With an Open Drain Pulse Width Modulated Output
A1356
Programming Guidelines
Overview
Programming is accomplished by sending a series of input voltage pulses serially through the VCC pin of the device. A unique
combination of different voltage level pulses controls the internal
programming logic of the device to select a desired programmable parameter and change its value. There are three voltage levels
that must be taken into account when programming. These levels
are referred to as high, VP(HIGH) , mid, VP(MID) , and low, VP(LOW).
Definition of Terms
Register The section of the programming logic that controls the
choice of programmable modes and parameters.
The 1356 features Try mode, Blow mode and Lock mode:
Key A series of mid-level voltage pulses used to select a register,
with a value expressed as the decimal equivalent of the binary
value. The LSB of a register is denoted as key 1, or bit 0.
• In Try mode, the value of multiple programmable parameters
may be set and measured simultaneously. The parameter values
are stored temporarily, and reset after cycling the supply voltage.
Bit Field The internal fuses unique to each register, represented
as a binary number. Changing the bit field settings of a particular
register causes its programmable parameter to change, based on
the internal programming logic.
Code The number used to identify the combination of fuses
activated in a bit field, expressed as the decimal equivalent of the
binary value. The LSB of a bit field is denoted as code 1, or bit 0.
• In Blow mode, the value of a single programmable parameter
may be set and measured, and then permanently set by blowing
solid-state fuses internal to the device. Additional parameters
may be blown sequentially. This mode also is used for blowing the device-level fuse (when Lock mode is enabled), which
permanently blocks the further programming of all parameters.
Addressing Increasing the bit field code of a selected register
by serially applying a pulse train through the VCC pin of the
device. Each parameter can be measured during the addressing
process, but the internal fuses must be blown before the programming code (and parameter value) becomes permanent.
• Lock mode prevents all future programming of the device. This
is accomplished by blowing a special fuse using Blow mode.
Fuse Blowing Applying a high voltage pulse of sufficient
duration to permanently set an addressed bit by blowing a fuse
internal to the device. After a bit (fuse) has been blown, it cannot
be reset.
The programming sequence is designed to help prevent the
device from being programmed accidentally; for example, as a
result of noise on the supply line. Although any programmable
variable power supply can be used to generate the pulse waveforms, Allegro highly recommends using the Allegro Sensor
Evaluation Kit, available on the Allegro website On-line Store.
The manual for that kit is available for download free of charge,
and provides additional information on programming these
devices.
Blow Pulse A high voltage pulse of sufficient duration to blow
the addressed fuse.
Cycling the Supply Powering-down, and then powering-up the
supply voltage. Cycling the supply is used to clear the programming settings in Try mode.
Programming Pulse Requirements, Protocol at TA = 25 °C
Characteristic
Programming
Voltage
Symbol
Notes
VP(LOW)
VP(MID)
Measured at the VCC pin.
VP(HIGH)
Programming
Current
IP
tLOW
Pulse Width
Minimum supply current required to ensure proper fuse blowing. In addition, a
minimum capacitance, CBLOW = 0.1 μF, must be connected between the supply and
GND pins during programming to provide the current necessary for fuse blowing.
The blowing capacitor should be removed and the load capacitance used for properly
programming duty cycle measurements.
Min.
Typ.
Max.
Unit
–
5
5.5
V
13
15
16
V
26
27
28
V
300
–
–
mA
Duration of VP(LOW) for separating VP(MID) and VP(HIGH) pulses.
40
–
–
μs
tACTIVE
Duration of VP(MID) and VP(HIGH) pulses for register selection or bit field addressing.
40
–
–
μs
tBLOW
Duration of VP(HIGH) pulses for fuse blowing.
40
–
–
μs
Pulse Rise Time
tPr
Rise time required for transitions from VP(LOW) to either VP(MID) or VP(HIGH).
5
–
100
μs
Pulse Fall Time
tPf
Fall time required for transitions from VP(HIGH) to either VP(MID) or VP(LOW).
5
–
100
μs
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115 Northeast Cutoff
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12
High Precision Linear Hall-Effect Sensor IC
With an Open Drain Pulse Width Modulated Output
A1356
Programming Procedures
• Register Mode 2:
Try mode
And there are four registers that select among the four programmable parameters:
• Register 1:
Sensitivity, Sens
• Register 2:
Quiescent duty cycle output, D(Q)
• Register 3:
Pulse width modulated carrier frequency , fPWM
• Register 5:
Lock (device locking)
Fuse Blowing
After the required code is found for a given parameter, its value
can be set permanently by blowing individual fuses in the appropriate register bit field. Blowing is accomplished by applying a
VP(HIGH) pulse, called a blow pulse, of sufficient duration at the
VP(HIGH) level to permanently set an addressed bit by blowing a
fuse internal to the device. Due to power requirements, the fuse
for each bit in the bit field must be blown individually. To accomplish this, the code representing the required parameter value
must be translated to a binary number. For example, as shown
in figure 6, decimal code 5 is equivalent to the binary number
101. Therefore bit 2 (code 4) must be addressed and blown, the
device power supply cycled, and then bit 0 (code 1) addressed
V+
V+
VP(HIGH)
VP(HIGH)
VP(MID)
VP(MID)
Code 2n – 1
Blow and Lock modes
Code 2n – 2
• Register Mode 1:
When addressing the bit field, the number of VP(MID) pulses
is represented by a decimal number called a code. Addressing
activates the corresponding fuse locations in the given bit field
by increasing the binary value of an internal DAC. The value of
the bit field (and code) increases by one with the falling edge
of each VP(MID) pulse, up to the maximum possible code (see
the Programming Logic table). As the value of the bit field code
increases, the value of the programmable parameter changes.
Measurements can be taken after each pulse to determine if the
required result for the programmable parameter has been reached.
Cycling the supply voltage resets all the locations in the bit field
that have unblown fuses to their initial states.
Code 2
The A1356 has two registers that select among the three programmable modes:
Bit Field Addressing
After a programmable parameter has been selected, a VP(HIGH)
pulse transitions the programming logic into the bit field addressing state. Applying a series of VP(MID) pulses to the VCC pin of
the device, as shown in figure 5, increments the bit field of the
selected parameter.
Code 1
Mode and Parameter Selection
Each programmable mode and parameter can be accessed through
specific registers. To select a register, a sequence of voltage
pulses consisting of a VP(HIGH) pulse, a series of VP(MID) pulses,
and a VP(HIGH) pulse (with no VCC supply interruptions) must be
applied serially to the supply pin. The quantity of VP(MID) pulses
is called the key, and uniquely identifies each register. The pulse
train used for selection of the first register, key 1, is shown in
figure 4.
VP(LOW)
VP(LOW)
tLOW
0
tACTIVE
Figure 4. Parameter selection pulse train. This shows the sequence for
selecting the register corresponding to key 1, indicated by a single VP(MID)
pulse.
0
Figure 5. Bit field addressing pulse train. Addressing the bit field by
increasing the code causes the programmable parameter value to change.
The number of bits available for a given programming code, n, varies
among parameters; for example, the bit field for D(Q) has 8 bits available,
which allows 255 separate codes to be used.
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115 Northeast Cutoff
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13
High Precision Linear Hall-Effect Sensor IC
With an Open Drain Pulse Width Modulated Output
A1356
and blown. An appropriate sequence for blowing code 5 is shown
in figure 7. The order of blowing bits, however, is not important.
Blowing bit 0 first, and then bit 2 is acceptable.
• A 0.1 μF blowing capacitor, CBLOW , must be mounted between
the supply pin and the GND pin during programming, to ensure
enough current is available to blow fuses.
Note: After blowing, the programming is not reversible, even
after cycling the supply power. Although a register bit field fuse
cannot be reset after it is blown, additional bits within the same
register can be blown at any time until the device is locked. For
example, if bit 1 (binary 10) has been blown, it is still possible to
blow bit 0. The end result would be binary 11 (decimal code 3).
• The application capacitance, CL , should be used when measuring the output duty cycle during programming.
Locking the Device
After the desired code for each parameter is programmed, the
device can be locked to prevent further programming of any
parameters.
• The following programming order is recommended:
• The power supply used for programming must be capable of
delivering at least 26 V and 300 mA.
• Be careful to observe the tLOW delay time before powering
down the device after blowing each bit.
1. fPWM
2. Sens
3. D(Q)
Additional Guidelines
The additional guidelines in this section should be followed to
ensure the proper behavior of these devices:
4. Lock the device (only after all other parameters have been
programmed and validated, because this prevents any further
programming of the device)
Programming Modes
Bit Field Selection
Address Code Format
(Decimal Equivalent)
Code 5
Code in Binary
(Binary)
1 0 1
Fuse Blowing
Target Bits
Fuse Blowing
Address Code Format
Bit 2
Try Mode Try mode allows multiple programmable parameters
to be tested simultaneously without permanently setting any
values. In this mode, each VP(HIGH) pulse will indefinitely loop
the programming logic through the mode, register, and bit field
selection states.
Bit 0
After powering the VCC supply, select mode key 2, the desired
parameter register, and address its bit field. When addressing the
bit field, each VP(MID) pulse increments the value of the parameter register up to the maximum possible code (see Programming
Logic section). The addressed parameter value is stored in the
device even after the programming drive voltage is removed from
Code 4
Code 1
(Decimal Equivalents)
Figure 6. Example of code 5 broken into its binary components, which are
code 4 and code 1.
V+
VP(HIGH)
VP(MID)
VP(LOW)
0
Cycle VCC
supply
1
Mode
Selection
(Key 1)
1
2
Parameter
Selection
(Key 2)
1
2
3
Addressing
Bitfield 2
(Code 4)
4
Blow
Code 4
tBLOW
tLow
Cycle VCC
supply
Figure 7. Example of Blow Mode programming pulses applied to the VCC pin. In this example, DC(Q)
(Parameter Key 2) is addressed to code 4 (i.e bit 2) and its value is permanently blown.
Allegro MicroSystems, LLC
115 Northeast Cutoff
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14
High Precision Linear Hall-Effect Sensor IC
With an Open Drain Pulse Width Modulated Output
A1356
the VCC pin, allowing its value to be measured. To test an additional programmable parameter in conjunction with the original,
enter an additional VP(HIGH) pulse on the VCC pin to reenter the
parameter selection field. Select a different parameter register,
and address its bit field, without any supply interruptions. Both
parameter values will be stored and can be measured after removing the programming drive voltage. Multiple programming combinations can be tested to achieve optimal application accuracy.
See figure 8 for an example of the Try mode pulse train.
Single parameters can be still addressed in the Blow mode before
fuse blowing. Simultaneous addressing of multiple parameters,
as in Try mode, is not possible. After powering the VCC supply,
select the desired parameter register and address its bit field.
When addressing the bit field, each VP(MID) pulse increments the
value of the parameter register, up to the maximum possible code
(see Programming Logic table). The addressed parameter value
is stored in the device even after the programming drive voltage
is removed from the VCC pin, allowing its value to be measured.
It is not possible to decrease the value of the register without
resetting the parameter bit field. To reset the bit field, and thus
the value of the programmable parameter, cycle the supply, VCC,
voltage.
Registers can be addressed and re-addressed an indefinite number
of times in any order. After the required code is found for each
register, cycle the supply and blow the bit field using Blow mode.
Blow Mode After the required value of the programmable
parameter is found using Try mode, its corresponding code
should be blown to make its value permanent. To do this, select
the required parameter register, and address and blow each
required bit separately (as described in the Fuse Blowing section). The supply must be cycled between blowing each bit of a
given code. After a bit is blown, cycling the supply will not reset
its value.
It is possible to switch between Try and Blow modes, in that after
individual programmable parameters have been blown in Blow
mode, other parameters can be still tested in Try mode.
Lock Mode To lock the device, address the Lock bit and apply
a blow pulse with CBLOW in place. After locking the device, no
future programming of any parameter is possible.
V+
VP(HIGH)
VP(MID)
VP(LOW)
1
2
Mode
Selection
(Key 2, Try Mode)
1
Parameter
Selection
(Key 1)
1
2
Addressing
(Code 3)
3
1
2
Parameter
Selection
(Key 2)
1
2
Addressing
(Code 2)
0
Figure 8. Example of Try mode programming pulses applied to the VCC pin. In this example,
Sensitivity (parameter key 1) is addressed to code 3, and D(Q) (parameter key 2) is addressed
to code 2. The values set in the Sensitivity and D(Q) registers will be held in the device until the
supply is cycled. Permanent fuse blowing cannot be accomplished in Try mode.
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115 Northeast Cutoff
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15
High Precision Linear Hall-Effect Sensor IC
With an Open Drain Pulse Width Modulated Output
A1356
Programming State Machine
VP(MID)
VP(HIGH)
VP(HIGH)
VP(MID)
VP(MID)
VP(MID)
2 x VP(HIGH)
VP(HIGH)
VP(MID)
VP(MID)
VP(MID)
VP(MID)
VP(HIGH)
VP(MID)
VP(MID)
VP(MID)
VP(MID)
VP(MID)
VP(HIGH)
VP(MID)
VP(MID)
VP(HIGH)
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115 Northeast Cutoff
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16
High Precision Linear Hall-Effect Sensor IC
With an Open Drain Pulse Width Modulated Output
A1356
Programming Logic Table
Mode or Parameter
Name
(Register Key)
Bit Field Address
Description
Binary Format
[MSB → LSB]
Decimal Equivalent Code
Blow, Lock
(1)
01
1
Try
(2)
10
2
Programmable Mode
Blow parameter bit field fuse
Blow Lock fuse to lock device
Try code
Programmable Parameter
Sensitivity
(1)
D(Q)
(2)
PWM Frequency
(3)
Calibration Test Mode,
Lock
(5)
000000000
0
011111111
255
Initial value, Sens = SensPRE
Maximum Sens value in range
Initial value, D(Q) = D(Q)PRE
000000000
0
011111111
255
Maximum quiescent duty cycle in range
100000000
256
Switch from programming increasing D(Q) to
programming decreasing D(Q)
111111111
511
000000000
0
Minimum quiescent duty cycle in range
Initial value; fPWM = fPWMPRE
000001111
15
Minimum PWM frequency in range
000000000
0
Initial value
000010000
16
Enable Output Calibration Test Mode
1000000000
512
Enable blowing Lock fuse to lock device
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
17
High Precision Linear Hall-Effect Sensor IC
With an Open Drain Pulse Width Modulated Output
A1356
Output Calibration Test Mode
In customer applications, the PWM interface circuitry (body
control module; BCM in figure 9) and the A1356 may be powered
via different power and ground circuits. As a result, the ground
reference for the A1356 may differ from the ground reference of
the BCM. In some customer applications this ground difference
can be as large as ± 0.5 V. Differences in the ground reference for
the A1356 and the BCM can result in variations in the threshold voltage used to measure the duty cycle of the A1356. If the
PWM conversion threshold voltage varies, then the duty cycle
will vary because there is a finite rise time (tr) and fall time (tf)
in the PWM waveform. This problem is shown in figure 10. The
A1356 Output Calibration mode is used to compensate for this
error in the duty cycle. While the A1356 is in Output Calibration mode, the device output waveform is a fixed 50% duty cycle
(the programmed quiescent duty cycle value) regardless of the
applied external magnetic field. After powering-up, the A1356
outputs its quiescent duty cycle waveform for 50 ms, regardless
of the applied magnetic field (see figure 11). This allows the
BCM to compare the measured quiescent duty cycle with an ideal
50% duty cycle. This test period allows end users to compensate
for any threshold errors that result from a difference in system
ground potentials.
VREG
1
VCC
A1356
RPU
PWMOUT
BCM
3
CL
GND
2
GND1
GND2
Threshold Output Voltage,
VOUT(th) (V)
Figure 9. In many applications the A1356 may be powered using a different ground
reference than the BCM. This may cause the ground reference for the A1356 (GND 1) to
differ from the ground reference of the BCM (GND 2) by as much as to ± 0.5 V.
PWM period
3.5
2.5
1.5
VOUT(th)high
VOUT(th)(centered)
VOUT(th)(low)
∆tr
∆tf
Duty Cycle
shorter than
expected
Time
Duty Cycle at
expected duration
Duty Cycle longer
than expected
Figure 10. When the threshold voltage, VOUT(th) , is correctly centered between , VOUT(th)high and , VOUT(th)low , the duty cycle
accurately coincides with the applied magnetic field. If the threshold voltage is raised, the output duty cycle appears shorter
than expected. Conversely, if the threshold voltage is lowered, the output duty cycle is longer than expected.
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115 Northeast Cutoff
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18
A1356
High Precision Linear Hall-Effect Sensor IC
With an Open Drain Pulse Width Modulated Output
After the initial 50 ms has elapsed, the duty cycle will correspond
to an applied magnetic field as expected. The 50 ms calibration
test time corresponds with a target PWM frequency of 2 kHz. If
the PWM frequency is programmed away from its target of 2 kHz,
the duration of the calibration test time will scale inversely with the
change in PWM frequency.
This test mode is optional and must be enabled by blowing its
Calibration sequence
programming bit. After the test mode bit has been blown, the device
enters Output Calibration mode every time the device is powered-on.
This test mode is provided so that the user can compensate for
differences in the ground potential between the A1356 and any
interface circuitry used to measure the pulse width of the A1356
output.
PWM proportional to
magnetic field
Figure 11. After powering-on, the A1356 outputs a 50% DC for the first 50 ms, regardless of the applied magnetic
field (Output Calibration mode in effect). After the initial 50 ms has elapsed, the output responds to a magnetic field
as expected. The example in this figure assumes that a large +B field is applied to the device after the initial 50 ms.
Allegro MicroSystems, LLC
115 Northeast Cutoff
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1.508.853.5000; www.allegromicro.com
19
High Precision Linear Hall-Effect Sensor IC
With an Open Drain Pulse Width Modulated Output
A1356
Package KB, 3-Pin SIP
+0.08
5.21 –0.05
45°
C
B
1.55 ±0.05
2.60 D
1.33 D
+0.08
3.43 –0.05
D
Mold Ejector
Pin Indent
Branded
Face
1
0.84 REF
2.16
MAX
E
14.73 ±0.51
+0.06
0.38 –0.03
1
2
Standard Branding Reference View
N = Device part number
Y = Last two digits of year of manufacture
W = Week of manufacture
A
+0.07
0.51 –0.05
NNNN
YYWW
45°
3
For Reference Only; not for tooling use (reference DWG-9009)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A
Dambar removal protrusion (6X)
B
Gate and tie bar burr area
C
Active Area Depth 0.43 mm REF
D
Hall element (not to scale)
E
Branding scale and appearance at supplier discretion
1.90 NOM
Copyright ©2010-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
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20
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