A1359 Datasheet

A1359
Factory-Programmed Dual Output Linear Hall Effect Sensor IC
With Analog and Pulse Width Modulated Outputs
Features and Benefits
Description
• Dual tracking outputs: analog voltage output and pulse
width modulated (PWM) output
• Matched analog and PWM outputs enable user to detect
various output error conditions
• Factory-programmed offset, sensitivity, and polarity
• Sensitivity temperature coefficient (TC) and QVO/QD
temperature coefficient programmed at Allegro™ for
improved accuracy
• High speed chopping scheme minimizes quiescent voltage
output (QVO) drift across temperature
• Temperature-stable QVO and sensitivity
• Output voltage clamps provide short circuit diagnostic
capabilities
• Wide ambient temperature range: –40°C to 150°C
• Immune to mechanical stress
• Enhanced EMC performance for stringent automotive
applications
New applications for linear output Hall effect sensors, such
as displacement and angular position, require high accuracy
in conjunction with redundant outputs. The Allegro A1359
programmable, linear, Hall effect sensor IC has been designed
specifically to achieve both goals. The features associated
with this linear device make it ideal for use in automotive
and industrial applications requiring high accuracy, and
this temperature-stable device operates across an extended
temperature range: –40°C to 150°C.
The accuracy of the device is enhanced via programmability
at the Allegro factory for optimization of device sensitivity,
the quiescent voltage output (QVO: output with no magnetic
field), and quiescent duty cycle (QD) for a given application or
circuit. The A1359 also allows optimized performance across
the entire operating temperature range via programming the
temperature coefficients for both sensitivity and QVO/QD at
Allegro end-of-line test. This ratiometric Hall effect sensor IC
provides a analog voltage, and a PWM signal with duty cycle,
that are proportional to the applied magnetic field.
Package: 8-pin TSSOP (suffix LE)
surface mount
Each BiCMOS monolithic circuit integrates a Hall element,
temperature-compensating circuitry to reduce the intrinsic
sensitivity drift of the Hall element, a small-signal high-gain
Not to scale
Continued on the next page…
Functional Block Diagram
VSUPPLY
VCC
Chopper
Switches
Amp
Signal
Recovery
Signal
Conditioning
Low-Pass
Filter
100 nF
PWM
Frequency Trim
PWMOUT
PWM Carrier
Generation
GND
A1359-DS, Rev. 1
VOUT
RPULLUP
Sensitivity, QVO, and
Temperature Compensation
CBYPASS
Mismatch
Compensation
A1359
Factory-Programmed Dual Output Linear Hall Effect Sensor IC
With Analog and Pulse Width Modulated Outputs
Description (continued)
amplifier, a clamped low-impedance output stage and a proprietary
dynamic offset cancellation technique.
The A1359 is provided in an 8-contact surface mount TSSOP
(suffix LE) which is lead (Pb) free, with 100% matte tin
leadframe plating.
Selection Guide
Part Number
Factory Programmed Output Polarity
Forward: Output voltage increases with increasing
A1359LLETR-T
positive (south) applied magnetic field
Reverse: Output voltage increases with increasing
A1359LLETR-RP-T
negative (north) applied magnetic field
*Contact Allegro for additional packing options
Packing*
4000 units / reel
4000 units / reel
Absolute Maximum Ratings
Characteristic
Symbol
Forward Supply Voltage
VCC
Reverse Supply Voltage
VRCC
Forward Output Voltage
VOUT
Reverse Output Voltage
VROUT
Forward PWM Output Voltage
VPWM
Reverse PWM Output Voltage
Output Source Current
Output Sink Current
PWM Output Source Current
PWM Output Sink Current
Notes
Refer to Power Derating section
Refer to Power Derating section
Refer to Power Derating section
Rating
Unit
6
V
–0.1
V
7
V
–0.1
V
7
V
–0.1
V
IOUT(SOURCE)
VOUT to GND
2
mA
IOUT(SINK)
VCC to VOUT
10
mA
VPWM > –0.5 V, TA = 25°C
–50
mA
Internal current limiting is intended to protect the
device from momentary short circuits and not
intended for continuous operation
25
mA
VRPWM
IPWM(SOURCE)
IPWM(SINK)
Operating Ambient Temperature
TA
–40 to 150
ºC
Storage Temperature
Tstg
–65 to 170
ºC
TJ(max)
165
ºC
Maximum Junction Temperature
Temperature range L
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
Factory-Programmed Dual Output Linear Hall Effect Sensor IC
With Analog and Pulse Width Modulated Outputs
A1359
Terminal List Table
Number
Name
1
PWMOUT
2
VCC
8 NC
3
NC
7 GND
4
VOUT
5
NC
No connect, tie to either GND or VCC
6
NC
No connect, tie to either GND or VCC
7
GND
8
NC
Pin-out Diagram
PWMOUT 1
VCC 2
NC 3
6 NC
VOUT 4
5 NC
Function
Open drain PWM output
Input power supply; tie to GND with bypass capacitor
No connect, tie to either GND or VCC
Output signal
Device ground
No connect, tie to either GND or VCC
Thermal Characteristics may require derating at maximum conditions, see application information
Characteristic
Symbol
RθJA
Package Thermal Resistance
Test Conditions*
On 4-layer PCB based on JEDEC standard
Value
Unit
145
ºC/W
*Additional thermal information available on the Allegro website
Power Dissipation versus Ambient Temperature
1000
900
800
600
(R
QJ
A
=
14
500
5
ºC
/W
400
)
Power Dissipation, PD (mW)
700
300
200
100
0
20
40
60
80
100
120
140
Temperature, TA (°C)
160
180
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
Factory-Programmed Dual Output Linear Hall Effect Sensor IC
With Analog and Pulse Width Modulated Outputs
A1359
OPERATING CHARACTERISTICS Valid over full operating temperature range, TA, CBYPASS = 0.1 μF , VCC = 5 V,
unless otherwise noted
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit1
Electrical Characteristics
Supply Voltage
VCC
Undervoltage Threshold2
4.5
5.0
5.5
V
VUVLOHI
TA = 25°C (device powers on)
–
–
3
V
VUVLOLOW
TA = 25°C (device powers off)
2.5
–
–
V
Supply Current
ICC
VCC = 5 V
–
10
13.5
mA
Supply Zener Clamp Voltage
VZ
TA = 25°C, ICC = 20 mA
6
8.3
–
V
Bandwidth3
BWi
Internal
Small signal, –3 dB
–
2
–
kHz
fC
TA = 25°C
–
400
–
kHz
VN
TA = 25°C, CBYPASS = 0.1 μF, Sens = 5 mV/G,
no load on VOUT
–
6
–
mV(p-p)
Input Referred RMS Noise Density3
VNRMS
T = 25°C, CBYPASS = open, no load on VOUT,
f << BWi
–
1.9
–
mG/√Hz
DC Output Resistance3
ROUT
–
<1
–
Ω
4.7
–
–
kΩ
Chopping Frequency3,4
Analog Output Characteristics
Output Referred Noise3
Output Load Resistance3
Output Load Capacitance3
Analog Output Current Limit
Output Voltage
RL
VOUT to GND
CL
VOUT to GND
–
–
10
nF
ILIMIT(ALG)
RPULLUP = 0 Ω
10
–
80
mA
VCLPH
TA = 25°C, B = +350 G,
RL = 10 kΩ (VOUT to GND)
4.25
4.5
4.65
V
VCLPL
TA = 25°C, B = –350 G,
RL = 10 kΩ (VOUT to VCC)
0.40
0.5
0.70
V
Impulse magnetic field of 300 G
–
–
500
μs
Clamp5
Response Time3
tRESPONSE_
Settling Time3
tSETTLEVOUT
VOUT
TA = 25°C, Primary Overload > 5000 G
–
–
750
μs
Power-On Time for Analog3
tPOVOUT
TA = 25°C, CL (probe) = 10 pF, on VOUT
–
250
–
μs
Delay to Clamp for Analog3
tCLPVOUT
TA = 25°C, CL = 10 nF, on VOUT
–
30
–
μs
PWM Output Characteristics
IPWMOUT(SINK) ≤ 20 mA, PWMOUT transistor on
–
–
0.6
V
IPWMOUT(SINK) ≤ 10 mA, PWMOUT transistor on
–
–
0.5
V
ILIMIT
RPULLUP = 0 Ω
30
60
110
mA
PWMOUT Leakage Current
ILEAK
VCC = GND, 0 V ≤ VPWMOUT ≤ 5 V,
PWMOUT transistor off
–
0.1
10
μA
PWMOUT Zener Clamp Voltage
VZOUT
PWMOUT Saturation Voltage
VSAT
PWMOUT Current Limit
PWMOUT Rise Time3
PWMOUT Fall Time3
Power-On Time for PWM3
Delay to Clamp for
PWM3
Response Time3
Settling Time3
IPWMOUT(SINK) = 10 mA, TA = 25ºC
28
–
–
V
tr
TA = 25°C, RPULLUP = 2 kΩ, CL = 20 pF
–
3
–
μs
tf
TA = 25°C, RPULLUP = 2 kΩ, CL = 20 pF
–
3
–
μs
tPOPWM
TA = 25°C, CL (probe) = 10 pF, on PWMOUT
–
500
–
μs
tCLPPWM
TA = 25°C, CL = 10 nF, on PWMOUT
–
250
–
μs
TA = 25°C, Impulse magnetic field of 300 G
–
–
1.5
ms
TA = 25°C, Primary Overload > 5000 G
–
–
2.25
ms
tRESPONSE_
PWM
tSETTLEPWM
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
Factory-Programmed Dual Output Linear Hall Effect Sensor IC
With Analog and Pulse Width Modulated Outputs
A1359
OPERATING CHARACTERISTICS (continued) Valid over full operating temperature range, TA, CBYPASS = 0.1 μF , VCC = 5 V,
unless otherwise noted
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit1
PWM Output Characteristics (continued)
Load Resistance3,6
Load Capacitance3,6
Duty Cycle Jitter3
RPULLUP
PWMOUT to VCC
2000
–
–
Ω
CL
PWMOUT to GND
–
–
10
nF
Measured over 1000 PWM output clock periods,
3 sigma values, Sens = 9 mV/G
–
±0.18
–
%D
2.45
2.5
2.55
V
JitterPWM
Quiescent Voltage Output (QVO)
TA = 25°C
Quiescent Voltage Output
VOUT(Q)
Quiescent Voltage Output
Equivalent PWM
D(Q)
TA = 25°C, VCC = 4.5 to 5.5 V
49
50
51
%D
fPWM
TA = 25°C
3.6
4
4.4
kHz
Programmed at TA = 150°C, calculated relative
to Sens at 25°C
0.08
0.12
0.16
%/°C
A1359LLETR-T
B = ±125 G, TA = 25°C
8.73
9.0
9.27
mV/G
A1359LLETR-RP-T
B = ±125 G, TA = 25°C
–9.27
–9.0
–8.73
mV/G
–57.4
–
+57.4
mV
–85
–
+85
mV
LinERR
–
±0.5
–
%
SymERR
–
±0.5
–
%
PWM Carrier Frequency
Carrier Frequency
Sensitivity
Sensitivity Temperature Coefficient
Analog Sensitivity7
TCSENS
Sen
Error Components
PWM to Analog Output Mismatch8
Linearity Sensitivity
Error9
Symmetry Sensitivity Error9
Ratiometry Quiescent Voltage
Output Error10
Ratiometry Sensitivity Error9
Ratiometry Clamp Error10
VOUTERR
1.75 V < VOUT < 3.25 V
VOUT = 1.25 V, VOUT = 3.75 V
RatVOUT(Q)
Across supply voltage range,
(relative to VCC = 5 V)
–
±0.5
–
%
RatSens
Across supply voltage range,
(relative to VCC = 5 V)
–
±0.5
–
%
TA = 25°C, across supply voltage range, (relative
to VCC = 5 V)
–
±0.5
–
%
–17
–
+17
mV
–
±2
–
%
RatVOUTCLP
Quiescent Voltage Output Drift Through
Temperature Range
∆VOUT(Q)
TA =150°C
Sensitivity Drift Due to Package
Hysteresis
∆SensPKG
TA = 25°C, after temperature cycling
11
G (gauss) = 0.1 mT (millitesla).
power-up, the output is held low until VCC exceeds VUVLOHI . When the device reaches the operational power level, the output remains valid until
VCC drops below VUVLOLO , when the output is pulled low.
3Determined by design and characterization, not evaluated at final test.
4f varies as much as approximately ±20% across the full operating ambient temperature range and process.
c
5V
CLPL and VCLPH scale with VCC , due to ratiometry.
6Load capacitance and resistance directly effects the rise time of the PWM output by t = 0.35 × 2 × π × R × C .
r
L
L
7Room temperature sensitivity can drift, ΔSens
LIFE , by an additional 3% (typical worst case) over the life of the product.
8See Characteristic Definitions section.
9Applicable to both analog and PWM channels. Tested at Allegro factory for only the analog channel, and determined by design and characterization
for the PWM channel.
10Applies only to the analog channel.
2At
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
Factory-Programmed Dual Output Linear Hall Effect Sensor IC
With Analog and Pulse Width Modulated Outputs
A1359
Characteristic Definitions
Power-On Time When the supply is ramped to its operating
voltage, the device requires a finite time to power its internal
components before supplying a valid PWM output duty-cycle.
Power-On Time for analog output, tPOVOUT, is defined as the time
it takes for the output voltage to settle within ±10% of its steady
state value after the power supply has reached its minimum specified operating voltage, VCC(min). (See figure 1.)
Power-On Time is specified in a different way for the PWM output than the analog output. For the PWM output, the Power-On
Time, tPOPWM, is defined as the time it takes for the duty cycle to
settle within ±10% of the target steady state value from the time
the power supply has reached the minimum specified operating
voltage, VCC(min). (See figure 2.)
Response Time The time interval, tRESPONSEPWM or
tRESPONSEVOUT , between: a) when the applied magnetic field
reaches 90% of its final value, and b) when the sensor IC reaches
90% of its output corresponding to the applied magnetic field
(PWM duty cycle or analog VOUT ). Figure 3 illustrates an
example with the PWM output. Response time is conceptually
the same for the analog output.
V
VCC
VCC(typ)
VOUT
90% VOUT
VCC
VCC(min)
VCC(min)
t1
Time
tPOVOUT
VPWMOUT
t2
t1= time at which power supply reaches
minimum specified operating voltage
First valid duty cycle
t2= time at which output voltage settles
within ±10% of its steady state value
under an applied magnetic field
0
Time
tPOPWM
+t
Figure 1. Definition of analog Power-On Time, tPOVOUT
Figure 2. Definition of PWM Power-On Time, tPOPWM
ADC – DC corresponds to the A field
BDC – DC corresponds to the B field
CDC – DC corresponds to the 0.9 × C field
1 ms
0.9 × C
C
B-field
A
B
Time
ADC
BDC
CDC
PWMOUT
Propagation
Delay
Response
Time
Figure 3. Definition of Response Time for PWM output
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
Factory-Programmed Dual Output Linear Hall Effect Sensor IC
With Analog and Pulse Width Modulated Outputs
A1359
Delay to Clamp A large magnetic input step may cause the
clamp to overshoot its steady state value. The delay to clamp,
tCLPVOUT , is defined as the time it takes for the output voltage
to settle within 1% of its steady state value after initially passing
through its steady state voltage. This is conceptually the same for
the PWM output duty cycle settling to the steady state value. (See
figure 4.)
Quiescent Voltage Output In the quiescent state (no significant magnetic field: B = 0 G), the analog output, VOUT, is ratiometric to the supply voltage, VCC , throughout the entire operating
range of VCC . The PWM output, VPWMOUT , by virtue of being a
% duty-cycle will remain at 50% nominal throughout the entire
VCC operating range (4.5 to 5.5 V).
Quiescent Output Drift through Temperature Range Due
to internal component tolerances and thermal considerations, the
Quiescent Voltage Output, VOUT(Q) , may drift from its nominal
value across the operating ambient temperature, TA. For purposes
of specification, the Quiescent Voltage Output Drift Through
Temperature Range, ∆VOUT(Q) (mV), is defined as:
∆VOUT(Q) = VOUT(Q)(TA) – VOUT(Q)(25°C)
(1)
Sensitivity Assuming the sensitivity of the device is positive
(Positive Polarity: A1359LLETR-T), the presence of a southpolarity magnetic field perpendicular to the branded surface of
the package face increases the output voltage from its quiescent
value toward the supply voltage rail. The amount of the output
Magnetic Input Signal
VPWMOUT or VOUT
tCLPPWM or
tCLPVOUT
t1
t2
t1= time at which output voltage initially
reaches steady state clamp voltage
t2= time at which output voltage settles to
within 1% of steady state clamp voltage
time (μs)
Figure 4. Definition of Delay to Clamp
where BPOS and BNEG are two magnetic fields with opposite
polarities.
Sensitivity Temperature Coefficient Device sensitivity
changes as temperature changes, with respect to its programmed
Sensitivity Temperature Coefficient, TCSENS. TCSENS is programmed at 150°C, and calculated relative to the nominal
sensitivity programming temperature of 25°C. TCSENS (%/°C) is
defined as:
 1 
SensT2 – SensT1

TCSENS = 
100% 
×
SensT1
 T2–T1

(3)
where T1 is the nominal Sens programming temperature of 25°C,
and T2 is the TCSENS programming temperature of 150°C. The
ideal value of Sens through the full ambient temperature range,
SensIDEAL(TA), is defined as:
SensIDEAL(TA) = SensT1× [100% +TCSENS (TA –T1)]
Magnetic Input Signal
Device Output,
VPWMOUT or VOUT (V)
VCLP(HIGH)
voltage increase is proportional to the magnitude of the magnetic
field applied. Conversely, the application of a north polarity field
decreases the output voltage from its quiescent value. For the
case of the reverse polarity device (A1359LLETR-RP-T), the
presence of a south-polarity magnetic field perpendicular to the
branded surface of the package face decreases the output voltage from its quiescent value toward the ground rail. The amount
of the output voltage decrease is proportional to the magnitude
of the magnetic field applied. Conversely, the application of a
north polarity field increases the output voltage from its quiescent
value. This proportionality is specified as the magnetic sensitivity, Sens (mV/G), of the device and is defined as:
VOUT(BPOS) – VOUT(BNEG)
Sens =
(2)
BPOS – BNEG
(4)
Sensitivity Drift Due to Package Hysteresis Package
stress and relaxation can cause the device sensitivity at TA = 25°C
to change during and after temperature cycling. This change in
sensitivity follows a hysteresis curve. For purposes of specification, the Sensitivity Drift Due to Package Hysteresis, ∆SensPKG,
is defined as:
∆SensPKG =
Sens(25°C)2 – Sens(25°C)1
Sens(25°C)1
× 100 (%)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
(5)
7
Factory-Programmed Dual Output Linear Hall Effect Sensor IC
With Analog and Pulse Width Modulated Outputs
A1359
where Sens(25°C)1 is the programmed value of sensitivity
at TA = 25°C, and Sens(25°C)2 is the value of sensitivity at
TA = 25°C, after temperature cycling TA up to 150°C, down to
–40°C, and back to up 25°C.
Linearity Sensitivity Error The A1359 is designed to provide
linear output in response to a ramping applied magnetic field.
Consider two magnetic fields, B1 and B2. Ideally, the sensitivity
of a device is the same for both fields, for a given supply voltage
and temperature. Linearity error is present when there is a difference between the sensitivities measured at B1 and B2.
Linearity Sensitivity Error is calculated separately for the positive
(LinERRPOS) and negative (LinERRNEG ) applied magnetic fields.
Linearity error (%) is measured and defined as:
 SensBPOS2 

LinERRPOS = 1–
 SensBPOS1 
× 100 (%)
 SensBNEG2

LinERRNEG = 1–
 SensBNEG1
× 100 (%)
(6)
|VOUT(Bx) – VOUT(Q)|
Bx
Ratiometry Error The A1359 provides a ratiometric output.
This means that the quiescent voltage output, VOUT(Q) , magnetic sensitivity, Sens, and clamp voltage, VCLPH and VCLPL, are
proportional to the supply voltage, VCC . In other words, when
the supply voltage increases or decreases by a certain percentage, each characteristic also increases or decreases by the same
percentage. Error is the difference between the measured change
in the supply voltage relative to 5 V, and the measured change in
each characteristic.
The ratiometric error in quiescent voltage output, RatVOUT(Q)
(%), for a given supply voltage, VCC, is defined as:
where:
SensBx =
Symmetry Sensitivity Error The magnetic sensitivity of the
A1359 device is constant for any two applied magnetic fields of
equal magnitude and opposite polarities. Symmetry Sensitivity
Error, SymERR (%), is measured and defined as:
 SensBPOS 
 × 100 (%)
SymERR = 1–
(10)
 SensBNEG 
where SensBx is as defined in equation 7, and BPOS and
BNEG are positive and negative magnetic fields such that
|BPOS| = |BNEG|.
(7)
and BPOSx and BNEGx are positive and negative magnetic
fields, with respect to the quiescent voltage output such that
BPOS2 > BPOS1 and BNEG2 > BNEG1.
 VOUT(Q)(VCC) / VOUT(Q)(5V) 

RatERRVOUT(Q) = 1–
VCC / 5 V


The ratiometric error in magnetic sensitivity, RatSens (%), for a
given supply voltage, VCC , is defined as:
Then:
RatERRSens = 1–
LinERR = max( |LinERRPOS | , |LinERRNEG |)
(8)
Clamping Range The output voltage clamps, VCLPH and
VCLPL , limit the operating magnetic range of the applied field in
which the device provides a linear output. The maximum positive and negative applied magnetic fields in the operating range
can be calculated:
VCLP(HIGH) – VOUT(Q)
Sens
VOUT(Q) – VCLP(LOW)
|BNEG(max)| =
Sens
× 100 (%) (11)
|BPOS(max)| =
(9)
Sens(VCC) / Sens(5V)
VCC / 5 V
× 100 (%)
(12)
The ratiometric error in the clamp voltages, RatVOUTCLP (%), for
a given supply voltage, VCC, is defined as:
RatVOUTCLP = 1–
VCLP(VCC) / VCLP(5V)
VCC / 5 V
× 100 (%)
(13)
where VCLP is either VCLPH or VCLPL.
Note: Equations 11 and 13 apply to the analog channel (VOUT),
only. Recall that for the PWM output, the 0 G output is 50% from
4.5 to 5.5 V. However, as sensitivity is ratiometric with VCC for
both analog and PWM channels, equation 12 applies to both the
analog and the PWM channels.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
A1359
Factory-Programmed Dual Output Linear Hall Effect Sensor IC
With Analog and Pulse Width Modulated Outputs
Duty Cycle Jitter The duty cycle of the PWM output may vary
slightly over time despite the presence of a constant applied magnetic field and a constant Carrier Frequency, fPWM , for the PWM
signal. This phenomenon is known as jitter, JitterPWM (%) , and is
defined as:
JitterPWM = ±
DB(max) – DB(min)
2
VCC
VUVLOLO
tUVLO
(14)
where DB(max) and DB(min) are the maximum and minimum
duty cycles, measured in 1000 PWM clock periods, in a constant
applied magnetic field.
Undervoltage Lockout The A1359 features an undervoltage lockout function that ensures that the device will output a
valid signal when VCC is above a certain threshold, VUVLOHI ,
and remains valid until VCC falls below a lower threshold,
VUVLOLOW . The undervoltage lockout feature provides a hysteresis of operation to eliminate indeterminate output states.
The output of the A1359 is held low (GND) until VCC exceeds
VUVLOHI . When VCC exceeds VUVLOHI , the device powers-up
and the output provides a ratiometric output voltage proportional
to the input magnetic signal, and VCC . If VCC should drop back
down below VUVLOLOW for more than tuvlo after the device is
powered-up, the output would be pulled low. (See figure 5.)
PWM to Analog Output Mismatch When comparing the
PWM output to the analog output for channel mismatch, the
following equation is used to convert PWM (% D, duty cycle) to
voltage (V):
VPWMOUT = D(Q) + D(field) = VOUT(Q) × 20.0 %D / V
+ VOUT(B) × 21.0%D / V
where:
VUVLOHI
(15)
D(Q) is the quiescent PWM signal with no input field (B = 0 G),
and D(field) is the PWM signal in response to the input magnetic
field. In other words, the product of PWM sensitivity (%D/G)
and input magnetic field (G). (See figure 6.)
VPWMOUT
or VOUT
time
Figure 5. UVLO operation
+VPWMOUT (V)
VOUTERR=
±85 mV
Digital
Channel
3.75
3.25
VOUTERR=
±85 mV
1.75
VOUTERR=
±57.4 mV
1.25
1.25
1.75
3.25
3.75
+VOUT (V)
Analog Channel
Figure 6. Definition of PWM to Analog Output Mismatch, VOUTERR
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
A1359
Factory-Programmed Dual Output Linear Hall Effect Sensor IC
With Analog and Pulse Width Modulated Outputs
Typical Application Circuit
RPULLUP
A1359
PWMOUT
VOUT
VCC
0.1 μF
5V
RL
GND
CL
4.7 nF
Optional: Recommended
for EMC robustness
Figure 7. Typical application circuit
Chopper Stabilization Technique
When using Hall-effect technology, a limiting factor for
switchpoint accuracy is the small signal voltage developed across
the Hall element. This voltage is disproportionally small relative
to the offset that can be produced at the output of the Hall sensor
IC. This makes it difficult to process the signal while maintaining an accurate, reliable output over the specified operating
temperature and voltage ranges. Chopper stabilization is a unique
approach used to minimize Hall offset on the chip. Allegro
employs a patented technique to remove key sources of the output drift induced by thermal and mechanical stresses. This offset
reduction technique is based on a signal modulation-demodulation process. The undesired offset signal is separated from the
magnetic field-induced signal in the frequency domain, through
modulation. The subsequent demodulation acts as a modulation
process for the offset, causing the magnetic field-induced signal
to recover its original spectrum at base band, while the DC offset
becomes a high-frequency signal. The magnetic-sourced signal
then can pass through a low-pass filter, while the modulated DC
offset is suppressed. In addition to the removal of the thermal and
stress related offset, this novel technique also reduces the amount
of thermal noise in the Hall sensor while completely removing
the modulated residue resulting from the chopper operation. The
chopper stabilization technique uses a high frequency sampling
clock. For demodulation process, a sample-and-hold technique
is used. This high-frequency operation allows a greater sampling
rate, which results in higher accuracy and faster signal-processing
capability. This approach desensitizes the chip to the effects
of thermal and mechanical stresses, and produces devices that
have extremely stable quiescent Hall output voltages and precise
recoverability after temperature cycling. This technique is made
possible through the use of a BiCMOS process, which allows the
use of low-offset, low-noise amplifiers in combination with highdensity logic integration and sample-and-hold circuits.
Regulator
Clock/Logic
Hall Element
Amp
Anti-aliasing Tuned
LP Filter
Filter
Figure 8. Concept of chopper stabilization technique
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
Factory-Programmed Dual Output Linear Hall Effect Sensor IC
With Analog and Pulse Width Modulated Outputs
A1359
Package LE, 8-Pin TSSOP
E
3.00±0.10
8
0.45
8º
0º
0.65
8
0.20
0.09
1.70
D
6.40 BSC
6.10
4.40±0.10
0.60 +0.15
–0.10
2.20 D
A
1.00 REF
1
2
1 2
0.25 BSC
1.50
D
SEATING PLANE
GAUGE PLANE
B
PCB Layout Reference View
Branded Face
0.30
0.19
0.65 BSC
C
1.10 MAX
0.15
0.05
1
For Reference Only; not for tooling use (reference MO-153 AA)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Reference land pattern layout (reference IPC7351 SOP65P640X110-8M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias can improve
thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
59R
YYWW
SEATING
PLANE
0.10 C
359
YYWW
8X
1
A1359LLETR-T
C
A1359LLETR-RP-T
Branding Reference View
Top line is device designator
= Supplier emblem
Y = Last two digits of year of manufacture
W = Week of manufacture
Branding scale and appearance at supplier discretion
D Hall element, not to scale
E Active Area Depth 0.36 mm REF
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
A1359
Factory-Programmed Dual Output Linear Hall Effect Sensor IC
With Analog and Pulse Width Modulated Outputs
Revision History
Revision
Revision Date
Rev. 1
June 18, 2013
Description of Revision
Update ICC and package drawing
Copyright ©2011-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
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