DEMO MANUAL DC2290A LTC2387/LTC2386/LTC2385 18-/16-Bit, 15Msps/10Msps/5Msps, High Speed SAR ADCs Description Demonstration circuit 2290A features the LTC®2387 family. With up to 15Msps, these differential input, single channel, 18-/16-Bit, serial, high speed successive approximation register (SAR) ADCs are available in a 32-Pin QFN package. The LTC2387 family has an internal 20ppm/°C reference and a serial LVDS interface. The following text refers to the LTC2387 but applies to all members of the family, the only difference being the sample rate and the number of bits. The DC2290A demonstrates the AC performance of the LTC2387 in conjunction with the DC718 data collection board. Differential amplifier demo boards are available separately that provide amplification of low level differential signals if required (see Table 2). Alternatively, by connecting the DC2290A into a customer application the performance of the LTC2387 can be evaluated directly in that circuit. Design files for this circuit board are available at http://www.linear.com/demo/DC2290A L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PScope is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Board Photo 6VDC POWER SUPPLY CLOCK SIGNAL FROM GENERATOR SIGNAL GENERATOR TO DC718 Figure 1. DC2290A Connection Diagram dc2290afb 1 DEMO MANUAL DC2290A DC718 Quick Start Procedure Connect the DC2290A to a DC718 USB High Speed Data Collection Board using edge connector J1. Connect the DC718 to a host PC with a standard USB A/B cable. Apply a low noise differential signal to J6 (AIN+) and J5 (AIN–). Note that the DC2290A requires a differential input signal of approximately 8.192V peak-to-peak to reach 0dBFS. If a differential signal source of this amplitude is not available use one of the recommended differential amplifier demo boards available to increase the signal level. For a clock source, apply a low jitter 10dBm sine wave or square wave to connector J4. See Table 1 for maximum clock frequen- cies. Note that J4 has a 50Ω termination resistor to ground. Run the PScope™ software (Pscope.exe version K73 or later) supplied with DC718 or download it from www. linear.com/software. Complete software documentation is available from the Help menu. Updates can be downloaded from the Tools menu. Check for updates periodically as new features may be added. The PScope software should recognize the DC2290A and configure itself automatically. Click the Collect button (Figure 2) to begin acquiring data. The Collect button then changes to Pause, which can be used to stop data acquisition. Table 1. DC2290A Assembly Options U1 PART NUMBER MAX CONVERSION RATE # OF BITS MAX CLOCK FREQUENCY DC2290A-A VERSION LTC2387CUH-18#PBF 15Msps 18 15MHz DC2290A-B LTC2387CUH-16#PBF 15Msps 16 15MHz DC2290A-C LTC2386CUH-18#PBF 10Msps 18 10MHz DC2290A-D LTC2386CUH-16#PBF 10Msps 16 10MHz DC2290A-E LTC2385CUH-18#PBF 5Msps 18 5MHz DC2290A-F LTC2385CUH-16#PBF 5Msps 16 5MHz Hardware Setup SIGNAL CONNECTIONS JUMPERS J2: JTAG. Factory use only. JP1: EEPROM. Factory use only. J3: FPGA Program. Factory use only. JP2: Lanes. Use this jumper to select either single lane or two lane data output mode from the LTC2387. The default setting is 1. The 1 setting clocks out all data on pin DA of the LTC2387. The 2 setting clocks out data alternately on pins DA and DB of the LTC2387. J4: CLK IN. This input has a 50Ω termination resistor, and is intended to be driven by a low jitter, 10dBm sine or square wave. To achieve full AC performance of this part, the clock jitter should be kept under 2psRMS. This input is capacitively coupled so that the input clock can be either 0V to 3.3V or ±1.65V. This eliminates the need for level shifting. To run at the maximum conversion rate, apply the frequency specified in Table 1. J5: AIN– Input. This is the negative signal input. J6: AIN+ Input. This is the positive signal input. 2 JP3: Test Pattern. Use this jumper to deliver a fixed repeating test pattern from the LTC2387. The default setting is OFF. The output data will be –97796 if the jumper is in the ON position in 1 lane mode, and will be –52996 in 2 lane mode. JP4: ADC ON. Use this jumper to enable or disable the ADC. The default setting is ON. dc2290afb DEMO MANUAL DC2290A Hardware Setup Figure 2. DC2290A PScope Screenshot Table 2. DC2290A (LTC2387 Family) Driver Board INPUT FREQUENCY DRIVE BOARD AMPLIFIER Up to 10kHz DC2402 LT6237 Up to 1MHz DC2403 LT6200 Contact Factory Contact Factory > 1MHz dc2290afb 3 DEMO MANUAL DC2290A Parts List ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER DC2290A Required Circuit Components 1 3 C7, C41, C42 CAP., X5R, 0.022µF, 25V, 10%, 0402 2 4 C9, C13, C16, C21 CAP., NPO, 10pF, 50V, 5%, 0402 AVX, 04023A100KAT2A 3 7 C32, C37, C47, C59, C64, C68, C77 CAP., X7R, 10µF, 6.3V, 10%, 0805 AVX, 08056C106KAT2A 4 5 C31, C51, C66, C69, C71 CAP., X7R, 1µF, 10V, 10%, 0603 AVX, 0603ZC105KAT2A 5 1 C40 CAP., X5R, 3.3µF, 10V, 10%, 06035 C1608X5R1A335K 6 2 C5, C97 CAP., X5R, 47µF, 6.3V, 20%, 0805 TAIYO YUDEN, JMK212BJ476MG-T 7 1 C90 CAP., X5R, 22µF, 16V, 20%, 1210 AVX, 1210YD226MAT2A 8 1 C8 CAP., X5R, 0.0047µF, 25V, 10%, 0402 AVX, 04023D472KAT2A 9 33 C1, C2, C3, C4, C12, C14, C15, C17, C18, C19, C20, C22, C24, C26, C27, C28, C29, C30, C33, C34, C35, C36, C38, C43, C44, C45, C46, C49, C55, C56, C57, C58, C98 CAP., X5R, 0.1µF, 10V, 10%, 0402 AVX, 0402ZD104KAT2A 10 5 C23, C54, C63, C67, C87 CAP., X7R, 0.1µF, 16V, 10%, 0603 NIC, NMC0603X7R104K16TRPF 11 4 C25, C48, C65, C70 CAP., X7R, 0.01µF, 6.3V, 10%, 0603 MURATA, GRM188R70J103KA01D 12 2 C10, C11 CAP., X5R, 0.01µF, 25V, 10%, 0402 AVX, 04023D103MAT2A 13 0 C74 CAP, DNI, 0603 14 1 C76 CAP., X7R, 2.2µF, 10V, 10%, 0603 15 1 C95 CAP., X7R, 0.0022µF, 50V, 10%, 0402 16 7 C6, C52, C53, C60, C80, C96, C99 CAP., X5R, 4.7µF, 10V, 10%, 0603 AVX 0603ZD475KAT2A 17 2 C73, C75 CAP., NPO, 82pF, 25V, 10%, 0603 AVX, 06033A820KAT2A 18 8 E1, E2, E3, E4, E5, E6, E7, E8 TEST POINT, TURRET, .064" MILL MAX, 2308-2-00-80-00-00-07-0 19 2 E9, E10 TEST POINT, TURRET, .094" MILL-MAX, 2501-2-00-80-00-00-07-0 AVX, 0603ZC225KAT2A 20 1 J1 HEADER, 20 × 2, 0.1IN, STRAIGHT_PINS SAMTEC, TSW-120-07-L-D 21 2 J2, J3 HEADER, 2 × 5, 0.100" SAMTEC, TSW-105-07-L-D 22 2 J5, J6 CONN, SMA, 50Ω, EDGE-LAUNCH, FEMALE E.F. JOHNSON, 142-0701-851 23 1 J4 CONN BNC FEM JACK PC MNT STRGHT AMPHENOL CONNEX, 112404 24 4 JP1, JP2, JP3, JP4 HEADER, 1 × 3, 0.100" SAMTEC, TSW-103-07-L-S 25 4 L1, L2, L3, L5 FERRITE BEAD, 33Ω, 0603 MURATA, BLM18PG330SN1L 26 1 R44 RES., 0Ω, 1/10W, 0603 PANASONIC, ERJ-3GEY0R00V 27 1 R71 RES., 0Ω, 1/10W, 0402 PANASONIC, ERJ-2GEY0R00V 28 0 R38, R45, R46, R55, R57, R72 RES, DNI, 0603 29 19 R1, R2, R3, R4, R5, R7, R8, R14, R15,R16, R17, R18, R19, R20, R21, R23, R25, R68, R69 RES., 33Ω, 1/10W, 5%, 0402 YAGEO, RC0402JR-0733RL 30 3 R32, R36, R37 RES., 33Ω, 1/10W, 5%, 0603 YAGEO, RC0603JR-0733RL 31 4 R29, R30, R31, R35 RES., 100Ω, 1/10W, 1%, 0201 YAGEO, RC201FR-07101L 32 2 R49, R50 RES., 10.0Ω, 1/10W, 1%, 0603 PANASONIC, ERJ-3EKF10R0V 33 1 R41 RES., 49.9Ω, 1/10W, 1%, 1206 PANASONIC, ERJ-8ENF49R9V 34 7 R6, R9, R10, R12, R13, R53, R54, R70 RES., 10k, 1/10W, 5%, 0402 PANASONIC, ERJ-2GEYJ103V 35 3 R22, R24, R26 RES., 4.99k, 1/10W, 5%, 0603 PANASONIC, ERJ-3GEYJ4991V 36 3 R27, R39, R40 RES.,1.00k, 1/10W, 5%, 0603 PANASONIC, ERJ-3GEYJ102V 4 dc2290afb DEMO MANUAL DC2290A Parts List ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER 37 1 R11 RES.,1.00k, 1/10W, 5%, 0402 PANASONIC, ERJ-2GEYJ102V 38 1 R28 RES.,1.43k, 1/10W, 1%, 0603 PANASONIC, ERJ-3EKF1431V 39 1 D1, D2, D3, D4 DIODE, SCHOTTKY 30V, 200MW, SOD323 DIODE INC., BAT54WS-7-F 40 1 U1 IC, CONFIG DEVICE 4MBIT, SO8 ALTERA, EPCS4SI8N 41 1 U2 IC, EEPROM 2KBIT 400kHz, TSSOP8 MICROCHIP, 24LC024-I/ST 42 1 U3 IC, CYCLONE III FPGA 5k, EQFP144 ALTERA, EP3C5E144C7N 43 1 U4 IC, MICROPOWER REGULATOR, SO8 LINEAR TECH., LT1763CS8#PBF 44 1 U5 IC, LINEAR REGULATOR, SO8 LINEAR TECH., LT3021ES8-1.2#PBF 45 1 U11 IC, INVERTER UHS SINGLE SC70-5 FAIRCHILD, NC7SZ04P5X 46 2 U8, U12 IC, MICROPOWER REGULATOR, SO8 LINEAR TECH., LT1763CS8-2.5#PBF 47 1 U9 IC, FLIP FLOP D-TYPE LOG, US8 ON SEMI., NL17SZ74USG 48 1 U13 IC, MICROPOWER REGULATOR, SO8 LINEAR TECH., LT1763CS8-5#PBF 49 1 U14 IC, VOLTAGE REFERENCE, MSOP8 LINEAR TECH., LTC6655BHMS8-4.096#PBF 50 1 U17 IC, OP-AMP, TSOT23-5 LINEAR TECH., LT6202CS5#PBF 51 6 SHOWN ON ASSY DWG SHUNT, 0.100 SAMTEC, SNT-100-BK-G 52 4 MH1-MH4 STANDOFF, NYLON 0.25" KEYSTONE, 8831 (SNAP ON) 0 R34 RES, DNI, 0402 DC2290A-A 1 2 1 R33 RES.,1.00k, 1/10W, 5%, 0402 PANASONIC, ERJ-2GEYJ102V 3 1 U10 I.C., SAR ADC, QFN32UH-5×5 LINEAR TECH., LTC2387CUH-18#PBF PANASONIC, ERJ-2GEYJ102V DC2290A-B 1 1 R34 RES.,1.00k, 1/10W, 5%, 0402 2 0 R33 RES.,DNI, 0402 3 1 U10 I.C., SAR ADC, QFN32UH-5×5 1 0 R34 RES, DNI, 0402 2 1 R33 RES.,1.00k, 1/10W, 5%, 0402 PANASONIC, ERJ-2GEYJ102V 3 1 U10 I.C., SAR ADC, QFN32UH-5×5 LINEAR TECH., LTC2386CUH-18#PBF 1 1 R34 RES.,1.00k, 1/10W, 5%, 0402 PANASONIC, ERJ-2GEYJ102V 2 0 R33 RES.,DNI, 0402 3 1 U10 I.C., SAR ADC, QFN32UH-5×5 1 0 R34 RES, DNI, 0402 2 1 R33 RES.,1.00k, 1/10W, 5%, 0402 PANASONIC, ERJ-2GEYJ102V 3 1 U10 I.C., SAR ADC, QFN32UH-5×5 LINEAR TECH., LTC2385CUH-18#PBF 1 1 R34 RES.,1.00k, 1/10W, 5%, 0402 PANASONIC, ERJ-2GEYJ102V 2 0 R33 RES.,DNI, 0402 3 1 U10 I.C., SAR ADC, QFN32UH-5×5 LINEAR TECH., LTC2387CUH-16#PBF DC2290A-C DC2290A-D LINEAR TECH., LTC2386CUH-16#PBF DC2290A-E DC2290A-F LINEAR TECH., LTC2385CUH-16#PBF dc2290afb 5 A B C TP18 TP17 TP16 TP14 E10 TP19 E9 TP15 +6V C90 47uF 1210 C40 3.3uF C66 1uF C51 1uF C31 1uF C71 1uF 5 8 5 8 5 8 5 8 5 8 SHDN IN U5 LT3021ES8-1.2 SHDN IN U12 LT1763CS8-2.5 SHDN IN U8 LT1763CS8-2.5 SHDN IN U4 LT1763CS8 SHDN IN U13 LT1763CS8-5 GND GND GND 3 6 7 GND GND GND 3 6 7 GND GND GND Powers the voltage reference IC. 2 * SEN OUT BYP SEN OUT BYP SEN OUT BYP SEN OUT BYP SEN OUT 3 2 4 2 1 4 2 1 4 2 1 4 2 1 R27 1k R28 1.43k C68 10uF 0805 E6 Powers the ADC. +3V C32 10uF 0805 E2 E4 E3 +2.5V L2 33 Ohm FB L1 33 Ohm FB L3 33 Ohm FB C37 10uF 0805 L5 33 Ohm FB VCC_1.2V Powers the CPLD VCCINT. C59 10uF 0805 VDDL Powers the ADC. C47 10uF 0805 OVDD Powers the CPLD VCCIO. Powers the CPLD VCCA. Powers the CPLD VCCPLL. Powers the ADC I/O. VCCA_2.5V VCCIO_2.5V VCCPLL_1.2V TP3 TP5 TP1 TP2 Powers the logic inverters (3PL), flip-flop. E1 Powers the CPLD mamory device. C65 0.01uF C48 0.01uF C25 0.01uF C70 0.01uF VDD VCMMN J6 J5 TP10 1 U17 LT6202CS5 - + C87 +6V 0.1uF R50 10 R49 10 4 3 C74 DNI R54 10K 0402 R53 10K 0402 VREF C75 82pF C73 82pF C80 4.7uF TP8 R44 0 TP7 VCM C76 2.2uF C60 4.7uF 5 6 7 8 REFIN E5 C57 0.1uF 0402 C77 10uF 0805 R38 DNI C64 10uF 0805 REFBUF VDD C53 4.7uF R41 49.9 1206 C67 0.1uF GND GND VIN SHDN GND VOUT_S VOUT_F GND 4 3 2 1 U14 LTC6655BHMS8-4.096 +6V JP2 JP4 JP3 C69 1uF 3 2 1 3 2 1 3 2 1 2 4 C63 0.1uF OVDD R36 33 DB+ DB- VDDL OVDD DA+ DA- CLK+ CLK- CNV+ CNV- CLR DA+ DA- DCO+ DCO- DB+ DB- C49 0.1uF 0402 R37 33 PR VCC CLK+ CLK- R35 100 0201 1 Thursday, December 03, 2015 B C D 1 2 A TP6 0.1uF C54 CLKIN 8 7 +2.5V TP13 R32 33 GND 2_LANE 18 17 24 23 28 27 20 19 16 15 C99 4.7uF DCO+ DCO- 6 4 CLK U9 NL17SZ74 U11 NC7SZ04P5X +2.5V VDDL C58 0.1uF 0402 R39 1K R40 1K +2.5V REFIN VCM REFBUF REFBUF IN+ IN- C56 0.1uF 0402 9 32 7 8 2 3 C55 0.1uF 0402 TP4 U10 LTC238X-XX C52 4.7uF J4 1 TECHNOLOGY E7 TP9 CNV_EN This circuit conditions the edges of the CNV pulse as follows: The rising edge of CNV is driven by a rising edge of CLKIN. The falling edge of CNV is driven by a falling edge of CNV_EN, so it is wider than 'N' clock cycles. The circuit serves to eliminate jitter on the CNV pulse due to CPLD jitter. The risiing edge of the CNV pulse is thus driven by CLKIN, not CNV_EN. 12 11 VDD VDD 3 6 7 GND GND GND 3 6 7 GND 6 AGND 4 GND GND GND GND GND GND GND 1 4 10 21 26 29 33 5 3 OVDD 31 30 REFGND REFGND 5 6 VDDL VDDL TESTPAT 14 D 5 2 TWOLANES 25 22 ~PD 13 2 D Q 1 CP Q 3 6 5 2 DEMO MANUAL DC2290A Schematic Diagram dc2290afb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. A B 19 27 36 41 48 57 63 82 95 108 118 123 131 140 145 C23 0.1uF R24 4.99K 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 R22 4.99K 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 1 2 3 DB8 DB7 DB6 DB5 DB4 DB3 DB2 JP1 CLK2 CLK3 IO1 IO2 IO3_VREF2 IO4_RUP1 IO5_RDN1 IO6 CYCLONE3-EP3C5E144 U3C R26 4.99K 0402 0402 0402 0402 0402 0402 0402 J1 PCB EDGE CONN. R8 33 R7 33 R5 33 R4 33 R3 33 R2 33 R1 33 24 25 28 30 31 32 33 34 VCCD_PLL1 VCCD_PLL2 VCCA1 VCCA2 VCCIO8 VCCIO8 VCCIO7 VCCIO7 VCCIO6 VCCIO5 VCCIO4 VCCIO4 VCCIO3 VCCIO3 VCCIO2 VCCIO1 VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT 37 109 35 107 130 139 117 122 93 81 56 62 40 47 26 17 5 29 45 61 78 102 116 134 + C97 47uF 0805 C27 0.1uF 0402 C96 4.7uF C24 0.1uF 0402 C11 0.01uF 0402 C26 0.1uF 0402 C20 0.1uF 0402 C10 0.01uF 0402 C38 0.1uF 0402 C7 22nF 0402 VCCA_2.5V C15 0.1uF 0402 2 38 39 42 43 44 46 49 50 51 52 53 C8 4.7nF 0402 VCCPLL_1.2V C95 2.2nF 0402 C19 0.1uF 0402 +3V CYCLONE3-EP3C5E144 C4 0.1uF 0402 C35 0.1uF 0402 C42 22nF 0402 C44 0.1uF 0402 IO1_DIFFIOB1P IO2_DIFFIOB1N IO3 IO4 IO5 IO6_VREF3 IO7_DIFFIOB9P IO8_DIFFIOB9N IO9 IO10_DIFFIOB11P IO11_DIFFIOB11N U3D VCC_1.2V DB14 DB13 DB12 DB11 DB10 DB9 C3 0.1uF 0402 C1 0.1uF 0402 0402 0402 0402 0402 0402 0402 C36 0.1uF 0402 C41 22nF 0402 C45 0.1uF 0402 C2 0.1uF 0402 C18 0.1uF 0402 C33 0.1uF 0402 C6 4.7uF C28 0.1uF 0402 C14 0.1uF 0402 C29 0.1uF 0402 C34 0.1uF 0402 C5 47uF 0805 C30 0.1uF 0402 C22 0.1uF 0402 C46 0.1uF 0402 R19 33 R18 33 R17 33 R16 33 R15 33 R14 33 VCCIO_2.5V C98 0.1uF 0402 Note that only the VCCIO rails may be changed. 6 5 7 3 2 1 CYCLONE3-EP3C5E144 GND GND GNDA1 GND GND GND GND GND GND GNDA2 GND GND GND GND GND SCL SDA WP A2 A1 A0 U2 24LC024-I /ST U3A 1 2 3 4 7 10 11 22 23 OUTPUT_LATCH DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 C VCC GND 4 DB17 DB16 8 CYCLONE3-EP3C5E144 IO1 IO2 IO3 IO4 IO5_VREF1 IO6_DIFFL4P IO7_DIFFL4N CLK0 CLK1 CYCLONE3-EP3C5E144 IO1_DIFFIOB12P IO2_DIFFIOB12N IO3 IO4_DIFFIOB16P IO5_DIFFIOB16N IO6 IO7_VREF4 IO8_RUP2 IO9_RDN2 IO10 IO11 IO12_DIFFIOB21P IO13_DIFFIOB21N IO14 U3E 54 55 58 59 60 64 65 66 67 68 69 70 71 72 CNV_EN CYCLONE3-EP3C5E144 IO1 IO2 IO3 IO4_RUP3 IO4_RDN3 IO5 IO6_VREF5 IO7 IO8_DIFFIOR8N IO9_DIFFIOR8P CLK7_DIFFCLK3N CLK6_DIFFCLK3P U3F 73 74 75 76 77 79 80 83 84 85 88 89 6 8 9 12 13 14 15 16 18 20 21 86 87 92 94 96 97 98 99 101 103 DATA1 FLASH_nCE nSTATUS DCLK DATA0 nCONFIG TDI TCK TMS TDO NCE +3V R6 10K DCO+ DB- R29 100 0201 DB+ DA- R30 100 0201 DA+ DCO- R31 100 0201 R72 DNI R71 0 R9 10K R11 1K R10 10K R34 DNI R33 1K R13 10K C16 10pF +3V C17 0.1uF 0402 EPCS4SI8 nCS DATA VCC GND U1 1 3 5 7 9 D2 BAT54WS C13 10pF IO1_DIFFIOT11N IO2_DIFFIOT11P IO3_DIFFIOT10N IO4_DIFFIOT10P IO5 IO6_VREF8 IO7 IO8 IO9 IO10 IO11_DIFFIOT01N IO12_DIFFIOT01P 128 129 132 133 135 136 137 138 141 142 143 144 R21 33 R20 33 R69 33 R68 33 0402 0402 0402 0402 CYCLONE3-EP3C5E144 U3I C21 10pF D4 BAT54WS TDI 110 111 112 113 114 115 119 120 121 124 125 126 127 +3V CYCLONE3-EP3C5E144 TCK TDO TMS 8 7 6 5 IO1 IO2 IO3 IO4 IO5_RUP4 IO6_RDN4 IO7_VREF7 IO8_DIFFIOT16N IO9_DIFFIOT16P IO10 IO11 IO12_DIFFIOT12N IO13_DIFFIOT12P U3H DB16 DB1 DB0 DB17 C9 10pF +3V VCC VCC DCLK ASDI J3 HD2X5-100 2 4 6 8 10 J2 HD2X5-100 D1 BAT54WS +3V 1 2 3 4 +3V 2 4 6 8 10 1 3 5 7 9 CLKIN 90 91 100 104 105 106 VCCA_2.5V CYCLONE3-EP3C5E144 CLK5_DIFFCLK2N CLK4_DIFFCLK2P IO1 IO2 IO3_VREF6 IO4 U3G C12 0.1uF 0402 D3 BAT54WS +3V R12 10K CLK- CLK+ VCCIO_2.5V 2_LANE MSEL[0,1,2] pins must be set as follows: For VCCIO = 2.5V/3.0V: 1 1 0 For VCCIO = 3.3V: 0 1 0 C43 0.1uF 0402 VCCA_2.5V CONF_DONE R70 10K VCCIO_2.5V Be sure to disable the following pin options in Quartus: DEV_OE, DEV_CLRn, INIT_DONE, CRC_ERROR ,CLK_USR, nCEO OUTPUT_LATCH DB15 ASDO nCSO nSTATUS DCLK IO3_DATA0 nCONFIG TDI TCK TMS TDO nCE IO4_DEV_OE IO5_DEV_CLRn CONF_DONE MSEL0 MSEL1 MSEL2 IO6_INIT_DONE IO7_CRC_ERROR IO8_nCEO IO9_CLKUSR 0402 0402 CYCLONE3-EP3C5E144 U3J R25 33 R23 33 1 2 U3B 1 2 D 1 2 1 2 2 TECHNOLOGY 1 Wednesday, May 27, 2015 B C D 2 2 A 1 DEMO MANUAL DC2290A Schematic Diagram dc2290afb 7 DEMO MANUAL DC2290A DEMONSTRATION BOARD IMPORTANT NOTICE Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions: This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations. If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive. Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and observe good laboratory practice standards. Common sense is encouraged. This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC application engineer. Mailing Address: Linear Technology 1630 McCarthy Blvd. Milpitas, CA 95035 Copyright © 2004, Linear Technology Corporation 8 dc2290afb Linear Technology Corporation LT 0116 REV B • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2015