40001775B

PIC16(L)F1764/5/8/9
14/20-Pin, 8-Bit Flash Microcontrollers
Description
The PIC16(L)F1764/5/8/9 family offers intelligent analog with digital peripherals to create up to two independent closedloop channels. These 14 and 20-pin devices enable the ability to interconnect the on-chip peripherals to create custom
functions specific to each application; helping simplify the implementation of a complex control system and give
designers the flexibility to innovate.
Core Features
Digital Peripherals
• C Compiler Optimized RISC Architecture
• Only 49 Instructions
• Operating Speed:
- DC – 32 MHz clock input
- 125 ns minimum instruction cycle
• Interrupt Capability
• 16-Level Deep Hardware Stack
• Up to Four 8-Bit Timers
• Up to Three 16-Bit Timers
• Power-on Reset (POR)
• Configurable Power-up Timer (PWRT)
• Brown-out Reset (BOR) with Selectable Trip Point
• Extended Watchdog Timer (EWDT):
- Low-power 31 kHz WDT
- Software-selectable prescaler
- Software-selectable enable
• Configurable Logic Cell (CLC):
- Up to three CLCs; up to four selected inputs
- Integrated combinational and state logic
• Up to Two Complementary Output Generators
(COG):
- Push-Pull, Full-Bridge and Steering modes
• Up to Two Capture/Compare/PWM (CCP)
modules
• Pulse-Width Modulators (PWM):
- Up to two 10-bit PWMs
- Up to two 16-bit PWMs
• Peripheral Pin Select (PPS):
- Configure any digital pin to output
• Serial Communications:
- Enhanced USART (EUSART)
- SPI, I2C, RS-232, RS-485, LIN compatible
- Auto-Baud Detect, auto-wake-up on start
• Up to 18 I/O Pins:
- Individually programmable pull-ups
- Slew rate control
- Interrupt-On-Change (IOC) with edge select
• Up to Two Data Signal Modulators (DSM)
Memory
•
•
•
•
Up to 14 Kbytes Flash Program Memory
Up to 1024 Bytes Data RAM Memory
Direct, Indirect and Relative Addressing modes
High-Endurance Flash (HEF):
- 128B of nonvolatile data storage
- 100K erase/write cycles
Operating Characteristics
• Operating Voltage Range:
- 1.8V to 3.6V (PIC16LF1764/5/8/9)
- 2.3V to 5.5V (PIC16F1764/5/8/9)
• Temperature Range:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
eXtreme Low-Power (XLP) Features
•
•
•
•
Sleep mode: 50 nA @ 1.8V, typical
Watchdog Timer: 500 nA @ 1.8V, typical
Secondary Oscillator: 500 nA @ 32 kHz
Operating Current:
- 8 A @ 32 kHz, 1.8V, typical
- 32 A/MHz @ 1.8V, typical
• Low-Power BOR (LPBOR):
- 200 nA in Sleep
 2014-2015 Microchip Technology Inc.
Intelligent Analog Peripherals
• 10-Bit Analog-to-Digital Converter (ADC):
- Up to 12 external channels
- Conversion available during Sleep
• Up to Two Operational Amplifiers (OPA):
- Selectable internal and external channels
• Up to Four Fast Comparators (COMP):
- Up to five external inverting inputs
- Up to eight external non-inverting inputs
- Fixed Voltage Reference at non-inverting
input(s)
- Comparator outputs externally accessible
• Digital-to-Analog Converters (DAC):
- Up to two 10-bit resolution DACs
- Up to two 5-bit resolution DACs
DS40001775B-page 1
PIC16(L)F1764/5/8/9
Intelligent Analog Peripherals (Cont.)
Clocking Structure
• Voltage Reference:
- Fixed Voltage Reference (FVR): 1.024V,
2.048V and 4.096V output levels
• Zero-Cross Detector (ZCD):
- Detect high-voltage AC signal
• Programmable Ramp Generator (PRG):
- Slope compensation
- Ramp generation
• High-Current Drive I/Os:
- 100 mA capacity @ 5V
• 16 MHz Internal Oscillator:
- ±1% at calibration
- Selectable frequency range, 32 MHz to
31 kHz
• 31 kHz Low-Power Internal Oscillator
• 4x Phase-Locked Loop (PLL):
- For up to 32 MHz internal operation
• External Oscillator Block with:
- Three External Clock modes up to 32 MHz
Debug(1)
I2C/SPI
EUSART
Peripheral Pin Select
High-Current I/Os
Programmable Ramp Gen
Zero-Cross Detect
Op Amp
CLC
1/3
Data Signal Modulator
3
COG
8-Bit Timers w/HLT
12
10/16-Bit PWM
16-Bit Timers
512
CCP
I/O Pins(2)
128
5/10-Bit DAC
Data SRAM (Bytes)
4096/7
10-Bit ADC (ch)
High-Endurance Flash (B)
PIC16(L)F1764 (A)
Comparator
Program Memory Flash
(Words/Kbytes)
Device
PIC16(L)F1764/5/8/9 FAMILY TYPES
Data Sheet Index
TABLE 1:
2
8
1/1
1
1/1
1
1
3
1
1
1
2
Y
1
1
I/H
PIC16(L)F1765 (A) 8192/14 128 1024 12
3
1/3
2
8
1/1
1
1/1
1
1
3
1
1
1
2
Y
1
1
I/H
PIC16(L)F1768 (A)
18
3
1/3
4
12
2/2
2
2/2
2
2
3
2
1
2
2
Y
1
1
I/H
PIC16(L)F1769 (A) 8192/14 128 1024 18
3
1/3
4
12
2/2
2
2/2
2
2
3
2
1
2
2
Y
1
1
I/H
Note
1:
2:
4096/7
128
512
Debugging Methods: (I) – Integrated on Chip; (H) – via ICD Header; E – Emulation Product.
One pin is input-only.
Data Sheet Index: (Unshaded devices are described in this document.)
A.
DS-40001775 PIC16(L)F1764/5/8/9 Data Sheet, 14/20-Pin 8-Bit Flash Microcontrollers.
Note:
For other small form factor package availability and marking information, please visit
http://www.microchip.com/packaging or contact your local sales office.
TABLE 2:
PACKAGES
Packages
PIC16(L)F1764
PIC16(L)F1765
PIC16(L)F1768
PIC16(L)F1769
Note:
PDIP
SOIC
TSSOP
QFN
SSOP
















Pin details are subject to change.
DS40001775B-page 2
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
PIN DIAGRAMS
VDD
1
RA5
2
RA4
3
MCLR/VPP/RA3
4
RC5
5
RC4
6
RC3
7
PIC16(L)F1765
14-PIN PDIP, SOIC, TSSOP
PIC16(L)F1764
FIGURE 1:
14
13
VSS
RA0/ICSPDAT
12
RA1/ICSPCLK
11
RA2
10
RC0
9
RC1
8
RC2
Note: See Table 3 for location of all peripheral functions.
VSS
NC
NC
16-PIN QFN (4x4)
VDD
FIGURE 2:
16 15 14 13
12 RA0
RA5 1
RA4 2
MCLR/VPP/RA3 3
PIC16(L)F1764
PIC16(L)F1765
11 RA1
10 RA2
9 RC0
5
6
7
8
RC4
RC3
RC2
RC1
RC5 4
Note: See Table 3 for location of all peripheral functions.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 3
PIC16(L)F1764/5/8/9
20-PIN PDIP, SOIC, SSOP
VDD
1
RA5
2
20 VSS
19 RA0
RA4
3
18 RA1
MCLR/VPP/RA3
4
17 RA2
RC5
5
RC4
6
RC3
7
RC6
8
RC7
9
12 RB5
RB7
10
11 RB6
PIC16(L)F1768
PIC16(L)F1769
FIGURE 3:
16 RC0
15 RC1
14 RC2
13 RB4
Note: See Table 4 for location of all peripheral functions.
RA0
VSS
VDD
RA5
20-PIN QFN (4x4)
RA4
FIGURE 4:
20 19 18 17 16
15 RA1
MCLR/VPP/RA3 1
RC5 2
RC4 3
PIC16(L)F1768
PIC16(L)F1769
14 RA2
13 RC0
7
8
9 10
RB4
6
RB5
11 RC2
RB6
RC6 5
RB7
12 RC1
RC7
RC3 4
Note: See Table 4 for location of all peripheral functions.
DS40001775B-page 4
 2014-2015 Microchip Technology Inc.
Op Amp
Comparator
Zero Cross
Programmable
Ramp Generator
Timers
PWM
CCP
COG
CLC
Modulator
EUSART
MSSP
Interrupts
Pull-ups
Hi Current
Basic
12
AN0
VREFDAC1REFDAC3REF-
DAC1OUT1
DAC3OUT1
—
C1IN0+
—
—
—
—
—
—
—
—
—
—
IOC
Y
—
ICSPDAT
RA1
12
11
AN1
VREF+
DAC1REF+
DAC3REF+
—
—
C1IN0C2IN0-
—
—
—
—
—
—
—
—
—
—
IOC
Y
—
ICSPCLK
RA2
11
10
AN2
—
—
—
—
ZCD
—
T0CKI(1)
—
—
COG1IN(1)
—
—
—
—
INT(1)
IOC
Y
—
—
RA3
4
3
—
—
—
—
—
—
—
T6CKI(1)
—
—
—
—
MD1CH(1)
—
—
IOC
Y
—
VPP
MCLR
RA4
3
2
AN3
—
—
—
—
—
—
T1G(1)
SOSCO
—
—
—
—
MD1CL(1)
—
—
IOC
Y
—
OSC2
CLKOUT
RA5
2
1
—
—
—
—
—
—
—
T1CKI(1)
T2CKI(1)
SOSCI
—
—
—
CLCIN3(1)
MD1MOD(1)
—
—
IOC
Y
—
OSC1
CLKIN
RC0
10
9
AN4
—
—
OPA1IN+
C2IN0+
—
—
T5CKI(1)
—
—
—
—
—
—
SCL(1)
SCK(1,3)
IOC
Y
—
—
RC1
9
8
AN5
—
—
OPA1IN-
C1IN1C2IN1-
—
—
T4CKI(1)
—
—
—
CLCIN2(1)
—
—
SDI(1)
SDA(1,3)
IOC
Y
—
—
RC2
8
7
AN6
—
—
OPA1OUT
C1IN2C2IN2-
—
PRG1IN0
—
—
—
—
—
—
—
—
IOC
Y
—
—
RC3
7
6
AN7
—
—
—
C1IN3C2IN3-
—
—
T5G(1)
—
—
—
CLCIN0(1)
—
—
SS(1)
IOC
Y
—
—
RC4
6
5
—
—
—
—
—
—
PRG1R(1)
T3G(1)
—
—
—
CLCIN1(1)
—
CK(1)
—
IOC
Y
Y
—
RC5
5
4
—
—
—
—
—
—
PRG1F(1)
T3CKI(1)
—
CCP1(1)
—
—
—
RX(1,3)
—
IOC
Y
Y
—
VDD
1
16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDD
VSS
14
13
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VSS
OUT(2)
—
—
—
—
—
—
C1OUT
—
—
—
PWM3
CCP1
COG1A
CLC1OUT
MD1OUT
DT(3)
SDO
INT
—
—
—
—
—
—
—
—
—
C2OUT
—
—
—
PWM5
—
COG1B
CLC2OUT
—
TX
SDA(3)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
COG1C
CLC3OUT
—
CK
SCK
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
COG1D
—
—
—
SCL(3)
—
—
—
—
DAC
13
Reference
ADC
RA0
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS Input Selection register. See Table 12-1.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS Output Selection registers. See Table 12-2.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
PIC16(L)F1764/5/8/9
DS40001775B-page 5
16-Pin QFN
14-PIN AND 16-PIN ALLOCATION TABLE (PIC16(L)F1764/5)
14-Pin PDIP/SOIC/TSSOP
TABLE 3:
I/O
 2014-2015 Microchip Technology Inc.
PIN ALLOCATION TABLES
Comparator
Zero Cross
Programmable
Ramp Generator
Timers
PWM
CCP
COG
CLC
Modulator
EUSART
MSSP
Interrupts
Pull-ups
Hi Current
Basic
16
AN0
VREFDAC1REFDAC2REFDAC3REFDAC4REF-
DAC1OUT1
DAC2OUT1
DAC3OUT1
DAC4OUT1
—
C1IN0+
C3IN0+
—
—
—
—
—
—
—
—
—
—
IOC
Y
—
ICSPDAT
RA1
18
15
AN1
VREF+
DAC1REF+
DAC2REF+
DAC3REF+
DAC4REF+
—
—
C1IN0C2IN0C3IN0C4IN0-
—
—
—
—
—
—
—
—
—
—
IOC
Y
—
ICSPCLK
RA2
17
14
AN2
—
—
—
—
ZCD
—
T0CKI(1)
—
—
COG1IN(1)
COG2IN(1)
—
—
—
—
INT(1)
IOC
Y
—
—
RA3
4
1
—
—
—
—
—
—
—
T6CKI(1)
—
—
—
—
MD1CH(1)
MD2CH(1)
—
—
IOC
Y
—
VPP
MCLR
ICD
RA4
3
20
AN3
—
—
—
—
—
—
T1G(1)
SOSCO
—
—
—
—
MD1CL(1)
MD2CL(1)
—
—
IOC
Y
—
OSC2
CLKOUT
RA5
2
19
—
—
—
—
—
—
—
T1CKI(1)
T2CKI(1)
SOSCI
—
—
—
CLCIN3(1)
MD1MOD(1)
MD2MOD(1)
—
—
IOC
Y
—
OSC1
CLKIN
RB4
13
10
AN10
—
—
OPA1IN0-
—
—
—
—
—
—
—
—
—
—
SDI(1)
SDA(1,3)
IOC
Y
—
—
RB5
12
9
AN11
—
—
OPA1IN0+
—
—
—
—
—
—
—
—
—
RX(1,3)
—
IOC
Y
—
—
RB6
11
8
—
—
—
—
C1IN1+
C3IN1+
—
—
—
—
—
—
—
—
—
SCL(1)
SCK(1,3)
IOC
Y
—
—
RB7
10
7
—
—
—
—
C2IN1+
C4IN1+
—
—
—
—
—
—
—
—
CK(1)
—
IOC
Y
—
—
RC0
16
13
AN4
—
—
—
C2IN0+
C4IN0+
—
—
T5CKI(1)
—
—
—
—
—
—
—
IOC
Y
—
—
RC1
15
12
AN5
—
—
—
C1IN1C2IN1C3IN1C4IN1-
—
—
T4CKI(1)
—
—
—
CLCIN2(1)
—
—
—
IOC
Y
—
—
RC2
14
11
AN6
—
—
OPA1OUT
OPA2IN1OPA2IN1+
C1IN2C2IN2-
—
PRG1IN0
PRG2IN1
—
—
—
—
—
—
—
—
IOC
Y
—
—
Op Amp
ADC
19
DAC
20-Pin QFN
RA0
Reference
20-Pin PDIP/SOIC/SSOP
 2014-2015 Microchip Technology Inc.
I/O
20-PIN ALLOCATION TABLE (PIC16(L)F1768/9)
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS Input Selection register. See Table 12-1.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS Output Selection registers. See Table 12-2.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
PIC16(L)F1764/5/8/9
DS40001775B-page 6
TABLE 4:
ADC
Reference
DAC
Comparator
Zero Cross
Timers
PWM
CCP
COG
CLC
Modulator
EUSART
MSSP
Interrupts
Pull-ups
Hi Current
Basic
7
4
AN7
—
—
OPA2OUT
OPA1IN1OPA1IN1+
C1IN3C2IN3C3IN3C4IN3-
—
PRG2IN0
PRG1IN1
T5G(1)
—
CCP2(1)
—
CLCIN0(1)
—
—
—
IOC
Y
—
—
RC4
6
3
—
—
—
—
—
—
PRG1R(1)
PRG2R(1)
T3G(1)
—
—
—
CLCIN1(1)
—
—
—
IOC
Y
Y
—
RC5
5
2
—
—
—
—
—
—
PRG1F(1)
PRG2F(1)
T3CKI(1)
—
CCP1(1)
—
—
—
—
—
IOC
Y
Y
—
RC6
8
5
AN8
—
—
OPA2IN0-
—
—
—
—
—
—
—
—
—
—
SS(1)
IOC
Y
—
—
RC7
9
6
AN9
—
—
OPA2IN0+
—
—
—
—
—
—
—
—
—
—
—
IOC
Y
—
—
VDD
1
18
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VSS
Programmable
Ramp Generator
20-Pin QFN
RC3
Op Amp
20-Pin PDIP/SOIC/SSOP
20-PIN ALLOCATION TABLE (PIC16(L)F1768/9) (CONTINUED)
I/O
 2014-2015 Microchip Technology Inc.
TABLE 4:
17
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C1OUT
—
—
—
PWM3
CCP1
COG1A
CLC1OUT
MD1OUT
DT(3)
SDO
—
—
—
—
—
—
—
—
—
—
C2OUT
—
—
—
PWM4
CCP2
COG1B
CLC2OUT
MD2OUT
TX
SDA(3)
—
—
—
—
—
—
—
—
—
—
C3OUT
—
—
—
PWM5
—
COG1C
CLC3OUT
—
CK
SCK
—
—
—
—
—
—
—
—
—
—
C4OUT
—
—
—
PWM6
—
COG1D
—
—
—
SCL(3)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
COG2A
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
COG2B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
COG2C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
COG2D
—
—
—
—
—
—
—
—
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS Input Selection register. See Table 12-1.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS Output Selection registers. See Table 12-2.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
DS40001775B-page 7
PIC16(L)F1764/5/8/9
20
OUT(2) —
PIC16(L)F1764/5/8/9
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 11
2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 23
3.0 Memory Organization ................................................................................................................................................................. 25
4.0 Device Configuration .................................................................................................................................................................. 63
5.0 Oscillator Module (with Fail-Safe Clock Monitor) ....................................................................................................................... 71
6.0 Resets ........................................................................................................................................................................................ 89
7.0 Interrupts .................................................................................................................................................................................... 99
8.0 Power-Down Mode (Sleep) ...................................................................................................................................................... 113
9.0 Watchdog Timer (WDT) ........................................................................................................................................................... 117
10.0 Flash Program Memory Control ............................................................................................................................................... 121
11.0 I/O Ports ................................................................................................................................................................................... 139
12.0 Peripheral Pin Select (PPS) Module ........................................................................................................................................ 157
13.0 Interrupt-On-Change ................................................................................................................................................................ 165
14.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 173
15.0 Temperature Indicator Module ................................................................................................................................................. 177
16.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 179
17.0 5-Bit Digital-to-Analog Converter (DAC) Module ...................................................................................................................... 193
18.0 10-Bit Digital-to-Analog Converter (DAC) Module .................................................................................................................... 197
19.0 Comparator Module.................................................................................................................................................................. 203
20.0 Zero-Cross Detection (ZCD) Module........................................................................................................................................ 213
21.0 Timer0 Module ......................................................................................................................................................................... 219
22.0 Timer1/3/5 Module with Gate Control....................................................................................................................................... 222
23.0 Timer2/4/6 Module ................................................................................................................................................................... 233
24.0 Capture/Compare/PWM Modules ............................................................................................................................................ 253
25.0 10-Bit Pulse-Width Modulation (PWM) Module ........................................................................................................................ 267
26.0 16-Bit Pulse-Width Modulation (PWM) Module ........................................................................................................................ 273
27.0 Complementary Output Generator (COG) Module................................................................................................................... 299
28.0 Configurable Logic Cell (CLC).................................................................................................................................................. 339
29.0 Operational Amplifier (OPA) Modules ...................................................................................................................................... 353
30.0 Programmable Ramp Generator (PRG) Module ...................................................................................................................... 359
31.0 Data Signal Modulator (DSM) .................................................................................................................................................. 373
32.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 383
33.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 439
34.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 469
35.0 Instruction Set Summary .......................................................................................................................................................... 471
36.0 Electrical Specifications............................................................................................................................................................ 485
37.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 519
38.0 Development Support............................................................................................................................................................... 533
39.0 Packaging Information.............................................................................................................................................................. 537
Appendix A: Data Sheet Revision History ......................................................................................................................................... 557
The Microchip Web Site .................................................................................................................................................................... 559
Customer Change Notification Service ............................................................................................................................................. 559
Customer Support ............................................................................................................................................................................. 559
Product Identification System ............................................................................................................................................................ 561
DS40001775B-page 8
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
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If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
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Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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 2014-2015 Microchip Technology Inc.
DS40001775B-page 9
PIC16(L)F1764/5/8/9
NOTES:
DS40001775B-page 10
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
Figure 1-1 shows a block diagram of the
PIC16(L)F1764/5 devices. Figure 1-2 shows a block
diagram of the PIC16(L)F1768/9 devices. Table 1-2 and
Table 1-3 show the pinout descriptions.
Refer to Table 1-1 for peripherals available per device.
DEVICE PERIPHERAL
SUMMARY
Enhanced Universal Synchronous/Asynchronous
Receiver/Transmitter (EUSART)
EUSART
●
●
●
●
MSSP
●
●
●
●
Op Amp 1
●
●
●
●
●
●
●
●
●
●
●
●
●
●
PIC16(L)F1765
PIC16(L)F1768
PIC16(L)F1769
Master Synchronous Serial Ports
PIC16(L)F1764
TABLE 1-1:
Peripheral
Analog-to-Digital Converter (ADC)
●
●
●
●
PWM3
Fixed Voltage Reference (FVR)
●
●
●
●
PWM4
Zero-Cross Detection (ZCD)
●
●
●
●
Temperature Indicator
●
●
●
●
●
●
●
●
●
Peripheral
Op Amp
Op Amp 2
10-Bit Pulse-Width Modulator (PWM)
●
PWM5
●
PRG2
●
●
●
●
●
Timer2
●
●
●
●
●
Timer4
●
●
●
●
●
●
Timer6
●
●
●
●
●
●
Timer1
●
●
●
●
●
●
Timer3
●
●
●
●
Timer5
●
●
●
●
5-Bit Digital-to-Analog Converter (DAC)
●
Timer0
16-Bit Timers
●
DAC2
DAC3
●
●
10-Bit Digital-to-Analog Converter (DAC)
DAC1
●
8-Bit Timers
Programmable Ramp Generator (PRG)
●
●
PWM6
COG2
PRG1
●
16-Bit Pulse-Width Modulator (PWM)
Complementary Output Generator (COG)
COG1
PIC16(L)F1769
The PIC16(L)F1764/5/8/9 are described within this data
sheet. See Table 2 for available package configurations.
DEVICE PERIPHERAL
SUMMARY (CONTINUED)
PIC16(L)F1768
TABLE 1-1:
PIC16(L)F1765
DEVICE OVERVIEW
PIC16(L)F1764
1.0
●
DAC4
●
●
●
●
Capture/Compare/PWM (CCP/ECCP) Modules
CCP1
●
●
CCP2
●
●
●
●
Comparators
C1
●
●
●
●
C2
●
●
●
●
C3
●
●
C4
●
●
Configurable Logic Cell (CLC)
CLC1
●
●
●
●
CLC2
●
●
●
●
CLC3
●
●
●
●
●
●
●
●
●
●
Data Signal Modulator (DSM)
DSM1
DSM2
 2014-2015 Microchip Technology Inc.
DS40001775B-page 11
PIC16(L)F1764/5/8/9
1.1
1.1.1
Register and Bit Naming
Conventions
REGISTER NAMES
When there are multiple instances of the same
peripheral in a device, the peripheral control registers
will be depicted as the concatenation of a peripheral
identifier, peripheral instance and control identifier. The
control registers section will show just one instance of
all the register names with an ‘x’ in the place of the
peripheral instance number. This naming convention
may also be applied to peripherals when there is only
one instance of that peripheral in the device to maintain
compatibility with other devices in the family that
contain more than one.
1.1.2
BIT NAMES
There are two variants for bit names:
• Short name: Bit function abbreviation
• Long name: Peripheral abbreviation + short name
1.1.2.1
Short Bit Names
Short bit names are an abbreviation for the bit function.
For example, some peripherals are enabled with the
EN bit. The bit names shown in the registers are the
short name variant.
Short bit names are useful when accessing bits in C
programs. The general format for accessing bits by the
short name is RegisterNamebits.ShortName. For
example, the enable bit, EN, in the COG1CON0 register can be set in C programs with the instruction
COG1CON0bits.EN = 1.
Short names are generally not useful in assembly
programs because the same name may be used by
different peripherals in different bit positions. When this
occurs, during the include file generation, all instances
of that short bit name are appended with an underscore
plus the name of the register in which the bit resides to
avoid naming contentions.
1.1.2.2
Long Bit Names
Long bit names are constructed by adding a peripheral
abbreviation prefix to the short name. The prefix is
unique to the peripheral thereby making every long bit
name unique. The long bit name for the COG1 enable
bit is the COG1 prefix, G1, appended with the enable
bit short name, EN, resulting in the unique bit name
G1EN.
Long bit names are useful in both C and assembly programs. For example, in C the COG1CON0 enable bit
can be set with the G1EN = 1 instruction. In assembly,
this bit can be set with the BSF COG1CON0,G1EN
instruction.
DS40001775B-page 12
1.1.2.3
Bit Fields
Bit fields are two or more adjacent bits in the same
register. Bit fields adhere only to the short bit naming
convention. For example, the three Least Significant
bits of the COG1CON0 register contain the mode
control bits. The short name for this field is MD. There
is no long bit name variant. Bit field access is only
possible in C programs. The following example
demonstrates a C program instruction for setting the
COG1 to the Push-Pull mode:
COG1CON0bits.MD = 0x5;
Individual bits in a bit field can also be accessed with
long and short bit names. Each bit is the field name
appended with the number of the bit position within the
field. For example, the Most Significant mode bit has
the short bit name MD2, and the long bit name is
G1MD2. The following two examples demonstrate
assembly program sequences for setting the COG1 to
Push-Pull mode:
Example 1:
MOVLW
ANDWF
MOVLW
IORWF
~(1<<G1MD1)
COG1CON0,F
1<<G1MD2 | 1<<G1MD0
COG1CON0,F
Example 2:
BSF
BCF
BSF
COG1CON0,G1MD2
COG1CON0,G1MD1
COG1CON0,G1MD0
1.1.3
1.1.3.1
REGISTER AND BIT NAMING
EXCEPTIONS
Status, Interrupt and Mirror Bits
Status, interrupt enables, interrupt flags and mirror bits
are contained in registers that span more than one
peripheral. In these cases, the bit name shown is
unique, so there is no prefix or short name variant.
1.1.3.2
Legacy Peripherals
There are some peripherals that do not strictly adhere
to these naming conventions. Peripherals that have
existed for many years and are present in almost every
device are the exceptions. These exceptions were
necessary to limit the adverse impact of the new
conventions on legacy code. Peripherals that do
adhere to the new convention will include a table in the
registers section indicating the long name prefix for
each peripheral instance. Peripherals that fall into the
exception category will not have this table. These
peripherals include, but are not limited to, the following:
• EUSART
• MSSP
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
FIGURE 1-1:
PIC16(L)F1764/5 BLOCK DIAGRAM
Program
Flash Memory
PORTA
RAM
CLKOUT
Timing
Generation
CLKIN
HFINTOSC/
LFINTOSC
Oscillator
PORTC
CPU
Figure 1-1
MCLR
DSM
PRG
ZCD
Op Amp
Temp.
Indicator
Note 1:
Timers
8-Bit
PWMs
ADC
10-Bit
Timers
16-Bit
FVR
DAC
5-Bit
DAC
10-Bit
MSSP
Comparators
COG
CCP
EUSART
CLCs
See applicable chapters for more information on peripherals.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 13
PIC16(L)F1764/5/8/9
FIGURE 1-2:
PIC16(L)F1768/9 BLOCK DIAGRAM
Program
Flash Memory
PORTA
RAM
PORTB
CLKOUT
Timing
Generation
CLKIN
HFINTOSC/
LFINTOSC
Oscillator
PORTC
CPU
Figure 1-1
MCLR
DSMs
PRGs
ZCD
Op Amps
Temp.
Indicator
Note 1:
Timers
8-Bit
PWMs
ADC
10-Bit
Timers
16-Bit
FVR
DACs
5-Bit
DACs
10-Bit
MSSP
Comparators
COG
CCPs
EUSART
CLCs
See applicable chapters for more information on peripherals.
DS40001775B-page 14
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
TABLE 1-2:
PIC16(L)F1764/5 PINOUT DESCRIPTION
Name
RA0/AN0/C1IN0+/VREF-/
DAC1REF-/DAC3REF-/
DAC1OUT1/DAC3OUT1/
ICSPDAT
Function
RA0
RA3/T6CKI/MD1CH/MCLR/VPP
RA4/AN3/SOSCO/T1G/
MD1CL/OSC2/CLKOUT
Description
TTL/ST CMOS General purpose I/O.
AN
—
C1IN0+
AN
—
Comparator C1 positive input.
VREF-
AN
—
ADC negative reference.
DAC1REF-
AN
—
DAC1 negative reference.
DAC3REF-
AN
—
DAC3 negative reference.
DAC1OUT1
—
AN
DAC1 voltage output.
DAC3OUT1
—
AN
DAC3 voltage output.
RA1
ST
ADC Channel 0 input.
CMOS ICSP™ data I/O.
TTL/ST CMOS General purpose I/O.
AN1
AN
—
ADC Channel 1 input.
C1IN0-
AN
—
Comparator C1 negative input.
C2IN0-
AN
—
Comparator C2 negative input.
VREF+
AN
—
ADC positive reference.
DAC1REF+
AN
—
DAC1 positive reference.
DAC3REF+
AN
—
DAC3 positive reference.
ST
—
Serial programming clock.
ICSPCLK
RA2/AN2/ZCD/T0CKI/COG1IN/
INT
Output
Type
AN0
ICSPDAT
RA1/AN1/C1IN0-/C2IN0-/VREF+/
DAC1REF+/DAC3REF+/
ICSPCLK
Input
Type
RA2
TTL/ST CMOS General purpose I/O.
AN2
AN
—
ADC Channel 2 input.
ZCD
AN
—
Zero-Cross Detection input.
T0CKI
TTL/ST
—
Timer0 clock input.
COG1IN(1)
TTL/ST
—
Complementary Output Generator 1 input.
INT(1)
TTL/ST
—
Interrupt input.
RA3
TTL/ST
—
General purpose input.
T6CKI(1)
TTL/ST
—
Timer6 clock input.
MD1CH(1)
TTL/ST
—
Data Signal Modulator 1 high carrier input.
MCLR
ST
—
Master Clear input.
VPP
HV
—
Programming enable.
RA4
AN3
TTL/ST CMOS General purpose I/O.
AN
—
SOSCO
—
XTAL
T1G(1)
TTL/ST
—
MD1CL(1)
TTL/ST
—
OSC2
—
XTAL
CLKOUT
—
ADC Channel 3 input.
Secondary Oscillator connection.
Timer1 gate input.
Data Signal Modulator 1 low carrier input.
Crystal/Resonator (LP, XT, HS modes).
CMOS FOSC/4 output.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output
OD = Open-Drain
TTL = TTL compatible input ST
= Schmitt Trigger input with CMOS levels
I2C = Schmitt Trigger input with I2C
HV = High Voltage
XTAL = Crystal levels
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS Input Selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as peripheral digital outputs with the
PPS Output Selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 15
PIC16(L)F1764/5/8/9
TABLE 1-2:
PIC16(L)F1764/5 PINOUT DESCRIPTION (CONTINUED)
Name
RA5/T1CKI/T2CKI/CLCIN3/
MD1MOD/SOSCI/OSC1/CLKIN
Function
RA5
RC2/AN6/OPA1OUT/C1IN2-/
C2IN2-/PRG1IN0
RC3/AN7/C1IN3-/C2IN3-/T5G/
CLCIN0/SS
Description
TTL/ST CMOS General purpose I/O.
TTL/ST
—
Timer1 clock input.
T2CKI(1)
TTL/ST
—
Timer2 clock input.
CLCIN3(1)
TTL/ST
—
CLC Input 3.
Data Signal Modulator modulation input.
(1)
TTL/ST
—
SOSCI
—
XTAL
OSC1
XTAL
—
Crystal/Resonator (LP, XT, HS modes).
CLKIN
ST
—
External Clock input (EC mode).
RC0
Secondary Oscillator connection.
TTL/ST CMOS General purpose I/O.
AN4
AN
OPA1IN+
AN
—
Operational Amplifier 1 non-inverting input.
C2IN0+
AN
—
Comparator 2 positive input.
T5CKI(1)
TTL/ST
—
Timer5 clock input.
SCL(1,3)
I2C
—
I2C clock output.
TTL/ST
—
SPI clock input.
SCK(1)
RC1/AN5/OPA1IN-/C1IN1-/
C2IN1-/T4CKI/CLCIN2/SDI/SDA
Output
Type
T1CKI(1)
MD1MOD
RC0/AN4/OPA1IN+/C2IN0+/
T5CKI/SCL/SCK
Input
Type
RC1
ADC Channel 4 input.
TTL/ST CMOS General purpose I/O.
AN5
AN
XTAL
OPA1IN-
AN
—
Operational Amplifier 1 inverting input.
C1IN1-
AN
—
Comparator 1 negative input.
C2IN1-
AN
—
Comparator 2 negative input.
T4CKI(1)
TTL/ST
—
Timer4 clock input.
CLCIN2(1)
TTL/ST
—
CLC Input 2.
SDI(1)
TTL/ST
—
SPI data input.
SDA(1)
I2C
—
I2C data output.
RC2
ADC Channel 5 input.
TTL/ST CMOS General purpose I/O.
AN6
AN
—
OPA1OUT
—
AN
Operational Amplifier 1 output.
C1IN2-
AN
—
Comparator 1 negative input.
C2IN2-
AN
—
Comparator 2 negative input.
PRG1IN0
AN
—
Ramp Generator 1 reference voltage input.
RC3
ADC Channel 6 input.
TTL/ST CMOS General purpose I/O.
AN7
AN
—
ADC Channel 7 input.
C1IN3-
AN
—
Comparator 1 negative input.
C2IN3-
AN
—
Comparator 2 negative input.
T5G(1)
TTL/ST
—
Timer5 gate input.
CLCIN0(1)
TTL/ST
—
CLC Input 0.
TTL/ST
—
SPI Slave Select input.
(1)
SS
Legend: AN = Analog input or output CMOS = CMOS compatible input or output
OD = Open-Drain
TTL = TTL compatible input ST
= Schmitt Trigger input with CMOS levels
I2C = Schmitt Trigger input with I2C
HV = High Voltage
XTAL = Crystal levels
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS Input Selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as peripheral digital outputs with the
PPS Output Selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
DS40001775B-page 16
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
TABLE 1-2:
PIC16(L)F1764/5 PINOUT DESCRIPTION (CONTINUED)
Name
RC4/T3G/PRG1R/CLCIN1/CK
Function
RC4
Output
Type
Description
TTL/ST CMOS General purpose I/O.
T3G(1)
TTL/ST
—
Timer3 gate input.
PRG1R(1)
TTL/ST
—
Ramp generator set_rising input.
CLCIN1(1)
TTL/ST
—
CLC Input 1.
CK
TTL/ST
—
EUSART clock input.
RC5
TTL/ST CMOS General purpose I/O.
(1)
RC5/T3CKI/PRG1F/CCP1/RX
Input
Type
T3CKI(1)
TTL/ST
—
Timer3 clock input.
PRG1F(1)
TTL/ST
—
Ramp generator set_falling input.
CCP1(1)
TTL/ST
—
CCP1 capture input.
RX(1,3)
TTL/ST
—
EUSART receive input.
VDD
VDD
Power
—
Positive supply.
VSS
VSS
Power
—
Ground reference.
OUT
(2)
C1OUT
CMOS Comparator 1 output.
C2OUT
CMOS Comparator 2 output.
CCP1
MD1OUT
CMOS Compare/PWM1 output.
CMOS Data Signal Modulator 1 output.
PWM3
CMOS PWM3 output.
PWM5
CMOS PWM5 output.
COG1A
CMOS Complementary Output Generator Output A.
COG1B
CMOS Complementary Output Generator Output B.
COG1C
CMOS Complementary Output Generator Output C.
COG1D
CMOS Complementary Output Generator Output D.
SDA(3)
SCK
SCL
(3)
SDO
OD
I2C data output.
CMOS SPI clock output.
OD
I2C clock output.
CMOS SPI data output.
TX
CMOS EUSART asynchronous TX data out.
CK
CMOS EUSART synchronous clock out.
DT(3)
CMOS EUSART synchronous data output.
CLC1OUT
CMOS Configurable Logic Cell 1 output.
CLC2OUT
CMOS Configurable Logic Cell 2 output.
CLC3OUT
CMOS Configurable Logic Cell 3 output.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output
OD = Open-Drain
TTL = TTL compatible input ST
= Schmitt Trigger input with CMOS levels
I2C = Schmitt Trigger input with I2C
HV = High Voltage
XTAL = Crystal levels
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS Input Selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as peripheral digital outputs with the
PPS Output Selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 17
PIC16(L)F1764/5/8/9
TABLE 1-3:
PIC16(L)F1768/9 PINOUT DESCRIPTION
Name
Function
RA0/AN0/C1IN0+/C3IN0+/VREF-/
DAC1REF-/DAC2REF-/
DAC3REF-/DAC4REF-/
DAC1OUT1/DAC2OUT1./
DAC3OUT1/DAC4OUT1/
ICSPDAT
RA0
RA2/AN2/ZCD/T0CKI/COG1IN/
COG2IN/INT
Description
TTL/ST CMOS General purpose I/O.
AN
—
ADC Channel 0 input.
C1IN0+
AN
—
Comparator C1 positive input.
C3IN0+
AN
DAC1REF-
AN
—
DAC1 negative reference.
DAC2REF-
AN
—
DAC2 negative reference.
DAC3REF-
AN
—
DAC3 negative reference.
Comparator C3 positive input.
DAC4REF-
AN
—
DAC4 negative reference.
DAC1OUT1
—
AN
DAC1 voltage output.
DAC2OUT1
—
AN
DAC2 voltage output.
DAC3OUT1
—
AN
DAC3 voltage output.
DAC4OUT1
—
AN
DAC4 voltage output.
VREF-
AN
—
ADC negative reference.
RA1
ST
CMOS ICSP™ data I/O.
TTL/ST CMOS General purpose I/O.
AN1
AN
—
ADC Channel 1 input.
C1IN0-
AN
—
Comparator C1 negative input.
C2IN0-
AN
—
Comparator C2 negative input.
C3IN0-
AN
—
Comparator C3 negative input.
C4IN0-
AN
—
Comparator C4 negative input.
DAC1REF+
AN
—
DAC1 positive reference.
DAC2REF+
AN
—
DAC2 positive reference.
DAC3REF+
AN
—
DAC3 positive reference.
DAC4REF+
AN
—
DAC4 positive reference.
VREF+
AN
—
ADC positive reference.
ICSPCLK
ST
—
Serial programming clock.
RA2
TTL/ST CMOS General purpose I/O.
AN2
AN
—
ADC Channel 2 input.
ZCD
AN
—
Zero-Cross Detection input.
T0CKI(1)
TTL/ST
—
Timer0 clock input.
COG1IN(1)
TTL/ST
—
Complementary Output Generator 1 input.
(1)
TTL/ST
—
Complementary Output Generator 2 input.
TTL/ST
—
Interrupt input.
COG2IN
INT(1)
RA3/T6CKI/MD1CH/MD2CH/
MCLR/VPP
Output
Type
AN0
ICSPDAT
RA1/AN1/C1IN0-/C2IN0-/
C3IN0-/C4IN0-/VREF+/
DAC1REF+/DAC2REF+/
DAC3REF+/DAC4REF+/
ICSPCLK
Input
Type
RA3
TTL/ST CMOS General purpose I/O.
T6CKI(1)
TTL/ST
—
Timer6 clock input.
MD1CH(1)
TTL/ST
—
Data Signal Modulator 1 high carrier input.
MD2CH(1)
TTL/ST
—
Data Signal Modulator 2 high carrier input.
MCLR
ST
—
Master Clear input.
VPP
HV
—
Programming enable.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output
OD = Open-Drain
TTL = TTL compatible input ST
= Schmitt Trigger input with CMOS levels
I2C = Schmitt Trigger input with I2C
HV = High Voltage
XTAL = Crystal levels
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS Input Selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as peripheral digital outputs with the
PPS Output Selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
DS40001775B-page 18
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
TABLE 1-3:
PIC16(L)F1768/9 PINOUT DESCRIPTION (CONTINUED)
Name
RA4/AN3/SOSCO/T1G/
DSM1CL/DSM2CL/OSC2/
CLKOUT
RA5/T1CKI/T2CKI/CLCIN3/
DSM1MOD/DSM2MOD/
SOSCI/OSC1/CLKIN
Function
RA4
Input
Type
Output
Type
Description
TTL/ST CMOS General purpose I/O.
AN3
AN
—
SOSCO
—
XTAL
T1G(1)
TTL/ST
—
Timer1 gate input.
DSM1CL(1)
TTL/ST
—
Data Signal Modulator 1 low carrier input.
DSM2CL(1)
TTL/ST
—
OSC2
—
XTAL
CLKOUT
—
RA5
ADC Channel 3 input.
Secondary Oscillator connection.
Data Signal Modulator 2 low carrier input.
Crystal/Resonator (LP, XT, HS modes).
CMOS FOSC/4 output.
TTL/ST CMOS General purpose I/O.
T1CKI(1)
TTL/ST
—
Timer1 clock input.
T2CKI(1)
TTL/ST
—
Timer2 clock input.
CLCIN3(1)
TTL/ST
—
CLC Input 3.
TTL/ST
—
Data Signal Modulator 1 modulation input.
DSM2MOD(1) TTL/ST
—
Data Signal Modulator 2 modulation input.
(1)
DSM1MOD
SOSCI
XTAL
—
Secondary Oscillator connection.
OSC1
XTAL
—
Crystal/Resonator (LP, XT, HS modes).
ST
—
External Clock input (EC mode).
CLKIN
RB4/AN10/OPA1IN0-/SDI/SDA
RB4
TTL/ST CMOS General purpose I/O.
AN10
AN
—
ADC Channel 10 input.
OPA1IN0-
AN
—
Operational Amplifier 1 inverting input.
SDI(1)
TTL/ST
—
SPI data input.
SDA(1,3)
I2C
—
I2C data output.
RB5/AN11/OPA1IN0+/RX
RB5
AN11
TTL/ST CMOS General purpose I/O.
AN
—
ADC Channel 11 input.
OPA1IN0+
AN
—
Operational Amplifier 1 non-inverting input.
RX(1,3)
TTL/ST
—
EUSART receive input.
RB6/C1IN1+/C3IN1+/SCK/SCL
RB6
C1IN1+
TTL/ST CMOS General purpose I/O.
AN
—
Comparator C1 positive input.
C3IN1+
AN
—
Comparator C3 positive input.
SCK(1)
TTL/ST
—
SPI clock input.
SCL(1,3)
I2C
—
I2C clock output.
RB7/C2IN1+/C4IN1+/CK
RB7
TTL/ST CMOS General purpose I/O.
C2IN1+
AN
—
C4IN1+
AN
—
Comparator C4 positive input.
CK(1)
TTL/ST
—
EUSART clock input.
RC0
TTL/ST CMOS General purpose I/O.
RC0/AN4/C2IN0+/C4IN0+/
T5CKI
AN4
AN
C2IN0+
AN
Comparator C2 positive input.
ADC Channel 4 input.
—
Comparator C2 positive input.
C4IN0+
AN
—
Comparator C4 positive input.
T5CKI(1)
TTL/ST
—
Timer5 clock input.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output
OD = Open-Drain
TTL = TTL compatible input ST
= Schmitt Trigger input with CMOS levels
I2C = Schmitt Trigger input with I2C
HV = High Voltage
XTAL = Crystal levels
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS Input Selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as peripheral digital outputs with the
PPS Output Selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 19
PIC16(L)F1764/5/8/9
TABLE 1-3:
PIC16(L)F1768/9 PINOUT DESCRIPTION (CONTINUED)
Name
RC1/AN5/C1IN1-/C2IN1-/
C3IN1-/C4IN1-/T4CKI/CLCIN2
RC2/AN6/OPA1OUT/OPA2IN1-/
OPA2IN1+/C1IN2-/C2IN2-/
PRG1IN0/PRG2IN1
Function
RC1
RC5/T3CKI/PRG1F/PRG2F/
CCP1
Description
TTL/ST CMOS General purpose I/O.
AN
XTAL
C1IN1-
AN
—
Comparator 1 negative input.
C2IN1-
AN
—
Comparator 2 negative input.
C3IN1-
AN
—
Comparator 3 negative input.
C4IN1-
AN
—
Comparator 4 negative input.
T4CKI(1)
TTL/ST
—
Timer4 clock input.
CLCIN2(1)
TTL/ST
—
CLC Input 2.
RC2
ADC Channel 5 input.
TTL/ST CMOS General purpose I/O.
AN6
AN
—
OPA1OUT
—
AN
OPA2IN1-
AN
ADC Channel 6 input.
Operational Amplifier 1 output.
Operational Amplifier 2 inverting input.
OPA2IN1+
AN
C1IN2-
AN
—
Comparator 1 negative input.
C2IN2-
AN
—
Comparator 2 negative input.
PRG1IN0
AN
—
Ramp Generator 1 reference voltage input.
AN
—
Ramp Generator 2 reference voltage input.
RC3
Operational Amplifier 2 non-inverting input.
TTL/ST CMOS General purpose I/O.
AN7
AN
—
ADC Channel 7 input.
OPA2OUT
—
AN
Operational Amplifier 2 output.
OPA1IN1-
AN
OPA1IN1+
AN
C1IN3-
AN
—
Comparator 1 negative input.
C2IN3-
AN
—
Comparator 2 negative input.
C3IN3-
AN
—
Comparator 3 negative input.
C4IN3-
AN
—
Comparator 4 negative input.
PRG1IN1
AN
—
Ramp Generator 1 reference voltage input.
PRG2IN0
AN
—
Ramp Generator 2 reference voltage input.
Timer5 gate input.
(1)
Operational Amplifier 1 inverting input.
Operational Amplifier 1 non-inverting input.
TTL/ST
—
CCP2(1)
TTL/ST
—
CCP2 capture input.
CLCIN0(1)
TTL/ST
—
CLC Input 0.
T5G
RC4/T3G/PRG1R/PRG2R/
CLCIN1
Output
Type
AN5
PRG2IN1
RC3/AN7/OPA2OUT/OPA1IN1-/
OPA1IN1+/C1IN3-/C2IN3-/
C3IN3-/C4IN3-/PRG1IN1/
PRG2IN0/T5G/CCP2/CLCIN0
Input
Type
RC4
TTL/ST CMOS General purpose I/O.
T3G(1)
TTL/ST
—
Timer3 gate input.
PRG1R(1)
TTL/ST
—
Ramp Generator 1 set_rising input.
PRG2R(1)
TTL/ST
—
Ramp Generator 2 set_rising input.
CLCIN1(1)
TTL/ST
—
CLC Input 1.
RC5
TTL/ST CMOS General purpose I/O.
T3CKI(1)
TTL/ST
—
Timer3 clock input.
PRG1F(1)
TTL/ST
—
Ramp Generator 1 set_falling input.
PRG2F(1)
TTL/ST
—
Ramp Generator 2 set_falling input.
CCP1(1)
TTL/ST
—
CCP1 capture input.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output
OD = Open-Drain
TTL = TTL compatible input ST
= Schmitt Trigger input with CMOS levels
I2C = Schmitt Trigger input with I2C
HV = High Voltage
XTAL = Crystal levels
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS Input Selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as peripheral digital outputs with the
PPS Output Selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
DS40001775B-page 20
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
TABLE 1-3:
PIC16(L)F1768/9 PINOUT DESCRIPTION (CONTINUED)
Name
Function
RC6/AN8/OPA2IN0-/SS
RC6
Output
Type
Description
TTL/ST CMOS General purpose I/O.
AN8
AN
—
ADC Channel 8 input.
OPA2IN0-
AN
—
Operational Amplifier 2 inverting input.
SS(1)
TTL/ST
—
SPI Slave Select input.
RC7
TTL/ST CMOS General purpose I/O.
RC7/AN9/OPA2IN0+
AN9
AN
—
ADC Channel 9 input.
OPA2IN0+
AN
—
Operational Amplifier 2 non-inverting input.
VDD
Power
—
Positive supply.
VSS
Power
—
Ground reference.
VDD
VSS
OUT(2)
Input
Type
C1OUT
CMOS Comparator 1 output.
C2OUT
CMOS Comparator 2 output.
C3OUT
CMOS Comparator 3 output.
C4OUT
CMOS Comparator 4 output.
CCP1
CMOS Compare/PWM1 output.
CCP2
CMOS Compare/PWM2 output.
MD1OUT
CMOS Data Signal Modulator 1 output.
MD2OUT
CMOS Data Signal Modulator 2 output.
PWM3
CMOS PWM3 output.
PWM4
CMOS PWM4 output.
PWM5
CMOS PWM5 output.
PWM6
CMOS PWM6 output.
COG1A
CMOS Complementary Output Generator 1 Output A.
COG1B
CMOS Complementary Output Generator 1 Output B.
COG1C
CMOS Complementary Output Generator 1 Output C.
COG1D
CMOS Complementary Output Generator 1 Output D.
COG2A
CMOS Complementary Output Generator 2 Output A.
COG2B
CMOS Complementary Output Generator 2 Output B.
COG2C
CMOS Complementary Output Generator 2 Output C.
COG2D
CMOS Complementary Output Generator 2 Output D.
SDA(3)
SCK
SCL(3)
SDO
OD
I2C data output.
CMOS SPI clock output.
OD
I2C clock output.
CMOS SPI data output.
TX
CMOS EUSART asynchronous TX data out.
CK
CMOS EUSART synchronous clock out.
DT(3)
CMOS EUSART synchronous data output.
CLC1OUT
CMOS Configurable Logic Cell 1 output.
CLC2OUT
CMOS Configurable Logic Cell 2 output.
CLC3OUT
CMOS Configurable Logic Cell 3 output.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output
OD = Open-Drain
TTL = TTL compatible input ST
= Schmitt Trigger input with CMOS levels
I2C = Schmitt Trigger input with I2C
HV = High Voltage
XTAL = Crystal levels
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS Input Selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as peripheral digital outputs with the
PPS Output Selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 21
PIC16(L)F1764/5/8/9
1.2
routed to a pin with the PPS selection feature, it is not
necessary to do so. Table 1-4 shows all the possible
inter-peripheral signal connections. Please refer to the
corresponding peripheral section to obtain the
multiplexer selection codes for the desired connection.
Peripheral Connection Matrix
Input selection multiplexers on many of the peripherals
enable selecting the output of another peripheral, such
that the signal path is contained entirely within the
device. Although the peripheral output can also be
TABLE 1-4:
PERIPHERAL CONNECTION MATRIX
DS40001775B-page 22
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
Timer0 Clock
CCP Clock
Timer2/4/6 Clock
CCP Capture
Timer1/3/5 Gate
●
●
●
●
Timer2/4/6 Reset
●
●
●
●
●
●
●
●
16-Bit PWM
●
10-Bit PWM
●
●
Op Amp Override
Op Amp -
DSM Mod
Op Amp +
DSM CL
●
DSM CH
●
CLC
●
Comparator -
●
Comparator +
PRG Analog Input
●
PRG Rising/Falling
5-Bit DAC
COG Shutdown
COG Rising/Falling
10-Bit DAC
FVR
ZCD
PRG
10-Bit DAC
5-Bit DAC
CCP
Comparator (sync)
Comparator (async)
CLC
DSM
COG
EUSART TX/CK
EUSART DT
MSSP SCK/SCL
MSSP SDO/SDA
Op Amp
10-Bit PWM
16-Bit PWM
Timer0 Overflow
Timer2 = T2PR
Timer4 = T4PR
Timer6 = T6PR
Timer2 Postscale
Timer4 Postscale
Timer6 Postscale
Timer1 Overflow
Timer3 Overflow
Timer5 Overflow
SOSC
FOSC/4
FOSC
HFINTOSC
LFINTOSC
MFINTOSC
IOCIF
PPS Input Pin
COG Clock
Peripheral Output
ADC Trigger
Peripheral Input
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 2014-2015 Microchip Technology Inc.
●
PIC16(L)F1764/5/8/9
2.0
Relative Addressing modes are available. Two File
Select Registers (FSRs) provide the ability to read
program and data memory.
ENHANCED MID-RANGE CPU
This family of devices contains an enhanced mid-range
8-bit CPU core. The CPU has 49 instructions. Interrupt
capability includes automatic context saving. The
hardware stack is 16 levels deep and has Overflow and
Underflow Reset capability. Direct, Indirect and
FIGURE 2-1:
•
•
•
•
Automatic Interrupt Context Saving
16-Level Stack with Overflow and Underflow
File Select Registers
Instruction Set
CORE BLOCK DIAGRAM
15
Configuration
15
MUX
Flash
Program
Memory
Program
Bus
16-Level Stack
(15-bit)
14
Instruction
InstructionReg
reg
8
Data Bus
Program Counter
RAM
Program Memory
Read (PMR)
12
RAM Addr
Addr MUX
Indirect
Addr
12
12
Direct Addr 7
5
BSR
FSR Reg
reg
15
FSR0reg
Reg
FSR
FSR1 Reg
15
STATUS Reg
8
3
Power-up
Timer
Instruction
Decode and
Control
OSC1/CLKIN
OSC2/CLKOUT
Timing
Generation
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
MUX
MUX
ALU
8
W Reg
Brown-out
Reset
Internal
Oscillator
Block
VDD
 2014-2015 Microchip Technology Inc.
VSS
DS40001775B-page 23
PIC16(L)F1764/5/8/9
2.1
Automatic Interrupt Context
Saving
During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 7.5 “Automatic Context Saving”
for more information.
2.2
16-Level Stack with Overflow and
Underflow
These devices have a hardware stack memory 15 bits
wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF)
in the PCON register, and if enabled, will cause a
Software Reset. See Section 3.5 “Stack” for more
details.
DS40001775B-page 24
2.3
File Select Registers
There are two 16-bit File Select Registers (FSRs).
FSRs can access all file registers and program
memory, which allows one Data Pointer for all memory.
When an FSRn points to program memory, there is one
additional instruction cycle in instructions using INDFn to
allow the data to be fetched. General purpose memory
can now also be addressed linearly, providing the ability
to access contiguous data larger than 80 bytes. There
are also new instructions to support the FSRs. See
Section 3.6 “Indirect Addressing” for more details.
2.4
Instruction Set
There are 49 instructions for the enhanced mid-range
CPU to support the features of the CPU. See
Section 35.0 “Instruction Set Summary” for more
details.
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
3.0
MEMORY ORGANIZATION
These devices contain the following types of memory:
• Program Memory:
- Configuration Words
- Device ID
- User ID
- Flash Program Memory
• Data Memory:
- Core Registers
- Special Function Registers
- General Purpose RAM
- Common RAM
3.1
The enhanced mid-range core has a 15-bit Program
Counter (PC) capable of addressing a 32K x 14 program
memory space. Table 3-1 shows the memory sizes
implemented for the PIC16(L)F1764/5/8/9 family.
Accessing a location above these boundaries will cause
a wrap around within the implemented memory space.
The Reset vector is at 0000h and the interrupt vector is
at 0004h (see Figure 3-1).
3.2
Note 1: The method to access Flash memory
through the PMCON registers is described
in Section 10.0 “Flash Program Memory
Control”.
The following features are associated with access and
control of program memory and data memory:
Program Memory Organization
High-Endurance Flash
This device has a 128-byte section of high-endurance
Program Flash Memory (PFM) in lieu of data EEPROM.
This area is especially well suited for nonvolatile data
storage that is expected to be updated frequently over
the life of the end product. See Section 10.2 “Flash
Program Memory Overview” for more information on
writing data to PFM. See Section 3.2.1.2 “Indirect
Read with FSRn” for more information about using the
FSRn registers to read byte data stored in PFM.
• PCL and PCLATH
• Stack
• Indirect Addressing
TABLE 3-1:
DEVICE SIZES AND ADDRESSES
Program Memory Space
(Words)
Last Program Memory
Address
High-Endurance Flash
Memory Address Range(1)
PIC16(L)F1764
4,096
0FFFh
0F80h-0FFFh
PIC16(L)F1765
8,192
1FFFh
1F80h-1FFFh
PIC16(L)F1768
4,096
0FFFh
0F80h-0FFFh
PIC16(L)F1769
8,192
1FFFh
1F80h-1FFFh
Device
Note 1:
High-endurance Flash applies to the low byte of each address in the range.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 25
PIC16(L)F1764/5/8/9
FIGURE 3-1:
PROGRAM MEMORY MAP
AND STACK FOR
PIC16(L)F1764/5/8/9
PC<14:0>
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
15
READING PROGRAM MEMORY AS
DATA
There are two methods of accessing constants in
program memory. The first method is to use tables of
RETLW instructions. The second method is to set an
FSRn to point to the program memory.
3.2.1.1
RETLW Instruction
Stack Level 0
Stack Level 1
The RETLW instruction can be used to provide access
to tables of constants. The recommended way to create
such a table is shown in Example 3-1.
Stack Level 15
EXAMPLE 3-1:
Reset Vector
0000h
Interrupt Vector
0004h
0005h
Page 0
On-Chip
Program
Memory
3.2.1
07FFh
0800h
Page 1
Rollover to Page 0
0FFFh
1000h
constants
BRW
RETLW
RETLW
RETLW
RETLW
DATA0
DATA1
DATA2
DATA3
RETLW INSTRUCTION
;Add Index in W to
;program counter to
;select data
;Index0 data
;Index1 data
my_function
;… LOTS OF CODE…
MOVLW
DATA_INDEX
call constants
;… THE CONSTANT IS IN W
The BRW instruction makes this type of table very
simple to implement. If your code must remain portable
with previous generations of microcontrollers, then the
BRW instruction is not available, so the older table read
method must be used.
3.2.1.2
Rollover to Page 1
7FFFh
Indirect Read with FSRn
The program memory can be accessed as data by
setting bit 7 of the FSRnH register and reading the
matching INDFn register. The MOVIW instruction will
place the lower eight bits of the addressed word in the
W register. Writes to the program memory cannot be
performed via the INDFn registers. Instructions that
access the program memory via the FSRn require one
extra instruction cycle to complete. Example 3-2
demonstrates accessing the program memory via an
FSRn.
The high directive will set bit 7 if a label points to a
location in program memory.
DS40001775B-page 26
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
EXAMPLE 3-2:
ACCESSING PROGRAM
MEMORY VIA FSRn
constants
DW DATA0
;First constant
DW DATA1
;Second constant
DW DATA2
DW DATA3
my_function
;… LOTS OF CODE…
MOVLW DATA_INDEX
ADDLW LOW constants
MOVWF FSR1L
MOVLW HIGH constants ;MSb sets
automatically
MOVWF FSR1H
BTFSC STATUS, C
;carry from ADDLW?
INCF
FSR1H, f
;yes
MOVIW 0[FSR1]
;THE PROGRAM MEMORY IS IN W
3.3
3.3.1
The core registers contain the registers that directly
affect the basic operation. The core registers occupy
the first 12 addresses of every data memory bank
(addresses, x00h/x08h through x0Bh/x8Bh). These
registers are listed below in Table 3-2. For detailed
information, see Table 3-15.
TABLE 3-2:
Data Memory Organization
The data memory is partitioned in 32 memory banks
with 128 bytes in a bank. Each bank consists of
(Figure 3-2):
•
•
•
•
12 core registers
20 Special Function Registers (SFRs)
Up to 80 bytes of General Purpose RAM (GPR)
16 bytes of common RAM
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers (FSRs). See Section 3.6 “Indirect
Addressing” for more information.
Data memory uses a 12-bit address. The upper five bits
of the address define the Bank address and the lower
seven bits select the registers/RAM in that bank.
CORE REGISTERS
3.3.1.1
CORE REGISTERS
Addresses
BANKx
x00h or x80h
x01h or x81h
x02h or x82h
x03h or x83h
x04h or x84h
x05h or x85h
x06h or x86h
x07h or x87h
x08h or x88h
x09h or x89h
x0Ah or x8Ah
x0Bh or x8Bh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
STATUS Register
The STATUS register, shown in Register 3-1, contains:
• The arithmetic status of the ALU
• The Reset status
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits, refer to Section 35.0
“Instruction Set Summary”.
Note:
 2014-2015 Microchip Technology Inc.
The C and DC bits operate as Borrow and
Digit Borrow out bits, respectively, in
subtraction.
DS40001775B-page 27
PIC16(L)F1764/5/8/9
REGISTER 3-1:
U-0
STATUS: STATUS REGISTER
U-0
—
—
U-0
R-1/q
—
TO
R-1/q
PD
R/W-0/u
R/W-0/u
(1)
Z
DC
R/W-0/u
C(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7-5
Unimplemented: Read as ‘0’
bit 4
TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3
PD: Power-Down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0
C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand.
DS40001775B-page 28
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
3.3.2
SPECIAL FUNCTION REGISTER
FIGURE 3-2:
The Special Function Registers (SFRs) are registers
used by the application to control the desired operation
of peripheral functions in the device. The SFR occupies
the 20 bytes after the core registers of every data
memory bank (addresses, x0Ch/x8Ch through
x1Fh/x9Fh). The registers associated with the operation
of each peripheral are described in the corresponding
peripheral chapters of this data sheet.
3.3.3
7-Bit Bank
Offset
0Bh
0Ch
GENERAL PURPOSE RAM
Core Registers
(12 bytes)
Special Function Registers
(20 bytes maximum)
1Fh
20h
Linear Access to GPR
The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3.6.2
“Linear Data Memory” for more information.
3.3.4
Memory Region
00h
There are up to 80 bytes of General Purpose Registers
(GPRs) in each data memory bank. The GPR occupies
the space immediately after the SFR of selected data
memory banks. The number of banks selected depends
on the total amount of GPR space available in the
device.
3.3.3.1
BANKED MEMORY
PARTITIONING
General Purpose RAM
(80 bytes maximum)
COMMON RAM
There are 16 bytes of common RAM accessible from all
banks.
6Fh
70h
Common RAM
(16 bytes)
7Fh
3.3.5
DEVICE MEMORY MAPS
The memory maps for the device family are shown in
Tables 3-3 through 3-14.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 29
PIC16(L)F1764 MEMORY MAP (BANKS 0-7)
BANK 0
000h
BANK 1
080h
Core Registers
(Table 3-2)
00Bh
BANK 2
100h
Core Registers
(Table 3-2)
08Bh
BANK 3
180h
Core Registers
(Table 3-2)
10Bh
BANK 4
200h
Core Registers
(Table 3-2)
18Bh
BANK 5
280h
Core Registers
(Table 3-2)
20Bh
BANK 6
300h
Core Registers
(Table 3-2)
28Bh
BANK 7
380h
Core Registers
(Table 3-2)
30Bh
Core Registers
(Table 3-2)
38Bh
00Ch
PORTA
08Ch
TRISA
10Ch
LATA
18Ch
ANSELA
20Ch
WPUA
28Ch
ODCONA
30Ch
SLRCONA
38Ch
00Dh
—
08Dh
—
10Dh
—
18Dh
—
20Dh
—
28Dh
—
30Dh
—
38Dh
INLVLA
—
00Eh
PORTC
08Eh
TRISC
10Eh
LATC
18Eh
ANSELC
20Eh
WPUC
28Eh
ODCONC
30Eh
SLRCONC
38Eh
INLVLC
00Fh
—
08Fh
—
10Fh
CMOUT
18Fh
—
20Fh
—
28Fh
—
30Fh
—
38Fh
—
010h
—
090h
—
110h
CM1CON0
190h
—
210h
—
290h
—
310h
—
390h
—
011h
PIR1
091h
PIE1
111h
CM1CON1
191h
PMADRL
211h
SSP1BUF
291h
CCPR1L
311h
—
391h
IOCAP
012h
PIR2
092h
PIE2
112h
CM1NSEL
192h
PMADRH
212h
SSP1ADD
292h
CCPR1H
312h
—
392h
IOCAN
013h
PIR3
093h
PIE3
113h
CM1PSEL
193h
PMDATL
213h
SSP1MSK
293h
CCP1CON
313h
—
393h
IOCAF
014h
PIR4
094h
PIE4
114h
CM2CON0
194h
PMDATH
214h
SSP1STAT
294h
CCP1CAP
314h
—
394h
—
015h
TMR0
095h
OPTION_REG
115h
CM2CON1
195h
PMCON1
215h
SSP1CON1
295h
—
315h
—
395h
—
016h
TMR1L
096h
PCON
116h
CM2NSEL
196h
PMCON2
216h
SSP1CON2
296h
—
316h
—
396h
—
017h
TMR1H
097h
WDTCON
117h
CM2PSEL
197h
VREGCON(1)
217h
SSP1CON3
297h
—
317h
—
397h
IOCCP
018h
T1CON
098h
OSCTUNE
118h
—
198h
—
218h
—
298h
—
318h
—
398h
IOCCN
019h
T1GCON
099h
OSCCON
119h
—
199h
RC1REG
219h
—
299h
—
319h
—
399h
IOCCF
01Ah
T2TMR
09Ah
OSCSTAT
11Ah
—
19Ah
TX1REG
21Ah
—
29Ah
—
31Ah
—
39Ah
—
01Bh
T2PR
09Bh
ADRESL
11Bh
—
19Bh
SP1BRGL
21Bh
—
29Bh
—
31Bh
—
39Bh
MD1CON0
01Ch
T2CON
09Ch
ADRESH
11Ch
—
19Ch
SP1BRGH
21Ch
—
29Ch
—
31Ch
—
39Ch
MD1CON1
01Dh
T2HLT
09Dh
ADCON0
11Dh
—
19Dh
RC1STA
21Dh
BORCON
29Dh
—
31Dh
—
39Dh
MD1SRC
01Eh
T2CLKCON
09Eh
ADCON1
11Eh
—
19Eh
TX1STA
21Eh
FVRCON
29Eh
CCPTMRS
31Eh
—
39Eh
MD1CARL
01Fh
T2RST
09Fh
ADCON2
11Fh
—
19Fh
BAUD1CON
21Fh
ZCD1CON
29Fh
—
31Fh
—
39Fh
MD1CARH
320h
General Purpose
Register
16 Bytes
3A0h
020h
0A0h
 2014-2015 Microchip Technology Inc.
General
Purpose
Register
80 Bytes
120h
General
Purpose
Register
80 Bytes
1A0h
General
Purpose
Register
80 Bytes
220h
General
Purpose
Register
80 Bytes
2A0h
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
32Fh
Unimplemented
Read as ‘0’
06Fh
0EFh
16Fh
1EFh
26Fh
2EFh
36Fh
070h
0F0h
170h
1F0h
270h
2F0h
370h
Common RAM
70h-7Fh
07Fh
Accesses
70h-7Fh
0FFh
Accesses
70h-7Fh
17Fh
Legend:
= Unimplemented data memory locations, read as ‘0’.
Note 1: Unimplemented on PIC16LF1764.
Accesses
70h-7Fh
1FFh
Accesses
70h-7Fh
27Fh
Accesses
70h-7Fh
2FFh
Unimplemented
Read as ‘0’
330h
3EFh
3F0h
Accesses
70h-7Fh
37Fh
Accesses
70h-7Fh
3FFh
PIC16(L)F1764/5/8/9
DS40001775B-page 30
TABLE 3-3:
 2014-2015 Microchip Technology Inc.
TABLE 3-4:
PIC16LF1765 MEMORY MAP (BANKS 0-7)
BANK 0
000h
BANK 1
080h
Core Registers
(Table 3-2)
00Bh
BANK 2
100h
Core Registers
(Table 3-2)
08Bh
BANK 3
180h
Core Registers
(Table 3-2)
10Bh
BANK 4
200h
Core Registers
(Table 3-2)
18Bh
BANK 5
280h
Core Registers
(Table 3-2)
20Bh
BANK 6
300h
Core Registers
(Table 3-2)
28Bh
BANK 7
380h
Core Registers
(Table 3-2)
30Bh
Core Registers
(Table 3-2)
38Bh
00Ch
PORTA
08Ch
TRISA
10Ch
LATA
18Ch
ANSELA
20Ch
WPUA
28Ch
ODCONA
30Ch
SLRCONA
38Ch
00Dh
—
08Dh
—
10Dh
—
18Dh
—
20Dh
—
28Dh
—
30Dh
—
38Dh
INLVLA
—
00Eh
PORTC
08Eh
TRISC
10Eh
LATC
18Eh
ANSELC
20Eh
WPUC
28Eh
ODCONC
30Eh
SLRCONC
38Eh
INLVLC
00Fh
—
08Fh
—
10Fh
CMOUT
18Fh
—
20Fh
—
28Fh
—
30Fh
—
38Fh
—
010h
—
090h
—
110h
CM1CON0
190h
—
210h
—
290h
—
310h
—
390h
—
011h
PIR1
091h
PIE1
111h
CM1CON1
191h
PMADRL
211h
SSP1BUF
291h
CCPR1L
311h
—
391h
IOCAP
012h
PIR2
092h
PIE2
112h
CM1NSEL
192h
PMADRH
212h
SSP1ADD
292h
CCPR1H
312h
—
392h
IOCAN
013h
PIR3
093h
PIE3
113h
CM1PSEL
193h
PMDATL
213h
SSP1MSK
293h
CCP1CON
313h
—
393h
IOCAF
014h
PIR4
094h
PIE4
114h
CM2CON0
194h
PMDATH
214h
SSP1STAT
294h
CCP1CAP
314h
—
394h
—
015h
TMR0
095h
OPTION_REG
115h
CM2CON1
195h
PMCON1
215h
SSP1CON
295h
—
315h
—
395h
—
016h
TMR1L
096h
PCON
116h
CM2NSEL
196h
PMCON2
216h
SSP1CON2
296h
—
316h
—
396h
—
017h
TMR1H
097h
WDTCON
117h
CM2PSEL
197h
VREGCON(1)
217h
SSP1CON3
297h
—
317h
—
397h
IOCCP
T1CON
098h
OSCTUNE
118h
—
198h
—
218h
—
298h
—
318h
—
398h
IOCCN
019h
T1GCON
099h
OSCCON
119h
—
199h
RC1REG
219h
—
299h
—
319h
—
399h
IOCCF
01Ah
T2TMR
09Ah
OSCSTAT
11Ah
—
19Ah
TX1REG
21Ah
—
29Ah
—
31Ah
—
39Ah
—
01Bh
T2PR
09Bh
ADRESL
11Bh
—
19Bh
SP1BRGL
21Bh
—
29Bh
—
31Bh
—
39Bh
MD1CON0
01Ch
T2CON
09Ch
ADRESH
11Ch
—
19Ch
SP1BRGH
21Ch
—
29Ch
—
31Ch
—
39Ch
MD1CON1
01Dh
T2HLT
09Dh
ADCON0
11Dh
—
19Dh
RC1STA
21Dh
BORCON
29Dh
—
31Dh
—
39Dh
MD1SRC
01Eh
T2CLKCON
09Eh
ADCON1
11Eh
—
19Eh
TX1STA
21Eh
FVRCON
29Eh
CCPTMRS
31Eh
—
39Eh
MD1CARL
01Fh
T2RST
09Fh
ADCON2
11Fh
—
19Fh
BAUD1CON
21Fh
ZCD1CON
29Fh
—
31Fh
—
39Fh
MD1CARH
020h
0A0h
General
Purpose
Register
80 Bytes
120h
General
Purpose
Register
80 Bytes
1A0h
General
Purpose
Register
80 Bytes
220h
General
Purpose
Register
80 Bytes
2A0h
General
Purpose
Register
80 Bytes
320h
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes’
06Fh
0EFh
16Fh
1EFh
26Fh
2EFh
36Fh
070h
0F0h
170h
1F0h
270h
2F0h
370h
DS40001775B-page 31
Common RAM
70h-7Fh
07Fh
Accesses
70h-7Fh
0FFh
Accesses
70h-7Fh
17Fh
Legend:
= Unimplemented data memory locations, read as ‘0’.
Note 1: Unimplemented on PIC16LF1765.
Accesses
70h-7Fh
1FFh
Accesses
70h-7Fh
27Fh
Accesses
70h-7Fh
2FFh
3A0h
General
Purpose
Register
80 Bytes’
3EFh
3F0h
Accesses
70h-7Fh
37Fh
Accesses
70h-7Fh
3FFh
PIC16(L)F1764/5/8/9
018h
PIC16(L)F1768 MEMORY MAP (BANKS 0-7)
BANK 0
000h
BANK 1
080h
Core Registers
(Table 3-2)
00Bh
BANK 2
100h
Core Registers
(Table 3-2)
08Bh
BANK 3
180h
Core Registers
(Table 3-2)
10Bh
BANK 4
200h
Core Registers
(Table 3-2)
18Bh
BANK 5
280h
Core Registers
(Table 3-2)
20Bh
BANK 6
300h
Core Registers
(Table 3-2)
28Bh
BANK 7
380h
Core Registers
(Table 3-2)
30Bh
Core Registers
(Table 3-2)
38Bh
00Ch
PORTA
08Ch
TRISA
10Ch
LATA
18Ch
ANSELA
20Ch
WPUA
28Ch
ODCONA
30Ch
SLRCONA
38Ch
00Dh
PORTB
08Dh
TRISB
10Dh
LATB
18Dh
ANSELB
20Dh
WPUB
28Dh
ODCONB
30Dh
SLRCONB
38Dh
INLVLA
INLVLB
00Eh
PORTC
08Eh
TRISC
10Eh
LATC
18Eh
ANSELC
20Eh
WPUC
28Eh
ODCONC
30Eh
SLRCONC
38Eh
INLVLC
00Fh
—
08Fh
—
10Fh
CMOUT
18Fh
—
20Fh
—
28Fh
—
30Fh
—
38Fh
—
010h
—
090h
—
110h
CM1CON0
190h
—
210h
—
290h
—
310h
—
390h
—
011h
PIR1
091h
PIE1
111h
CM1CON1
191h
PMADRL
211h
SSP1BUF
291h
CCPR1L
311h
—
391h
IOCAP
012h
PIR2
092h
PIE2
112h
CM1NSEL
192h
PMADRH
212h
SSP1ADD
292h
CCPR1H
312h
—
392h
IOCAN
013h
PIR3
093h
PIE3
113h
CM1PSEL
193h
PMDATL
213h
SSP1MSK
293h
CCP1CON
313h
—
393h
IOCAF
014h
PIR4
094h
PIE4
114h
CM2CON0
194h
PMDATH
214h
SSP1STAT
294h
CCP1CAP
314h
—
394h
IOCBP
IOCBN
015h
TMR0
095h
OPTION_REG
115h
CM2CON1
195h
PMCON1
215h
SSP1CON1
295h
—
315h
—
395h
016h
TMR1L
096h
PCON
116h
CM2NSEL
196h
PMCON2
216h
SSP1CON2
296h
—
316h
—
396h
IOCBF
017h
TMR1H
097h
WDTCON
117h
CM2PSEL
197h
VREGCON(1)
217h
SSP1CON3
297h
—
317h
—
397h
IOCCP
018h
T1CON
098h
OSCTUNE
118h
CM3CON0
198h
—
218h
—
298h
CCPR2L
318h
—
398h
IOCCN
019h
T1GCON
099h
OSCCON
119h
CM3CON1
199h
RC1REG
219h
—
299h
CCPR2H
319h
—
399h
IOCCF
01Ah
T2TMR
09Ah
OSCSTAT
11Ah
CM3NSEL
19Ah
TX1REG
21Ah
—
29Ah
CCP2CON
31Ah
—
39Ah
—
01Bh
T2PR
09Bh
ADRESL
11Bh
CM3PSEL
19Bh
SP1BRGL
21Bh
—
29Bh
CCP2CAP
31Bh
MD2CON0
39Bh
MD1CON0
01Ch
T2CON
09Ch
ADRESH
11Ch
CM4CON0
19Ch
SP1BRGH
21Ch
—
29Ch
—
31Ch
MD2CON1
39Ch
MD1CON1
01Dh
T2HLT
09Dh
ADCON0
11Dh
CM4CON1
19Dh
RC1STA
21Dh
BORCON
29Dh
—
31Dh
MD2SRC
39Dh
MD1SRC
01Eh
T2CLKCON
09Eh
ADCON1
11Eh
CM4NSEL
19Eh
TX1STA
21Eh
FVRCON
29Eh
CCPTMRS
31Eh
MD2CARL
39Eh
MD1CARL
01Fh
T2RST
09Fh
ADCON2
11Fh
CM4PSEL
19Fh
BAUD1CON
21Fh
ZCD1CON
29Fh
—
31Fh
MD2CARH
39Fh
MD1CARH
320h
General Purpose Register
16 Bytes
3A0h
020h
0A0h
 2014-2015 Microchip Technology Inc.
General
Purpose
Register
80 Bytes
120h
General
Purpose
Register
80 Bytes
1A0h
General
Purpose
Register
80 Bytes
220h
General
Purpose
Register
80 Bytes
2A0h
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
32Fh
Unimplemented
Read as ‘0’
06Fh
0EFh
16Fh
1EFh
26Fh
2EFh
36Fh
070h
0F0h
170h
1F0h
270h
2F0h
370h
Common RAM
70h-7Fh
07Fh
Accesses
70h-7Fh
0FFh
Accesses
70h-7Fh
17Fh
Legend:
= Unimplemented data memory locations, read as ‘0’.
Note 1: Unimplemented on PIC16LF1768.
Accesses
70h-7Fh
1FFh
Accesses
70h-7Fh
27Fh
Accesses
70h-7Fh
2FFh
Unimplemented
Read as ‘0’
330h
3EFh
3F0h
Accesses
70h-7Fh
37Fh
Accesses
70h-7Fh
3FFh
PIC16(L)F1764/5/8/9
DS40001775B-page 32
TABLE 3-5:
 2014-2015 Microchip Technology Inc.
TABLE 3-6:
PIC16(L)F1769 MEMORY MAP (BANKS 0-7)
BANK 0
000h
BANK 1
080h
Core Registers
(Table 3-2)
00Bh
BANK 2
100h
Core Registers
(Table 3-2)
08Bh
BANK 3
180h
Core Registers
(Table 3-2)
10Bh
BANK 4
200h
Core Registers
(Table 3-2)
18Bh
BANK 5
280h
Core Registers
(Table 3-2)
20Bh
BANK 6
300h
Core Registers
(Table 3-2)
28Bh
BANK 7
380h
Core Registers
(Table 3-2)
30Bh
Core Registers
(Table 3-2)
38Bh
00Ch
PORTA
08Ch
TRISA
10Ch
LATA
18Ch
ANSELA
20Ch
WPUA
28Ch
ODCONA
30Ch
SLRCONA
38Ch
00Dh
PORTB
08Dh
TRISB
10Dh
LATB
18Dh
ANSELB
20Dh
WPUB
28Dh
ODCONB
30Dh
SLRCONB
38Dh
INLVLA
INLVLB
00Eh
PORTC
08Eh
TRISC
10Eh
LATC
18Eh
ANSELC
20Eh
WPUC
28Eh
ODCONC
30Eh
SLRCONC
38Eh
INLVLC
00Fh
—
08Fh
—
10Fh
CMOUT
18Fh
—
20Fh
—
28Fh
—
30Fh
—
38Fh
—
010h
—
090h
—
110h
CM1CON0
190h
—
210h
—
290h
—
310h
—
390h
—
011h
PIR1
091h
PIE1
111h
CM1CON1
191h
PMADRL
211h
SSP1BUF
291h
CCPR1L
311h
—
391h
IOCAP
012h
PIR2
092h
PIE2
112h
CM1NSEL
192h
PMADRH
212h
SSP1ADD
292h
CCPR1H
312h
—
392h
IOCAN
013h
PIR3
093h
PIE3
113h
CM1PSEL
193h
PMDATL
213h
SSP1MSK
293h
CCP1CON
313h
—
393h
IOCAF
014h
PIR4
094h
PIE4
114h
CM2CON0
194h
PMDATH
214h
SSP1STAT
294h
CCP1CAP
314h
—
394h
IOCBP
015h
TMR0
095h
OPTION_REG
115h
CM2CON1
195h
PMCON1
215h
SSP1CON1
295h
—
315h
—
395h
IOCBN
016h
TMR1L
096h
PCON
116h
CM2NSEL
196h
PMCON2
216h
SSP1CON2
296h
—
316h
—
396h
IOCBF
017h
TMR1H
097h
WDTCON
117h
CM2PSEL
197h
VREGCON(1)
217h
SSP1CON3
297h
—
317h
—
397h
IOCCP
018h
T1CON
098h
OSCTUNE
118h
CM3CON0
198h
—
218h
—
298h
CCPR2L
318h
—
398h
IOCCN
019h
T1GCON
099h
OSCCON
119h
CM3CON1
199h
RC1REG
219h
—
299h
CCPR2H
319h
—
399h
IOCCF
01Ah
T2TMR
09Ah
OSCSTAT
11Ah
CM3NSEL
19Ah
TX1REG
21Ah
—
29Ah
CCP2CON
31Ah
—
39Ah
—
01Bh
T2PR
09Bh
ADRESL
11Bh
CM3PSEL
19Bh
SP1BRGL
21Bh
—
29Bh
CCP2CAP
31Bh
MD2CON0
39Bh
MD1CON0
MD1CON1
T2CON
09Ch
ADRESH
11Ch
CM4CON0
19Ch
SP1BRGH
21Ch
—
29Ch
—
31Ch
MD2CON1
39Ch
T2HLT
09Dh
ADCON0
11Dh
CM4CON1
19Dh
RC1STA
21Dh
BORCON
29Dh
—
31Dh
MD2SRC
39Dh
MD1SRC
01Eh
T2CLKCON
09Eh
ADCON1
11Eh
CM4NSEL
19Eh
TX1STA
21Eh
FVRCON
29Eh
CCPTMRS
31Eh
MD2CARL
39Eh
MD1CARL
01Fh
T2RST
09Fh
ADCON2
11Fh
CM4PSEL
19Fh
BAUD1CON
21Fh
ZCD1CON
29Fh
—
31Fh
MD2CARH
39Fh
MD1CARH
020h
0A0h
General
Purpose
Register
80 Bytes
120h
General
Purpose
Register
80 Bytes
1A0h
General
Purpose
Register
80 Bytes
220h
General
Purpose
Register
80 Bytes
2A0h
General
Purpose
Register
80 Bytes
320h
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
06Fh
0EFh
16Fh
1EFh
26Fh
2EFh
36Fh
070h
0F0h
170h
1F0h
270h
2F0h
370h
DS40001775B-page 33
Common RAM
70h – 7Fh
07Fh
Accesses
70h-7Fh
0FFh
Accesses
70h-7Fh
17Fh
Legend:
= Unimplemented data memory locations, read as ‘0’.
Note 1: Unimplemented on PIC16LF1769.
Accesses
70h-7Fh
1FFh
Accesses
70h-7Fh
27Fh
Accesses
70h-7Fh
2FFh
3A0h
General
Purpose
Register
80 Bytes
3EFh
3F0h
Accesses
70h-7Fh
37Fh
Accesses
70h-7Fh
3FFh
PIC16(L)F1764/5/8/9
01Ch
01Dh
PIC16(L)F1764 MEMORY MAP (BANKS 8-23)
BANK 8
400h
BANK 9
480h
Core Registers
(Table 3-2)
40Bh
40Ch
40Dh
40Eh
40Fh
410h
411h
412h
413h
414h
415h
416h
417h
418h
419h
41Ah
41Bh
41Ch
41Dh
41Eh
41Fh
420h
—
—
HIDRVC
—
—
—
—
T4TMR
T4PR
T4CON
T4HLT
T4CLKCON
T4RST
—
T6TMR
T6PR
T6CON
T6HLT
T6CLKCON
T6RST
Core Registers
(Table 3-2)
48Bh
48Ch
48Dh
48Eh
48Fh
490h
491h
492h
493h
494h
495h
496h
497h
498h
499h
49Ah
49Bh
49Ch
49Dh
49Eh
49Fh
4A0h
Unimplemented
Read as ‘0’
46Fh
470h
—
—
—
—
—
—
—
TMR3L
TMR3H
T3CON
T3GCON
—
—
—
TMR5L
TMR5H
T5CON
T5GCON
—
—
 2014-2015 Microchip Technology Inc.
Accesses
70h-7Fh
80Bh
80Ch
Unimplemented
Read as ‘0’
86Fh
870h
Unimplemented
Read as ‘0’
8EFh
8F0h
Accesses
70h-7Fh
87Fh
Legend:
Unimplemented
Read as ‘0’
96Fh
970h
Accesses
70h-7Fh
8FFh
Unimplemented
Read as ‘0’
9EFh
9F0h
Accesses
70h-7Fh
97Fh
= Unimplemented data memory locations, read as ‘0’.
Unimplemented
Read as ‘0’
A6Fh
A70h
Accesses
70h-7Fh
9FFh
Core Registers
(Table 3-2)
B8Bh
B8Ch
Unimplemented
Read as ‘0’
B6Fh
B70h
Accesses
70h-7Fh
AFFh
BANK 23
B80h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Accesses
70h-7Fh
A7Fh
BANK 22
B0Bh
B0Ch
AEFh
AF0h
Accesses
70h-7Fh
7FFh
B00h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
BEFh
BF0h
Accesses
70h-7Fh
B7Fh
—
—
—
—
—
—
—
—
PRG1RTSS
PRG1FTSS
PRG1INS
PRG1CON0
PRG1CON1
PRG1CON2
—
—
—
—
—
—
Unimplemented
Read as ‘0’
Accesses
70h-7Fh
BANK 21
A8Bh
A8Ch
78Bh
78Ch
78Dh
78Eh
78Fh
790h
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
79Bh
79Ch
79Dh
79Eh
79Fh
7A0h
7EFh
7F0h
77Fh
A80h
Core Registers
(Table 3-2)
—
COG2PHR
COG2PHF
COG2BLKR
COG2BLKF
COG2DBR
COG2DBF
COG2CON0
COG2CON1
COG2RIS0
COG2RIS1
COG2RSIM0
COG2RSIM1
COG2FIS0
COG2FIS1
COG2FSIM0
COG2FSIM1
COG2ASD0
COG2ASD1
COG2STR
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Accesses
70h-7Fh
BANK 20
A0Bh
A0Ch
70Bh
70Ch
70Dh
70Eh
70Fh
710h
711h
712h
713h
714h
715h
716h
717h
718h
719h
71Ah
71Bh
71Ch
71Dh
71Eh
71Fh
720h
76Fh
770h
6FFh
A00h
Core Registers
(Table 3-2)
—
COG1PHR
COG1PHF
COG1BLKR
COG1BLKF
COG1DBR
COG1DBF
COG1CON0
COG1CON1
COG1RIS0
COG1RIS1
COG1RSIM0
COG1RSIM1
COG1FIS0
COG1FIS1
COG1FSIM0
COG1FSIM1
COG1ASD0
COG1ASD1
COG1STR
BANK 15
780h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Accesses
70h-7Fh
BANK 19
98Bh
98Ch
68Bh
68Ch
68Dh
68Eh
68Fh
690h
691h
692h
693h
694h
695h
696h
697h
698h
699h
69Ah
69Bh
69Ch
69Dh
69Eh
69Fh
6A0h
6EFh
6F0h
67Fh
980h
Core Registers
(Table 3-2)
—
—
—
—
—
—
—
—
—
—
—
PWM3DCL
PWM3DCH
PWM3CON
—
—
—
—
—
—
BANK 14
700h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Accesses
70h-7Fh
BANK 18
90Bh
90Ch
60Bh
60Ch
60Dh
60Eh
60Fh
610h
611h
612h
613h
614h
615h
616h
617h
618h
619h
61Ah
61Bh
61Ch
61Dh
61Eh
61Fh
620h
66Fh
670h
5FFh
900h
Core Registers
(Table 3-2)
—
—
—
—
DACLD
DAC1CON0
DAC1REFL
DAC1REFH
—
—
—
DAC3CON0
DAC3REF
—
—
—
—
—
—
—
BANK 13
680h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Accesses
70h-7Fh
BANK 17
88Bh
88Ch
58Bh
58Ch
58Dh
58Eh
58Fh
590h
591h
592h
593h
594h
595h
596h
597h
598h
599h
59Ah
59Bh
59Ch
59Dh
59Eh
59Fh
5A0h
5EFh
5F0h
57Fh
880h
Core Registers
(Table 3-2)
—
—
—
OPA1NCHS
OPA1PCHS
OPA1CON
OPA1ORS
—
—
—
—
—
—
—
—
—
—
—
—
—
BANK 12
600h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Accesses
70h-7Fh
BANK 16
800h
50Bh
50Ch
50Dh
50Eh
50Fh
510h
511h
512h
513h
514h
515h
516h
517h
518h
519h
51Ah
51Bh
51Ch
51Dh
51Eh
51Fh
520h
56Fh
570h
4FFh
BANK 11
580h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
4EFh
4F0h
47Fh
BANK 10
500h
Accesses
70h-7Fh
BFFh
PIC16(L)F1764/5/8/9
DS40001775B-page 34
TABLE 3-7:
 2014-2015 Microchip Technology Inc.
TABLE 3-8:
PIC16(L)F1765 MEMORY MAP (BANKS 8-23)
BANK 8
400h
BANK 9
480h
Core Registers
(Table 3-2)
40Bh
40Ch
40Dh
40Eh
40Fh
410h
411h
412h
413h
414h
415h
416h
417h
418h
419h
41Ah
41Bh
41Ch
41Dh
41Eh
41Fh
420h
—
—
HIDRVC
—
—
—
—
T4TMR
T4PR
T4CON
T4HLT
T4CLKCON
T4RST
—
T6TMR
T6PR
T6CON
T6HLT
T6CLKCON
T6RST
Core Registers
(Table 3-2)
48Bh
48Ch
48Dh
48Eh
48Fh
490h
491h
492h
493h
494h
495h
496h
497h
498h
499h
49Ah
49Bh
49Ch
49Dh
49Eh
49Fh
4A0h
—
—
—
—
—
—
—
TMR3L
TMR3H
T3CON
T3GCON
—
—
—
TMR5L
TMR5H
T5CON
T5GCON
—
—
Accesses
70h-7Fh
47Fh
DS40001775B-page 35
87Fh
Legend:
Accesses
70h-7Fh
8EFh
8F0h
90Bh
90Ch
8FFh
Accesses
70h-7Fh
97Fh
64Fh
650h
66Fh
670h
= Unimplemented data memory locations, read as ‘0’.
6EFh
6F0h
Accesses
70h-7Fh
BANK 23
B80h
Core Registers
(Table 3-2)
B0Bh
B0Ch
Accesses
70h-7Fh
Accesses
70h-7Fh
BANK 22
Unimplemented
Read as ‘0’
AFFh
Unimplemented
Read as ‘0’
7FFh
B00h
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
B8Bh
B8Ch
Unimplemented
Read as ‘0’
B6Fh
B70h
B7Fh
—
—
—
—
—
—
—
—
PRG1RTSS
PRG1FTSS
PRG1INS
PRG1CON0
PRG1CON1
PRG1CON2
—
—
—
—
—
—
7EFh
7F0h
77Fh
A8Bh
A8Ch
78Bh
78Ch
78Dh
78Eh
78Fh
790h
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
79Bh
79Ch
79Dh
79Eh
79Fh
7A0h
Accesses
70h-7Fh
BANK 21
AEFh
AF0h
—
COG2PHR
COG2PHF
COG2BLKR
COG2BLKF
COG2DBR
COG2DBF
COG2CON0
COG2CON1
COG2RIS0
COG2RIS1
COG2RSIM0
COG2RSIM1
COG2FIS0
COG2FIS1
COG2FSIM0
COG2FSIM1
COG2ASD0
COG2ASD1
COG2STR
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Accesses
70h-7Fh
Unimplemented
Read as ‘0’
A7Fh
70Bh
70Ch
70Dh
70Eh
70Fh
710h
711h
712h
713h
714h
715h
716h
717h
718h
719h
71Ah
71Bh
71Ch
71Dh
71Eh
71Fh
720h
76Fh
770h
A80h
BANK 15
780h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Core Registers
(Table 3-2)
A6Fh
A70h
—
COG1PHR
COG1PHF
COG1BLKR
COG1BLKF
COG1DBR
COG1DBF
COG1CON0
COG1CON1
COG1RIS0
COG1RIS1
COG1RSIM0
COG1RSIM1
COG1FIS0
COG1FIS1
COG1FSIM0
COG1FSIM1
COG1ASD0
COG1ASD1
COG1STR
6FFh
A0Bh
A0Ch
Accesses
70h-7Fh
68Bh
68Ch
68Dh
68Eh
68Fh
690h
691h
692h
693h
694h
695h
696h
697h
698h
699h
69Ah
69Bh
69Ch
69Dh
69Eh
69Fh
6A0h
BANK 20
Unimplemented
Read as ‘0’
9FFh
Unimplemented
Read as ‘0’
A00h
98Bh
98Ch
Accesses
70h-7Fh
General Purpose
Register 48 Bytes
67Fh
Core Registers
(Table 3-2)
9EFh
9F0h
—
—
—
—
—
—
—
—
—
—
—
PWM3DCL
PWM3DCH
PWM3CON
—
—
—
—
—
—
BANK 14
700h
Core Registers
(Table 3-2)
Accesses
70h-7Fh
BANK 19
Unimplemented
Read as ‘0’
96Fh
970h
General
Purpose
Register
80 Bytes
980h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
60Bh
60Ch
60Dh
60Eh
60Fh
610h
611h
612h
613h
614h
615h
616h
617h
618h
619h
61Ah
61Bh
61Ch
61Dh
61Eh
61Fh
620h
Accesses
70h-7Fh
BANK 18
BANK 13
680h
Core Registers
(Table 3-2)
—
—
—
—
DACLD
DAC1CON0
DAC1REFL
DAC1REFH
—
—
—
DAC3CON0
DAC3REF
—
—
—
—
—
—
—
5FFh
900h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
86Fh
870h
Accesses
70h-7Fh
BANK 17
88Bh
88Ch
58Bh
58Ch
58Dh
58Eh
58Fh
590h
591h
592h
593h
594h
595h
596h
597h
598h
599h
59Ah
59Bh
59Ch
59Dh
59Eh
59Fh
5A0h
5EFh
5F0h
57Fh
880h
Core Registers
(Table 3-2)
—
—
—
OPA1NCHS
OPA1PCHS
OPA1CON
OPA1ORS
—
—
—
—
—
—
—
—
—
—
—
—
—
BANK 12
600h
Core Registers
(Table 3-2)
General
Purpose
Register
80 Bytes
Accesses
70h-7Fh
BANK 16
80Bh
80Ch
50Bh
50Ch
50Dh
50Eh
50Fh
510h
511h
512h
513h
514h
515h
516h
517h
518h
519h
51Ah
51Bh
51Ch
51Dh
51Eh
51Fh
520h
56Fh
570h
4FFh
800h
Core Registers
(Table 3-2)
General
Purpose
Register
80 Bytes
4EFh
4F0h
BANK 11
580h
Accesses
70h-7Fh
Unimplemented
Read as ‘0’
BEFh
BF0h
BFFh
Accesses
70h-7Fh
PIC16(L)F1764/5/8/9
General
Purpose
Register
80 Bytes
46Fh
470h
BANK 10
500h
PIC16(L)F1768 MEMORY MAP (BANKS 8-23)
BANK 8
400h
BANK 9
480h
Core Registers
(Table 3-2)
40Bh
40Ch
40Dh
40Eh
40Fh
410h
411h
412h
413h
414h
415h
416h
417h
418h
419h
41Ah
41Bh
41Ch
41Dh
41Eh
41Fh
420h
—
—
HIDRVC
—
—
—
—
T4TMR
T4PR
T4CON
T4HLT
T4CLKCON
T4RST
—
T6TMR
T6PR
T6CON
T6HLT
T6CLKCON
T6RST
Core Registers
(Table 3-2)
48Bh
48Ch
48Dh
48Eh
48Fh
490h
491h
492h
493h
494h
495h
496h
497h
498h
499h
49Ah
49Bh
49Ch
49Dh
49Eh
49Fh
4A0h
Unimplemented
Read as ‘0’
46Fh
470h
—
—
—
—
—
—
—
TMR3L
TMR3H
T3CON
T3GCON
—
—
—
TMR5L
TMR5H
T5CON
T5GCON
—
—
 2014-2015 Microchip Technology Inc.
Accesses
70h-7Fh
80Bh
80Ch
Unimplemented
Read as ‘0’
86Fh
870h
Unimplemented
Read as ‘0’
8EFh
8F0h
Accesses
70h-7Fh
87Fh
Legend:
Unimplemented
Read as ‘0’
96Fh
970h
Accesses
70h-7Fh
8FFh
Unimplemented
Read as ‘0’
9EFh
9F0h
Accesses
70h-7Fh
97Fh
= Unimplemented data memory locations, read as ‘0’.
Unimplemented
Read as ‘0’
A6Fh
A70h
Accesses
70h-7Fh
9FFh
Core Registers
(Table 3-2)
B8Bh
B8Ch
Unimplemented
Read as ‘0’
B6Fh
B70h
Accesses
70h-7Fh
AFFh
BANK 23
B80h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Accesses
70h-7Fh
A7Fh
BANK 22
B0Bh
B0Ch
AEFh
AF0h
Accesses
70h-7Fh
7FFh
B00h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
BEFh
BF0h
Accesses
70h-7Fh
B7Fh
—
—
—
—
—
—
—
—
PRG1RTSS
PRG1FTSS
PRG1INS
PRG1CON0
PRG1CON1
PRG1CON2
PRG2RTSS
PRG2FTSS
PRG2INS
PRG2CON0
PRG2CON1
PRG2CON2
Unimplemented
Read as ‘0’
Accesses
70h-7Fh
BANK 21
A8Bh
A8Ch
78Bh
78Ch
78Dh
78Eh
78Fh
790h
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
79Bh
79Ch
79Dh
79Eh
79Fh
7A0h
7EFh
7F0h
77Fh
A80h
Core Registers
(Table 3-2)
—
COG2PHR
COG2PHF
COG2BLKR
COG2BLKF
COG2DBR
COG2DBF
COG2CON0
COG2CON1
COG2RIS0
COG2RIS1
COG2RSIM0
COG2RSIM1
COG2FIS0
COG2FIS1
COG2FSIM0
COG2FSIM1
COG2ASD0
COG2ASD1
COG2STR
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Accesses
70h-7Fh
BANK 20
A0Bh
A0Ch
70Bh
70Ch
70Dh
70Eh
70Fh
710h
711h
712h
713h
714h
715h
716h
717h
718h
719h
71Ah
71Bh
71Ch
71Dh
71Eh
71Fh
720h
76Fh
770h
6FFh
A00h
Core Registers
(Table 3-2)
—
COG1PHR
COG1PHF
COG1BLKR
COG1BLKF
COG1DBR
COG1DBF
COG1CON0
COG1CON1
COG1RIS0
COG1RIS1
COG1RSIM0
COG1RSIM1
COG1FIS0
COG1FIS1
COG1FSIM0
COG1FSIM1
COG1ASD0
COG1ASD1
COG1STR
BANK 15
780h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Accesses
70h-7Fh
BANK 19
98Bh
98Ch
68Bh
68Ch
68Dh
68Eh
68Fh
690h
691h
692h
693h
694h
695h
696h
697h
698h
699h
69Ah
69Bh
69Ch
69Dh
69Eh
69Fh
6A0h
6EFh
6F0h
67Fh
980h
Core Registers
(Table 3-2)
—
—
—
—
—
—
—
—
—
—
—
PWM3DCL
PWM3DCH
PWM3CON
PWM4DCL
PWM4DCH
PWM4CON
—
—
—
BANK 14
700h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Accesses
70h-7Fh
BANK 18
90Bh
90Ch
60Bh
60Ch
60Dh
60Eh
60Fh
610h
611h
612h
613h
614h
615h
616h
617h
618h
619h
61Ah
61Bh
61Ch
61Dh
61Eh
61Fh
620h
66Fh
670h
5FFh
900h
Core Registers
(Table 3-2)
—
—
—
—
DACLD
DAC1CON0
DAC1REFL
DAC1REFH
DAC2CON0
DAC2REFL
DAC2REFH
DAC3CON0
DAC3REF
DAC4CON0
DAC4REF
—
—
—
—
—
BANK 13
680h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Accesses
70h-7Fh
BANK 17
88Bh
88Ch
58Bh
58Ch
58Dh
58Eh
58Fh
590h
591h
592h
593h
594h
595h
596h
597h
598h
599h
59Ah
59Bh
59Ch
59Dh
59Eh
59Fh
5A0h
5EFh
5F0h
57Fh
880h
Core Registers
(Table 3-2)
—
—
—
OPA1NCHS
OPA1PCHS
OPA1CON
OPA1ORS
OPA2NCHS
OPA2PCHS
OPA2CON
OPA2ORS
—
—
—
—
—
—
—
—
—
BANK 12
600h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Accesses
70h-7Fh
BANK 16
800h
50Bh
50Ch
50Dh
50Eh
50Fh
510h
511h
512h
513h
514h
515h
516h
517h
518h
519h
51Ah
51Bh
51Ch
51Dh
51Eh
51Fh
520h
56Fh
570h
4FFh
BANK 11
580h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
4EFh
4F0h
47Fh
BANK 10
500h
Accesses
70h-7Fh
BFFh
PIC16(L)F1764/5/8/9
DS40001775B-page 36
TABLE 3-9:
 2014-2015 Microchip Technology Inc.
TABLE 3-10:
PIC16(L)F1769 MEMORY MAP (BANKS 8-23)
BANK 8
400h
BANK 9
480h
Core Registers
(Table 3-2)
40Bh
40Ch
40Dh
40Eh
40Fh
410h
411h
412h
413h
414h
415h
416h
417h
418h
419h
41Ah
41Bh
41Ch
41Dh
41Eh
41Fh
420h
—
—
HIDRVC
—
—
—
—
T4TMR
T4PR
T4CON
T4HLT
T4CLKCON
T4RST
—
T6TMR
T6PR
T6CON
T6HLT
T6CLKCON
T6RST
Core Registers
(Table 3-2)
48Bh
48Ch
48Dh
48Eh
48Fh
490h
491h
492h
493h
494h
495h
496h
497h
498h
499h
49Ah
49Bh
49Ch
49Dh
49Eh
49Fh
4A0h
—
—
—
—
—
—
—
TMR3L
TMR3H
T3CON
T3GCON
—
—
—
TMR5L
TMR5H
T5CON
T5GCON
—
—
Accesses
70h-7Fh
47Fh
DS40001775B-page 37
Accesses
70h-7Fh
87Fh
Legend:
90Bh
90Ch
8EFh
8F0h
8FFh
64Fh
650h
66Fh
670h
97Fh
6EFh
6F0h
A7Fh
BANK 23
B80h
B0Bh
B0Ch
Core Registers
(Table 3-2)
B8Bh
B8Ch
Unimplemented
Read as ‘0’
B6Fh
B70h
Accesses
70h-7Fh
AFFh
7FFh
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Accesses
70h-7Fh
Accesses
70h-7Fh
BANK 22
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
BEFh
BF0h
Accesses
70h-7Fh
B7Fh
—
—
—
—
—
—
—
—
PRG1RTSS
PRG1FTSS
PRG1INS
PRG1CON0
PRG1CON1
PRG1CON2
PRG2RTSS
PRG2FTSS
PRG2INS
PRG2CON0
PRG2CON1
PRG2CON2
Unimplemented
Read as ‘0’
Accesses
70h-7Fh
B00h
AEFh
AF0h
78Bh
78Ch
78Dh
78Eh
78Fh
790h
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
79Bh
79Ch
79Dh
79Eh
79Fh
7A0h
7EFh
7F0h
77Fh
A8Bh
A8Ch
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
BANK 21
Unimplemented
Read as ‘0’
—
COG2PHR
COG2PHF
COG2BLKR
COG2BLKF
COG2DBR
COG2DBF
COG2CON0
COG2CON1
COG2RIS0
COG2RIS1
COG2RSIM0
COG2RSIM1
COG2FIS0
COG2FIS1
COG2FSIM0
COG2FSIM1
COG2ASD0
COG2ASD1
COG2STR
76Fh
770h
A80h
A6Fh
A70h
70Bh
70Ch
70Dh
70Eh
70Fh
710h
711h
712h
713h
714h
715h
716h
717h
718h
719h
71Ah
71Bh
71Ch
71Dh
71Eh
71Fh
720h
Accesses
70h-7Fh
Core Registers
(Table 3-2)
Accesses
70h-7Fh
—
COG1PHR
COG1PHF
COG1BLKR
COG1BLKF
COG1DBR
COG1DBF
COG1CON0
COG1CON1
COG1RIS0
COG1RIS1
COG1RSIM0
COG1RSIM1
COG1FIS0
COG1FIS1
COG1FSIM0
COG1FSIM1
COG1ASD0
COG1ASD1
COG1STR
BANK 15
780h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
BANK 20
Unimplemented
Read as ‘0’
9FFh
68Bh
68Ch
68Dh
68Eh
68Fh
690h
691h
692h
693h
694h
695h
696h
697h
698h
699h
69Ah
69Bh
69Ch
69Dh
69Eh
69Fh
6A0h
6FFh
A0Bh
A0Ch
9EFh
9F0h
= Unimplemented data memory locations, read as ‘0’.
Unimplemented
Read as ‘0’
A00h
Core Registers
(Table 3-2)
Accesses
70h-7Fh
General Purpose
Register 48 Bytes
67Fh
98Bh
98Ch
96Fh
970h
—
—
—
—
—
—
—
—
—
—
—
PWM3DCL
PWM3DCH
PWM3CON
PWM4DCL
PWM4DCH
PWM4CON
—
—
—
BANK 14
700h
Core Registers
(Table 3-2)
Accesses
70h-7Fh
BANK 19
Unimplemented
Read as ‘0’
Accesses
70h-7Fh
General
Purpose
Register
80 Bytes
980h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
60Bh
60Ch
60Dh
60Eh
60Fh
610h
611h
612h
613h
614h
615h
616h
617h
618h
619h
61Ah
61Bh
61Ch
61Dh
61Eh
61Fh
620h
Accesses
70h-7Fh
BANK 18
BANK 13
680h
Core Registers
(Table 3-2)
—
—
—
—
DACLD
DAC1CON0
DAC1REFL
DAC1REFH
DAC2CON0
DAC2REFL
DAC2REFH
DAC3CON0
DAC3REF
DAC4CON0
DAC4REF
—
—
—
—
—
5FFh
900h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
86Fh
870h
Accesses
70h-7Fh
BANK 17
88Bh
88Ch
58Bh
58Ch
58Dh
58Eh
58Fh
590h
591h
592h
593h
594h
595h
596h
597h
598h
599h
59Ah
59Bh
59Ch
59Dh
59Eh
59Fh
5A0h
5EFh
5F0h
57Fh
880h
Core Registers
(Table 3-2)
—
—
—
OPA1NCHS
OPA1PCHS
OPA1CON
OPA1ORS
OPA2NCHS
OPA2PCHS
OPA2CON
OPA2ORS
—
—
—
—
—
—
—
—
—
BANK 12
600h
Core Registers
(Table 3-2)
General
Purpose
Register
80 Bytes
Accesses
70h-7Fh
BANK 16
80Bh
80Ch
50Bh
50Ch
50Dh
50Eh
50Fh
510h
511h
512h
513h
514h
515h
516h
517h
518h
519h
51Ah
51Bh
51Ch
51Dh
51Eh
51Fh
520h
56Fh
570h
4FFh
800h
Core Registers
(Table 3-2)
General
Purpose
Register
80 Bytes
4EFh
4F0h
BANK 11
580h
Accesses
70h-7Fh
BFFh
PIC16(L)F1764/5/8/9
General
Purpose
Register
80 Bytes
46Fh
470h
BANK 10
500h
PIC16(L)F1764/5/8/9 MEMORY MAP (BANKS 24-31)
BANK 24
C00h
BANK 25
C80h
Core Registers
(Table 3-2)
C0Bh
BANK 26
D00h
Core Registers
(Table 3-2)
C8Bh
Core Registers
(Table 3-2)
D0Bh
—
C8Ch
—
D0Ch
—
C0Dh
—
C8Dh
—
D0Dh
—
C0Eh
—
C8Eh
—
D0Eh
—
C0Fh
—
C8Fh
—
D0Fh
—
C10h
—
C90h
—
D10h
—
C11h
—
C91h
—
D11h
—
C12h
—
C92h
—
D12h
—
C13h
—
C93h
—
D13h
—
C14h
—
C94h
—
D14h
—
C15h
—
C95h
—
D15h
—
C16h
—
C96h
—
D16h
—
C17h
—
C97h
—
D17h
—
C18h
—
C98h
—
D18h
—
C19h
—
C99h
—
D19h
—
C1Ah
—
C9Ah
—
D1Ah
—
C1Bh
—
C9Bh
—
D1Bh
—
C1Ch
—
C9Ch
—
D1Ch
—
C1Dh
—
C9Dh
—
D1Dh
—
C1Eh
—
C9Eh
—
D1Eh
—
C1Fh
—
C9Fh
—
D1Fh
—
CA0h
Unimplemented
Read as ‘0’
BANK 28
E00h
Core Registers
(Table 3-2)
D8Bh
C0Ch
C20h
BANK 27
D80h
BANK 29
E80h
Core Registers
(Table 3-2)
E0Bh
See Table 3-12
and Table 3-13
for Register
Mapping Details
BANK 30
F00h
Core Registers
(Table 3-2)
E8Bh
See Table 3-12
and Table 3-13
for Register
Mapping Details
Core Registers
(Table 3-2)
F0Bh
See Table 3-12
and Table 3-13
for Register
Mapping Details
Unimplemented
Read as ‘0’
 2014-2015 Microchip Technology Inc.
D6Fh
DEFh
E6Fh
EEFh
F6Fh
CF0h
D70h
DF0h
E70h
EF0h
F70h
CFFh
See Table 3-14
for Register
Mapping Details
Unimplemented
Read as ‘0’
CEFh
CFFh
F8Bh
D20h
C70h
Legend:
Core Registers
(Table 3-2)
See Table 3-12
and Table 3-13
for Register
Mapping Details
C6Fh
Accesses
70h-7Fh
BANK 31
F80h
Accesses
70h-7Fh
D7Fh
Accesses
70h-7Fh
= Unimplemented data memory locations, read as ‘0’.
DFFh
Accesses
70h-7Fh
E7Fh
Accesses
70h-7Fh
EFFh
Accesses
70h-7Fh
F7Fh
FEFh
Accesses
70h-7Fh
FF0h
FFFh
Accesses
70h-7Fh
PIC16(L)F1764/5/8/9
DS40001775B-page 38
TABLE 3-11:
PIC16(L)F1764/5/8/9
TABLE 3-12:
PIC16(L)F1764/5 MEMORY MAP (BANKS 27-30)
Bank 27
Bank 28
D8Ch
D8Dh
D8Eh
—
—
E0Ch
E0Dh
PWMEN
D8Fh
D90h
D91h
PWMLD
PWMOUT
PWM5PHL
D92h
D93h
Bank 29
Bank 30
—
—
E8Ch
E8Dh
—
—
F0Ch
F0Dh
—
—
E0Eh
—
E8Eh
E0Fh
E10h
E11h
PPSLOCK
INTPPS
T0CKIPPS
E8Fh
E90h
E91h
—
—
RA0PPS
RA1PPS
F0Eh
F0Fh
F10h
F11h
—
CLCDATA
CLC1CON
CLC1POL
PWM5PHH
PWM5DCL
E12h
E13h
T1CKIPPS
T1GPPS
E92h
E93h
RA2PPS
—
F12h
F13h
CLC1SEL0
CLC1SEL1
D94h
D95h
D96h
D97h
PWM5DCH
PWM5PRL
PWM5PRH
PWM5OFL
E14h
E15h
E16h
E17h
F14h
F15h
F16h
CLC1SEL2
CLC1SEL3
CLC1GLS0
PWM5OFH
PWM5TMRL
PWM5TMRH
E18h
E19h
E1Ah
E94h
E95h
E96h
E97h
E98h
E99h
E9Ah
RA4PPS
RA5PPS
—
D98h
D99h
D9Ah
CCP1PPS
—
COG1INPPS
—
—
T2CKIPPS
T3CKIPPS
—
—
—
F17h
F18h
F19h
CLC1GLS1
CLC1GLS2
CLC1GLS3
D9Bh
D9Ch
D9Dh
PWM5CON
PWM5INTE
PWM5INTF
E1Bh
E1Ch
E1Dh
T3GPPS
T4CKIPPS
T5CKIPPS
E9Bh
E9Ch
E9Dh
—
—
—
F1Ah
F1Bh
F1Ch
CLC2CON
CLC2POL
CLC2SEL0
D9Eh
D9Fh
DA0h
DA1h
DA2h
DA3h
DA4h
DA5h
DA6h
DA7h
DA8h
DA9h
DAAh
DABh
DACh
DADh
DAEh
DAFh
DB0h
DB1h
DB2h
DB3h
DB4h
DB5h
DB6h
DB7h
DB8h
DB9h
PWM5CLKCON
PWM5LDCON
PWM5OFCON
—
—
—
—
—
—
E1Eh
E1Fh
E20h
E21h
E22h
E23h
E24h
E25h
E26h
T5GPPS
T6CKIPPS
SSPCLKPPS
SSPDATPPS
SSPSSPPS
—
RXPPS
CKPPS
—
E9Eh
E9Fh
EA0h
EA1h
EA2h
EA3h
EA4h
EA5h
EA6h
—
—
—
RC0PPS
RC1PPS
RC2PPS
RC3PPS
RC4PPS
RC5PPS
—
F1Dh
F1Eh
F1Fh
F20h
F21h
F22h
F23h
F24h
F25h
F26h
CLC2SEL1
CLC2SEL2
CLC2SEL3
CLC2GLS0
CLC2GLS1
CLC2GLS2
CLC2GLS3
CLC3CON
CLC3POL
CLC3SEL0
—
—
—
E27h
E28h
E29h
—
CLCIN0PPS
CLCIN1PPS
EA7h
EA8h
EA9h
—
—
—
F27h
F28h
F29h
CLC3SEL1
CLC3SEL2
CLC3SEL3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
E2Ah
E2Bh
E2Ch
E2Dh
E2Eh
E2Fh
E30h
E31h
E32h
E33h
E34h
E35h
E36h
E37h
E38h
CLCIN2PPS
CLCIN3PPS
PRG1FPPS
PRG1RPPS
—
—
MD1CHPPS
MD1CLPPS
MD1MODPPS
—
—
—
—
—
—
EAAh
EABh
EACh
EADh
EAEh
EAFh
EB0h
EB1h
EB2h
EB3h
EB4h
EB5h
EB6h
EB7h
EB8h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
F2Ah
F2Bh
F2Ch
F2Dh
F2Eh
F2Fh
F30h
F31h
F32h
F33h
F34h
F35h
F36h
F37h
F38h
CLC3GLS0
CLC3GLS1
CLC3GLS2
CLC3GLS3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
E39h
E3Ah
E3Bh
E3Ch
—
—
—
—
EB9h
EBAh
EBBh
EBCh
—
—
—
—
F39h
F3Ah
F3Bh
F3Ch
—
—
—
—
—
—
—
E3Dh
E3Eh
E3Fh
—
—
—
EBDh
EBEh
EBFh
—
—
—
F3Dh
F3Eh
F3Fh
—
—
—
DBAh
DBBh
DBCh
DBDh
DBEh
DBFh
DC0h
E40h
—
DEFh
Legend:
EC0h
—
E6Fh
F40h
—
EEFh
—
F6Fh
= Unimplemented data memory locations, read as ‘0’,
 2014-2015 Microchip Technology Inc.
DS40001775B-page 39
PIC16(L)F1764/5/8/9
TABLE 3-13:
PIC16(L)F1768/9 MEMORY MAP (BANKS 27-30)
Bank 27
D8Ch
D8Dh
D8Eh
D8Fh
D90h
D91h
D92h
D93h
D94h
D95h
D96h
D97h
D98h
D99h
D9Ah
D9Bh
D9Ch
D9Dh
D9Eh
D9Fh
DA0h
DA1h
DA2h
DA3h
DA4h
DA5h
DA6h
DA7h
DA8h
DA9h
DAAh
DABh
DACh
DADh
DAEh
DAFh
DB0h
DB1h
DB2h
DB3h
DB4h
DB5h
DB6h
DB7h
DB8h
DB9h
DBAh
DBBh
DBCh
DBDh
DBEh
DBFh
DC0h
—
—
PWMEN
PWMLD
PWMOUT
PWM5PHL
PWM5PHH
PWM5DCL
PWM5DCH
PWM5PRL
PWM5PRH
PWM5OFL
PWM5OFH
PWM5TMRL
PWM5TMRH
PWM5CON
PWM5INTE
PWM5INTF
PWM5CLKCON
PWM5LDCON
PWM5OFCON
PWM6PHL
PWM6PHH
PWM6DCL
PWM6DCH
PWM6PRL
PWM6PRH
PWM6OFL
PWM6OFH
PWM6TMRL
PWM6TMRH
PWM6CON
PWM6INTE
PWM6INTF
PWM6CLKCON
PWM6LDCON
PWM6OFCON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bank 28
E0Ch
E0Dh
E0Eh
E0Fh
E10h
E11h
E12h
E13h
E14h
E15h
E16h
E17h
E18h
E19h
E1Ah
E1Bh
E1Ch
E1Dh
E1Eh
E1Fh
E20h
E21h
E22h
E23h
E24h
E25h
E26h
E27h
E28h
E29h
E2Ah
E2Bh
E2Ch
E2Dh
E2Eh
E2Fh
E30h
E31h
E32h
E33h
E34h
E35h
E36h
E37h
E38h
E39h
E3Ah
E3Bh
E3Ch
E3Dh
E3Eh
E3Fh
E40h
—
DEFh
Legend:
DS40001775B-page 40
—
—
—
PPSLOCK
INTPPS
T0CKIPPS
T1CKIPPS
T1GPPS
CCP1PPS
CCP2PPS
COG1INPPS
COG2INPPS
—
T2CKIPPS
T3CKIPPS
T3GPPS
T4CKIPPS
T5CKIPPS
T5GPPS
T6CKIPPS
SSPCLKPPS
SSPDATPPS
SSPSSPPS
—
RXPPS
CKPPS
—
—
CLCIN0PPS
CLCIN1PPS
CLCIN2PPS
CLCIN3PPS
PRG1FPPS
PRG1RPPS
PRG2FPPS
PRG2RPPS
MD1CHPPS
MD1CLPPS
MD1MODPPS
MD2CHPPS
MD2CLPPS
MD2MODPPS
—
—
—
—
—
—
—
—
—
—
Bank 29
E8Ch
E8Dh
E8Eh
E8Fh
E90h
E91h
E92h
E93h
E94h
E95h
E96h
E97h
E98h
E99h
E9Ah
E9Bh
E9Ch
E9Dh
E9Eh
E9Fh
EA0h
EA1h
EA2h
EA3h
EA4h
EA5h
EA6h
EA7h
EA8h
EA9h
EAAh
EABh
EACh
EADh
EAEh
EAFh
EB0h
EB1h
EB2h
EB3h
EB4h
EB5h
EB6h
EB7h
EB8h
EB9h
EBAh
EBBh
EBCh
EBDh
EBEh
EBFh
EC0h
—
E6Fh
—
—
—
—
RA0PPS
RA1PPS
RA2PPS
—
RA4PPS
RA5PPS
—
—
—
—
—
—
RB4PPS
RB5PPS
RB6PPS
RB7PPS
RC0PPS
RC1PPS
RC2PPS
RC3PPS
RC4PPS
RC5PPS
RC6PPS
RC7PPS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bank 30
F0Ch
F0Dh
F0Eh
F0Fh
F10h
F11h
F12h
F13h
F14h
F15h
F16h
F17h
F18h
F19h
F1Ah
F1Bh
F1Ch
F1Dh
F1Eh
F1Fh
F20h
F21h
F22h
F23h
F24h
F25h
F26h
F27h
F28h
F29h
F2Ah
F2Bh
F2Ch
F2Dh
F2Eh
F2Fh
F30h
F31h
F32h
F33h
F34h
F35h
F36h
F37h
F38h
F39h
F3Ah
F3Bh
F3Ch
F3Dh
F3Eh
F3Fh
F40h
—
EEFh
—
—
—
CLCDATA
CLC1CON
CLC1POL
CLC1SEL0
CLC1SEL1
CLC1SEL2
CLC1SEL3
CLC1GLS0
CLC1GLS1
CLC1GLS2
CLC1GLS3
CLC2CON
CLC2POL
CLC2SEL0
CLC2SEL1
CLC2SEL2
CLC2SEL3
CLC2GLS0
CLC2GLS1
CLC2GLS2
CLC2GLS3
CLC3CON
CLC3POL
CLC3SEL0
CLC3SEL1
CLC3SEL2
CLC3SEL3
CLC3GLS0
CLC3GLS1
CLC3GLS2
CLC3GLS3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
F6Fh
= Unimplemented data memory locations, read as ‘0’,
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
TABLE 3-14:
PIC16(L)F1764/5/8/9 MEMORY MAP (BANK 31)
Bank 31
F8Ch
FE3h
FE4h
FE5h
STATUS_SHAD
WREG_SHAD
FE6h
FE7h
BSR_SHAD
PCLATH_SHAD
FE8h
FE9h
FSR0L_SHAD
FSR0H_SHAD
FEAh
FEBh
FSR1L_SHAD
FSR1H_SHAD
FECh
—
FEDh
FEEh
STKPTR
TOSL
FEFh
Legend:
 2014-2015 Microchip Technology Inc.
Unimplemented
Read as ‘0’
TOSH
= Unimplemented data memory locations, read as ‘0’,
DS40001775B-page 41
PIC16(L)F1764/5/8/9
3.3.6
CORE FUNCTION REGISTERS
SUMMARY
The core function registers listed in Table 3-15 can be
addressed from any bank.
TABLE 3-15:
Addr
CORE FUNCTION REGISTERS SUMMARY(1)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
All Other
Resets
Bank 0-31
x00h or
INDF0
x80h
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx uuuu uuuu
x01h or
INDF1
x81h
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
xxxx xxxx uuuu uuuu
x02h or
PCL
x82h
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
x03h or
STATUS
x83h
—
—
—
TO
PD
Z
DC
C
---1 1000 ---q quuu
x04h or
FSR0L
x84h
Indirect Data Memory Address 0 Low Pointer
0000 0000 uuuu uuuu
x05h or
FSR0H
x85h
Indirect Data Memory Address 0 High Pointer
0000 0000 0000 0000
x06h or
FSR1L
x86h
Indirect Data Memory Address 1 Low Pointer
0000 0000 uuuu uuuu
x07h or
FSR1H
x87h
Indirect Data Memory Address 1 High Pointer
0000 0000 0000 0000
x08h or
BSR
x88h
x09h or
WREG
x89h
—
—
—
BSR4
BSR3
BSR2
BSR1
BSR0
Working Register
x0Ah or
PCLATH
x8Ah
—
x0Bh or
INTCON
x8Bh
GIE
0000 0000 uuuu uuuu
Write Buffer for the upper 7 bits of the Program Counter
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
-000 0000 -000 0000
INTF
IOCIF
Legend:
x = unknown; u = unchanged; q = value depends on condition; - = unimplemented, read as ‘0’.
Shaded locations are unimplemented, read as ‘0’.
Note
These registers can be addressed from any bank.
1:
DS40001775B-page 42
---0 0000 ---0 0000
0000 0000 0000 0000
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
TABLE 3-16:
Addr
Name
SPECIAL FUNCTION REGISTER SUMMARY
Bit 7
Bit 6
—
—
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
Value on
POR, BOR
Value on
All Other
Resets
Bank 0
00Ch PORTA
RA<5:0>
00Dh PORTB(2)
RB<7:4>
RC<7:6>(2)
00Eh PORTC
--xx xxxx --uu uuuu
—
xxxx ---- uuuu ----
RC<5:0>
xxxx xxxx uuuu uuuu
00Fh
—
Unimplemented
—
—
010h
—
Unimplemented
—
—
011h
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
012h PIR2
OSFIF
C2IF
C1IF
—
BCL1IF
C4IF(2)
C3IF(2)
CCP2IF(2)
000- 0000 000- 0000
013h PIR3
PWM6IF(2)
PWM5IF
COG1IF
ZCDIF
COG2IF(2)
CLC3IF
CLC2IF
CLC1IF
0000 0000 0000 0000
014h PIR4
—
—
TMR5GIF
TMR5IF
TMR3GIF
TMR3IF
TMR6IF
TRM4IF
--00 0000 --00 0000
015h TMR0
Timer0 Module Register
0000 0000 0000 0000
016h TMR1L
Holding Register for the Least Significant Byte of the 16-Bit TMR1 Register
xxxx xxxx uuuu uuuu
017h TMR1H
Holding Register for the Most Significant Byte of the 16-Bit TMR1 Register
xxxx xxxx uuuu uuuu
018h T1CON
CS<1:0>
019h T1GCON
GE
CKPS<1:0>
GPOL
GTM
GSPM
01Ah T2TMR
Holding Register for the 8-Bit TMR2 Register
01Bh T2PR
TMR2 Period Register
OSCEN
SYNC
GGO/DONE
GVAL
—
ON
0000 00-0 uuuu uu-u
GSS<1:0>
0000 0x00 uuuu uxuu
0000 0000 0000 0000
1111 1111 1111 1111
01Ch T2CON
ON
CKPS<2:0>
OUTPS<3:0>
01Dh T2HLT
PSYNC
CKPOL
CKSYNC
01Eh T2CLKCON
—
—
—
—
CS<3:0>
---- 0000 ---- 0000
01Fh T2RST
—
—
—
—
RSEL<3:0>
---- 0000 ---- 0000
—
—
0000 0000 0000 0000
MODE<4:0>
0000 0000 0000 0000
Bank 1
08Ch TRISA
(2)
08Dh TRISB
—(1)
TRISA<5:4>
TRISB<7:4>
TRISC<7:6>(2)
08Eh TRISC
TRISA<2:0>
—
—
--11 1111 --11 1111
—
—
1111 ---- 1111 ----
TRISC<5:0>
1111 1111 1111 1111
08Fh
—
Unimplemented
—
—
090h
—
Unimplemented
—
—
091h PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
092h PIE2
OSFIE
C2IE
C1IE
—
BCL1IE
093h PIE3
(2)
C3IE(2)
CCP2IE(2)
000- 0000 000- 0000
PWM5IE
COG1IE
ZCDIE
COG2IE
CLC3IE
CLC2IE
CLC1IE
0000 0000 0000 0000
—
—
TMR5GIE
TMR5IE
TMR3GIE
TMR3IE
TMR6IE
TRM4IE
--00 0000 --00 0000
095h OPTION_REG
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
096h PCON
STKOVF
STKUNF
—
RWDT
RMCLR
097h WDTCON
—
—
098h OSCTUNE
—
—
099h OSCCON
SPLLEN
09Ah OSCSTAT
SOSCR
094h PIE4
PWM6IE
C4IE(2)
(2)
09Bh ADRESL
ADC Result Register Low
09Ch ADRESH
ADC Result Register High
09Dh ADCON0
—
09Eh ADCON1
ADFM
09Fh ADCON2
Legend:
Note 1:
2:
3:
4:
RI
POR
WDTPS<4:0>
1111 1111 1111 1111
BOR
00-1 11qq qq-q qquu
SWDTEN
--01 0110 --01 0110
TUN<5:0>
IRCF<3:0>
PLLR
PS<2:0>
OSTS
HFIOFR
--00 0000 --00 0000
—
HFIOFL
MFIOFR
SCS<1:0>
LFIOFR
0011 1-00 0011 1-00
HFIOFS
00q0 0q0q qqqq qq0q
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CHS<4:0>
ADCS<2:0>
TRIGSEL<4:0>
GO/DONE
—
ADNREF
—
ADON
ADPREF<1:0>
—
—
-000 0000 -000 0000
0000 -000 0000 -000
0000 0--- 0000 0---
x = unknown; u = unchanged; q = value depends on condition; - = unimplemented, read as ‘0’; r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Unimplemented, read as ‘1’.
PIC16(L)F1768/9 only.
PIC16(L)F1764/5 only.
Unimplemented on PIC16LF1764/5/8/9.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 43
PIC16(L)F1764/5/8/9
TABLE 3-16:
Addr
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
—
—
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
All Other
Resets
Bank 2
10Ch LATA
10Dh LATB(2)
LATA<5:4>
—
LATB<7:4>
LATC<7:6>(2)
10Eh LATC
LATA<2:0>
—
—
--xx -xxx --uu -uuu
—
—
MC2OUT
MC1OUT
---- 0000 ---- 0000
LATC<5:0>
xxxx ---- uuuu ---xxxx xxxx uuuu uuuu
MC4OUT(2) MC3OUT(2)
10Fh CMOUT
—
—
—
—
110h
CM1CON0
ON
OUT
—
POL
ZLF
Reserved
HYS
SYNC
00-0 0100 00-0 0100
111h
CM1CON1
—
—
—
—
—
—
INTP
INTN
---- --00 ---- --00
112h
CM1NSEL
—
—
—
—
—
NCH<2:0>
113h
CM1PSEL
—
—
—
—
—
PCH<2:0>
114h
CM2CON0
ON
OUT
—
POL
ZLF
Reserved
HYS
SYNC
00-0 0100 00-0 0100
115h
CM2CON1
—
—
—
—
—
—
INTP
INTN
---- --00 ---- --00
116h
CM2NSEL
—
—
—
—
—
NCH<2:0>
117h
CM2PSEL
—
—
—
—
—
PCH<2:0>
118h
CM3CON0(2)
ON
OUT
—
POL
ZLF
Reserved
HYS
SYNC
00-0 0100 00-0 0100
119h
CM3CON1(2)
—
—
—
—
—
—
INTP
INTN
---- --00 ---- --00
11Ah CM3NSEL(2)
—
—
—
—
—
NCH<2:0>
11Bh CM3PSEL(2)
—
—
—
—
—
PCH<2:0>
11Ch CM4CON0(2)
ON
OUT
—
POL
ZLF
Reserved
HYS
SYNC
00-0 0100 00-0 0100
11Dh CM4CON1(2)
—
—
—
—
—
—
INTP
INTN
---- --00 ---- --00
11Eh CM4NSEL(2)
—
—
—
—
—
NCH<2:0>
---- -000 ---- -000
11Fh CM4PSEL(2)
—
—
—
—
—
PCH<2:0>
---- -000 ---- -000
—
—
—
ANSA4
—
---- -000 ---- -000
---- -000 ---- -000
---- -000 ---- -000
---- -000 ---- -000
---- -000 ---- -000
---- -000 ---- -000
Bank 3
18Ch ANSELA
18Dh ANSELB(2)
ANSB<7:4>
ANSC<7:6>(2)
18Eh ANSELC
—
—
—
ANSA<2:0>
—
—
---1 -111 ---1 -111
—
ANSC<3:0>
1111 ---- 1111 ---11-- 1111 11-- 1111
18Fh
—
Unimplemented
—
—
190h
—
Unimplemented
—
—
191h PMADRL
Program Memory Address Register Low Byte
—(1)
192h PMADRH
193h PMDATL
Program Memory Address Register High Byte
—
—
195h PMCON1
—(1)
CFGS
—
xxxx xxxx uuuu uuuu
Program Memory Read Data Register High Byte
LWLO
--xx xxxx --uu uuuu
FREE
WRERR
WREN
WR
RD
—
—
—
VREGPM
Reserved
Program Memory Control Register 2
197h VREGCON(4)
198h
1000 0000 1000 0000
Program Memory Read Data Register Low Byte
194h PMDATH
196h PMCON2
0000 0000 0000 0000
—
—
—
1000 x000 1000 q000
0000 0000 0000 0000
Unimplemented
---- --01 ---- --01
—
199h RC1REG
EUSART Receive Data Register
19Ah TX1REG
EUSART Transmit Data Register
—
0000 0000 0000 0000
0000 0000 0000 0000
19Bh SP1BRGL
SP1BRG<7:0>
19Ch SP1BRGH
SP1BRG<15:8>
0000 0000 0000 0000
0000 0000 0000 0000
19Dh RC1STA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 0000 0000 0000
19Eh TX1STA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
0000 0010 0000 0010
ABDOVF
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN
01-0 0-00 01-0 0-00
19Fh BAUD1CON
Legend:
Note 1:
2:
3:
4:
x = unknown; u = unchanged; q = value depends on condition; - = unimplemented, read as ‘0’; r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Unimplemented, read as ‘1’.
PIC16(L)F1768/9 only.
PIC16(L)F1764/5 only.
Unimplemented on PIC16LF1764/5/8/9.
DS40001775B-page 44
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
TABLE 3-16:
Addr
Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7
Bit 6
—
—
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
Value on
POR, BOR
Value on
All Other
Resets
Bank 4
20Ch WPUA
20Dh WPUB(2)
WPUA<5:0
WPUB<7:4>
—
WPUC<7:6>(2)
20Eh WPUC
--11 1111 --11 1111
1111 ---- 1111 ----
WPUC<5:0>
1111 1111 1111 1111
20Fh
—
Unimplemented
—
—
210h
—
Unimplemented
—
—
211h
SSP1BUF
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
212h SSP1ADD
ADD<7:0>
213h SSP1MSK
MSK<7:0>
0000 0000 0000 0000
1111 1111 1111 1111
214h SSP1STAT
SMP
CKE
D/A
P
215h SSP1CON1
WCOL
SSPOV
SSPEN
CKP
216h SSP1CON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
0000 0000 0000 0000
217h SSP1CON3
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
0000 0000 0000 0000
218h
—
21Ch
—
R/W
UA
BF
0000 0000 0000 0000
SSPM<3:0>
0000 0000 0000 0000
Unimplemented
—
21Dh BORCON
SBOREN
BORFS
—
—
21Eh FVRCON
FVREN
FVRRDY
TSEN
TSRNG
EN
—
OUT
POL
—
—
21Fh ZCD1CON
S
—
—
—
CDAFVR<1:0>
—
BORRDY
ADFVR<1:0>
—
INTP
—
10-- ---q uu-- ---u
0q00 0000 0q00 0000
INTN
0-x0 --00 0-x0 --00
Bank 5
28Ch ODCONA
28Dh ODCONB(2)
28Eh ODCONC
ODA<5:4>
—
ODB<7:4>
—
ODC<7:6>(2)
ODA<2:0>
—
—
--00 -000 --00 -000
—
ODC<5:0>
0000 ---- 0000 ---0000 0000 0000 0000
28Fh
—
Unimplemented
—
—
290h
—
Unimplemented
—
—
291h CCPR1L
Capture/Compare/PWM Register 1 (LSB)
292h CCPR1H
Capture/Compare/PWM Register 1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
293h CCP1CON
EN
—
OUT
FMT
294h CCP1CAP
—
—
—
—
295h
—
297h
—
Capture/Compare/PWM Register 2 (LSB)
Capture/Compare/PWM Register 2 (MSB)
—
OUT
FMT
29Bh CCP2CAP(2)
—
—
—
—
Legend:
Note 1:
2:
3:
4:
—
MODE<3:0>
—
0-00 0000 0-00 0000
CTS<2:0>
Unimplemented
P4TSEL<1:0>(2)
—
xxxx xxxx uuuu uuuu
EN
29Fh
---- -000 ---- -000
xxxx xxxx uuuu uuuu
29Ah CCP2CON(2)
29Eh CCPTMRS
0-00 0000 0-00 0000
CTS<2:0>
—
299h CCPR2H(2)
—
—
Unimplemented
298h CCPR2L(2)
29Ch
—
29Dh
MODE<3:0>
---- -000 ---- -000
—
P3TSEL<1:0>
C2TSEL<1:0>(2)
C1TSEL<1:0>
Unimplemented
—
0000 0000 0000 0000
—
—
x = unknown; u = unchanged; q = value depends on condition; - = unimplemented, read as ‘0’; r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Unimplemented, read as ‘1’.
PIC16(L)F1768/9 only.
PIC16(L)F1764/5 only.
Unimplemented on PIC16LF1764/5/8/9.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 45
PIC16(L)F1764/5/8/9
TABLE 3-16:
Addr
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
—
—
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
All Other
Resets
Bank 6
30Ch SLRCONA
30Dh SLRCONB(2)
—
—
SLRA<2:0>
—
SLRC<7:6>(2)
30Eh SLRCONC
30Fh
—
31Ah
SLRA<5:4>
SLRB<7:4>
—
—
--11 -111 --11 -111
—
SLRC<5:0>
1111 ---- 1111 ---1111 1111 1111 1111
Unimplemented
—
—
31Bh MD2CON0(2)
EN
—
OUT
OPOL
—
—
—
BIT
0-00 ---0 0-00 ---0
31Ch MD2CON1(2)
—
—
CHPOL
CHSYNC
—
—
CLPOL
CLSYNC
--00 --00 --00 --00
31Dh MD2SRC(2)
—
—
—
31Eh MD2CARL(2)
—
—
—
—
CL<3:0>
---- 0000 ---- 0000
31Fh MD2CARH(2)
—
—
—
—
CH<3:0>
---- 0000 ---- 0000
—
—
MS<4:0>
---0 0000 ---0 0000
Bank 7
38Ch INLVLA
38Dh INLVLB(2)
INLVLA<5:0>
INLVLB<7:4>
—
INLVLC<7:6>(2)
38Eh INLVLC
--11 1111 --11 1111
—
—
—
INLVLC<5:0>
1111 ---- 1111 ---1111 1111 1111 1111
38Fh
—
Unimplemented
—
—
390h
—
Unimplemented
—
—
391h IOCAP
—
—
IOCAP<5:0>
--00 0000 --00 0000
392h IOCAN
—
—
IOCAN<5:0>
--00 0000 --00 0000
393h IOCAF
—
—
IOCAF<5:0>
--00 0000 --00 0000
394h IOCBP(2)
IOCBP<7:4>
—
—
—
—
0000 ---- 0000 ----
395h IOCBN(2)
IOCBN<7:4>
—
—
—
—
0000 ---- 0000 ----
396h IOCBF(2)
IOCBF<7:4>
—
—
—
—
0000 ---- 0000 ----
397h IOCCP
IOCCP<7:6>(2)
IOCCP<5:0>
0000 0000 0000 0000
398h IOCCN
IOCCN<7:6>(2)
IOCCN<5:0>
0000 0000 0000 0000
399h IOCCF
IOCCF<7:6>(2)
IOCCF<5:0>
0000 0000 0000 0000
39Ah
—
Unimplemented
—
—
39Bh MD1CON0
EN
—
OUT
OPOL
—
39Ch MD1CON1
—
—
CHPOL
CHSYNC
—
39Dh MD1SRC
—
—
—
39Eh MD1CARL
—
—
—
—
CL<3:0>
---- 0000 ---- 0000
39Fh MD1CARH
—
—
—
—
CH<3:0>
---- 0000 ---- 0000
Legend:
Note 1:
2:
3:
4:
—
—
BIT
0-00 ---0 0-00 ---0
—
CLPOL
CLSYNC
--00 --00 --00 --00
MS<4:0>
---0 0000 ---0 0000
x = unknown; u = unchanged; q = value depends on condition; - = unimplemented, read as ‘0’; r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Unimplemented, read as ‘1’.
PIC16(L)F1768/9 only.
PIC16(L)F1764/5 only.
Unimplemented on PIC16LF1764/5/8/9.
DS40001775B-page 46
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
TABLE 3-16:
Addr
Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
All Other
Resets
—
—
Bank 8
40Ch
—
40Dh
—
40Eh HIDRVC
40Fh
—
412h
—
Unimplemented
—
—
HIDC<5:4>
—
—
—
—
Unimplemented
--00 ---- --00 ---—
413h T4TMR
Holding Register for the 8-Bit TMR4 Register
413h T4PR
TMR4 Period Register
—
0000 0000 0000 0000
1111 1111 1111 1111
415h T4CON
ON
416h T4HLT
PSYNC
CKPOL
CKSYNC
417h T4CLKCON
—
—
—
—
CS<3:0>
---- 0000 ---- 0000
418h T4RST
—
—
—
—
RSEL<3:0>
---- 0000 ---- 0000
419h
—
CKPS<2:0>
OUTPS<3:0>
0000 0000 0000 0000
MODE<4:0>
0000 0000 0000 0000
Unimplemented
—
41Ah T6TMR
Holding Register for the 8-Bit TMR4 Register
41Bh T6PR
TMR4 Period Register
—
0000 0000 0000 0000
1111 1111 1111 1111
41Ch T6CON
ON
CKPS<2:0>
OUTPS<3:0>
41Dh T6HLT
PSYNC
CKPOL
CKSYNC
41Eh T6CLKCON
—
—
—
—
CS<3:0>
---- 0000 ---- 0000
41Fh T6RST
—
—
—
—
RSEL<3:0>
---- 0000 ---- 0000
0000 0000 0000 0000
MODE<4:0>
0000 0000 0000 0000
Bank 9
48Ch
to
492h
—
Unimplemented
—
493h TMR3L
Holding Register for the Least Significant Byte of the 16-Bit TMR1 Register
494h TMR3H
Holding Register for the Most Significant Byte of the 16-Bit TMR1 Register
495h T3CON
CS<1:0>
496h T3GCON
497h
to
499h
—
GE
GPOL
CKPS<1:0>
GTM
GSPM
GGO/DONE
GVAL
49Ch T5CON
Legend:
Note 1:
2:
3:
4:
ON
GSS<1:0>
CS<1:0>
GE
GPOL
0000 00-0 uuuu uu-u
0000 0x00 uuuu uxuu
—
Holding Register for the Most Significant Byte of the 16-Bit TMR1 Register
—
—
Unimplemented
Holding Register for the Least Significant Byte of the 16-Bit TMR1 Register
49Eh
to
49Fh
xxxx xxxx uuuu uuuu
SYNC
49Ah TMR5L
49Dh T5GCON
xxxx xxxx uuuu uuuu
OSCEN
49Bh TMR5H
CKPS<1:0>
GTM
GSPM
—
—
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
OSCEN
SYNC
GGO/DONE
GVAL
—
ON
GSS<1:0>
Unimplemented
0000 00-0 uuuu uu-u
0000 0x00 uuuu uxuu
—
—
x = unknown; u = unchanged; q = value depends on condition; - = unimplemented, read as ‘0’; r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Unimplemented, read as ‘1’.
PIC16(L)F1768/9 only.
PIC16(L)F1764/5 only.
Unimplemented on PIC16LF1764/5/8/9.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 47
PIC16(L)F1764/5/8/9
TABLE 3-16:
Addr
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
All Other
Resets
—
—
Bank 10
50Ch
—
50Eh
—
Unimplemented
50Fh OPA1NCHS
—
—
—
—
NCH<3:0>
510h OPA1PCHS
—
—
—
—
PCH<3:0>
511h
OPA1CON
EN
—
—
UG
512h OPA1ORS
—
—
—
513h OPA2NCHS(2)
—
—
—
—
NCH<3:0>
514h OPA2PCHS(2)
—
—
—
—
PCH<3:0>
515h OPA2CON(2)
EN
—
—
UG
516h OPA2ORS(2)
—
—
—
517h
—
51Fh
—
—
ORPOL
---- 0000 ---- 0000
---- 0000 ---- 0000
ORM<1:0>
ORS<4:0>
—
ORPOL
0--0 -000 0--0 -000
---0 0000 ---0 0000
---- 0000 ---- 0000
---- 0000 ---- 0000
ORM<1:0>
ORS<4:0>
0--0 -000 0--0 -000
---0 0000 ---0 0000
Unimplemented
—
—
Bank 11
590h DACLD
---
---
---
---
591h DAC1CON0
EN
FM
OE1
---
--PSS<1:0>
592h DAC1REFL
REF<7:0>
593h DAC1REFH
REF<15:8>
594h DAC2CON0(2)
EN
FM
OE1
--REF<7:0>
596h DAC2REFH(2)
REF<15:8>
EN
---
OE1
598h DAC3REF
---
---
---
599h DAC4CON0(2)
EN
---
OE1
59Ah DAC4REF(2)
---
---
---
59Bh
to
59Fh
Legend:
Note 1:
2:
3:
4:
—
---
DAC2LD(2)
DAC1LD
NSS<1:0>
000- 0000 000- 0000
0000 0000 0000 0000
NSS<1:0>
000- 0000 000- 0000
0000 0000 0000 0000
0000 0000 0000 0000
PSS<1:0>
NSS<1:0>
REF<4:0>
---
---- --00 ---- --00
0000 0000 0000 0000
PSS<1:0>
595h DAC2REFL(2)
597h DAC3CON0
---
PSS<1:0>
0-0- 0000 0-00 0000
---0 0000 ---0 0000
NSS<1:0>
REF<4:0>
0-0- 0000 0-00 0000
---0 0000 ---0 0000
Unimplemented
—
—
x = unknown; u = unchanged; q = value depends on condition; - = unimplemented, read as ‘0’; r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Unimplemented, read as ‘1’.
PIC16(L)F1768/9 only.
PIC16(L)F1764/5 only.
Unimplemented on PIC16LF1764/5/8/9.
DS40001775B-page 48
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
TABLE 3-16:
Addr
Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
All Other
Resets
—
—
Bank 12
60Ch
to
616h
—
Unimplemented
617h PWM3DCL
DC<1:0>
—
—
618h PWM3DCH
619h PWM3CON
EN
61Ah PWM4DCL(2)
—
61Dh
—
61Fh
—
—
—
xx-- ---- uu-- ----
DC<1:0>
xxxx xxxx uuuu uuuu
OUT
POL
—
—
—
—
0-00 ---- 0-00 ----
—
—
—
—
—
—
00-- ---- uu-- ----
—
—
—
—
61Bh PWM4DCH(2)
61Ch PWM4CON(2)
—
DC<9:2>
DC<9:2>
EN
—
—
Unimplemented
—
Unimplemented
OUT
0000 0000 uuuu uuuu
POL
0-00 ---- 0-00 ---—
—
—
—
Bank 13
68Ch
68Dh COG1PHR
—
—
COG Rising Edge Phase Delay Count Register
--00 0000 --00 0000
68Eh COG1PHF
—
—
COG Falling Edge Phase Delay Count Register
--00 0000 --00 0000
68Fh COG1BLKR
—
—
COG Rising Edge Blanking Count Register
--00 0000 --00 0000
690h COG1BLKF
—
—
COG Falling Edge Blanking Count Register
--00 0000 --00 0000
691h COG1DBR
—
—
COG Rising Edge Dead-band Count Register
--00 0000 --00 0000
692h COG1DBF
—
—
COG Falling Edge Dead-band Count Register
693h COG1CON0
EN
LD
—
694h COG1CON1
RDBS
FDBS
—
—
695h COG1RIS0
696h COG1RIS1
POLD
RIS15(2)
00-0 0000 00-0 0000
POLA
RSIM15(2)
0000 0000 0000 0000
0000 0000 0000 0000
RSIM<14:8>
0000 0000 0000 0000
FIS<7:0>
FIS15(2)
0000 0000 0000 0000
FIS<14:8>
0000 0000 0000 0000
FSIM<7:0>
0000 0000 0000 0000
FSIM15(2)
69Dh COG1ASD0
ASE
ARSEN
69Eh COG1ASD1
AS7E
AS6E
AS5E
AS4E
AS3E
69Fh COG1STR
SDATD
SDATC
SDATB
SDATA
STRD
FSIM<14:8>
ASDBD<1:0>
00-- 0000 00-- 0000
0000 0000 0000 0000
69Ch COG1FSIM1
Note 1:
2:
3:
4:
POLB
RSIM<7:0>
69Bh COG1FSIM0
Legend:
POLC
RIS<14:8>
699h COG1FIS0
69Ah COG1FIS1
MD<2:0>
RIS<7:0>
697h COG1RSIM0
698h COG1RSIM1
--00 0000 --00 0000
CS<1:0>
0000 0000 0000 0000
ASDAC<1:0>
—
—
0001 01-- 0001 01--
AS2E
AS1E
AS0E
0000 0000 0000 0000
STRC
STRB
STRA
0000 0000 0000 0000
x = unknown; u = unchanged; q = value depends on condition; - = unimplemented, read as ‘0’; r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Unimplemented, read as ‘1’.
PIC16(L)F1768/9 only.
PIC16(L)F1764/5 only.
Unimplemented on PIC16LF1764/5/8/9.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 49
PIC16(L)F1764/5/8/9
TABLE 3-16:
Addr
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
All Other
Resets
—
—
Bank 14
70Ch
—
Unimplemented
70Dh COG2PHR(2)
—
—
COG Rising Edge Phase Delay Count Register
--00 0000 --00 0000
70Eh COG2PHF(2)
—
—
COG Falling Edge Phase Delay Count Register
--00 0000 --00 0000
70Fh COG2BLKR(2)
—
—
COG Rising Edge Blanking Count Register
--00 0000 --00 0000
710h COG2BLKF(2)
—
—
COG Falling Edge Blanking Count Register
--00 0000 --00 0000
COG2DBR(2)
—
—
COG Rising Edge Dead-band Count Register
--00 0000 --00 0000
712h COG2DBF(2)
—
—
COG Falling Edge Dead-band Count Register
713h COG2CON0(2)
EN
LD
—
714h COG2CON1(2)
RDBS
FDBS
—
711h
--00 0000 --00 0000
CS<1:0>
—
MD<2:0>
POLD
POLC
POLB
00-0 0000 00-0 0000
POLA
00-- 0000 00-- 0000
715h COG2RIS0(2)
RIS<7:0>
0000 0000 0000 0000
716h COG2RIS1(2)
RIS<15:8>
0000 0000 0000 0000
717h COG2RSIM0(2)
RSIM<7:0>
0000 0000 0000 0000
718h COG2RSIM1(2)
RSIM<15:8>
0000 0000 0000 0000
719h COG2FIS0(2)
FIS<7:0>
0000 0000 0000 0000
71Ah COG2FIS1(2)
FIS<15:8>
0000 0000 0000 0000
71Bh COG2FSIM0(2)
FSIM<7:0>
0000 0000 0000 0000
71Ch COG2FSIM1(2)
FSIM<15:8>
0000 0000 0000 0000
71Dh COG2ASD0(2)
ASE
ARSEN
71Eh COG2ASD1(2)
AS7E
AS6E
AS5E
AS4E
AS3E
71Fh COG2STR(2)
SDATD
SDATC
SDATB
SDATA
STRD
ASDBD<1:0>
ASDAC<1:0>
—
—
0001 01-- 0001 01--
AS2E
AS1E
AS0E
0000 0000 0000 0000
STRC
STRB
STRA
0000 0000 0000 0000
Bank 15
78Ch
—
793h
—
Unimplemented
—
—
794h PRG1RTSS
—
—
—
—
RTSS<3:0>
---- 0000 ---- 0000
795h PRG1FTSS
—
—
—
—
FTSS<3:0>
---- 0000 ---- 0000
796h PRG1INS
—
—
—
—
INS<3:0>
797h PRG1CON0
EN
—
FEDG
REDG
798h PRG1CON1
—
—
—
—
799h PRG1CON2
—
—
—
79Ah PRG2RTSS(2)
—
—
—
—
RTSS<3:0>
---- 0000 ---- 0000
79Bh PRG2FTSS(2)
—
—
—
—
FTSS<3:0>
---- 0000 ---- 0000
79Ch PRG2INS(2)
—
—
—
—
INS<3:0>
79Dh PRG2CON0(2)
EN
—
FEDG
REDG
79Eh PRG2CON1(2)
—
—
—
—
79Fh PRG2CON2(2)
—
—
—
MODE<1:0>
—
RDY
---- 0000 ---- 0000
OS
GO
0-00 0000 0-00 0000
FPOL
RPOL
---- -000 ---- -000
ISET<4:0>
MODE<1:0>
—
RDY
---0 0000 ---0 0000
---- 0000 ---- 0000
OS
GO
0-00 0000 0-00 0000
FPOL
RPOL
---- -000 ---- -000
ISET<4:0>
---0 0000 ---0 0000
Bank 16-26
x0Ch/
x8Ch
—
x1Fh/
x9Fh
Legend:
Note 1:
2:
3:
4:
—
Unimplemented
—
—
x = unknown; u = unchanged; q = value depends on condition; - = unimplemented, read as ‘0’; r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Unimplemented, read as ‘1’.
PIC16(L)F1768/9 only.
PIC16(L)F1764/5 only.
Unimplemented on PIC16LF1764/5/8/9.
DS40001775B-page 50
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
TABLE 3-16:
Addr
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
All Other
Resets
—
—
Bank 27
D8Ch
—
D8Dh
—
Unimplemented
D8Eh PWMEN
—
—
MPWM6EN(2)
MPWM5EN
—
—
—
—
--00 ---- --00 ----
D8Fh PWMLD
—
—
MPWM6LD(2)
MPWM5LD
—
—
—
—
--00 ---- --00 ----
D90h PWMOUT
—
—
—
—
—
—
--00 ---- --00 ----
MPWM6OUT(2) MPWM5OUT
D91h PWM5PHL
PH<7:0>
xxxx xxxx uuuu uuuu
D92h PWM5PHH
PH<15:8>
xxxx xxxx uuuu uuuu
D93h PWM5DCL
DC<7:0>
xxxx xxxx uuuu uuuu
D94h PWM5DCH
DC<15:8>
xxxx xxxx uuuu uuuu
D95h PWM5PRL
PR<7:0>
xxxx xxxx uuuu uuuu
D96h PWM5PRH
PR<15:8>
xxxx xxxx uuuu uuuu
D97h PWM5OFL
OF<7:0>
xxxx xxxx uuuu uuuu
D98h PWM5OFH
OF<15:8>
xxxx xxxx uuuu uuuu
D99h PWM5TMRL
TMR<7:0>
0000 0000 0000 0000
D9Ah PWM5TMRH
TMR<15:8>
0000 0000 0000 0000
D9Bh PWM5CON
EN
—
OUT
POL
MODE<1:0>
—
—
D9Ch PWM5INTE
—
—
—
—
OFIE
0-00 00-- 0-00 00--
PHIE
DCIE
PRIE
D9Dh PWM5INTF
—
—
—
—
---- 0000 ---- 0000
OFIF
PHIF
DCIF
PRIF
D9Eh PWM5CLKCON
—
---- 0000 ---- 0000
—
—
D9Fh PWM5LDCON
LDA
—
—
—
—
LDS(2)
DA0h PWM5OFCON
—
00-- ---0 00-- ---0
OFO
—
—
—
OFS(2)
-000 ---0 -000 ---0
PS<2:0>
LDT(2)
—
OFM<1:0>(2)
CS<1:0>
-000 --00 -000 --00
DA1h PWM6PHL(2)
PH<7:0>
xxxx xxxx uuuu uuuu
DA2h PWM6PHH(2)
PH<15:8>
xxxx xxxx uuuu uuuu
DA3h PWM6DCL(2)
DC<7:0>
xxxx xxxx uuuu uuuu
DA4h PWM6DCH(2)
DC<15:8>
xxxx xxxx uuuu uuuu
DA5h PWM6PRL(2)
PR<7:0>
xxxx xxxx uuuu uuuu
DA6h PWM6PRH(2)
PR<15:8>
xxxx xxxx uuuu uuuu
DA7h PWM6OFL(2)
OF<7:0>
xxxx xxxx uuuu uuuu
DA8h PWM6OFH(2)
OF<15:8>
xxxx xxxx uuuu uuuu
DA9h PWM6TMRL(2)
TMR<7:0>
0000 0000 0000 0000
DAAh PWM6TMRH(2)
TMR<15:8>
0000 0000 0000 0000
DABh PWM6CON(2)
EN
—
OUT
POL
DACh PWM6INTE(2)
—
—
—
—
OFIE
DADh PWM6INTF(2)
—
—
—
—
DAEh PWM6CLKCON(2)
—
DAFh PWM6LDCON(2)
LDA
DB0h PWM6OFCON(2)
—
DB1h
to
DBFh
Legend:
Note 1:
2:
3:
4:
—
—
—
0-00 00-- 0-00 00--
PHIE
DCIE
PRIE
---- 0000 ---- 0000
OFIF
PHIF
DCIF
PRIF
---- 0000 ---- 0000
—
—
—
—
—
—
LDS
00-- ---0 00-- ---0
OFO
—
—
—
OFS
-000 ---0 -000 ---0
PS<2:0>
LDT
—
OFM<1:0>
MODE<1:0>
CS<1:0>
Unimplemented
-000 --00 -000 --00
—
—
x = unknown; u = unchanged; q = value depends on condition; - = unimplemented, read as ‘0’; r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Unimplemented, read as ‘1’.
PIC16(L)F1768/9 only.
PIC16(L)F1764/5 only.
Unimplemented on PIC16LF1764/5/8/9.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 51
PIC16(L)F1764/5/8/9
TABLE 3-16:
Addr
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
All Other
Resets
—
—
Bank 28
E0Ch
—
E0Eh
—
Unimplemented
E0Fh PPSLOCK
—
—
—
PPSLOCKED ---- ---0
---- ---0
E10h INTPPS
—
—
—
INTPPS<4:0>
---0 0010
---u uuuu
E11h T0CKIPPS
—
—
—
T0CKIPPS<4:0>
---0 0010
---u uuuu
E12h T1CKIPPS
—
—
—
T1CKIPPS<4:0>
---0 0101
---u uuuu
E13h T1GPPS
—
—
—
T1GPPS<4:0>
---0 0100
---u uuuu
E14h CCP1PPS
—
—
—
CCP1PPS<4:0>
---1 0101
---u uuuu
E15h CCP2PPS(2)
—
—
—
CCP2PPS<4:0>
---1 0011
---u uuuu
E16h COG1INPPS
—
—
—
COG1INPPS<4:0>
---0 0010
---u uuuu
E17h COG2INPPS(2)
—
—
—
COG2INPPS<4:0>
---0 0010
---u uuuu
E18h
—
—
—
—
—
Unimplemented
—
—
E19h T2CKIPPS
—
—
—
T2CKIPPS<4:0>
---0 0101
---u uuuu
E1Ah T3CKIPPS
—
—
—
T3CKIPPS<4:0>
---1 0101
---u uuuu
E1Bh T3GPPS
—
—
—
T3GPPS<4:0>
---1 0100
---u uuuu
E1Ch T4CKIPPS
—
—
—
T4CKIPPS<4:0>
---1 0001
---u uuuu
E1Dh T5CKIPPS
—
—
—
T5CKIPPS<4:0>
---1 0000
---u uuuu
E1Eh T5GPPS
—
—
—
T5GPPS<4:0>
---1 0011
---u uuuu
E1Fh T6CKIPPS
—
—
—
T6CKIPPS<4:0>
---0 0011
---u uuuu
—
—
—
SSPCLKPPS<4:0>
---1 0000(3) ---u uuuu
—
—
—
SSPCLKPPS<4:0>
---0 1110(2) ---u uuuu
—
—
—
SSPDATPPS<4:0>
---1 0001(3) ---u uuuu
—
—
—
SSPDATPPS<4:0>
---0 1100(2) ---u uuuu
—
—
—
SSPSSPPS<4:0>
---1 0011(3) ---u uuuu
—
—
—
SSPSSPPS<4:0>
---1 0110(2) ---u uuuu
—
—
—
RXPPS<4:0>
---1 0101(3) ---u uuuu
—
—
—
RXPPS<4:0>
---0 1101(2) ---u uuuu
—
—
—
CKPPS<4:0>
---1 0100(3) ---u uuuu
—
—
—
CKPPS<4:0>
---0 1111(2) ---u uuuu
E20h SSPCLKPPS
E21h SSPDATPPS
E22h SSPSSPPS
E23h
—
Unimplemented
E24h RXPPS
E25h CKPPS
—
E26h
—
Unimplemented
—
E27h
—
Unimplemented
—
—
—
—
E28h CLCIN0PPS
—
—
—
CLCIN0PPS<4:0>
---1 0011
---u uuuu
E29h CLCIN1PPS
—
—
—
CLCIN1PPS<4:0>
---1 0100
---u uuuu
E2Ah CLCIN2PPS
—
—
—
CLCIN2PPS<4:0>
---1 0001
---u uuuu
E2Bh CLCIN3PPS
—
—
—
CLCIN3PPS<4:0>
---0 0101
---u uuuu
E2Ch PRG1RPPS
—
—
—
PRG1RPPS<4:0>
---1 0100
---u uuuu
E2Dh PRG1FPPS
—
—
—
PRG1FPPS<4:0>
---1 0101
---u uuuu
E2Eh PRG2RPPS(2)
—
—
—
PRG2RPPS<4:0>
---1 0100
---u uuuu
E2Fh PRG2FPPS(2)
—
—
—
PRG2FPPS<4:0>
---1 0101
---u uuuu
E30h MD1CHPPS
—
—
—
MD1CHPPS<4:0>
---0 0011
---u uuuu
E31h MD1CLPPS
—
—
—
MD1CLPPS<4:0>
---0 0100
---u uuuu
Legend:
Note 1:
2:
3:
4:
x = unknown; u = unchanged; q = value depends on condition; - = unimplemented, read as ‘0’; r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Unimplemented, read as ‘1’.
PIC16(L)F1768/9 only.
PIC16(L)F1764/5 only.
Unimplemented on PIC16LF1764/5/8/9.
DS40001775B-page 52
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
TABLE 3-16:
Addr
Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
All Other
Resets
Bit 7
Bit 6
Bit 5
E32h MD1MODPPS
—
—
—
MD1MODPPS<4:0>
---0 0101 ---u uuuu
E33h MD2CHPPS(2)
—
—
—
MD2CHPPS<4:0>
---0 0011 ---u uuuu
E34h MD2CLPPS(2)
—
—
—
MD2CLPPS<4:0>
---0 0100 ---u uuuu
E35h MD2MODPPS(2)
—
—
—
MD2MODPPS<4:0>
---0 0101 ---u uuuu
Bank 28 (Continued)
E36h
to
E7Fh
—
Unimplemented
—
—
—
Unimplemented
—
—
Bank 29
E8Ch
—
E8Fh
E90h RA0PPS
—
—
—
RA0PPS<4:0>
---0 0000 ---u uuuu
E91h RA1PPS
—
—
—
RA1PPS<4:0>
---0 0000 ---u uuuu
E92h RA2PPS
—
—
—
RA2PPS<4:0>
---0 0000 ---u uuuu
—
—
—
RA4PPS<4:0>
---0 0000 ---u uuuu
—
—
—
RA5PPS<4:0>
---0 0000 ---u uuuu
E93h
—
E94h RA4PPS
E95h RA5PPS
Unimplemented
—
—
E96h
—
Unimplemented
—
—
E97h
—
Unimplemented
—
—
E98h
—
Unimplemented
—
—
E99h
—
Unimplemented
—
—
E9Ah
—
Unimplemented
—
—
E9Bh
—
Unimplemented
—
—
E9Ch RB4PPS(2)
—
—
—
RB4PPS<4:0>
---0 0000 ---u uuuu
E9Dh RB5PPS(2)
—
—
—
RB5PPS<4:0>
---0 0000 ---u uuuu
E9Eh RB6PPS(2)
—
—
—
RB6PPS<4:0>
---0 0000 ---u uuuu
E9Fh RB7PPS(2)
—
—
—
RB7PPS<4:0>
---0 0000 ---u uuuu
EA0h RC0PPS
—
—
—
RC0PPS<4:0>
---0 0000 ---u uuuu
EA1h RC1PPS
—
—
—
RC1PPS<4:0>
---0 0000 ---u uuuu
EA2h RC2PPS
—
—
—
RC2PPS<4:0>
---0 0000 ---u uuuu
EA3h RC3PPS
—
—
—
RC3PPS<4:0>
---0 0000 ---u uuuu
EA4h RC4PPS
—
—
—
RC4PPS<4:0>
---0 0000 ---u uuuu
EA5h RC5PPS
—
—
—
RC5PPS<4:0>
---0 0000 ---u uuuu
EA6h RC6PPS(2)
—
—
—
RC6PPS<4:0>
---0 0000 ---u uuuu
EA7h RC7PPS(2)
—
—
—
RC7PPS<4:0>
---0 0000 ---u uuuu
EA8h
—
EEFh
Legend:
Note 1:
2:
3:
4:
—
Unimplemented
—
—
x = unknown; u = unchanged; q = value depends on condition; - = unimplemented, read as ‘0’; r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Unimplemented, read as ‘1’.
PIC16(L)F1768/9 only.
PIC16(L)F1764/5 only.
Unimplemented on PIC16LF1764/5/8/9.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 53
PIC16(L)F1764/5/8/9
TABLE 3-16:
Addr
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
All Other
Resets
—
—
Bank 30
F0Ch
—
F0Eh
—
Unimplemented
F0Fh CLCDATA
—
—
—
—
—
F10h CLC1CON
EN
—
OUT
INTP
INTN
F11h CLC1POL
POL
—
—
—
G4POL
F12h CLC1SEL0
—
—
—
D1S<4:0>
---x xxxx ---u uuuu
F13h CLC1SEL1
—
—
—
D2S<4:0>
---x xxxx ---u uuuu
F14h CLC1SEL2
—
—
—
D3S<4:0>
---x xxxx ---u uuuu
F15h CLC1SEL3
—
—
—
D4S<4:0>
F16h CLC1GLS0
G1D4T
G1D4N
G1D3T
G1D3N
G1D2T
G1D2N
G1D1T
G1D1N
xxxx xxxx uuuu uuuu
F17h CLC1GLS1
G2D4T
G2D4N
G2D3T
G2D3N
G2D2T
G2D2N
G2D1T
G2D1N
xxxx xxxx uuuu uuuu
F18h CLC1GLS2
G3D4T
G3D4N
G3D3T
G3D3N
G3D2T
G3D2N
G3D1T
G3D1N
xxxx xxxx uuuu uuuu
F19h CLC1GLS3
G4D4T
G4D4N
G4D3T
G4D3N
G4D2T
G4D2N
G4D1T
G4D1N
xxxx xxxx uuuu uuuu
F1Ah CLC2CON
EN
—
OUT
INTP
INTN
F1Bh CLC2POL
POL
—
—
—
G4POL
F1Ch CLC2SEL0
—
—
—
D1S<4:0>
---x xxxx ---u uuuu
F1Dh CLC2SEL1
—
—
—
D2S<4:0>
---x xxxx ---u uuuu
F1Eh CLC2SEL2
—
—
—
D3S<4:0>
---x xxxx ---u uuuu
F1Fh CLC2SEL3
—
—
—
D4S<4:0>
F20h CLC2GLS0
G1D4T
G1D4N
G1D3T
G1D3N
G1D2T
G1D2N
G1D1T
G1D1N
xxxx xxxx uuuu uuuu
F21h CLC2GLS1
G2D4T
G2D4N
G2D3T
G2D3N
G2D2T
G2D2N
G2D1T
G2D1N
xxxx xxxx uuuu uuuu
F22h CLC2GLS2
G3D4T
G3D4N
G3D3T
G3D3N
G3D2T
G3D2N
G3D1T
G3D1N
xxxx xxxx uuuu uuuu
F23h CLC2GLS3
G4D4T
G4D4N
G4D3T
G4D3N
G4D2T
G4D2N
G4D1T
G4D1N
xxxx xxxx uuuu uuuu
F24h CLC3CON
EN
—
OUT
INTP
INTN
F25h CLC3POL
POL
—
—
—
G4POL
F26h CLC3SEL0
—
—
—
D1S<4:0>
---x xxxx ---u uuuu
F27h CLC3SEL1
—
—
—
D2S<4:0>
---x xxxx ---u uuuu
F28h CLC3SEL2
—
—
—
D3S<4:0>
---x xxxx ---u uuuu
F29h CLC3SEL3
—
—
—
D4S<4:0>
F2Ah CLC3GLS0
G1D4T
G1D4N
G1D3T
G1D3N
G1D2T
G1D2N
G1D1T
G1D1N
xxxx xxxx uuuu uuuu
F2Bh CLC3GLS1
G2D4T
G2D4N
G2D3T
G2D3N
G2D2T
G2D2N
G2D1T
G2D1N
xxxx xxxx uuuu uuuu
F2Ch CLC3GLS2
G3D4T
G3D4N
G3D3T
G3D3N
G3D2T
G3D2N
G3D1T
G3D1N
xxxx xxxx uuuu uuuu
F2Dh CLC3GLS3
G4D4T
G4D4N
G4D3T
G4D3N
G4D2T
G4D2N
G4D1T
G4D1N
xxxx xxxx uuuu uuuu
F2Eh
—
F6Fh
Legend:
Note 1:
2:
3:
4:
—
MLC3OUT
MLC2OUT
MLC1OUT
MODE<2:0>
G3POL
G2POL
0-00 0000 0-00 0000
G1POL
G2POL
0-00 0000 0-00 0000
G1POL
0--- xxxx 0--- uuuu
---x xxxx ---u uuuu
MODE<2:0>
G3POL
0--- xxxx 0--- uuuu
---x xxxx ---u uuuu
MODE<2:0>
G3POL
---- -000 ---- -000
G2POL
0-00 0000 0-00 0000
G1POL
0--- xxxx 0--- uuuu
---x xxxx ---u uuuu
Unimplemented
—
—
x = unknown; u = unchanged; q = value depends on condition; - = unimplemented, read as ‘0’; r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Unimplemented, read as ‘1’.
PIC16(L)F1768/9 only.
PIC16(L)F1764/5 only.
Unimplemented on PIC16LF1764/5/8/9.
DS40001775B-page 54
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
TABLE 3-16:
Addr
Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
All Other
Resets
—
—
Bank 31
F8Ch
to
FE3h
—
FE4h STATUS_
SHAD
FE5h WREG_
SHAD
Unimplemented
—
—
—
—
—
Z
DC
Working Register Shadow
FE6h BSR_SHAD
—
FE7h PCLATH_
SHAD
—
—
C
---- -xxx ---- -uuu
xxxx xxxx uuuu uuuu
—
Bank Select Register Shadow
Program Counter Latch High Register Shadow
---x xxxx ---u uuuu
-xxx xxxx -uuu uuuu
FE8h FSR0L_
SHAD
Indirect Data Memory Address 0 Low Pointer Shadow
xxxx xxxx uuuu uuuu
FE9h FSR0H_
SHAD
Indirect Data Memory Address 0 High Pointer Shadow
xxxx xxxx uuuu uuuu
FEAh FSR1L_
SHAD
Indirect Data Memory Address 1 Low Pointer Shadow
xxxx xxxx uuuu uuuu
FEBh FSR1H_
SHAD
Indirect Data Memory Address 1 High Pointer Shadow
xxxx xxxx uuuu uuuu
FECh
Unimplemented
—
FEDh STKPTR
FEEh TOSL
FEFh TOSH
Legend:
Note 1:
2:
3:
4:
—
—
—
—
Current Stack Pointer
Top of Stack Low byte
—
Top of Stack High Byte
—
---1 1111 ---1 1111
xxxx xxxx uuuu uuuu
-xxx xxxx -uuu uuuu
x = unknown; u = unchanged; q = value depends on condition; - = unimplemented, read as ‘0’; r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Unimplemented, read as ‘1’.
PIC16(L)F1768/9 only.
PIC16(L)F1764/5 only.
Unimplemented on PIC16LF1764/5/8/9.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 55
PIC16(L)F1764/5/8/9
3.4
3.4.2
PCL and PCLATH
The Program Counter (PC) is 15 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<14:8>) is not directly
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 3-3 shows the five
situations for the loading of the PC.
FIGURE 3-3:
PC
LOADING OF PC IN
DIFFERENT SITUATIONS
14
PCH
6
7
PCL
0
PCLATH
PC
Instruction with
PCL as
Destination
8
ALU Result
PCH
PCL
0
GOTO, CALL
6
PCLATH
4
0
11
OPCODE <10:0>
PC
14
PCH
PCL
0
CALLW
6
PCLATH
PC
14
0
14
7
0
PCH
8
PCL
0
BRW
15
PC + W
PC
14
PCH
PCL
0
BRA
15
PC + OPCODE <8:0>
3.4.1
A computed GOTO is accomplished by adding an offset to
the Program Counter (ADDWF PCL). When performing a
table read using a computed GOTO method, care should
be exercised if the table location crosses a PCL memory
boundary (each 256-byte block). Refer to Application
Note AN556, “Implementing a Table Read” (DS00556).
3.4.3
MODIFYING PCL
COMPUTED FUNCTION CALLS
A computed function CALL allows programs to maintain
tables of functions and provide another way to execute
state machines or look-up tables. When performing a
table read using a computed function CALL, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block).
If using the CALL instruction, the PCH<2:0> and PCL
registers are loaded with the operand of the CALL
instruction. PCH<6:3> is loaded with PCLATH<6:3>.
The CALLW instruction enables computed calls by combining PCLATH and W to form the destination address.
A computed CALLW is accomplished by loading the W
register with the desired address and executing CALLW.
The PCL register is loaded with the value of W and
PCH is loaded with PCLATH.
3.4.4
W
COMPUTED GOTO
BRANCHING
The branching instructions add an offset to the PC.
This allows relocatable code and code that crosses
page boundaries. There are two forms of branching,
BRW and BRA. The PC will have incremented to fetch
the next instruction in both cases. When using either
branching instruction, a PCL memory boundary may be
crossed.
If using BRW, load the W register with the desired
unsigned address and execute BRW. The entire PC will
be loaded with the address PC + 1 + W.
If using BRA, the entire PC will be loaded with PC + 1 +,
the signed value of the operand of the BRA instruction.
Executing any instruction with the PCL register as the
destination simultaneously causes the Program
Counter PC<14:8> bits (PCH) to be replaced by the
contents of the PCLATH register. This allows the entire
contents of the Program Counter to be changed by
writing the desired upper seven bits to the PCLATH
register. When the lower eight bits are written to the
PCL register, all 15 bits of the Program Counter will
change to the values contained in the PCLATH register
and those being written to the PCL register.
DS40001775B-page 56
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
3.5
3.5.1
Stack
All devices have a 16-level x 15-bit wide hardware
stack (refer to Figure 3-1). The stack space is not part
of either program or data space. The PC is PUSHed
onto the stack when CALL or CALLW instructions are
executed or an interrupt causes a branch. The stack is
POPed in the event of a RETURN, RETLW or a RETFIE
instruction execution. PCLATH is not affected by a
PUSH or POP operation.
The stack operates as a circular buffer if the STVREN
bit is programmed to ‘0’ (Configuration Words). This
means that after the stack has been PUSHed sixteen
times, the seventeenth PUSH overwrites the value that
was stored from the first PUSH. The eighteenth PUSH
overwrites the second PUSH (and so on). The
STKOVF and STKUNF flag bits will be set on an Overflow/Underflow Reset, regardless of whether the Reset
is enabled.
Note:
There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL,
CALLW, RETURN, RETLW and RETFIE
instructions or the vectoring to an interrupt
address.
FIGURE 3-4:
ACCESSING THE STACK
The stack is available through the TOSH, TOSL and
STKPTR registers. STKPTR is the current value of the
Stack Pointer. TOSH:TOSL register pair points to the
TOP of the stack. Both registers are read/writable. TOS
is split into TOSH and TOSL due to the 15-bit size of the
PC. To access the stack, adjust the value of STKPTR,
which will position TOSH:TOSL, then read/write to
TOSH:TOSL. STKPTR is five bits to allow detection of
overflow and underflow.
Note:
Care should be taken when modifying the
STKPTR while interrupts are enabled.
During normal program operation, CALL, CALLW and
Interrupts will increment STKPTR while RETLW,
RETURN, and RETFIE will decrement STKPTR. At any
time, STKPTR can be inspected to see how much
stack is left. The STKPTR always points at the currently
used place on the stack. Therefore, a CALL or CALLW
will increment the STKPTR and then write the PC, and
a return will unload the PC and then decrement the
STKPTR.
Reference Figure 3-4 through Figure 3-7 for examples
of accessing the stack.
ACCESSING THE STACK EXAMPLE 1
Rev. 10-000043A
7/30/2013
TOSH:TOSL
0x0F
STKPTR = 0x1F
Stack Reset Disabled
(STVREN = 0)
0x0E
0x0D
0x0C
0x0B
Initial Stack Configuration:
0x0A
After Reset, the stack is empty. The
empty stack is initialized so the Stack
Pointer is pointing at 0x1F. If the Stack
Overflow/Underflow Reset is enabled, the
TOSH/TOSL register will return ‘0’. If the
Stack Overflow/Underflow Reset is
disabled, the TOSH/TOSL register will
return the contents of stack address
0x0F.
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
TOSH:TOSL
 2014-2015 Microchip Technology Inc.
0x1F
0x0000
STKPTR = 0x1F
Stack Reset Enabled
(STVREN = 1)
DS40001775B-page 57
PIC16(L)F1764/5/8/9
FIGURE 3-5:
ACCESSING THE STACK EXAMPLE 2
Rev. 10-000043B
7/30/2013
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
This figure shows the stack configuration
after the first CALL or a single interrupt.
If a RETURN instruction is executed, the
return address will be placed in the
Program Counter and the Stack Pointer
decremented to the empty state (0x1F).
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
TOSH:TOSL
FIGURE 3-6:
0x00
Return Address
STKPTR = 0x00
ACCESSING THE STACK EXAMPLE 3
Rev. 10-000043C
7/30/2013
0x0F
0x0E
0x0D
0x0C
After seven CALLs or six CALLs and an
interrupt, the stack looks like the figure on
the left. A series of RETURN instructions will
repeatedly place the return addresses into
the Program Counter and pop the stack.
0x0B
0x0A
0x09
0x08
0x07
TOSH:TOSL
DS40001775B-page 58
0x06
Return Address
0x05
Return Address
0x04
Return Address
0x03
Return Address
0x02
Return Address
0x01
Return Address
0x00
Return Address
STKPTR = 0x06
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
FIGURE 3-7:
ACCESSING THE STACK EXAMPLE 4
Rev. 10-000043D
7/30/2013
TOSH:TOSL
3.5.2
0x0F
Return Address
0x0E
Return Address
0x0D
Return Address
0x0C
Return Address
0x0B
Return Address
0x0A
Return Address
0x09
Return Address
0x08
Return Address
0x07
Return Address
0x06
Return Address
0x05
Return Address
0x04
Return Address
0x03
Return Address
0x02
Return Address
0x01
Return Address
0x00
Return Address
OVERFLOW/UNDERFLOW RESET
If the STVREN bit in Configuration Words is
programmed to ‘1’, the device will be reset if the stack
is PUSHed beyond the sixteenth level or POPed
beyond the first level, setting the appropriate bits
(STKOVF or STKUNF, respectively) in the PCON
register.
3.6
When the stack is full, the next CALL or
an interrupt will set the Stack Pointer to
0x10. This is identical to address 0x00 so
the stack will wrap and overwrite the
return address at 0x00. If the Stack
Overflow/Underflow Reset is enabled, a
Reset will occur and location 0x00 will
not be overwritten.
STKPTR = 0x10
Indirect Addressing
The INDFn registers are not physical registers. Any
instruction that accesses an INDFn register actually
accesses the register at the address specified by the
File Select Registers (FSRs). If the FSRn address
specifies one of the two INDFn registers, the read will
return ‘0’ and the write will not occur (though Status bits
may be affected). The FSRn register value is created
by the pair, FSRnH and FSRnL.
The FSRn registers form a 16-bit address that allows an
addressing space with 65536 locations. These locations
are divided into three memory regions:
• Traditional Data Memory
• Linear Data Memory
• Program Flash Memory
 2014-2015 Microchip Technology Inc.
DS40001775B-page 59
PIC16(L)F1764/5/8/9
FIGURE 3-8:
INDIRECT ADDRESSING
Rev. 10-000044A
7/30/2013
0x0000
0x0000
Traditional
Data Memory
0x0FFF
0x1000
0x0FFF
Reserved
0x1FFF
0x2000
Linear
Data Memory
0x29AF
0x29B0
Reserved
FSR
Address
Range
0x7FFF
0x8000
0x0000
Program
Flash Memory
0xFFFF
Note:
0x7FFF
Not all memory regions are completely implemented. Consult device memory tables for memory limits.
DS40001775B-page 60
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
3.6.1
TRADITIONAL DATA MEMORY
The traditional data memory is a region from FSRn
address, 0x000, to FSRn address, 0xFFF. The
addresses correspond to the absolute addresses of all
SFRs, GPRs and common registers.
FIGURE 3-9:
TRADITIONAL DATA MEMORY MAP
Rev. 10-000056A
7/31/2013
Direct Addressing
4 BSR 0
Indirect Addressing
From Opcode
6
0
Bank Select
7
FSRxH
0 0 0 0
Location Select
0x00
00000
Bank Select
00001
00010
11111
Bank 0 Bank 1
Bank 2
Bank 31
0 7
FSRxL
0
Location Select
0x7F
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PIC16(L)F1764/5/8/9
3.6.2
LINEAR DATA MEMORY
The linear data memory is the region from FSRn
address, 0x2000, to FSRn address, 0x29AF. This
region is a virtual region that points back to the 80-byte
blocks of GPR memory in all the banks.
Unimplemented memory reads as 0x00. Use of the
linear data memory region allows buffers to be larger
than 80 bytes because incrementing the FSRn beyond
one bank will go directly to the GPR memory of the next
bank.
The 16 bytes of common memory are not included in
the linear data memory region.
FIGURE 3-10:
LINEAR DATA MEMORY
MAP
3.6.3
PROGRAM FLASH MEMORY
To make constant data access easier, the entire
Program Flash Memory is mapped to the upper half of
the FSRn address space. When the MSB of FSRnH is
set, the lower 15 bits are the address in program
memory which will be accessed through INDFn. Only
the lower eight bits of each memory location are
accessible via INDFn. Writing to the Program Flash
Memory cannot be accomplished via the FSRn/INDFn
interface. All instructions that access Program Flash
Memory via the FSRn/INDFn interface will require one
additional instruction cycle to complete.
FIGURE 3-11:
PROGRAM FLASH
MEMORY MAP
Rev. 10-000057A
7/31/2013
7
FSRnH
0 0 1
0
7
FSRnL
Rev. 10-000058A
7/31/2013
7
1
0
FSRnH
0
Location Select
Location Select
0x2000
7
FSRnL
0
0x8000
0x0A0
Bank 1
0x0EF
Program
Flash
Memory
(low 8 bits)
0x120
Bank 2
0x16F
0x29AF
DS40001775B-page 62
0x0000
0x020
Bank 0
0x06F
0xF20
Bank 30
0xF6F
0xFFFF
0x7FFF
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
4.0
DEVICE CONFIGURATION
Device configuration consists of Configuration Words,
code protection and Device ID.
4.1
Configuration Words
Note:
The DEBUG bit in Configuration Words is
managed automatically by device
development tools, including debuggers
and programmers. For normal device
operation, this bit should be maintained as
a ‘1’.
There are several Configuration Word bits that allow
different oscillator and memory protection options.
These are implemented as Configuration Word 1 at
8007h and Configuration Word 2 at 8008h.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 63
PIC16(L)F1764/5/8/9
4.2
Register Definitions: Configuration Words
REGISTER 4-1:
CONFIG1: CONFIGURATION WORD 1
R/P-1
R/P-1
R/P-1
FCMEN
IESO
CLKOUTEN
R/P-1
R/P-1
BOREN<1:0>
bit 13
R/P-1
R/P-1
R/P-1
CP(1)
MCLRE
PWRTE
U-1
—
bit 8
R/P-1
R/P-1
WDTE<1:0>
R/P-1
R/P-1
R/P-1
FOSC<2:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared
‘1’ = Bit is set
-n = Value when blank or after Bulk Erase
bit 13
FCMEN: Fail-Safe Clock Monitor Enable bit
1 = On Fail-Safe Clock Monitor and Internal/External Switchover mode are both enabled
0 = Off Fail-Safe Clock Monitor is disabled
bit 12
IESO: Internal External Switchover bit
1 = On Internal/External Switchover mode is enabled
0 = Off Internal/External Switchover mode is disabled
bit 11
CLKOUTEN: Clock Out Enable bit
If FOSC<2:0> Configuration bits are Set to LP, XT, HS modes:
This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin.
All other FOSC<2:0> modes:
1 = On CLKOUT function is disabled. I/O function on the CLKOUT pin
0 = Off CLKOUT function is enabled on the CLKOUT pin
bit 10-9
BOREN<1:0>: Brown-out Reset Enable bits
11 = On
BOR is enabled
10 = NSLEEP BOR is enabled during operation and disabled in Sleep
01 = SBODEN BOR is controlled by the SBOREN bit of the BORCON register
00 = Off
BOR is disabled
bit 8
Unimplemented: Read as ‘1’
bit 7
CP: Code Protection bit(1)
1 = Off Program memory code protection is disabled
0 = On Program memory code protection is enabled
bit 6
MCLRE: MCLR/VPP Pin Function Select bit
If LVP bit = 1:
This bit is ignored.
If LVP bit = 0:
1 = On MCLR/VPP pin function is MCLR; weak pull-up is enabled
0 = Off MCLR/VPP pin function is a digital input, MCLR is internally disabled; weak pull-up is under
control of the WPUA3 bit
bit 5
PWRTE: Power-up Timer Enable bit
1 = Off PWRT is disabled
0 = On PWRT is enabled
Note 1:
The entire Flash program memory will be erased when the code protection is turned off during an erase.
When a bulk erase program memory command is executed, the entire Program Flash Memory and
configuration memory will be erased.
DS40001775B-page 64
 2014-2015 Microchip Technology Inc.
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REGISTER 4-1:
CONFIG1: CONFIGURATION WORD 1 (CONTINUED)
bit 4-3
WDTE<1:0>: Watchdog Timer Enable bit
11 = On
WDT is enabled
10 = NSLEEP WDT is enabled while running and disabled in Sleep
01 = SWDTEN WDT is controlled by the SWDTEN bit in the WDTCON register
00 = Off
WDT is disabled
bit 2-0
FOSC<2:0>: Oscillator Selection bits
111 = ECH
External Clock, High-Power mode: CLKIN supplied to OSC1/CLKIN pin
110 = ECM
External Clock, Medium Power mode: CLKIN supplied to OSC1/CLKIN pin
101 = ECL
External Clock, Low-Power mode: CLKIN supplied to OSC1/CLKIN pin
100 = INTOSC Internal HFINTOSC: I/O function on CLKIN pin
011 = EXTRC External RC circuit connected to CLKIN pin
010 = HS
High-speed crystal/resonator connected between OSC1 and OSC2 pins
001 = XT
Crystal/resonator connected between OSC1 and OSC2 pins
000 = LP
Low-power crystal connected between OSC1 and OSC2 pins
Note 1:
The entire Flash program memory will be erased when the code protection is turned off during an erase.
When a bulk erase program memory command is executed, the entire Program Flash Memory and
configuration memory will be erased.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 65
PIC16(L)F1764/5/8/9
REGISTER 4-2:
CONFIG2: CONFIGURATION WORD 2
R/P-1
(1)
LVP
R/P-1
DEBUG
R/P-1
(2)
R/P-1
(3)
LPBOR
BORV
R/P-1
R/P-1
STVREN
PLLEN
bit 13
bit 8
R/P-1
U-1
U-1
U-1
U-1
R/P-1
ZCD
—
—
—
—
PPS1WAY
R/P-1
R/P-1
WRT<1:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared
‘1’ = Bit is set
-n = Value when blank or after Bulk Erase
bit 13
LVP: Low-Voltage Programming Enable bit(1)
1 = On Low-Voltage Programming is enabled
0 = Off High-voltage on MCLR must be used for programming
bit 12
DEBUG: In-Circuit Debugger Mode bit(2)
1 = Off In-Circuit Debugger is disabled, ICSPCLK and ICSPDAT are general purpose I/O pins
0 = On In-Circuit Debugger is enabled, ICSPCLK and ICSPDAT are dedicated to the debugger
bit 11
LPBOR: Low-Power BOR Enable bit
1 = Off Low-Power Brown-out Reset is disabled
0 = On Low-Power Brown-out Reset is enabled
bit 10
BORV: Brown-out Reset Voltage Selection bit(3)
1 = LO Brown-out Reset Voltage (VBOR), low trip point is selected
0 = HI Brown-out Reset Voltage (VBOR), high trip point is selected
bit 9
STVREN: Stack Overflow/Underflow Reset Enable bit
1 = On Stack Overflow or Underflow will cause a Reset
0 = Off Stack Overflow or Underflow will not cause a Reset
bit 8
PLLEN: PLL Enable bit
1 = On 4xPLL is enabled
0 = Off 4xPLL is disabled
bit 7
ZCD: ZCD Enable bit
1 = Off ZCD is disabled, ZCD can be enabled by setting the ZCDSEN bit of ZCDCON
0 = On ZCD is always enabled
bit 6-3
Unimplemented: Read as ‘1’
bit 2
PPS1WAY: PPSLOCK Bit One-Way Set Enable bit
1 = On The PPSLOCK bit can only be set once after an unlocking sequence is executed; once
PPSLOCK is set, all future changes to PPS registers are prevented
0 = Off The PPSLOCK bit can be set and cleared as needed (provided an unlocking sequence is
executed)
Note 1:
2:
3:
The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.
The DEBUG bit in the Configuration Words is managed automatically by device development tools, including
debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.
See VBOR parameter for specific trip point voltages.
DS40001775B-page 66
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
REGISTER 4-2:
bit 1-0
CONFIG2: CONFIGURATION WORD 2 (CONTINUED)
WRT<1:0>: Flash Memory Self-Write Protection bits
4 kW Flash Memory (PIC16(L)F1764/8):
11 = Off Write protection is off
10 = Boot 0000h to 01FFh are write-protected, 0200h to 0FFFh may be modified by PMCON control
01 = Half 0000h to 07FFh are write-protected, 0800h to 0FFFh may be modified by PMCON control
00 = All
0000h to 0FFFh are write-protected, no addresses may be modified by PMCON control
8 kW Flash Memory (PIC16(L)F1765/9):
11 = Off Write protection is off
10 = Boot 0000h to 01FFh are write-protected, 0200h to 1FFFh may be modified by PMCON control
01 = Half 0000h to 0FFFh are write-protected, 1000h to 1FFFh may be modified by PMCON control
00 = All
0000h to 1FFFh are write-protected, no addresses may be modified by PMCON control
Note 1:
2:
3:
The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.
The DEBUG bit in the Configuration Words is managed automatically by device development tools, including
debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.
See VBOR parameter for specific trip point voltages.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 67
PIC16(L)F1764/5/8/9
4.3
Code Protection
Code protection allows the device to be protected from
unauthorized access. Program memory protection is
controlled independently. Internal access to the
program memory is unaffected by any code protection
setting.
4.3.1
PROGRAM MEMORY PROTECTION
The entire program memory space is protected from
external reads and writes by the CP bit in the
Configuration Words. When CP = 0, external reads and
writes of program memory are inhibited and a read will
return all ‘0’s. The CPU can continue to read program
memory, regardless of the protection bit settings.
Writing the program memory is dependent upon the
write protection setting. See Section 4.4 “Write
Protection” for more information.
DS40001775B-page 68
4.4
Write Protection
Write protection allows the device to be protected from
unintended self-writes. Applications, such as boot
loader software, can be protected while allowing other
regions of the program memory to be modified.
The WRT<1:0> bits in the Configuration Words define
the size of the program memory block that is protected.
4.5
User ID
Four memory locations (8000h-8003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
readable and writable during normal execution. See
Section 10.4 “User ID, Device ID and Configuration
Word Access” for more information on accessing
these memory locations. For more information on
checksum calculation, see the “PIC16(L)F170X
Memory Programming Specification” (DS40001683).
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
4.6
Device ID and Revision ID
The 14-bit Device ID word is located at 8006h and the
14-bit Revision ID is located at 8005h. These locations
are read-only and cannot be erased or modified. See
Section 10.4 “User ID, Device ID and Configuration
Word Access” for more information on accessing
these memory locations.
4.7
Development tools, such as device programmers and
debuggers, may be used to read the Device ID and
Revision ID.
Register Definitions: Device and Revision
REGISTER 4-3:
DEVID: DEVICE ID REGISTER
R
R
R
R
R
R
DEV<13:8>
bit 13
R
R
bit 8
R
R
R
R
R
R
DEV<7:0>
bit 7
bit 0
Legend:
R = Readable bit
bit 13-0
‘1’ = Bit is set
‘0’ = Bit is cleared
DEV<13:0>: Device ID bits
Device
DEVID<13:0> Values
PIC16F1764
11 0000 1000 0000 (3080h)
PIC16F1765
11 0000 1000 0001 (3081h)
PIC16F1768
11 0000 1000 0100 (3084h)
PIC16F1769
11 0000 1000 0101 (3085h)
PIC16LF1764
11 0000 1000 0010 (3082h)
PIC16LF1765
11 0000 1000 0011 (3083h)
PIC16LF1768
11 0000 1000 0110 (3086h)
PIC16LF1769
11 0000 1000 0111 (3087h)
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DS40001775B-page 69
PIC16(L)F1764/5/8/9
REGISTER 4-4:
REVID: REVISION ID REGISTER
R
R
R
R
R
R
REV<13:8>
bit 13
R
R
bit 8
R
R
R
R
R
R
REV<7:0>
bit 7
bit 0
Legend:
R = Readable bit
bit 13-0
‘1’ = Bit is set
‘0’ = Bit is cleared
REV<13:0>: Revision ID bits
DS40001775B-page 70
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
5.0
OSCILLATOR MODULE (WITH
FAIL-SAFE CLOCK MONITOR)
5.1
Overview
The oscillator module has a wide variety of clock
sources and selection features that allow it to be used
in a wide range of applications while maximizing performance and minimizing power consumption. Figure 5-1
illustrates a block diagram of the oscillator module.
Clock sources can be supplied from external oscillators,
quartz crystal resonators, ceramic resonators and
Resistor-Capacitor (RC) circuits. In addition, the system
clock source can be supplied from one of two internal
oscillators and PLL circuits, with a choice of speeds
selectable via software. Additional clock features
include:
• Selectable system clock source between external
or internal sources via software.
• Two-Speed Start-up mode, which minimizes
latency between external oscillator start-up and
code execution.
• Fail-Safe Clock Monitor (FSCM) designed to
detect a failure of the external clock source (LP,
XT, HS, ECH, ECM, ECL or EXTRC modes) and
switch automatically to the internal oscillator.
• Oscillator Start-up Timer (OST) ensures stability
of crystal oscillator sources.
 2014-2015 Microchip Technology Inc.
The oscillator module can be configured in one of the
following clock modes.
1.
2.
3.
4.
5.
6.
7.
8.
ECL – External Clock Low-Power mode
(0 MHz to 0.5 MHz).
ECM – External Clock Medium Power mode
(0.5 MHz to 4 MHz).
ECH – External Clock High-Power mode
(4 MHz to 32 MHz).
LP – 32 kHz Low-Power Crystal mode.
XT – Medium Gain Crystal or Ceramic Resonator
Oscillator mode (up to 4 MHz).
HS – High Gain Crystal or Ceramic Resonator
mode (4 MHz to 20 MHz).
EXTRC – External Resistor-Capacitor.
INTOSC – Internal Oscillator (31 kHz to 32 MHz).
Clock source modes are selected by the FOSC<2:0>
bits in the Configuration Words. The FOSCx bits
determine the type of oscillator that will be used when
the device is first powered.
The ECH, ECM and ECL Clock modes rely on an
external logic level signal as the device clock source.
The LP, XT and HS Clock modes require an external
crystal or resonator to be connected to the device.
Each mode is optimized for a different frequency range.
The EXTRC Clock mode requires an external resistor
and capacitor to set the oscillator frequency.
The Internal Oscillator Block (INTOSC) produces low,
medium and high-frequency clock sources, designated
LFINTOSC, MFINTOSC and HFINTOSC (see Internal
Oscillator Block, Figure 5-1). A wide selection of device
clock frequencies may be derived from these three
clock sources.
DS40001775B-page 71
PIC16(L)F1764/5/8/9
SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
FIGURE 5-1:
Secondary
Oscillator Timer1
Timer1 Clock Source Option
for Other Modules
SOSCO
T1OSCEN
Enable
Oscillator
SOSCI
External
Oscillator
T1OSC
01
LP, XT, HS, RC, EC
OSC2
0
Sleep
0
1
Sleep
PRIMUX
OSC1
00
4 x PLL
FOSC
To CPU and
Peripherals
1
PLLMUX
IRCF<3:0>
500 kHz
Source
16 MHz
(HFINTOSC)
500 kHz
(MFINTOSC)
31 kHz
Source
INTOSC
SCS<1:0>
0000
31 kHz (LFINTOSC)
WDT, PWRT, Fail-Safe Clock Monitor,
Two-Speed Start-up and Other Modules
Inputs
SCS<1:0> FOSC<2:0>
Outputs
PLLEN or
SPLLEN
0
= 100
= 00
≠ 100
≠ 00
x
DS40001775B-page 72
1x
1111
MUX
HFPLL
Postscaler
Internal
Oscillator
Block
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
31.25 kHz
31 kHz
IRCF<3:0>
PRIMUX
PLLMUX
xxxx
1
0
= 1110
1
1
≠ 1110
1
0
0
xxxx
0
0
1
xxxx
0
1
x
xxxx
x
x
1
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
5.2
Clock Source Types
Clock sources can be classified as external or internal.
External clock sources rely on external circuitry for the
clock source to function. Examples are: oscillator
modules (ECH, ECM, ECL modes), quartz crystal resonators or ceramic resonators (LP, XT and HS modes)
and Resistor-Capacitor (EXTRC) mode circuits.
Internal clock sources are contained within the oscillator
module. The Internal Oscillator Block has two internal
oscillators and a dedicated Phase-Locked Loop
(HFPLL) that are used to generate three internal system
clock sources: the 16 MHz High-Frequency Internal
Oscillator (HFINTOSC), 500 kHz Medium Frequency
Internal Oscillator (MFINTOSC) and the 31 kHz
Low-Frequency Internal Oscillator (LFINTOSC).
The system clock can be selected between external or
internal clock sources via the System Clock Select
(SCSx) bits in the OSCCON register. See Section 5.3
“Clock Switching” for additional information.
5.2.1
EXTERNAL CLOCK SOURCES
An external clock source can be used as the device
system clock by performing one of the following
actions:
• Program the FOSC<2:0> bits in the Configuration
Words to select an external clock source that will
be used as the default system clock upon a
device Reset.
• Write the SCS<1:0> bits in the OSCCON register
to switch the system clock source to:
- Secondary oscillator during run time, or
- An external clock source determined by the
value of the FOSCx bits.
See Section 5.3 “Clock Switching” for more
information.
5.2.1.1
EC Mode
The External Clock (EC) mode allows an externally
generated logic level signal to be the system clock
source. When operating in this mode, an external
clock source is connected to the OSC1 input.
OSC2/CLKOUT is available for general purpose I/O or
CLKOUT. Figure 5-2 shows the pin connections for EC
mode.
EC mode has three power modes to select from through
the Configuration Words:
The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC® MCU design is fully
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.
FIGURE 5-2:
EXTERNAL CLOCK (EC)
MODE OPERATION
Rev. 10-000045A
7/30/2013
Clock from
Ext. system
OSC1/CLKIN
PIC® MCU
FOSC/4 or I/O(1)
Note 1:
5.2.1.2
OSC2/CLKOUT
Output depends upon the CLKOUTEN bit
of the Configuration Words.
LP, XT, HS Modes
The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
OSC1 and OSC2 (Figure 5-3). The three modes select
a low, medium or high gain setting of the internal
inverter-amplifier to support various resonator types
and speed.
LP Oscillator mode selects the lowest gain setting of the
internal inverter-amplifier. LP mode current consumption
is the least of the three modes. This mode is designed to
drive only 32.768 kHz tuning-fork type crystals (watch
crystals).
XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current consumption is the medium of the three modes.
This mode is best suited to drive resonators with a
medium drive level specification.
HS Oscillator mode selects the highest gain setting of the
internal inverter-amplifier. HS mode current consumption
is the highest of the three modes. This mode is best
suited for resonators that require a high drive setting.
Figure 5-3 and Figure 5-4 show typical circuits for
quartz crystal and ceramic resonators, respectively.
• ECH – High power, 4-32 MHz
• ECM – Medium power, 0.5-4 MHz
• ECL – Low power, 0-0.5 MHz
 2014-2015 Microchip Technology Inc.
DS40001775B-page 73
PIC16(L)F1764/5/8/9
FIGURE 5-3:
QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
FIGURE 5-4:
CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
Rev. 10-000059A
7/30/2013
Rev. 10-000060A
7/30/2013
PIC® MCU
Ceramic
Resonator
PIC® MCU
OSC1/CLKIN
OSC1/CLKIN
C1
C1
C2
Note 1:
2:
To Internal
Logic
To Internal
Logic
Quartz
Crystal
RF(2)
RS(1)
OSC2/CLKOUT
RP(3)
Sleep
A series resistor (Rs) may be required for
quartz crystals with low drive level.
C2
Note 1:
The value of RF varies with the Oscillator mode
selected (typically between 2 MΩ and 10 MΩ).
Note 1: Quartz crystal characteristics vary according to type, package and manufacturer.
The user should consult the manufacturer
data sheets for specifications and
recommended application.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
3: For oscillator design assistance, reference
the following Microchip Application Notes:
• AN826, “Crystal Oscillator Basics and
Crystal Selection for rfPIC® and PIC®
Devices” (DS00826)
• AN849, “Basic PIC® Oscillator
Design” (DS00849)
• AN943, “Practical PIC® Oscillator
Analysis and Design” (DS00943)
• AN949, “Making Your Oscillator
Work” (DS00949)
DS40001775B-page 74
5.2.1.3
RS(1)
RF(2)
Sleep
OSC2/CLKOUT
A series resistor (Rs) may be required for
ceramic resonators with low drive level.
2:
The value of RF varies with the Oscillator mode
selected (typically between 2 MΩ and 10 MΩ).
3.
An additional parallel feedback resistor (RP)
may be required for proper ceramic resonator
operation.
Oscillator Start-up Timer (OST)
If the oscillator module is configured for LP, XT or HS
modes, the Oscillator Start-up Timer (OST) counts
1024 oscillations from OSC1. This occurs following a
Power-on Reset (POR) and when the Power-up Timer
(PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the Program Counter does not
increment and program execution is suspended,
unless either FSCM or Two-Speed Start-up is enabled.
In this case, code will continue to execute at the
selected INTOSC frequency while the OST is counting.
The OST ensures that the oscillator circuit, using a
quartz crystal resonator or ceramic resonator, has
started and is providing a stable system clock to the
oscillator module.
In order to minimize latency between external oscillator
start-up and code execution, the Two-Speed Clock
Start-up mode can be selected (see Section 5.4
“Two-Speed Clock Start-up Mode”).
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
5.2.1.4
4x PLL
The oscillator module contains a 4x PLL that can be
used with both external and internal clock sources to
provide a system clock source. The input frequency for
the 4x PLL must fall within specifications. See the PLL
Clock Timing Specifications in Table 36-9.
The 4x PLL may be enabled for use by one of two
methods:
1.
2.
Program the PLLEN bit in the Configuration
Words to a ‘1’.
Write the SPLLEN bit in the OSCCON register to
a ‘1’. If the PLLEN bit in the Configuration Words
is programmed to a ‘1’, then the value of
SPLLEN is ignored.
5.2.1.5
Secondary Oscillator
The secondary oscillator is a separate crystal oscillator
that is associated with the Timer1 peripheral. It is
optimized for timekeeping operations with a
32.768 kHz crystal connected between the SOSCO
and SOSCI device pins.
The secondary oscillator can be used as an alternate
system clock source and can be selected during run
time using clock switching. Refer to Section 5.3
“Clock Switching” for more information.
FIGURE 5-5:
QUARTZ CRYSTAL
OPERATION (SECONDARY
OSCILLATOR)
Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The
user should consult the manufacturer data
sheets for specifications and recommended
application.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
3: For oscillator design assistance, reference
the following Microchip Application Notes:
• AN826, “Crystal Oscillator Basics and
Crystal Selection for rfPIC® and PIC®
Devices” (DS00826)
• AN849, “Basic PIC® Oscillator
Design” (DS00849)
• AN943, “Practical PIC® Oscillator
Analysis and Design” (DS00943)
• AN949, “Making Your Oscillator
Work” (DS00949)
• TB097, “Interfacing a Micro Crystal
MS1V-T1K 32.768 kHz Tuning Fork
Crystal to a PIC16F690/SS”
(DS91097)
• AN1288, “Design Practices for
Low-Power External Oscillators”
(DS01288)
Rev. 10-000061A
7/30/2013
PIC® MCU
SOSCI
C1
To Internal
Logic
32.768 kHz
Quartz
Crystal
C2
SOSCO
 2014-2015 Microchip Technology Inc.
DS40001775B-page 75
PIC16(L)F1764/5/8/9
5.2.1.6
External RC Mode
5.2.2
The external Resistor-Capacitor (EXTRC) mode supports the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required.
The RC circuit connects to OSC1. OSC2/CLKOUT is
available for general purpose I/O or CLKOUT. The
function of the OSC2/CLKOUT pin is determined by the
CLKOUTEN bit in the Configuration Words.
Figure 5-6 shows the external RC mode connections.
FIGURE 5-6:
EXTERNAL RC MODES
Rev. 10-000062A
7/31/2013
PIC® MCU
REXT
CEXT
The device may be configured to use the Internal Oscillator Block as the system clock by performing one of
the following actions:
• Program the FOSC<2:0> bits in the Configuration
Words to select the INTOSC clock source, which
will be used as the default system clock upon a
device Reset.
• Write the SCS<1:0> bits in the OSCCON register
to switch the system clock source to the internal
oscillator during run time. See Section 5.3
“Clock Switching” for more information.
In INTOSC mode, OSC1/CLKIN is available for general
purpose I/O. OSC2/CLKOUT is available for general
purpose I/O or CLKOUT.
The function of the OSC2/CLKOUT pin is determined
by the CLKOUTEN bit in the Configuration Words.
VDD
OSC1/CLKIN
Internal
Clock
The Internal Oscillator Block has two independent
oscillators and a dedicated Phase-Locked Loop
(HFPLL) that can produce one of three internal system
clock sources.
1.
VSS
FOSC/4
or I/O(1)
OSC2/CLKOUT
Recommended values:10 kŸ ” REXT ” 100 kŸ, <3V
3 kŸ ” REXT ” 100 kŸ, 3-5V
CEXT > 20 pF, 2-5V
Note 1:
INTERNAL CLOCK SOURCES
Output depends upon the CLKOUTEN bit of the
Configuration Words.
2.
The RC oscillator frequency is a function of the supply
voltage, the Resistor (REXT) and Capacitor (CEXT)
values, and the operating temperature. Other factors
affecting the oscillator frequency are:
• Threshold voltage variation
• Component tolerances
• Packaging variations in capacitance
3.
The HFINTOSC (High-Frequency Internal
Oscillator) is factory calibrated and operates at
16 MHz. The HFINTOSC source is generated
from the 500 kHz MFINTOSC source and the
dedicated Phase-Locked Loop, HFPLL. The
frequency of the HFINTOSC can be
user-adjusted via software using the OSCTUNE
register (Register 5-3).
The MFINTOSC (Medium Frequency Internal
Oscillator) is factory calibrated and operates at
500 kHz. The frequency of the MFINTOSC can
be user-adjusted via software using the
OSCTUNE register (Register 5-3).
The LFINTOSC (Low-Frequency Internal
Oscillator) is uncalibrated and operates at
31 kHz.
The user also needs to take into account variation due
to tolerance of external RC components used.
DS40001775B-page 76
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
5.2.2.1
HFINTOSC
The High-Frequency Internal Oscillator (HFINTOSC) is
a factory calibrated, 16 MHz internal clock source. The
frequency of the HFINTOSC can be altered via
software using the OSCTUNE register (Register 5-3).
The output of the HFINTOSC connects to a postscaler
and multiplexer (see Figure 5-1). One of multiple
frequencies derived from the HFINTOSC can be
selected via software using the IRCF<3:0> bits of the
OSCCON register. See Section 5.2.2.7 “Internal
Oscillator Clock Switch Timing” for more information.
The HFINTOSC is enabled by:
• Configuring the IRCF<3:0> bits of the OSCCON
register for the desired HF frequency, and
• FOSC<2:0> = 100, or
• Setting the System Clock Source (SCS<1:0>) bits
of the OSCCON register to ‘1x’
A fast start-up oscillator allows internal circuits to power
up and stabilize before switching to HFINTOSC.
The High-Frequency Internal Oscillator Ready bit
(HFIOFR) of the OSCSTAT register indicates when the
HFINTOSC is running.
The High-Frequency Internal Oscillator Status Locked
bit (HFIOFL) of the OSCSTAT register indicates when
the HFINTOSC is running within 2% of its final value.
The High-Frequency Internal Oscillator Stable bit
(HFIOFS) of the OSCSTAT register indicates when the
HFINTOSC is running within 0.5% of its final value.
5.2.2.2
MFINTOSC
The Medium Frequency Internal Oscillator (MFINTOSC)
is a factory calibrated 500 kHz internal clock source.
The frequency of the MFINTOSC can be altered via
software using the OSCTUNE register (Register 5-3).
The output of the MFINTOSC connects to a postscaler
and multiplexer (see Figure 5-1). One of nine
frequencies derived from the MFINTOSC can be
selected via software using the IRCF<3:0> bits of the
OSCCON register. See Section 5.2.2.7 “Internal
Oscillator Clock Switch Timing” for more information.
The MFINTOSC is enabled by:
• Configuring the IRCF<3:0> bits of the OSCCON
register for the desired HF frequency, and
• FOSC<2:0> = 100, or
• Setting the System Clock Source (SCS<1:0>) bits
of the OSCCON register to ‘1x’
The Medium Frequency Internal Oscillator Ready bit
(MFIOFR) of the OSCSTAT register indicates when the
MFINTOSC is running.
 2014-2015 Microchip Technology Inc.
5.2.2.3
Internal Oscillator Frequency
Adjustment
The 500 kHz internal oscillator is factory calibrated.
This internal oscillator can be adjusted in software by
writing to the OSCTUNE register (Register 5-3). Since
the HFINTOSC and MFINTOSC clock sources are
derived from the 500 kHz internal oscillator, a change
in the OSCTUNE register value will apply to both.
The default value of the OSCTUNE register is ‘0’. The
value is a 6-bit two’s complement number. A value of
1Fh will provide an adjustment to the maximum
frequency. A value of 20h will provide an adjustment to
the minimum frequency.
When the OSCTUNE register is modified, the oscillator
frequency will begin shifting to the new frequency. Code
execution continues during this shift. There is no
indication that the shift has occurred.
OSCTUNE does not affect the LFINTOSC frequency.
Operation of features that depend on the LFINTOSC
clock source frequency, such as the Power-up Timer
(PWRT), Watchdog Timer (WDT), Fail-Safe Clock
Monitor (FSCM) and peripherals, are not affected by the
change in frequency.
5.2.2.4
LFINTOSC
The Low-Frequency Internal Oscillator (LFINTOSC) is
an uncalibrated 31 kHz internal clock source.
The output of the LFINTOSC connects to a multiplexer
(see Figure 5-1). Select 31 kHz, via software, using the
IRCF<3:0> bits of the OSCCON register. See
Section 5.2.2.7 “Internal Oscillator Clock Switch
Timing” for more information. The LFINTOSC is also
the frequency for the Power-up Timer (PWRT),
Watchdog Timer (WDT) and Fail-Safe Clock Monitor
(FSCM).
The LFINTOSC is enabled by selecting 31 kHz
(IRCF<3:0> (OSCCON<6:3>) = 000) as the system
clock source (SCS<1:0> (OSCCON<1:0> = 1x) or
when any of the following are enabled:
• Configuring the IRCF<3:0> bits of the OSCCON
register for the desired LF frequency, and
• FOSC<2:0> = 100, or
• Setting the System Clock Source (SCS<1:0>) bits
of the OSCCON register to ‘1x’
Peripherals that use the LFINTOSC are:
• Power-up Timer (PWRT)
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor (FSCM)
The Low-Frequency Internal Oscillator Ready bit
(LFIOFR) of the OSCSTAT register indicates when the
LFINTOSC is running.
DS40001775B-page 77
PIC16(L)F1764/5/8/9
5.2.2.5
Internal Oscillator Frequency
Selection
The system clock speed can be selected via software
using the Internal Oscillator Frequency Select bits
IRCF<3:0> of the OSCCON register.
The postscaled output of the 16 MHz HFINTOSC,
500 kHz MFINTOSC, and 31 Hz LFINTOSC connect to
a multiplexer (see Figure 5-1). The Internal Oscillator
Frequency Select bits, IRCF<3:0> of the OSCCON
register, select the frequency output of the internal
oscillators. One of the following frequencies can be
selected via software:
- 32 MHz (requires 4x PLL)
- 16 MHz
- 8 MHz
- 4 MHz
- 2 MHz
- 1 MHz
- 500 kHz (default after Reset)
- 250 kHz
- 125 kHz
- 62.5 kHz
- 31.25 kHz
- 31 kHz (LFINTOSC)
Note:
Following any Reset, the IRCF<3:0> bits
of the OSCCON register are set to ‘0111’
and the frequency selection is set to
500 kHz. The user can modify the IRCFx
bits to select a different frequency.
The IRCF<3:0> bits of the OSCCON register allow
duplicate selections for some frequencies. These
duplicate choices can offer system design trade-offs.
Lower power consumption can be obtained when
changing oscillator sources for a given frequency.
Faster transition times can be obtained between
frequency changes that use the same oscillator source.
5.2.2.6
32 MHz Internal Oscillator
Frequency Selection
The Internal Oscillator Block can be used with the
4x PLL associated with the External Oscillator Block to
produce a 32 MHz internal system clock source. The
following settings are required to use the 32 MHz
internal clock source:
• The SPLLEN bit in the OSCCON register must be
set to enable the 4x PLL or the PLLEN bit of the
Configuration Words must be programmed to a ‘1’.
Note:
When using the PLLEN bit of the
Configuration Words, the 4x PLL cannot
be disabled by software and the SPLLEN
option will not be available.
The 4x PLL is not available for use with the internal
oscillator when the SCSx bits of the OSCCON register
are set to ‘1x’. The SCSx bits must be set to ‘00’ to use
the 4x PLL with the internal oscillator.
5.2.2.7
Internal Oscillator Clock Switch
Timing
When switching between the HFINTOSC, MFINTOSC
and the LFINTOSC, the new oscillator may already be
shut down to save power (see Figure 5-7). If this is the
case, there is a delay after the IRCF<3:0> bits of the
OSCCON register are modified before the frequency
selection takes place. The OSCSTAT register will
reflect the current active status of the HFINTOSC,
MFINTOSC and LFINTOSC oscillators. The sequence
of a frequency selection is as follows:
1.
2.
3.
4.
5.
6.
7.
IRCF<3:0> bits of the OSCCON register are
modified.
If the new clock is shut down, a clock start-up
delay is started.
Clock switch circuitry waits for a falling edge of
the current clock.
The current clock is held low and the clock
switch circuitry waits for a rising edge in the new
clock.
The new clock is now active.
The OSCSTAT register is updated as required.
Clock switch is complete.
See Figure 5-7 for more details.
If the internal oscillator speed is switched between two
clocks of the same source, there is no start-up delay
before the new frequency is selected. Clock switching
time delays are shown in Table 5-1.
Start-up delay specifications are located in the oscillator
tables of Section 36.0 “Electrical Specifications”.
• The FOSCx bits in the Configuration Words must
be set to use the INTOSC source as the device
system clock (FOSC<2:0> = 100).
• The SCSx bits in the OSCCON register must be
cleared to use the clock determined by FOSC<2:0>
in the Configuration Words (SCS<1:0> = 00).
• The IRCFx bits in the OSCCON register must be
set to the 8 MHz HFINTOSC to use
(IRCF<3:0> = 1110).
DS40001775B-page 78
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
FIGURE 5-7:
HFINTOSC/
MFINTOSC
INTERNAL OSCILLATOR SWITCH TIMING
LFINTOSC (FSCM and WDT disabled)
HFINTOSC/
MFINTOSC
Start-up Time
2-Cycle Sync
Running
LFINTOSC
IRCF<3:0>
0
0
System Clock
HFINTOSC/
MFINTOSC
LFINTOSC (Either FSCM or WDT enabled)
HFINTOSC/
MFINTOSC
2-Cycle Sync
Running
LFINTOSC
0
IRCF<3:0>
0
System Clock
LFINTOSC
HFINTOSC/MFINTOSC
LFINTOSC Turns Off unless WDT or FSCM is Enabled
LFINTOSC
Start-up Time
HFINTOSC/
MFINTOSC
IRCF <3:0>
0
2-Cycle Sync
Running
0
System Clock
 2014-2015 Microchip Technology Inc.
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PIC16(L)F1764/5/8/9
5.3
Clock Switching
5.3.3
SECONDARY OSCILLATOR
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS) bits of the OSCCON
register. The following clock sources can be selected
using the SCS<1:0> bits:
The secondary oscillator is a separate crystal oscillator
associated with the Timer1 peripheral. It is optimized
for timekeeping operations with a 32.768 kHz crystal
connected between the SOSCO and SOSCI device
pins.
• Default system oscillator determined by the
FOSCx bits in the Configuration Words
• Timer1 32 kHz crystal oscillator
• Internal Oscillator Block (INTOSC)
The secondary oscillator is enabled using the OSCEN
control bit in the T1CON register. See Section 22.0
“Timer1/3/5 Module with Gate Control” for more
information about the Timer1 peripheral.
5.3.1
SYSTEM CLOCK SELECT (SCS)
BITS
The System Clock Select (SCS<1:0>) bits of the
OSCCON register select the system clock source that
is used for the CPU and peripherals.
• When SCS<1:0> = 00, the system clock source is
determined by the value of the FOSC<2:0> bits in
the Configuration Words.
• When SCS<1:0> = 01, the system clock source is
the secondary oscillator.
• When SCS<1:0> = 1x, the system clock source is
chosen by the internal oscillator frequency
selected by the IRCF<3:0> bits of the OSCCON
register. After a Reset, the SCSx bits of the
OSCCON register are always cleared.
Note:
Any automatic clock switch, which may
occur from Two-Speed Start-up or
Fail-Safe Clock Monitor, does not update
the SCS bits of the OSCCON register. The
user can monitor the OSTS bit of the
OSCSTAT register to determine the current
system clock source.
When switching between clock sources, a delay is
required to allow the new clock to stabilize. These
oscillator delays are shown in Table 5-1.
5.3.2
5.3.4
SECONDARY OSCILLATOR READY
(SOSCR) BIT
The user must ensure that the secondary oscillator is
ready to be used before it is selected as a system clock
source. The Secondary Oscillator Ready (SOSCR) bit
of the OSCSTAT register indicates whether the
secondary oscillator is ready to be used. After the
SOSCR bit is set, the SCSx bits can be configured to
select the secondary oscillator.
5.3.5
CLOCK SWITCH BEFORE SLEEP
When a clock switch from an old clock to a new clock is
requested just prior to entering Sleep mode, it is
necessary to confirm that the switch is complete before
the sleep instruction is executed. Failure to do so may
result in an incomplete switch and consequential loss
of the system clock altogether. Clock switching is
confirmed by monitoring the clock status bits in the
OSCSTAT register. Switch confirmation can be
accomplished by sensing that the ready bit for the new
clock is set or the ready bit for the old clock is cleared.
For example, when switching between the internal
oscillator with the PLL and the internal oscillator without
the PLL, monitor the PLLR bit. When PLLR is set, the
switch to 32 MHz operation is complete. Conversely,
when PLLR is cleared, the switch from 32 MHz
operation to the selected internal clock is complete.
OSCILLATOR START-UP TIMER
STATUS (OSTS) BIT
The Oscillator Start-up Timer Status (OSTS) bit of the
OSCSTAT register indicates whether the system clock
is running from the external clock source, as defined by
the FOSC<2:0> bits in the Configuration Words, or
from the internal clock source. In particular, OSTS
indicates that the Oscillator Start-up Timer (OST) has
timed out for LP, XT or HS modes. The OST does not
reflect the status of the secondary oscillator.
DS40001775B-page 80
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PIC16(L)F1764/5/8/9
5.4
If the OST count reaches 1024 before the device
enters Sleep mode, the OSTS bit of the OSCSTAT
register is set and program execution switches to the
external oscillator. However, the system may never
operate from the external oscillator if the time spent
awake is very short.
Two-Speed Clock Start-up Mode
Two-Speed Clock Start-up mode provides additional
power savings by minimizing the latency between
external oscillator start-up and code execution. In
applications that make heavy use of the Sleep mode,
Two-Speed Start-up will remove the external oscillator
start-up time from the time spent awake and can
reduce the overall power consumption of the device.
This mode allows the application to wake-up from
Sleep, perform a few instructions using the Internal
Oscillator Block, INTOSC, as the clock source and go
back to Sleep without waiting for the external oscillator
to become stable.
Note:
5.4.1
TWO-SPEED START-UP MODE
CONFIGURATION
Two-Speed Start-up mode is configured by the
following settings:
Two-Speed Start-up provides benefits when the oscillator module is configured for LP, XT or HS modes.
The Oscillator Start-up Timer (OST) is enabled for
these modes and must count 1024 oscillations before
the oscillator can be used as the system clock source.
• IESO (of the Configuration Words) = 1;
Internal/External Switchover bit (Two-Speed
Start-up mode enabled).
• SCS<1:0> (of the OSCCON register) = 00.
• FOSC<2:0> bits in the Configuration Words
configured for LP, XT or HS mode.
If the oscillator module is configured for any mode
other than LP, XT or HS mode, then Two-Speed
Start-up is disabled. This is because the external clock
oscillator does not require any stabilization time after
POR or an exit from Sleep.
TABLE 5-1:
Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit of the OSCSTAT register to
remain clear.
Two-Speed Start-up mode is entered after:
• Power-on Reset (POR) and, if enabled, after
Power-up Timer (PWRT) has expired, or
• Wake-up from Sleep.
OSCILLATOR SWITCHING DELAYS
Switch From
Switch To
Frequency
Oscillator Delay
Sleep
LFINTOSC
MFINTOSC
HFINTOSC(1)
31 kHz
31.25 kHz-500 kHz
31.25 kHz-16 MHz
Oscillator Warm-up Delay (TWARM)
Sleep
EC, RC(1)
DC- 32 MHz
2 cycles
RC(1)
LFINTOSC
EC,
DC-32 MHz
1 Cycle of Each
Sleep
Secondary Oscillator
LP, XT, HS(1)
32 kHz-20 MHz
1024 Clock Cycles (OST)
Any Clock Source
MFINTOSC
HFINTOSC(1)
31.25 kHz-500 kHz
31.25 kHz-16 MHz
2 s (approx.)
Any Clock Source
LFINTOSC
31 kHz
1 Cycle of Each
Any Clock Source
Secondary Oscillator
32 kHz
1024 Clock Cycles (OST)
PLL Inactive
PLL Active
16-32 MHz
2 ms (approx.)
Note 1:
PLL is inactive.
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DS40001775B-page 81
PIC16(L)F1764/5/8/9
5.4.2
1.
2.
3.
4.
5.
6.
7.
TWO-SPEED START-UP
SEQUENCE
5.4.3
Wake-up from Power-on Reset or Sleep.
Instructions begin execution by the internal
oscillator at the frequency set in the IRCF<3:0>
bits of the OSCCON register.
OST enabled to count 1024 clock cycles.
OST timed out, wait for falling edge of the
internal oscillator.
OSTS is set.
System clock held low until the next falling edge
of new clock (LP, XT or HS mode).
System clock is switched to external clock
source.
FIGURE 5-8:
CHECKING TWO-SPEED CLOCK
STATUS
Checking the state of the OSTS bit of the OSCSTAT
register will confirm if the microcontroller is running
from the external clock source, as defined by the
FOSC<2:0> bits in the Configuration Words, or the
internal oscillator.
TWO-SPEED START-UP
INTOSC
TOST
OSC1
0
1
1022 1023
OSC2
Program Counter
PC – N
PC
PC + 1
System Clock
DS40001775B-page 82
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PIC16(L)F1764/5/8/9
5.5
5.5.3
Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue operating should the external oscillator fail.
The FSCM can detect oscillator failure any time after
the Oscillator Start-up Timer (OST) has expired. The
FSCM is enabled by setting the FCMEN bit in the
Configuration Words. The FSCM is applicable to all
external Oscillator modes (LP, XT, HS, EC, Secondary
Oscillator and RC).
FIGURE 5-9:
FSCM BLOCK DIAGRAM
Clock Monitor
Latch
External
Clock
LFINTOSC
Oscillator
÷ 64
31 kHz
(~32 s)
488 Hz
(~2 ms)
S
Q
R
Q
Sample Clock
5.5.1
FAIL-SAFE DETECTION
The FSCM module detects a failed oscillator by
comparing the external oscillator to the FSCM sample
clock. The sample clock is generated by dividing the
LFINTOSC by 64. See Figure 5-9. Inside the fail
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of the
sample clock. A failure is detected when an entire
half-cycle of the sample clock elapses before the
external clock goes low.
5.5.2
The Fail-Safe condition is cleared after a Reset,
executing a SLEEP instruction or changing the SCSx
bits of the OSCCON register. When the SCSx bits are
changed, the OST is restarted. While the OST is
running, the device continues to operate from the
INTOSC selected in OSCCON. When the OST times
out, the Fail-Safe condition is cleared after successfully
switching to the external clock source. The OSFIF bit
should be cleared prior to switching to the external
clock source. If the Fail-Safe condition still exists, the
OSFIF flag will again become set by hardware.
5.5.4
Clock
Failure
Detected
FAIL-SAFE CONDITION CLEARING
RESET OR WAKE-UP FROM SLEEP
The FSCM is designed to detect an oscillator failure
after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after
any type of Reset. The OST is not used with the EC or
RC Clock modes so that the FSCM will be active as
soon as the Reset or wake-up has completed. When
the FSCM is enabled, the Two-Speed Start-up is also
enabled. Therefore, the device will always be executing
code while the OST is operating.
Note:
Due to the wide range of oscillator start-up
times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount of time, the user should check the
status bits in the OSCSTAT register to
verify the oscillator start-up and that the
system clock switchover has successfully
completed.
FAIL-SAFE OPERATION
When the external clock fails, the FSCM switches the
device clock to an internal clock source and sets the bit
flag OSFIF of the PIR2 register. Setting this flag will
generate an interrupt if the OSFIE bit of the PIE2
register is also set. The device firmware can then take
steps to mitigate the problems that may arise from a
failed clock. The system clock will continue to be
sourced from the internal clock source until the device
firmware successfully restarts the external oscillator
and switches back to external operation.
The internal clock source chosen by the FSCM is
determined by the IRCF<3:0> bits of the OSCCON
register. This allows the internal oscillator to be
configured before a failure occurs.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 83
PIC16(L)F1764/5/8/9
FIGURE 5-10:
FSCM TIMING DIAGRAM
Sample Clock
Oscillator
Failure
System
Clock
Output
Clock Monitor Output
(Q)
Failure
Detected
OSCFIF
Test
Note:
Test
Test
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
DS40001775B-page 84
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PIC16(L)F1764/5/8/9
5.6
Register Definitions: Oscillator Control
REGISTER 5-1:
R/W-0/0
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0/0
R/W-1/1
SPLLEN
R/W-1/1
R/W-1/1
IRCF<3:0>
U-0
R/W-0/0
—
R/W-0/0
SCS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
SPLLEN: Software PLL Enable bit
If PLLEN in Configuration Words = 1:
SPLLEN bit is ignored; 4x PLL is always enabled (subject to oscillator requirements).
If PLLEN in Configuration Words = 0:
1 = 4x PLL Is enabled
0 = 4x PLL is disabled
bit 6-3
IRCF<3:0>: Internal Oscillator Frequency Select bits
1111 = 16 MHz HF
1110 = 8 MHz or 32 MHz HF(2)
1101 = 4 MHz HF
1100 = 2 MHz HF
1011 = 1 MHz HF
1010 = 500 kHz HF(1)
1001 = 250 kHz HF(1)
1000 = 125 kHz HF(1)
0111 = 500 kHz MF (default upon Reset)
0110 = 250 kHz MF
0101 = 125 kHz MF
0100 = 62.5 kHz MF
0011 = 31.25 kHz HF(1)
0010 = 31.25 kHz MF
000x = 31 kHz LF
bit 2
Unimplemented: Read as ‘0’
bit 1-0
SCS<1:0>: System Clock Select bits
1x = Internal Oscillator Block
01 = Secondary oscillator
00 = Clock determined by FOSC<2:0> in the Configuration Words
Note 1:
2:
Duplicate frequency derived from HFINTOSC.
32 MHz when SPLLEN bit is set. Refer to Section 5.2.2.6 “32 MHz Internal Oscillator Frequency
Selection”.
 2014-2015 Microchip Technology Inc.
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REGISTER 5-2:
OSCSTAT: OSCILLATOR STATUS REGISTER
R-1/q
R-0/q
R-q/q
R-0/q
R-0/q
R-q/q
R-0/0
R-0/q
SOSCR
PLLR
OSTS
HFIOFR
HFIOFL
MFIOFR
LFIOFR
HFIOFS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
q = Conditional
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
SOSCR: Secondary Oscillator Ready bit
If T1OSCEN = 1:
1 = Secondary oscillator is ready
0 = Secondary oscillator is not ready
If T1OSCEN = 0:
1 = Secondary clock source is always ready
bit 6
PLLR 4x PLL Ready bit
1 = 4x PLL is ready
0 = 4x PLL is not ready
bit 5
OSTS: Oscillator Start-up Timer Status bit
1 = Running from the clock defined by the FOSC<2:0> bits of the Configuration Words
0 = Running from an internal oscillator (FOSC<2:0> = 100)
bit 4
HFIOFR: High-Frequency Internal Oscillator Ready bit
1 = HFINTOSC is ready
0 = HFINTOSC is not ready
bit 3
HFIOFL: High-Frequency Internal Oscillator Locked bit
1 = HFINTOSC is at least 2% accurate
0 = HFINTOSC is not 2% accurate
bit 2
MFIOFR: Medium Frequency Internal Oscillator Ready bit
1 = MFINTOSC is ready
0 = MFINTOSC is not ready
bit 1
LFIOFR: Low-Frequency Internal Oscillator Ready bit
1 = LFINTOSC is ready
0 = LFINTOSC is not ready
bit 0
HFIOFS: High-Frequency Internal Oscillator Stable bit
1 = HFINTOSC is at least 0.5% accurate
0 = HFINTOSC is not 0.5% accurate
DS40001775B-page 86
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REGISTER 5-3:
OSCTUNE: OSCILLATOR TUNING REGISTER
U-0
U-0
—
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TUN<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
TUN<5:0>: Frequency Tuning bits
100000 = Minimum frequency
•
•
•
111111 =
000000 = Oscillator module is running at the factory-calibrated frequency
000001 =
•
•
•
011110 =
011111 = Maximum frequency
TABLE 5-2:
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Name
Bit 7
OSCCON
SPLLEN
OSCSTAT
SOSCR
PLLR
OSCTUNE
—
—
OSFIF
C2IF
PIR2
PIE2
Bit 6
OSFIE
Bit 4
Bit 3
Bit 2
OSTS
Bit 1
—
IRCF<3:0>
HFIOFR
HFIOFL
Bit 0
SCS<1:0>
MFIOFR
LFIOFR
C2IE
C1IF
C1IE
—
—
CKPS<1:0>
Register
on Page
85
HFIOFS
TUN<5:0>
CS<1:0>
T1CON
Bit 5
86
87
BCL1IF
C4IF(1)
C3IF(1)
CCP2IF(1)
109
BCL1IE
(1)
C4IE
(1)
C3IE
CCP2IE(1)
106
OSCEN
SYNC
—
ON
230
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
Note 1: PIC16(L)F1768/9 only.
TABLE 5-3:
Name
CONFIG1
SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
13:8
—
—
FCMEN
IESO
CLKOUTEN
7:0
CP
MCLRE
PWRTE
WDTE<1:0>
Bit 10/2
Bit 9/1
Bit 8/0
BOREN<1:0>
—
FOSC<2:0>
Register
on Page
64
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
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PIC16(L)F1764/5/8/9
NOTES:
DS40001775B-page 88
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
6.0
RESETS
There are multiple ways to reset this device:
•
•
•
•
•
•
•
•
•
Power-on Reset (POR)
Brown-out Reset (BOR)
Low-Power Brown-out Reset (LPBOR)
MCLR Reset
WDT Reset
RESET instruction
Stack Overflow
Stack Underflow
Programming mode exit
FIGURE 6-1:
To allow VDD to stabilize, an optional power-up timer
can be enabled to extend the Reset time after a BOR
or POR event.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 6-1.
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Rev. 10-000006A
8/14/2013
ICSP™ Programming Mode Exit
RESET Instruction
Stack Underflow
Stack Overlfow
MCLRE
VPP/MCLR
Sleep
WDT
Time-out
Device
Reset
Power-on
Reset
VDD
BOR
Active(1)
Brown-out
Reset
LPBOR
Reset
Note 1:
R
LFINTOSC
Power-up
Timer
PWRTE
See Table 6-1 for BOR active conditions.
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6.1
Power-on Reset (POR)
6.2
Brown-out Reset (BOR)
The POR circuit holds the device in Reset until VDD has
reached an acceptable level for minimum operation.
Slow rising VDD, fast operating speeds or analog
performance may require greater than minimum VDD.
The PWRT, BOR or MCLR features can be used to
extend the start-up period until all device operation
conditions have been met.
The BOR circuit holds the device in Reset when VDD
reaches a selectable minimum level. Between the
POR and BOR, complete voltage range coverage for
execution protection can be implemented.
6.1.1
•
•
•
•
POWER-UP TIMER (PWRT)
The Power-up Timer provides a nominal 64 ms
time-out on POR or Brown-out Reset.
The device is held in Reset as long as PWRT is active.
The PWRT delay allows additional time for the VDD to
rise to an acceptable level. The Power-up Timer is
enabled by clearing the PWRTE bit in the Configuration
Words.
The Power-up Timer starts after the release of the POR
and BOR.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
TABLE 6-1:
The Brown-out Reset module has four operating
modes controlled by the BOREN<1:0> bits in the
Configuration Words. The four operating modes are:
BOR is always on
BOR is off when in Sleep
BOR is controlled by software
BOR is always off
Refer to Table 6-1 for more information.
The Brown-out Reset voltage level is selectable by
configuring the BORV bit in the Configuration Words.
A VDD noise rejection filter prevents the BOR from
triggering on small events. If VDD falls below VBOR for
a duration greater than parameter, TBORDC, the device
will reset. See Figure 6-2 for more information.
BOR OPERATING MODES
BOREN<1:0>
SBOREN
Device Mode
BOR Mode
11
x
X
Active
10
x
Awake
Active
Sleep
Disabled
1
X
Active
0
X
Disabled
x
X
Disabled
01
00
Note 1:
Instruction Execution upon:
Release of POR or Wake-up from Sleep
Waits for BOR ready (BORRDY = 1)(1)
Waits for BOR ready (BORRDY = 1)
Waits for BOR ready (BORRDY = 1)(1)
Begins immediately (BORRDY = x)
In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The
BOR Ready Flag (BORRDY = 1) will be set before the CPU is ready to execute instructions because the
BOR circuit is forced on by the BOREN<1:0> bits.
DS40001775B-page 90
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6.2.1
BOR IS ALWAYS ON
When the BOREN<1:0> bits of the Configuration
Words are programmed to ‘11’, the BOR is always on.
The device start-up will be delayed until the BOR is
ready and VDD is higher than the BOR threshold.
BOR protection is active during Sleep. The BOR does
not delay wake-up from Sleep.
6.2.2
BOR IS OFF IN SLEEP
When the BORENx bits of the Configuration Words are
programmed to ‘10’, the BOR is on, except in Sleep.
The device start-up will be delayed until the BOR is
ready and VDD is higher than the BOR threshold.
6.2.3
BOR CONTROLLED BY SOFTWARE
When the BORENx bits of the Configuration Words are
programmed to ‘01’, the BOR is controlled by the
SBOREN bit of the BORCON register. The device
start-up is not delayed by the BOR ready condition or
the VDD level.
BOR protection begins as soon as the BOR circuit is
ready. The status of the BOR circuit is reflected in the
BORRDY bit of the BORCON register.
BOR protection is unchanged by Sleep.
BOR protection is not active during Sleep. The device
wake-up will be delayed until the BOR is ready.
FIGURE 6-2:
BROWN-OUT SITUATIONS
VDD
Internal
Reset
VBOR
TPWRT(1)
VDD
Internal
Reset
VBOR
< TPWRT
TPWRT(1)
VDD
Internal
Reset
Note 1:
VBOR
TPWRT(1)
TPWRT delay only if the PWRTE bit is programmed to ‘0’.
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6.3
Register Definitions: BOR Control
REGISTER 6-1:
R/W-1/u
BORCON: BROWN-OUT RESET CONTROL REGISTER
R/W-0/u
SBOREN
BORFS
(1)
U-0
U-0
U-0
U-0
U-0
R-q/u
—
—
—
—
—
BORRDY
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
q = Value depends on condition
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
SBOREN: Software Brown-out Reset Enable bit
If BOREN <1:0> in Configuration Words  01:
SBOREN is read/write, but has no effect on the BOR.
If BOREN <1:0> in Configuration Words = 01:
1 = BOR is enabled
0 = BOR is disabled
bit 6
BORFS: Brown-out Reset Fast Start bit(1)
If BOREN<1:0> = 11 (always on) or BOREN<1:0> = 00 (always off):
BORFS is Read/Write, but has no effect.
If BOREN <1:0> = 10 (disabled in Sleep) or BOREN<1:0> = 01 (under software control):
1 = Band gap is forced on always (covers Sleep/wake-up/operating cases)
0 = Band gap operates normally and may turn off
bit 5-1
Unimplemented: Read as ‘0’
bit 0
BORRDY: Brown-out Reset Circuit Ready Status bit
1 = The Brown-out Reset circuit is active
0 = The Brown-out Reset circuit is inactive
Note 1:
The BOREN<1:0> bits are located in the Configuration Words.
DS40001775B-page 92
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6.4
Low-Power Brown-out Reset
(LPBOR)
The Low-Power Brown-out Reset (LPBOR) is an
essential part of the Reset subsystem. Refer to
Figure 6-1 to see how the BOR interacts with other
modules.
The LPBOR is used to monitor the external VDD pin.
When too low of a voltage is detected, the device is
held in Reset. When this occurs, a register bit (BOR) is
changed to indicate that a BOR Reset has occurred.
The same bit is set for both the BOR and the LPBOR.
Refer to Register 6-2.
6.4.1
ENABLING LPBOR
The LPBOR is controlled by the LPBOR bit of the
Configuration Words. When the device is erased, the
LPBOR module defaults to disabled.
6.4.1.1
LPBOR Module Output
The output of the LPBOR module is a signal indicating
whether or not a Reset is to be asserted. This signal is
OR’d together with the Reset signal of the BOR
module to provide the generic BOR signal, which goes
to the PCON register and to the power control block.
6.5
MCLR
The MCLR is an optional external input that can reset
the device. The MCLR function is controlled by the
MCLRE and the LVP bits of the Configuration Words
(Table 6-2).
TABLE 6-2:
MCLR CONFIGURATION
6.6
Watchdog Timer (WDT) Reset
The Watchdog Timer generates a Reset if the firmware
does not issue a CLRWDT instruction within the time-out
period. The TO and PD bits in the STATUS register are
changed to indicate the WDT Reset. See Section 9.0
“Watchdog Timer (WDT)” for more information.
6.7
RESET Instruction
A RESET instruction will cause a device Reset. The RI
bit in the PCON register will be set to ‘0’. See Table 6-4
for default conditions after a RESET instruction has
occurred.
6.8
Stack Overflow/Underflow Reset
The device can reset when the Stack Overflows or
Underflows. The STKOVF or STKUNF bits of the PCON
register indicate the Reset condition. These Resets are
enabled by setting the STVREN bit in the Configuration
Words. See Section 3.5.2 “Overflow/Underflow
Reset” for more information.
6.9
Programming Mode Exit
Upon exit of Programming mode, the device will
behave as if a POR had just occurred.
6.10
Power-up Timer
The Power-up Timer optionally delays device execution
after a BOR or POR event. This timer is typically used to
allow VDD to stabilize before allowing the device to start
running.
The Power-up Timer is controlled by the PWRTE bit of
the Configuration Words.
MCLRE
LVP
MCLR
0
0
Disabled
1
0
Enabled
6.11
x
1
Enabled
Upon the release of a POR or BOR, the following must
occur before the device will begin executing:
6.5.1
MCLR ENABLED
When MCLR is enabled and the pin is held low, the
device is held in Reset. The MCLR pin is connected to
VDD through an internal weak pull-up.
The device has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pulses.
Note:
6.5.2
A Reset does not drive the MCLR pin low.
MCLR DISABLED
When MCLR is disabled, the pin functions as a general
purpose input and the internal weak pull-up is under software control. See Section 11.1 “PORTA Registers” for
more information.
 2014-2015 Microchip Technology Inc.
1.
2.
3.
Start-up Sequence
Power-up Timer runs to completion (if enabled).
Oscillator Start-up Timer runs to completion (if
required for oscillator source).
MCLR must be released (if enabled).
The total time-out will vary based on oscillator
configuration and Power-up Timer configuration. See
Section 5.0 “Oscillator Module (with Fail-Safe
Clock Monitor)” for more information.
The Power-up Timer and Oscillator Start-up Timer run
independently of MCLR Reset. If MCLR is kept low
long enough, the Power-up Timer and Oscillator
Start-up Timer will expire. Upon bringing MCLR high,
the device will begin execution after 10 FOSC cycles
(see Figure 6-3). This is useful for testing purposes or
to synchronize more than one device operating in
parallel.
DS40001775B-page 93
PIC16(L)F1764/5/8/9
FIGURE 6-3:
RESET START-UP SEQUENCE
VDD
Internal POR
TPWRT
Power-up Timer
MCLR
TMCLR
Internal RESET
Oscillator Modes
External Crystal
TOST
Oscillator Start-up Timer
Oscillator
FOSC
Internal Oscillator
Oscillator
FOSC
External Clock (EC)
CLKIN
FOSC
DS40001775B-page 94
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6.12
Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and
PCON registers are updated to indicate the cause of
the Reset. Table 6-3 and Table 6-4 show the Reset
conditions of these registers.
TABLE 6-3:
RESET STATUS BITS AND THEIR SIGNIFICANCE
STKOVF STKUNF RWDT
RMCLR
RI
POR
BOR
TO
PD
Condition
0
0
1
1
1
0
x
1
1
Power-on Reset
0
0
1
1
1
0
x
0
x
Illegal, TO is set on POR
0
0
1
1
1
0
x
x
0
Illegal, PD is set on POR
0
0
u
1
1
u
0
1
1
Brown-out Reset
u
u
0
u
u
u
u
0
u
WDT Reset
u
u
u
u
u
u
u
0
0
WDT Wake-up from Sleep
u
u
u
u
u
u
u
1
0
Interrupt Wake-up from Sleep
u
u
u
0
u
u
u
u
u
MCLR Reset during Normal Operation
u
u
u
0
u
u
u
1
0
MCLR Reset during Sleep
u
u
u
u
0
u
u
u
u
RESET Instruction Executed
1
u
u
u
u
u
u
u
u
Stack Overflow Reset (STVREN = 1)
u
1
u
u
u
u
u
u
u
Stack Underflow Reset (STVREN = 1)
TABLE 6-4:
RESET CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
Power-on Reset
0000h
---1 1000
00-- 110x
MCLR Reset during Normal Operation
0000h
---u uuuu
uu-- 0uuu
MCLR Reset during Sleep
0000h
---1 0uuu
uu-- 0uuu
WDT Reset
0000h
---0 uuuu
uu-- uuuu
WDT Wake-up from Sleep
PC + 1
---0 0uuu
uu-- uuuu
Condition
Brown-out Reset
0000h
---1 1uuu
00-- 11u0
PC + 1(1)
---1 0uuu
uu-- uuuu
RESET Instruction Executed
0000h
---u uuuu
uu-- u0uu
Stack Overflow Reset (STVREN = 1)
0000h
---u uuuu
1u-- uuuu
Stack Underflow Reset (STVREN = 1)
0000h
---u uuuu
u1-- uuuu
Interrupt Wake-up from Sleep
Legend: u = unchanged; x = unknown; - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit (GIE) is set, the return address is
pushed onto the stack and the PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
 2014-2015 Microchip Technology Inc.
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6.13
Power Control (PCON) Register
The PCON register bits are shown in Register 6-2.
The Power Control (PCON) register contains flag bits
to differentiate between a:
•
•
•
•
•
•
•
Power-on Reset (POR)
Brown-out Reset (BOR)
Reset Instruction Reset (RI)
MCLR Reset (RMCLR)
Watchdog Timer Reset (RWDT)
Stack Underflow Reset (STKUNF)
Stack Overflow Reset (STKOVF)
6.14
Register Definitions: Power Control
REGISTER 6-2:
PCON: POWER CONTROL REGISTER
R/W/HS-0/q
R/W/HS-0/q
U-0
STKOVF
STKUNF
—
R/W/HC-1/q R/W/HC-1/q
RWDT
R/W/HC-1/q
RMCLR
R/W/HC-q/u R/W/HC-q/u
RI
POR
bit 7
BOR
bit 0
Legend:
HC = Hardware Clearable bit
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-m/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
STKOVF: Stack Overflow Flag bit
1 = A Stack Overflow occurred
0 = A Stack Overflow has not occurred or is cleared by firmware
bit 6
STKUNF: Stack Underflow Flag bit
1 = A Stack Underflow occurred
0 = A Stack Underflow has not occurred or is cleared by firmware
bit 5
Unimplemented: Read as ‘0’
bit 4
RWDT: Watchdog Timer Reset Flag bit
1 = A Watchdog Timer Reset has not occurred or is set to ‘1’ by firmware
0 = A Watchdog Timer Reset has occurred (cleared by hardware)
bit 3
RMCLR: MCLR Reset Flag bit
1 = A MCLR Reset has not occurred or is set to ‘1’ by firmware
0 = A MCLR Reset has occurred (cleared by hardware)
bit 2
RI: RESET Instruction Flag bit
1 = A RESET instruction has not been executed or is set to ‘1’ by firmware
0 = A RESET instruction has been executed (cleared by hardware)
bit 1
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset
occurs)
DS40001775B-page 96
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TABLE 6-5:
SUMMARY OF REGISTERS ASSOCIATED WITH RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BORCON
SBOREN
BORFS
—
—
—
—
—
BORRDY
92
PCON
STKOVF
STKUNF
—
RWDT
RMCLR
RI
POR
BOR
96
STATUS
—
—
—
TO
PD
Z
DC
C
28
WDTCON
—
—
SWDTEN
119
WDTPS<4:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.
 2014-2015 Microchip Technology Inc.
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PIC16(L)F1764/5/8/9
NOTES:
DS40001775B-page 98
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7.0
Many peripherals produce interrupts. Refer to the
corresponding chapters for details.
INTERRUPTS
The interrupt feature allows certain events to preempt
normal program flow. Firmware is used to determine
the source of the interrupt and act accordingly. Some
interrupts can be configured to wake the MCU from
Sleep mode.
A block diagram of the interrupt logic is shown in
Figure 7-1.
This chapter contains the following information for
interrupts:
•
•
•
•
•
Operation
Interrupt Latency
Interrupts during Sleep
INT Pin
Automatic Context Saving
FIGURE 7-1:
INTERRUPT LOGIC
Rev. 10-000010A
1/13/2014
TMR0IF
TMR0IE
Peripheral Interrupts
(TMR1IF) PIR1<0>
(TMR1IE) PIE1<0>
Wake-up
(If in Sleep mode)
INTF
INTE
IOCIF
IOCIE
Interrupt
to CPU
PEIE
PIRn<7>
PIEn<7>
 2014-2015 Microchip Technology Inc.
GIE
DS40001775B-page 99
PIC16(L)F1764/5/8/9
7.1
Operation
Interrupts are disabled upon any device Reset. They
are enabled by setting the following bits:
• GIE bit of the INTCON register
• Interrupt enable bit(s) for the specific interrupt
event(s)
• PEIE bit of the INTCON register (if the interrupt
enable bit of the interrupt event is contained in the
PIE1 or PIE2 register)
The RETFIE instruction exits the ISR by popping the
previous address from the stack, restoring the saved
context from the shadow registers and setting the
GIE bit.
For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.
Note 1: Individual interrupt flag bits are set,
regardless of the state of any other
enable bits.
2: All interrupts will be ignored while the GIE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.
The INTCON, PIR1 and PIR2 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will
be set, regardless of the status of the GIE, PEIE and
individual interrupt enable bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
• Current prefetched instruction is flushed
• GIE bit is cleared
• Current Program Counter (PC) is pushed onto the
stack
• Critical registers are automatically saved to the
shadow registers (see “Section 7.5 “Automatic
Context Saving”)
• PC is loaded with the interrupt vector, 0004h
7.2
Interrupt Latency
Interrupt latency is defined as the time from when the
interrupt event occurs to the time code execution at the
interrupt vector begins. The latency for synchronous
interrupts is three or four instruction cycles. For
asynchronous interrupts, the latency is three to five
instruction cycles, depending on when the interrupt
occurs. See Figure 7-2 and Figure 7-3 for more details.
The firmware within the Interrupt Service Routine (ISR)
should determine the source of the interrupt by polling
the interrupt flag bits. The interrupt flag bits must be
cleared before exiting the ISR to avoid repeated
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.
DS40001775B-page 100
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
FIGURE 7-2:
INTERRUPT LATENCY
OSC1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKR
Interrupt Sampled
during Q1
Interrupt
GIE
PC
Execute
PC – 1
PC
1-Cycle Instruction at PC
PC + 1
0004h
0005h
NOP
NOP
Inst(0004h)
PC + 1/FSR
ADDR
New PC/
PC + 1
0004h
0005h
Inst(PC)
NOP
NOP
Inst(0004h)
FSR ADDR
PC + 1
PC + 2
0004h
0005h
INST(PC)
NOP
NOP
NOP
Inst(0004h)
Inst(0005h)
FSR ADDR
PC + 1
0004h
0005h
INST(PC)
NOP
NOP
Inst(0004h)
Inst(PC)
Interrupt
GIE
PC
Execute
PC – 1
PC
2-Cycle Instruction at PC
Interrupt
GIE
PC
Execute
PC – 1
PC
3-Cycle Instruction at PC
Interrupt
GIE
PC
Execute
PC – 1
PC
3-Cycle Instruction at PC
 2014-2015 Microchip Technology Inc.
PC + 2
NOP
NOP
DS40001775B-page 101
PIC16(L)F1764/5/8/9
FIGURE 7-3:
INT PIN INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1 Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT(3)
(4)
INT Pin
(1)
(1)
INTF
Interrupt Latency(2)
(5)
GIE
INSTRUCTION FLOW
PC
PC
PC + 1
PC + 1
0004h
0005h
Instruction
Fetched
Inst (PC)
Inst (PC + 1)
—
Inst (0004h)
Inst (0005h)
Instruction
Executed
Inst (PC – 1)
Inst (PC)
Forced NOP
Forced NOP
Inst (0004h)
Note 1:
INTF flag is sampled here (every Q1).
2:
Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3:
CLKOUT not available in all Oscillator modes.
4:
For minimum width of INT pulse, refer to the AC specifications in Section 36.0 “Electrical Specifications”.
5:
INTF is enabled to be set any time during the Q4-Q1 cycles.
DS40001775B-page 102
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PIC16(L)F1764/5/8/9
7.3
Interrupts During Sleep
Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate interrupt enable bit(s) set
prior to entering Sleep.
On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEP instruction. The instruction directly after
the SLEEP instruction will always be executed
before branching to the ISR. Refer to Section 8.0
“Power-Down Mode (Sleep)” for more details.
7.4
INT Pin
The INT pin can be used to generate an asynchronous
edge-triggered interrupt. This interrupt is enabled by
setting the INTE bit of the INTCON register. The
INTEDG bit of the OPTION_REG register determines on
which edge the interrupt will occur. When the INTEDG
bit is set, the rising edge will cause the interrupt. When
the INTEDG bit is clear, the falling edge will cause the
interrupt. The INTF bit of the INTCON register will be set
when a valid edge appears on the INT pin. If the GIE and
INTE bits are also set, the processor will redirect
program execution to the interrupt vector.
 2014-2015 Microchip Technology Inc.
7.5
Automatic Context Saving
Upon entering an interrupt, the return PC address is
saved on the stack. Additionally, the following registers
are automatically saved in the shadow registers:
•
•
•
•
•
W register
STATUS register (except for TO and PD)
BSR register
FSR registers
PCLATH register
Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to
these registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding shadow register should be modified and the
value will be restored when exiting the ISR. The
shadow registers are available in Bank 31 and are
readable and writable. Depending on the user’s
application, other registers may also need to be saved.
DS40001775B-page 103
PIC16(L)F1764/5/8/9
7.6
Register Definitions: Interrupt Control
REGISTER 7-1:
INTCON: INTERRUPT CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R-0/0
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all active interrupts
0 = Disables all interrupts
bit 6
PEIE: Peripheral Interrupt Enable bit
1 = Enables all active peripheral interrupts
0 = Disables all peripheral interrupts
bit 5
TMR0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4
INTE: INT External Interrupt Enable bit
1 = Enables the INT external interrupt
0 = Disables the INT external interrupt
bit 3
IOCIE: Interrupt-On-Change Enable bit
1 = Enables the Interrupt-On-Change
0 = Disables the Interrupt-On-Change
bit 2
TMR0IF: Timer0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed
0 = TMR0 register did not overflow
bit 1
INTF: INT External Interrupt Flag bit
1 = The INT external interrupt occurred
0 = The INT external interrupt did not occur
bit 0
IOCIF: Interrupt-On-Change Interrupt Flag bit(1)
1 = When at least one of the Interrupt-On-Change pins changed state
0 = None of the Interrupt-On-Change pins have changed state
Note 1:
The IOCIF Flag bit is read-only and cleared when all the Interrupt-On-Change flags in the IOCxF registers
have been cleared by software.
Note:
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding
enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the
appropriate interrupt flag bits are clear prior to enabling an interrupt.
DS40001775B-page 104
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
REGISTER 7-2:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
TMR1GIE: Timer1 Gate Interrupt Enable bit
1 = Enables the Timer1 gate acquisition interrupt
0 = Disables the Timer1 gate acquisition interrupt
bit 6
ADIE: Analog-to-Digital Converter (ADC) Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
bit 5
RCIE: EUSART Receive Interrupt Enable bit
1 = Enables the EUSART receive interrupt
0 = Disables the EUSART receive interrupt
bit 4
TXIE: EUSART Transmit Interrupt Enable bit
1 = Enables the EUSART transmit interrupt
0 = Disables the EUSART transmit interrupt
bit 3
SSP1IE: Master Synchronous Serial Port (MSSP) Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 2
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1
TMR2IE: TMR2 to T2PR Match Interrupt Enable bit
1 = Enables the Timer2 to T2PR match interrupt
0 = Disables the Timer2 to T2PR match interrupt
bit 0
TMR1IE: Timer1 Overflow Interrupt Enable bit
1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt
Note:
Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 105
PIC16(L)F1764/5/8/9
REGISTER 7-3:
R/W-0/0
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0/0
OSFIE
R/W-0/0
C2IE
C1IE
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
BCL1IE
(1)
(1)
C4IE
C3IE
bit 7
R/W-0/0
CCP2IE(1)
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
OSFIE: Oscillator Fail Interrupt Enable bit
1 = Enables the Oscillator fail interrupt
0 = Disables the Oscillator fail interrupt
bit 6
C2IE: Comparator C2 Interrupt Enable bit
1 = Enables the Comparator C2 interrupt
0 = Disables the Comparator C2 interrupt
bit 5
C1IE: Comparator C1 Interrupt Enable bit
1 = Enables the Comparator C1 interrupt
0 = Disables the Comparator C1 interrupt
bit 4
Unimplemented: Read as ‘0’
bit 3
BCL1IE: MSSP Bus Collision Interrupt Enable bit
1 = Enables the MSSP bus collision interrupt
0 = Disables the MSSP bus collision interrupt
bit 2
C4IE: TMR6 to T6PR Match Interrupt Enable bit(1)
1 = Enables the Comparator C4 interrupt
0 = Disables the Comparator C4 interrupt
bit 1
C3IE: TMR4 to T4PR Match Interrupt Enable bit(1)
1 = Enables the Comparator C3 interrupt
0 = Disables the Comparator C3 interrupt
bit 0
CCP2IE: CCP2 Interrupt Enable bit(1)
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
Note 1:
Note:
PIC16(L)F1768/9 only.
Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
DS40001775B-page 106
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
REGISTER 7-4:
R/W-0/0
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
R/W-0/0
PWM6IE(1)
PWM5IE
R/W-0/0
COG1IE
R/W-0/0
ZCDIE
R/W-0/0
COG2IE
(1)
R/W-0/0
R/W-0/0
R/W-0/0
CLC3IE
CLC2IE
CLC1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
PWM6IE: PWM6 Interrupt Enable bit(1)
1 = PWM6 interrupt is enabled
0 = PWM6 interrupt is disabled
bit 6
PWM5IE: PWM5 Interrupt Enable bit
1 = PWM5 interrupt is enabled
0 = PWM5 interrupt is disabled
bit 5
COG1IE: COG1 Auto-Shutdown Interrupt Enable bit
1 = COG1 interrupt is enabled
0 = COG1 interrupt is disabled
bit 4
ZCDIE: Zero-Cross Detection Interrupt Enable bit
1 = ZCD interrupt is enabled
0 = ZCD interrupt is disabled
bit 3
COG2IE: COG2 Auto-Shutdown Interrupt Enable bit(1)
1 = COG2 interrupt is enabled
0 = COG2 interrupt is disabled
bit 2
CLC3IE: CLC3 Interrupt Enable bit
1 = CLC3 interrupt is enabled
0 = CLC3 interrupt is disabled
bit 1
CLC2IE: CLC2 Interrupt Enable bit
1 = CLC2 interrupt is enabled
0 = CLC2 interrupt is disabled
bit 0
CLC1IE: CLC1 Interrupt Enable bit
1 = CLC1 interrupt is enabled
0 = CLC1 interrupt is disabled
Note 1:
Note:
PIC16(L)F1768/9 only.
Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 107
PIC16(L)F1764/5/8/9
REGISTER 7-5:
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0/0
R/W-0/0
R-0/0
R-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
TMR1GIF: Timer1 Gate Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 6
ADIF: Analog-to-Digital Converter (ADC) Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 5
RCIF: EUSART Receive Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 4
TXIF: EUSART Transmit Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 3
SSP1IF: Master Synchronous Serial Port (MSSP) Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 2
CCP1IF: CCP1 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 1
TMR2IF: Timer2 to T2PR Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 0
TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Note:
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding
enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the
appropriate interrupt flag bits are clear prior to enabling an interrupt.
DS40001775B-page 108
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
REGISTER 7-6:
R/W-0/0
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0/0
OSFIF
R/W-0/0
C2IF
C1IF
U-0
—
R/W-0/0
BCL1IF
R/W-0/0
C4IF
(1)
R/W-0/0
C3IF
bit 7
(1)
R/W-0/0
CCP2IF(1)
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
OSFIF: Oscillator Fail Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 6
C2IF: Comparator C2 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 5
C1IF: Comparator C1 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 4
Unimplemented: Read as ‘0’
bit 3
BCL1IF: MSSP Bus Collision Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 2
C4IF: Comparator C4 Interrupt Flag bit(1)
1 = Interrupt is pending
0 = Interrupt is not pending
bit 1
C3IF: Comparator C3 Interrupt Flag bit(1)
1 = Interrupt is pending
0 = Interrupt is not pending
bit 0
CCP2IF: CCP2 Interrupt Flag bit(1)
1 = Interrupt is pending
0 = Interrupt is not pending
Note 1:
Note:
PIC16(L)F1768/9 only.
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding
enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the
appropriate interrupt flag bits are clear prior to enabling an interrupt.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 109
PIC16(L)F1764/5/8/9
REGISTER 7-7:
R/W-0/0
PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3
R/W-0/0
PWM6IF(1)
PWM5IF
R/W-0/0
R/W-0/0
COG1IF
ZCDIF
R/W-0/0
COG2IF
(1)
R/W-0/0
R/W-0/0
R/W-0/0
CLC3IF
CLC2IF
CLC1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
PWM6IF: PWM6 Interrupt Flag bit(1)
1 = Interrupt is pending
0 = Interrupt is not pending
bit 6
PWM5IF: PWM5 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 5
COG1IF: COG1 Auto-Shutdown Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 4
ZCDIF: Zero-Cross Detection Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 3
COG2IF: COG2 Auto-Shutdown Interrupt Flag bit(1)
1 = Interrupt is pending
0 = Interrupt is not pending
bit 2
CLC3IF: CLC3 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 1
CLC2IF: CLC2 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 0
CLC1IF: CLC1 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Note 1:
Note:
PIC16(L)F1768/9 only.
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding
enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the
appropriate interrupt flag bits are clear prior to enabling an interrupt.
DS40001775B-page 110
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
TABLE 7-1:
Name
INTCON
OPTION_REG
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
104
WPUEN
INTEDG TMR0CS TMR0SE
PSA
PS<2:0>
221
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
105
PIE2
OSFIE
C2IE
C1IE
—
BCL1IE
C4IE(1)
C3IE(1)
CCP2IE(1)
106
PIE3
PWM6IE(1)
PWM5IE
COG1IE
ZCDIE
CLC3IE
CLC2IE
CLC1IE
107
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
108
C1IF
—
BCL1IF
C4IF(1)
C3IF(1)
CCP2IF(1)
109
COG1IF
ZCDIF
COG2IF(1) CLC3IF
CLC2IF
CLC1IF
110
PIR2
PIR3
OSFIF
C2IF
PWM6IF(1) PWM5IF
(1)
COG2IE
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupts.
Note 1: PIC16(L)F1768/9 only.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 111
PIC16(L)F1764/5/8/9
NOTES:
DS40001775B-page 112
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
8.0
POWER-DOWN MODE (SLEEP)
8.1
Wake-up from Sleep
The Power-Down mode is entered by executing a
SLEEP instruction.
The device can wake-up from Sleep through one of the
following events:
Upon entering Sleep mode, the following conditions
exist:
1.
2.
3.
4.
5.
6.
1.
2.
3.
4.
5.
6.
7.
8.
9.
WDT will be cleared, but keeps running if
enabled for operation during Sleep.
PD bit of the STATUS register is cleared.
TO bit of the STATUS register is set.
CPU clock is disabled.
31 kHz LFINTOSC is unaffected and peripherals
that operate from it may continue operation in
Sleep.
Timer1 and peripherals that operate from
Timer1 continue operation in Sleep when the
Timer1 clock source selected is:
• LFINTOSC
• T1CKI
• Secondary oscillator
ADC is unaffected if the dedicated FRC oscillator
is selected.
I/O ports maintain the status they had before
SLEEP was executed (driving high, low or
high-impedance).
Resets other than WDT are not affected by
Sleep mode.
Refer to individual chapters for more details on
peripheral operation during Sleep.
To minimize current consumption, the following
conditions should be considered:
•
•
•
•
•
•
External Reset input on MCLR pin, if enabled.
Brown-out Reset (BOR), if enabled.
Power-on Reset (POR), if enabled.
Watchdog Timer, if enabled.
Any external interrupt.
Interrupts by peripherals capable of running
during Sleep (see individual peripheral for more
information).
The first three events will cause a device Reset. The
last three events are considered a continuation of
program execution. To determine whether a device
Reset or wake-up event occurred, refer to
Section 6.12 “Determining the Cause of a Reset”.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be enabled. Wake-up will
occur regardless of the state of the GIE bit. If the GIE
bit is disabled, the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
enabled, the device executes the instruction after the
SLEEP instruction, the device will then call the Interrupt
Service Routine. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should insert a NOP after the SLEEP instruction.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
I/O pins should not be floating
External circuitry sinking current from I/O pins
Internal circuitry sourcing current from I/O pins
Current draw from pins with internal weak pull-ups
Modules using 31 kHz LFINTOSC
Modules using secondary oscillator
I/O pins that are high-impedance inputs should be
pulled to VDD or VSS externally to avoid switching
currents caused by floating inputs.
Examples of internal circuitry that might be sourcing
current include modules such as the DAC and FVR
modules. See Section 17.0 “5-Bit Digital-to-Analog
Converter (DAC) Module” and Section 14.0 “Fixed
Voltage Reference (FVR)” for more information on
these modules.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 113
PIC16(L)F1764/5/8/9
8.1.1
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction:
- SLEEP instruction will execute as a NOP
- WDT and WDT prescaler will not be cleared
- TO bit of the STATUS register will not be set
- PD bit of the STATUS register will not be
cleared
FIGURE 8-1:
• If the interrupt occurs during or after the
execution of a SLEEP instruction:
- SLEEP instruction will be completely
executed
- Device will immediately wake-up from Sleep
- WDT and WDT prescaler will be cleared
- TO bit of the STATUS register will be set
- PD bit of the STATUS register will be cleared
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKIN(1)
TOST(3)
CLKOUT(2)
Interrupt Flag
Interrupt Latency(4)
GIE bit
(INTCON reg.)
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
Note 1:
2:
3:
4:
Processor in
Sleep
PC
PC + 1
PC + 2
PC + 2
Inst(PC) = Sleep
Inst(PC + 1)
Inst(PC + 2)
Inst(PC – 1)
Sleep
Inst(PC + 1)
PC + 2
Forced NOP
0004h
0005h
Inst(0004h)
Inst(0005h)
Forced NOP
Inst(0004h)
External clock. High, Medium, Low mode assumed.
CLKOUT is shown here for timing reference.
TOST = 1024 TOSC. This delay does not apply to EC, RC and INTOSC Oscillator modes or Two-Speed Start-up (see Section 5.4
“Two-Speed Clock Start-up Mode”.
GIE = 1 assumed. In this case, after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.
DS40001775B-page 114
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
8.2
Low-Power Sleep Mode
The PIC16F1764/5/8/9 devices contain an internal Low
Dropout (LDO) voltage regulator, which allows the
device I/O pins to operate at voltages up to 5.5V while
the internal device logic operates at a lower voltage.
The LDO and its associated reference circuitry must
remain active when the device is in Sleep mode. The
PIC16F1764/5/8/9 devices allow the user to optimize
the operating current in Sleep, depending on the
application requirements.
A Low-Power Sleep mode can be selected by setting
the VREGPM bit of the VREGCON register. With this
bit set, the LDO and reference circuitry are placed in a
low-power state when the device is in Sleep.
8.2.1
SLEEP CURRENT VS. WAKE-UP
TIME
In the default operating mode, the LDO and reference
circuitry remain in the normal configuration while in
Sleep. The device is able to exit Sleep mode quickly
since all circuits remain active. In Low-Power Sleep
mode, when waking up from Sleep, an extra delay time
is required for these circuits to return to the normal
configuration and stabilize.
8.2.2
PERIPHERAL USAGE IN SLEEP
Some peripherals that can operate in Sleep mode will
not operate properly with the Low-Power Sleep mode
selected. The Low-Power Sleep mode is intended for
use with the following peripherals only:
•
•
•
•
Brown-out Reset (BOR)
Watchdog Timer (WDT)
External interrupt pin/Interrupt-On-Change pins
Timer1 (with external clock source < 100 kHz)
Note:
The PIC16LF1764/5/8/9 devices do not
have a configurable Low-Power Sleep
mode. PIC16LF1764/5/8/9 devices are
unregulated devices and are always in the
lowest power state when in Sleep, with no
wake-up time penalty. These devices have
a lower maximum VDD and I/O voltage than
the PIC16F1764/5/8/9. See Section 36.0
“Electrical Specifications” for more
information.
The Low-Power Sleep mode is beneficial for applications that stay in Sleep mode for long periods of time.
The Normal mode is beneficial for applications that
need to wake from Sleep quickly and frequently.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 115
PIC16(L)F1764/5/8/9
8.3
Register Definitions: Voltage Regulator Control
VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1)
REGISTER 8-1:
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0/0
R/W-1/1
—
—
—
—
—
—
VREGPM
r
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
r = Reserved bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-2
Unimplemented: Read as ‘0’
bit 1
VREGPM: Voltage Regulator Power Mode Selection bit
1 = Low-Power Sleep mode is enabled in Sleep(2)
Draws lowest current in Sleep, slower wake-up.
0 = Normal Power mode is enabled in Sleep(2)
Draws higher current in Sleep, faster wake-up.
bit 0
Reserved: Read as ‘1’. Maintain this bit set.
Note 1:
2:
PIC16F1764/5/8/9 only.
See Section 36.0 “Electrical Specifications”.
TABLE 8-1:
Name
INTCON
IOCAP
IOCAN
IOCAF
IOCBP(1)
IOCBN(1)
IOCBF(1)
IOCCP
IOCCN
IOCCF
PIE1
PIE2
PIE3
PIR1
PIR2
PIR3
SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
Bit 7
GIE
—
—
—
Bit 6
Bit 5
PEIE
TMR0IE
—
—
—
IOCBP<7:4>
IOCBN<7:4>
IOCBF<7:4>
(1)
IOCCP<7:6>
IOCCN<7:6>(1)
IOCCF<7:6>(1)
TMR1GIE
ADIE
RCIE
OSFIE
C2IE
C1IE
PWM6IE(1) PWM5IE COG1IE
TMR1GIF
ADIF
RCIF
OSFIF
C2IF
C1IF
(1)
PWM6IF
PWM5IF COG1IF
Bit 4
INTE
TXIE
—
ZCDIE
TXIF
—
ZCDIF
Bit 3
Bit 2
IOCIE
TMR0IF
IOCAP<5:0>
IOCAN<5:0>
IOCAF<5:0>
—
—
—
—
—
—
IOCCP<5:0>
IOCCN<5:0>
IOCCF<5:0>
SSP1IE CCP1IE
BCL1IE
C4IE(1)
(1)
COG2IE
CLC3IE
SSP1IF CCP1IF
BCL1IF
C4IF(1)
COG2IF(1) CLC3IF
Bit 1
Bit 0
INTF
IOCIF
—
—
—
—
—
—
TMR2IE
C3IE(1)
CLC2IE
TMR2IF
C3IF(1)
CLC2IF
TMR1IE
CCP2IE(1)
CLC1IE
TMR1IF
CCP2IF(1)
CLC1IF
Register
on Page
104
167
167
168
168
169
169
170
170
171
105
106
107
108
109
110
—
—
—
TO
PD
Z
DC
C
28
STATUS
VREGCON(2)
—
—
—
—
—
—
VREGPM
r
116
WDTCON
—
—
WDTPS<4:0>
SWDTEN
119
Legend: — = unimplemented location, read as ‘0’; r = Reserved bit. Shaded cells are not used in Power-Down mode.
Note 1: PIC16(L)F1768/9 only.
2: PIC16F1764/5/8/9 only.
DS40001775B-page 116
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
9.0
WATCHDOG TIMER (WDT)
The Watchdog Timer is a system timer that generates
a Reset if the firmware does not issue a CLRWDT
instruction within the time-out period. The Watchdog
Timer is typically used to recover the system from
unexpected events.
FIGURE 9-1:
The WDT has the following features:
• Independent clock source
• Multiple operating modes:
- WDT is always on
- WDT is off when in Sleep
- WDT is controlled by software
- WDT is always off
• Configurable time-out period is from 1 ms to
256 seconds (nominal)
• Multiple Reset conditions
• Operation during Sleep
WATCHDOG TIMER BLOCK DIAGRAM
Rev. 10-000141A
7/30/2013
WDTE<1:0> = 01
SWDTEN
WDTE<1:0> = 11
LFINTOSC
23-%it Programmable
Prescaler WDT
WDT
Time-out
WDTE<1:0> = 10
Sleep
 2014-2015 Microchip Technology Inc.
WDTPS<4:0>
DS40001775B-page 117
PIC16(L)F1764/5/8/9
9.1
Independent Clock Source
9.3
Time-out Period
The WDT derives its time base from the 31 kHz
LFINTOSC internal oscillator. Time intervals in this
chapter are based on a nominal interval of 1 ms. See
Table 36-8 for the LFINTOSC specification.
The WDTPS<4:0> bits of the WDTCON register set the
time-out period from 1 ms to 256 seconds (nominal).
After a Reset, the default time-out period is two
seconds.
9.2
9.4
WDT Operating Modes
The Watchdog Timer module has four operating modes
controlled by the WDTE<1:0> bits in the Configuration
Words (see Table 9-1).
9.2.1
WDT IS ALWAYS ON
When the WDTE<1:0> bits of the Configuration Words
are set to ‘11’, the WDT is always on.
WDT protection is active during Sleep.
9.2.2
WDT IS OFF IN SLEEP
Clearing the WDT
The WDT is cleared when any of the following
conditions occur:
•
•
•
•
•
•
•
Any Reset
CLRWDT instruction is executed
Device enters Sleep
Device wakes up from Sleep
Oscillator fails
WDT is disabled
Oscillator Start-up Timer (OST) is running
When the WDTE<1:0> bits of the Configuration Words
are set to ‘10’, the WDT is on, except in Sleep.
See Table 9-2 for more information.
WDT protection is not active during Sleep.
9.5
9.2.3
WDT CONTROLLED BY SOFTWARE
When the WDTE<1:0> bits of the Configuration Words
are set to ‘01’, the WDT is controlled by the SWDTEN
bit of the WDTCON register.
WDT protection is unchanged by Sleep. See Table 9-1
for more details.
TABLE 9-1:
WDT OPERATING MODES
WDTE<1:0>
SWDTEN
Device
Mode
11
x
X
10
x
1
01
0
00
TABLE 9-2:
x
WDT Mode
Active
Awake
Active
Sleep
Disabled
X
X
Operation During Sleep
When the device enters Sleep, the WDT is cleared. If
the WDT is enabled during Sleep, the WDT resumes
counting.
When the device exits Sleep, the WDT is cleared
again. The WDT remains clear until the OST, if
enabled, completes. See Section 5.0 “Oscillator
Module (with Fail-Safe Clock Monitor)” for more
information on the OST.
When a WDT time-out occurs while the device is in
Sleep, no Reset is generated. Instead, the device
wakes up and resumes operation. The TO and PD bits
in the STATUS register are changed to indicate the
event. See the STATUS register (Register 3-1) for more
information.
Active
Disabled
Disabled
WDT CLEARING CONDITIONS
Conditions
WDT
WDTE<1:0> = 00
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enters Sleep
CLRWDT Command
Cleared
Oscillator Fail is Detected
Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP
Changes INTOSC Divider (IRCFx bits)
DS40001775B-page 118
Cleared until the end of OST
Unaffected
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
9.6
Register Definitions: Watchdog Control
REGISTER 9-1:
WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0
U-0
—
—
R/W-0/0
R/W-1/1
R/W-0/0
R/W-1/1
R/W-1/1
WDTPS<4:0>(1)
bit 7
R/W-0/0
SWDTEN
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-m/n = Value at POR and BOR/Value at all other Resets
bit 7-6
Unimplemented: Read as ‘0’
bit 5-1
WDTPS<4:0>: Watchdog Timer Period Select bits(1)
Bit Value = Prescale Rate
11111 = Reserved, results in minimum interval (1:32)
•
•
•
10011 = Reserved, results in minimum interval (1:32)
10010 = 1:8388608 (223) (Interval 256s nominal)
10001 = 1:4194304 (222) (Interval 128s nominal)
10000 = 1:2097152 (221) (Interval 64s nominal)
01111 = 1:1048576 (220) (Interval 32s nominal)
01110 = 1:524288 (219) (Interval 16s nominal)
01101 = 1:262144 (218) (Interval 8s nominal)
01100 = 1:131072 (217) (Interval 4s nominal)
01011 = 1:65536 (Interval 2s nominal) (Reset value)
01010 = 1:32768 (Interval 1s nominal)
01001 = 1:16384 (Interval 512 ms nominal)
01000 = 1:8192 (Interval 256 ms nominal)
00111 = 1:4096 (Interval 128 ms nominal)
00110 = 1:2048 (Interval 64 ms nominal)
00101 = 1:1024 (Interval 32 ms nominal)
00100 = 1:512 (Interval 16 ms nominal)
00011 = 1:256 (Interval 8 ms nominal)
00010 = 1:128 (Interval 4 ms nominal)
00001 = 1:64 (Interval 2 ms nominal)
00000 = 1:32 (Interval 1 ms nominal)
bit 0
SWDTEN: Software Enable/Disable for Watchdog Timer bit
If WDTE<1:0> = 1x:
This bit is ignored.
If WDTE<1:0> = 01:
1 = WDT is turned on
0 = WDT is turned off
If WDTE<1:0> = 00:
This bit is ignored.
Note 1:
Times are approximate. WDT time is based on 31 kHz LFINTOSC.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 119
PIC16(L)F1764/5/8/9
TABLE 9-3:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER
Bit 7
Bit 6
OSCCON
SPLLEN
STATUS
—
—
WDTCON
—
—
Bit 5
Bit 4
Bit 3
IRCF<3:0>
—
Bit 2
Bit 1
—
TO
PD
Bit 0
SCS<1:0>
Z
DC
WDTPS<4:0>
Register
on Page
85
C
28
SWDTEN
119
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
TABLE 9-4:
Name
CONFIG1
SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
13:8
—
—
FCMEN
IESO
CLKOUTEN
7:0
CP
MCLRE
PWRTE
WDTE<1:0>
Bit 10/2
Bit 9/1
BOREN<1:0>
Bit 8/0
—
FOSC<2:0>
Register
on Page
64
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
DS40001775B-page 120
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
10.0
FLASH PROGRAM MEMORY
CONTROL
The Flash program memory is readable and writable
during normal operation over the full VDD range.
Program memory is indirectly addressed using Special
Function Registers (SFRs). The SFRs used to access
program memory are:
•
•
•
•
•
•
PMCON1
PMCON2
PMDATL
PMDATH
PMADRL
PMADRH
When accessing the program memory, the
PMDATH:PMDATL register pair forms a 2-byte word
that holds the 14-bit data for read/write, and the
PMADRH:PMADRL register pair forms a 2-byte word
that holds the 15-bit address of the program memory
location being read.
The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip charge
pump rated to operate over the operating voltage range
of the device.
The Flash program memory can be protected in two
ways: by code protection (CP bit in the Configuration
Words) and write protection (WRT<1:0> bits in the
Configuration Words).
Code protection (CP = 0) disables access, reading and
writing to the Flash program memory via external
device programmers. Code protection does not affect
the self-write and erase functionality. Code protection
can only be reset by a device programmer performing
a bulk erase to the device, clearing all Flash program
memory, Configuration bits and User IDs.(1)
Write protection prohibits self-write and erase to a
portion or all of the Flash program memory, as defined
by the WRT<1:0> bits. Write protection does not affect
a device programmer’s ability to read, write or erase
the device.
Note 1: Code protection of the entire Flash
program memory array is enabled by
clearing the CP bit of the Configuration
Words.
10.1
PMADRL and PMADRH Registers
The PMADRH:PMADRL register pair can address up
to a maximum of 32K words of program memory. When
selecting a program address value, the MSB of the
address is written to the PMADRH register and the LSB
is written to the PMADRL register.
 2014-2015 Microchip Technology Inc.
10.1.1
PMCON1 AND PMCON2
REGISTERS
PMCON1 is the control register for Flash program
memory accesses.
Control bits, RD and WR, initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared by hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
The WREN bit, when set, will allow a write operation to
occur. On power-up, the WREN bit is clear. The
WRERR bit is set when a write operation is interrupted
by a Reset during normal operation. In these situations,
following Reset, the user can check the WRERR bit
and execute the appropriate error handling routine.
The PMCON2 register is a write-only register. Attempting
to read the PMCON2 register will return all ‘0’s.
To enable writes to the program memory, a specific
pattern (the unlock sequence), must be written to the
PMCON2 register. The required unlock sequence
prevents inadvertent writes to the program memory
write latches and Flash program memory.
10.2
Flash Program Memory Overview
It is important to understand the Flash program memory
structure for erase and programming operations. Flash
program memory is arranged in rows. A row consists of
a fixed number of 14-bit program memory words. A row
is the minimum size that can be erased by user software.
After a row has been erased, the user can reprogram
all or a portion of this row. Data to be written into the
program memory row is written to 14-bit wide data write
latches. These write latches are not directly accessible
to the user, but may be loaded via sequential writes to
the PMDATH:PMDATL register pair.
Note:
If the user wants to modify only a portion
of a previously programmed row, then the
contents of the entire row must be read
and saved in RAM prior to the erase.
Then, new data and retained data can be
written into the write latches to reprogram
the row of Flash program memory. However, any unprogrammed locations can be
written without first erasing the row. In this
case, it is not necessary to save and
rewrite the other previously programmed
locations.
See Table 10-1 for erase row size and the number of
write latches for Flash program memory.
DS40001775B-page 121
PIC16(L)F1764/5/8/9
TABLE 10-1:
FLASH MEMORY
ORGANIZATION BY DEVICE
Device
Row Erase
(words)
Write
Latches
(words)
PIC16(L)F1764
PIC16(L)F1765
PIC16(L)F1768
32
2.
3.
READING THE FLASH PROGRAM
MEMORY
Write
the
desired
address
to
the
PMADRH:PMADRL register pair.
Clear the CFGS bit of the PMCON1 register.
Then, set control bit, RD, of the PMCON1 register.
Once the read control bit is set, the Program Flash
Memory controller will use the second instruction cycle to
read the data. This causes the second instruction,
immediately following the “BSF PMCON1,RD” instruction,
to be ignored. The data is available in the very next cycle,
in the PMDATH:PMDATL register pair; therefore, it can
be read as two bytes in the following instructions.
The PMDATH:PMDATL register pair will hold this value
until another read or until it is written to by the user.
Note:
Rev. 10-000046A
7/30/2013
32
To read a program memory location, the user must:
1.
FLASH PROGRAM
MEMORY READ
FLOWCHART
Start
Read Operation
PIC16(L)F1769
10.2.1
FIGURE 10-1:
The two instructions following a program
memory read are required to be NOPs.
This prevents the user from executing a
2-cycle instruction on the next instruction
after the RD bit is set.
Select
Program or Configuration Memory
(CFGS)
Select
Word Address
(PMADRH:PMADRL)
Initiate Read operation
(RD = 1)
Instruction fetched ignored
NOP execution forced
Instruction fetched ignored
NOP execution forced
Data read now in
PMDATH:PMDATL
End
Read Operation
DS40001775B-page 122
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
FIGURE 10-2:
FLASH PROGRAM MEMORY READ CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Flash ADDR
PC + 1
INSTR (PC)
Flash Data
INSTR(PC – 1)
Executed Here
PMADRH,PMADRL
INSTR (PC + 1)
BSF PMCON1,RD
Executed Here
PC + 3
PMDATH,PMDATL
PC + 4
INSTR (PC + 3)
INSTR(PC + 2)
INSTR(PC + 1)
Instruction Ignored Instruction Ignored
Forced NOP
Forced NOP
Executed Here
Executed Here
PC + 5
INSTR (PC + 4)
INSTR(PC + 3)
Executed Here
INSTR(PC + 4)
Executed Here
RD bit
PMDATH
PMDATL
Register
EXAMPLE 10-1:
FLASH PROGRAM MEMORY READ
* This code block will read 1 word of program
* memory at the memory address:
PROG_ADDR_HI : PROG_ADDR_LO
*
data will be returned in the variables;
*
PROG_DATA_HI, PROG_DATA_LO
BANKSEL
MOVLW
MOVWF
MOVLW
MOVWF
PMADRL
PROG_ADDR_LO
PMADRL
PROG_ADDR_HI
PMADRH
; Select Bank for PMCON registers
;
; Store LSB of address
;
; Store MSB of address
BCF
BSF
NOP
NOP
PMCON1,CFGS
PMCON1,RD
;
;
;
;
Do not select Configuration Space
Initiate read
Ignored (Figure 10-1)
Ignored (Figure 10-1)
MOVF
MOVWF
MOVF
MOVWF
PMDATL,W
PROG_DATA_LO
PMDATH,W
PROG_DATA_HI
;
;
;
;
Get LSB of word
Store in user location
Get MSB of word
Store in user location
 2014-2015 Microchip Technology Inc.
DS40001775B-page 123
PIC16(L)F1764/5/8/9
10.2.2
FLASH MEMORY UNLOCK
SEQUENCE
The unlock sequence is a mechanism that protects the
Flash program memory from unintended self-write programming or erasing. The sequence must be executed
and completed without interruption to successfully
complete any of the following operations:
• Row Erase
• Load program memory write latches
• Write of program memory write latches to
program memory
• Write of program memory write latches to
User IDs
FIGURE 10-3:
FLASH PROGRAM
MEMORY UNLOCK
SEQUENCE FLOWCHART
Rev. 10-000047A
7/30/2013
Start
Unlock Sequence
Write 0x55 to
PMCON2
The unlock sequence consists of the following steps:
1. Write 55h to PMCON2.
2. Write AAh to PMCON2.
3. Set the WR bit in PMCON1.
4. NOP instruction.
5. NOP instruction.
Once the WR bit is set, the processor will always force
two NOP instructions. When an erase row or program row
operation is being performed, the processor will stall
internal operations (typically 2 ms) until the operation is
complete and then resume with the next instruction.
When the operation is loading the program memory write
latches, the processor will always force the two NOP
instructions and continue uninterrupted with the next
instruction.
Since the unlock sequence must not be interrupted,
global interrupts should be disabled prior to the unlock
sequence and re-enabled after the unlock sequence is
completed.
DS40001775B-page 124
Write 0xAA to
PMCON2
Initiate
Write or Erase operation
(WR = 1)
Instruction fetched ignored
NOP execution forced
Instruction fetched ignored
NOP execution forced
End
Unlock Sequence
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
10.2.3
ERASING FLASH PROGRAM
MEMORY
While executing code, program memory can only be
erased by rows. To erase a row:
1.
2.
3.
4.
5.
Load the PMADRH:PMADRL register pair with
any address within the row to be erased.
Clear the CFGS bit of the PMCON1 register.
Set the FREE and WREN bits of the PMCON1
register.
Write 55h, then AAh, to PMCON2 (Flash
programming unlock sequence).
Set control bit WR of the PMCON1 register to
begin the erase operation.
FIGURE 10-4:
FLASH PROGRAM
MEMORY ERASE
FLOWCHART
Rev. 10-000048A
7/30/2013
Start
Erase Operation
Disable Interrupts
(GIE = 0)
See Example 10-2.
After the “BSF PMCON1,WR” instruction, the processor
requires two cycles to set up the erase operation. The
user must place two NOP instructions immediately following the WR bit set instruction. The processor will
halt internal operations for the typical 2 ms erase time.
This is not Sleep mode as the clocks and peripherals
will continue to run. After the erase cycle, the processor
will resume operation with the third instruction after the
PMCON1 write instruction.
Select
Program or Configuration Memory
(CFGS)
Select Row Address
(PMADRH:PMADRL)
Select Erase Operation
(FREE = 1)
Enable Write/Erase Operation
(WREN = 1)
Unlock Sequence
(See Note 1)
CPU stalls while
Erase operation completes
(2 ms typical)
Disable Write/Erase Operation
(WREN = 0)
Re-enable Interrupts
(GIE = 1)
End
Erase Operation
Note 1: See Figure 10-3.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 125
PIC16(L)F1764/5/8/9
EXAMPLE 10-2:
ERASING ONE ROW OF PROGRAM MEMORY
Required
Sequence
; This row erase routine assumes the following:
; 1. A valid address within the erase row is loaded in ADDRH:ADDRL
; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
BCF
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
BCF
BSF
BSF
INTCON,GIE
PMADRL
ADDRL,W
PMADRL
ADDRH,W
PMADRH
PMCON1,CFGS
PMCON1,FREE
PMCON1,WREN
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
NOP
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
BCF
BSF
DS40001775B-page 126
PMCON1,WREN
INTCON,GIE
; Disable ints so required sequences will execute properly
; Load lower 8 bits of erase address boundary
; Load upper 6 bits of erase address boundary
; Not configuration space
; Specify an erase operation
; Enable writes
;
;
;
;
;
;
;
;
;
;
Start of required sequence to initiate erase
Write 55h
Write AAh
Set WR bit to begin erase
NOP instructions are forced as processor starts
row erase of program memory.
The processor stalls until the erase process is complete
after erase processor continues with 3rd instruction
; Disable writes
; Enable interrupts
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
10.2.4
WRITING TO FLASH PROGRAM
MEMORY
Program memory is programmed using the following
steps:
1.
2.
3.
4.
Load the address in PMADRH:PMADRL of the
row to be programmed.
Load each write latch with data.
Initiate a programming operation.
Repeat Steps 1 through 3 until all data is written.
Before writing to program memory, the word(s) to be
written must be erased or previously unwritten. Program
memory can only be erased one row at a time. No
automatic erase occurs upon the initiation of the write.
Program memory can be written one or more words at
a time. The maximum number of words written at one
time is equal to the number of write latches. See
Figure 10-5 (row writes to program memory with
32 write latches) for more details.
The write latches are aligned to the Flash row
address boundary, defined by the upper ten bits of
PMADRH:PMADRL (PMADRH<6:0>:PMADRL<7:5>),
with the lower five bits of PMADRL (PMADRL<4:0>)
determining the write latch being loaded. Write operations do not cross these boundaries. At the completion
of a program memory write operation, the data in the
write latches is reset to contain 0x3FFF.
The following steps should be completed to load the
write latches and program a row of program memory.
These steps are divided into two parts. First, each write
latch is loaded with data from the PMDATH:PMDATL
using the unlock sequence with LWLO = 1. When the
last word to be loaded into the write latch is ready, the
LWLO bit is cleared and the unlock sequence
executed. This initiates the programming operation,
writing all the latches into Flash program memory.
Note:
The special unlock sequence is required
to load a write latch with data or initiate a
Flash programming operation. If the
unlock sequence is interrupted, writing to
the latches or program memory will not be
initiated.
 2014-2015 Microchip Technology Inc.
1.
2.
3.
Set the WREN bit of the PMCON1 register.
Clear the CFGS bit of the PMCON1 register.
Set the LWLO bit of the PMCON1 register.
When the LWLO bit of the PMCON1 register is
‘1’, the write sequence will only load the write
latches and will not initiate the write to Flash
program memory.
4. Load the PMADRH:PMADRL register pair with
the address of the location to be written.
5. Load the PMDATH:PMDATL register pair with
the program memory data to be written.
6. Execute the unlock sequence (Section 10.2.2
“Flash Memory Unlock Sequence”). The write
latch is now loaded.
7. Increment the PMADRH:PMADRL register pair
to point to the next location.
8. Repeat Steps 5 through 7 until all but the last
write latch has been loaded.
9. Clear the LWLO bit of the PMCON1 register.
When the LWLO bit of the PMCON1 register is
‘0’, the write sequence will initiate the write to
Flash program memory.
10. Load the PMDATH:PMDATL register pair with
the program memory data to be written.
11. Execute the unlock sequence (Section 10.2.2
“Flash Memory Unlock Sequence”). The
entire program memory latch content is now
written to Flash program memory.
Note:
The program memory write latches are
reset to the blank state (0x3FFF) at the
completion of every write or erase
operation. As a result, it is not necessary
to load all the program memory write
latches. Unloaded latches will remain in
the blank state.
An example of the complete write sequence is shown in
Example 10-3. The initial address is loaded into the
PMADRH:PMADRL register pair; the data is loaded
using Indirect Addressing.
DS40001775B-page 127
7
BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES
6
0 7
5 4
PMADRH
-
r9
r8
r7
r6
r5
0
7
PMADRL
r4
r3
r2
r1
r0
c4
c3
c2
c1
-
5
-
0
7
PMDATH
PMDATL
6
c0
Rev. 10-000004A
7/30/2013
0
8
14
Program Memory Write Latches
5
10
14
PMADRL<4:0>
Write Latch #0
00h
14
CFGS = 0
 2014-2015 Microchip Technology Inc.
PMADRH<6:0>:
PMADRL<7:5>
Row
Address
Decode
14
14
14
Write Latch #30
1Eh
Write Latch #1
01h
14
Write Latch #31
1Fh
14
14
Row
Addr
Addr
Addr
Addr
000h
0000h
0001h
001Eh
001Fh
001h
0020h
0021h
003Eh
003Fh
002h
0040h
0041h
005Eh
005Fh
3FEh
7FC0h
7FC1h
7FDEh
7FDFh
3FFh
7FE0h
7FE1h
7FFEh
7FFFh
Flash Program Memory
400h
CFGS = 1
8000h - 8003h
8004h – 8005h
8006h
8007h – 8008h
8009h - 801Fh
USER ID 0 - 3
reserved
DEVICE ID
Dev / Rev
Configuration
Words
reserved
Configuration Memory
PIC16(L)F1764/5/8/9
DS40001775B-page 128
FIGURE 10-5:
PIC16(L)F1764/5/8/9
FIGURE 10-6:
FLASH PROGRAM MEMORY WRITE FLOWCHART
Start
Write Operation
Determine number of words
to be written into Program or
Configuration Memory.
The number of words cannot
exceed the number of words
per row.
(word_cnt)
Disable Interrupts
(GIE = 0)
Select
Program or Config. Memory
(CFGS)
Select Row Address
(PMADRH:PMADRL)
Enable Write/Erase
Operation (WREN = 1)
Load the value to write
(PMDATH:PMDATL)
Update the word counter
(word_cnt--)
Last word to
write ?
Yes
No
Unlock Sequence
(Figure10-3
x-x)
Figure
Select Write Operation
(FREE = 0)
No delay when writing to
Program Memory Latches
Load Write Latches Only
(LWLO = 1)
Increment Address
(PMADRH:PMADRL++)
Write Latches to Flash
(LWLO = 0)
Unlock Sequence
(Figure10-3
x-x)
Figure
CPU stalls while Write
operation completes
(2ms typical)
Disable
Write/Erase Operation
(WREN = 0)
Re-enable Interrupts
(GIE = 1)
End
Write Operation
 2014-2015 Microchip Technology Inc.
DS40001775B-page 129
PIC16(L)F1764/5/8/9
EXAMPLE 10-3:
;
;
;
;
;
;
;
WRITING TO FLASH PROGRAM MEMORY
This write routine assumes the following:
1. 64 bytes of data are loaded, starting at the address in DATA_ADDR
2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,
stored in little endian format
3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL
4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
BCF
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BSF
BSF
INTCON,GIE
PMADRH
ADDRH,W
PMADRH
ADDRL,W
PMADRL
LOW DATA_ADDR
FSR0L
HIGH DATA_ADDR
FSR0H
PMCON1,CFGS
PMCON1,WREN
PMCON1,LWLO
;
;
;
;
;
;
;
;
;
;
;
;
;
Disable ints so required sequences will execute properly
Bank 3
Load initial address
MOVIW
MOVWF
MOVIW
MOVWF
FSR0++
PMDATL
FSR0++
PMDATH
; Load first data byte into lower
;
; Load second data byte into upper
;
MOVF
XORLW
ANDLW
BTFSC
GOTO
PMADRL,W
0x1F
0x1F
STATUS,Z
START_WRITE
; Check if lower bits of address are '00000'
; Check if we're on the last of 32 addresses
;
; Exit if last of 32 words,
;
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
;
;
;
;
;
;
;
;
PMADRL,F
LOOP
; Still loading latches Increment address
; Write next latches
PMCON1,LWLO
; No more loading latches - Actually start Flash program
; memory write
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
;
;
;
;
;
;
;
;
;
;
;
;
;
Load initial data address
Load initial data address
Not configuration space
Enable writes
Only Load Write Latches
Required
Sequence
LOOP
NOP
INCF
GOTO
Required
Sequence
START_WRITE
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
NOP
BCF
BSF
DS40001775B-page 130
PMCON1,WREN
INTCON,GIE
Start of required write sequence:
Write 55h
Write AAh
Set WR bit to begin write
NOP instructions are forced as processor
loads program memory write latches
Start of required write sequence:
Write 55h
Write AAh
Set WR bit to begin write
NOP instructions are forced as processor writes
all the program memory write latches simultaneously
to program memory.
After NOPs, the processor
stalls until the self-write process in complete
after write processor continues with 3rd instruction
Disable writes
Enable interrupts
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
10.3
Modifying Flash Program Memory
When modifying existing data in a program memory
row, and data within that row must be preserved, it must
first be read and saved in a RAM image. Program
memory is modified using the following steps:
1.
2.
3.
4.
5.
6.
7.
Load the starting address of the row to be
modified.
Read the existing data from the row into a RAM
image.
Modify the RAM image to contain the new data
to be written into program memory.
Load the starting address of the row to be
rewritten.
Erase the program memory row.
Load the write latches with data from the RAM
image.
Initiate a programming operation.
FIGURE 10-7:
FLASH PROGRAM
MEMORY MODIFY
FLOWCHART
Rev. 10-000050A
7/30/2013
Start
Modify Operation
Read Operation
(See Note 1)
An image of the entire row
read must be stored in RAM
Modify Image
The words to be modified are
changed in the RAM image
Erase Operation
(See Note 2)
Write Operation
Use RAM image
(See Note 3)
End
Modify Operation
Note 1: See Figure 10-1.
2: See Figure 10-4.
3: See Figure 10-6.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 131
PIC16(L)F1764/5/8/9
10.4
User ID, Device ID and
Configuration Word Access
When read access is initiated on an address outside the
parameters listed in Table 10-2, the PMDATH:PMDATL
register pair is cleared, reading back ‘0’s.
Instead of accessing program memory, the User IDs,
Device ID/Revision ID and Configuration Words can be
accessed when CFGS = 1 in the PMCON1 register.
This is the region that would be pointed to by
PC<15> = 1, but not all addresses are accessible.
Different access may exist for reads and writes. Refer
to Table 10-2.
TABLE 10-2:
USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1)
Address
Function
Read Access
Write Access
8000h-8003h
User IDs
Yes
Yes
8005h-8006h
Device ID/Revision ID
Yes
No
8007h-8008h
Configuration Words 1 and 2
Yes
No
EXAMPLE 10-4:
CONFIGURATION WORD AND DEVICE ID ACCESS
* This code block will read 1 word of program memory at the memory address:
*
PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;
*
PROG_DATA_HI, PROG_DATA_LO
BANKSEL
MOVLW
MOVWF
CLRF
PMADRL
PROG_ADDR_LO
PMADRL
PMADRH
; Select correct Bank
;
; Store LSB of address
; Clear MSB of address
BSF
BCF
BSF
NOP
NOP
BSF
PMCON1,CFGS
INTCON,GIE
PMCON1,RD
INTCON,GIE
;
;
;
;
;
;
Select Configuration Space
Disable interrupts
Initiate read
Executed (See Figure 10-2)
Ignored (See Figure 10-2)
Restore interrupts
MOVF
MOVWF
MOVF
MOVWF
PMDATL,W
PROG_DATA_LO
PMDATH,W
PROG_DATA_HI
;
;
;
;
Get LSB of word
Store in user location
Get MSB of word
Store in user location
DS40001775B-page 132
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
10.5
Write/Verify
It is considered good programming practice to verify that
program memory writes agree with the intended value.
Since program memory is stored as a full page then the
stored program memory contents are compared with the
intended data stored in RAM after the last write is
complete.
FIGURE 10-8:
FLASH PROGRAM
MEMORY VERIFY
FLOWCHART
Rev. 10-000051A
7/30/2013
Start
Verify Operation
This routine assumes that the last
row of data written was from an
image saved on RAM. This image
will be used to verify the data
currently stored in Flash Program
Memory
Read Operation
(See Note 1)
PMDAT =
RAM image ?
No
Yes
Fail
Verify Operation
No
Last word ?
Yes
End
Verify Operation
Note 1: See Figure 10-1.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 133
PIC16(L)F1764/5/8/9
10.6
Register Definitions: Flash Program Memory Control
REGISTER 10-1:
R/W-x/u
PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PMDAT<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
PMDAT<7:0>: Read/Write Value for Least Significant bits of Program Memory bits
REGISTER 10-2:
PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER
U-0
U-0
—
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PMDAT<13:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
PMDAT<13:8>: Read/Write Value for Most Significant bits of Program Memory bits
DS40001775B-page 134
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
REGISTER 10-3:
R/W-0/0
PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PMADR<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
PMADR<7:0>: Specifies the Least Significant bits for Program Memory Address bits
REGISTER 10-4:
U-1
PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
—(1)
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PMADR<14:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
Unimplemented: Read as ‘1’
bit 6-0
PMADR<14:8>: Specifies the Most Significant bits for Program Memory Address bits
Note 1:
Unimplemented, read as ‘1’.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 135
PIC16(L)F1764/5/8/9
REGISTER 10-5:
U-1
PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER
R/W-0/0
(1)
—
CFGS
R/W-0/0
R/W/HC-0/0 R/W/HC-x/q(2)
(3)
LWLO
FREE
WRERR
R/W-0/0
R/S/HC-0/0
R/S/HC-0/0
WREN
WR
RD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
S = Settable Only bit
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HC = Hardware Clearable bit
bit 7
Unimplemented: Read as ‘1’
bit 6
CFGS: Configuration Select bit
1 = Accesses Configuration, User ID and Device ID registers
0 = Accesses Flash program memory
bit 5
LWLO: Load Write Latches Only bit(3)
1 = Only the addressed program memory write latch is loaded/updated on the next WR command
0 = The addressed program memory write latch is loaded/updated and a write of all program memory
write latches will be initiated on the next WR command
bit 4
FREE: Program Flash Erase Enable bit
1 = Performs an erase operation on the next WR command (hardware cleared upon completion)
0 = Performs a write operation on the next WR command
bit 3
WRERR: Program/Erase Error Flag bit(2)
1 = Condition indicates an improper program or erase sequence attempt, or termination (bit is set
automatically on any set attempt (writes ‘1’) of the WR bit)
0 = The program or erase operation completed normally
bit 2
WREN: Program/Erase Enable bit
1 = Allows program/erase cycles
0 = Inhibits programming/erasing of program Flash
bit 1
WR: Write Control bit
1 = Initiates a Flash program/erase operation
The operation is self-timed and the bit is cleared by hardware once operation is complete.
The WR bit can only be set (not cleared) in software.
0 = Program/erase operation to the Flash is complete and inactive
bit 0
RD: Read Control bit
1 = Initiates a program Flash read
Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software.
0 = Does not initiate a program Flash read
Note 1:
2:
3:
Unimplemented bit, read as ‘1’.
The WRERR bit is automatically set by hardware when a program memory write or erase operation is
started (WR = 1).
The LWLO bit is ignored during a program memory erase operation (FREE = 1).
DS40001775B-page 136
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
REGISTER 10-6:
W-0/0
PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
Program Memory Control Register 2
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
S = Bit can only be set
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
Program Memory Control 2: Flash Memory Unlock Pattern bits
To unlock writes, 55h must be written first, followed by AAh, before setting the WR bit of the PMCON1
register. The value written to this register is used to unlock the writes. There are specific timing
requirements on these writes.
TABLE 10-3:
SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
104
PMCON1
—(1)
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
136
PMCON2
Program Memory Control Register 2
PMADRL
PMADRH
137
PMADRL<7:0>
—(1)
135
PMADRH<6:0>
PMDATL
135
PMDATL<7:0>
—
PMDATH
—
134
PMDATH<5:0>
134
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.
Note 1: Unimplemented, read as ‘1’.
TABLE 10-4:
Name
CONFIG1
CONFIG2
SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
13:8
—
—
FCMEN
IESO
CLKOUTEN
7:0
CP
MCLRE PWRTE
Bit 10/2
Bit 9/1
Bit 8/0
BOREN<1:0>
WDTE<1:0>
—
FOSC<2:0>
13:8
—
—
LVP
DEBUG
LPBOR
BORV
7:0
ZCD
—
—
—
—
PPS1WAY
STVREN
PLLEN
Register
on Page
64
66
WRT<1:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 137
PIC16(L)F1764/5/8/9
NOTES:
DS40001775B-page 138
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
11.0
I/O PORTS
FIGURE 11-1:
GENERIC I/O PORT
OPERATION
Each port has six standard registers for its operation.
These registers are:
Rev. 10-000052A
7/30/2013
• TRISx registers (Data Direction)
• PORTx registers (reads the levels on the pins of
the device)
• LATx registers (Output Latch)
• INLVLx (Input Level Control)
• ODCONx registers (Open-Drain)
• SLRCONx registers (Slew Rate
Read LATx
TRISx
D
Q
Write LATx
Write PORTx
VDD
CK
Some ports may have one or more of the following
additional registers. These registers are:
Data Register
Data bus
• ANSELx (Analog Select)
• WPUx (Weak Pull-up)
I/O pin
Read PORTx
In general, when a peripheral is enabled on a port pin,
that pin cannot be used as a general purpose output.
However, the pin can still be read.
To digital peripherals
ANSELx
To analog peripherals
PORT AVAILABILITY PER
DEVICE
PIC16(L)F1764
●
●
PIC16(L)F1765
●
●
PIC16(L)F1768
●
●
●
PIC16(L)F1769
●
●
●
PORTA is a 6-bit wide, bidirectional port. The
corresponding Data Direction register is TRISA
(Register 11-2). Setting a TRISA bit (= 1) will make the
corresponding PORTA pin an input (i.e., disables the
output driver). Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., enables the
output driver and puts the contents of the output latch
on the selected pin). The exception is RA3, which is
input-only and its TRISA bit will always read as ‘1’.
Example 11-1 shows how to initialize PORTA.
PORTA
PORTC
VSS
11.1
Device
PORTB
TABLE 11-1:
The Data Latch (LATx registers) is useful for
Read-Modify-Write operations on the value that the I/O
pins are driving.
A write operation to the LATx register has the same
effect as a write to the corresponding PORTx register.
A read of the LATx register reads the values held in the
I/O PORT latches, while a read of the PORTx register
reads the actual I/O pin value.
Ports that support analog inputs have an associated
ANSELx register. When an ANSEL bit is set, the digital
input buffer associated with that bit is disabled.
Disabling the input buffer prevents analog signal levels
on the pin between a logic high and low from causing
excessive current in the logic input circuitry. A
simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 11-1.
 2014-2015 Microchip Technology Inc.
11.1.1
PORTA Registers
DATA REGISTER
Reading the PORTA register (Register 11-1) reads the
status of the pins, whereas writing to it, will write to the
PORT latch. All write operations are Read-Modify-Write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORTA Data Latch (LATA).
11.1.2
DIRECTION CONTROL
The TRISA register (Register 11-2) controls the
PORTA pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits
in the TRISA register are maintained set when using
them as analog inputs. I/O pins configured as analog
inputs always read ‘0’.
DS40001775B-page 139
PIC16(L)F1764/5/8/9
11.1.3
OPEN-DRAIN CONTROL
The ODCONA register (Register 11-6) controls the
open-drain feature of the port. Open-drain operation is
independently selected for each pin. When an
ODCONA bit is set, the corresponding port output
becomes an open-drain driver, capable of sinking
current only. When an ODCONA bit is cleared, the
corresponding port output pin is the standard push-pull
drive capable of sourcing and sinking current.
11.1.4
INPUT THRESHOLD CONTROL
The INLVLA register (Register 11-8) controls the input
voltage threshold for each of the available PORTA input
pins. A selection between the Schmitt Trigger CMOS or
the TTL compatible thresholds is available. The input
threshold is important in determining the value of a read
of the PORTA register and also the level at which an
Interrupt-On-Change occurs, if that feature is enabled.
See Table 36-4 for more information on threshold levels.
Note:
11.1.6
Note:
SLEW RATE CONTROL
The SLRCONA register (Register 11-7) controls the
slew rate option for each port pin. Slew rate control is
independently selectable for each port pin. When an
SLRCONA bit is set, the corresponding port pin drive is
slew rate limited. When an SLRCONA bit is cleared,
the corresponding port pin drive slews at the maximum
rate possible.
11.1.5
The state of the ANSELA bits has no effect on digital output functions. A pin with TRISx clear and ANSELx set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing Read-Modify-Write instructions on the
affected port.
The ANSELA bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSELA bits
must be initialized to ‘0’ by user software.
EXAMPLE 11-1:
;
;
;
;
INITIALIZING PORTA
This code example illustrates
initializing the PORTA register. The
other ports are initialized in the same
manner.
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
PORTA
PORTA
LATA
LATA
ANSELA
ANSELA
TRISA
B'00111000'
TRISA
;
;Init PORTA
;Data Latch
;
;
;digital I/O
;
;Set RA<5:3> as inputs
;and set RA<2:0> as
;outputs
Changing the input threshold selection
should be performed while all peripheral
modules are disabled. Changing the threshold level during the time a module is active
may inadvertently generate a transition
associated with an input pin, regardless of
the actual voltage level on that pin.
11.1.7
ANALOG CONTROL
Analog input functions, such as the ADC and
comparator inputs, are not shown in the Peripheral Pin
Select lists. These inputs are active when the I/O pin is
set for Analog mode using the ANSELA register. Digital
output functions may continue to control the pin when it
is in Analog mode.
The ANSELA register (Register 11-4) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELA bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
DS40001775B-page 140
PORTA FUNCTIONS AND OUTPUT
PRIORITIES
Each PORTA pin is multiplexed with other functions.
Each pin defaults to the PORT latch data after Reset.
Other functions are selected with the Peripheral Pin
Select (PPS) logic. See Section 12.0 “Peripheral Pin
Select (PPS) Module” for more information.
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
11.2
Register Definitions: PORTA
REGISTER 11-1:
U-0
PORTA: PORTA REGISTER
U-0
—
R/W-x/x
R/W-x/x
R-x/x
—
R/W-x/x
RA<5:0>
R/W-x/x
R/W-x/x
(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RA<5:0>: PORTA I/O Value bits(1)
1 = Port pin is > VIH
0 = Port pin is < VIL
Note 1:
Writes to PORTA are actually written to the corresponding LATA register. Reads from PORTA are the
return of actual I/O pin values.
REGISTER 11-2:
TRISA: PORTA TRI-STATE REGISTER
U-0
U-0
—
—
R/W-1/1
R/W-1/1
TRISA<5:4>
U-1
—(1)
R/W-1/1
R/W-1/1
R/W-1/1
TRISA<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
TRISA<5:4>: PORTA Tri-State Control bit
1 = PORTA pin is configured as an input (tri-stated)
0 = PORTA pin is configured as an output
bit 3
Unimplemented: Read as ‘1’(1)
bit 2-0
TRISA<2:0>: PORTA Tri-State Control bit
1 = PORTA pin is configured as an input (tri-stated)
0 = PORTA pin is configured as an output
Note 1:
Unimplemented, read as ‘1’.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 141
PIC16(L)F1764/5/8/9
REGISTER 11-3:
LATA: PORTA DATA LATCH REGISTER
U-0
U-0
—
—
R/W-x/u
R/W-x/u
U-0
LATA<5:4>(1)
R/W-x/u
R/W-x/u
R/W-x/u
LATA<2:0>(1)
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
LATA<5:4>: RA<5:4> Output Latch Value bits(1)
bit 3
Unimplemented: Read as ‘0’
bit 2-0
LATA<2:0>: RA<2:0> Output Latch Value bits(1)
Note 1:
Writes to PORTA are actually written to the corresponding LATA register. Reads from PORTA are the
return of actual I/O pin values.
REGISTER 11-4:
ANSELA: PORTA ANALOG SELECT REGISTER
U-0
U-0
U-0
R/W-1/1
U-0
—
—
—
ANSA4
—
R/W-1/1
R/W-1/1
R/W-1/1
ANSA<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-5
Unimplemented: Read as ‘0’
bit 4
ANSA4: Analog Select Between Analog or Digital Function on RA4 Pin bit
1 = Analog input; pin is assigned as an analog input, digital input buffer is disabled(1)
0 = Digital I/O; pin is assigned to port or digital special function
bit 3
Unimplemented: Read as ‘0’
bit 2-0
ANSA<2:0>: Analog Select Between Analog or Digital Function on RA<2:0> Pins bits
1 = Analog input; pin is assigned as an analog input, digital input buffer is disabled(1)
0 = Digital I/O; pin is assigned to port or digital special function
Note 1:
When setting a pin to an analog input, the corresponding TRISx bit must be set to Input mode in order to
allow external control of the voltage on the pin.
DS40001775B-page 142
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
REGISTER 11-5:
WPUA: WEAK PULL-UP PORTA REGISTER
U-0
U-0
—
—
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
WPUA<5:0>(1,2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
WPUA<5:0>: Weak Pull-up PORTA Register bits(1,2)
1 = Pull-up is enabled
0 = Pull-up is disabled
Note 1:
2:
The global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is configured as an output.
REGISTER 11-6:
ODCONA: PORTA OPEN-DRAIN CONTROL REGISTER
U-0
U-0
—
—
R/W-0/0
R/W-0/0
ODA<5:4>
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
ODA<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
ODA<5:4>: PORTA Open-Drain Enable bits
For RA<5:4> Pins:
1 = Port pins operate as open-drain drive (sink current only)
0 = Port pins operate as standard push-pull drive (source and sink current)
bit 3
Unimplemented: Read as ‘0’
bit 2-0
ODA<2:0>: PORTA Open-Drain Enable bits
For RA<2:0> Pins:
1 = Port pins operate as open-drain drive (sink current only)
0 = Port pins operate as standard push-pull drive (source and sink current)
 2014-2015 Microchip Technology Inc.
DS40001775B-page 143
PIC16(L)F1764/5/8/9
REGISTER 11-7:
SLRCONA: PORTA SLEW RATE CONTROL REGISTER
U-0
U-0
—
—
R/W-1/1
R/W-1/1
U-0
SLRA<5:4>
R/W-1/1
—
R/W-1/1
R/W-1/1
SLRA<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
SLRA<5:4>: PORTA Slew Rate Enable bits
For RA<5:4> Pins:
1 = Port pin slew rate is limited
0 = Port pin slews at maximum rate
bit 3
Unimplemented: Read as ‘0’
bit 2-0
SLRA<2:0>: PORTA Slew Rate Enable bits
For RA<2:0> Pins:
1 = Port pin slew rate is limited
0 = Port pin slews at maximum rate
REGISTER 11-8:
INLVLA: PORTA INPUT LEVEL CONTROL REGISTER
U-0
U-0
—
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
INLVLA<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
INLVLA<5:0>: PORTA Input Level Select bits
For RA<5:0> Pins:
1 = Port pin digital input operates with ST thresholds
0 = Port pin digital input operates with TTL thresholds
DS40001775B-page 144
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
TABLE 11-2:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
ANSELA
—
—
—
ANSA4
—
INLVLA
—
—
LATA
—
—
LATA<5:4>
ODCONA
—
—
ODA<5:4>
OPTION_REG WPUEN
Bit 2
Bit 1
Bit 0
ANSA<2:0>
142
—
LATA<2:0>
142
—
ODA<2:0>
143
PS<2:0>
221
INLVLA<5:0>
INTEDG TMR0CS TMR0SE
Register
on Page
144
PSA
PORTA
—
—
RA<5:0>
SLRCONA
—
—
SLRA<5:4>
—
SLRA<2:0>
144
141
TRISA
—
—
TRISA<5:4>
—(1)
TRISA<2:0>
141
WPUA
—
—
WPUA<5:0>
143
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.
Note 1: Unimplemented, read as ‘1’.
TABLE 11-3:
Name
CONFIG1
SUMMARY OF CONFIGURATION WORD WITH PORTA
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
13:8
—
—
FCMEN
IESO
CLKOUTEN
7:0
CP
MCLRE
PWRTE
WDTE<1:0>
Bit 10/2
Bit 9/1
Bit 8/0
BOREN<1:0>
—
FOSC<2:0>
Register
on Page
64
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 145
PIC16(L)F1764/5/8/9
11.3
11.3.1
PORTB Registers
(PIC16(L)F1768/9 only)
DATA REGISTER
PORTB is a 4-bit wide, bidirectional port. The
corresponding Data Direction register is TRISB
(Register 11-10). Setting a TRISB bit (= 1) will make
the corresponding PORTB pin an input (i.e., put the
corresponding output driver in a High-Impedance
mode). Clearing a TRISB bit (= 0) will make the
corresponding PORTB pin an output (i.e., enable the
output driver and put the contents of the output latch on
the selected pin). Example 11-1 shows how to initialize
an I/O port.
Reading the PORTB register (Register 11-9) reads the
status of the pins, whereas writing to it, will write to the
PORT latch. All write operations are Read-Modify-Write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORTB Data Latch (LATB).
11.3.2
DIRECTION CONTROL
The TRISB register (Register 11-10) controls the
PORTB pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits in
the TRISB register are maintained set when using them
as analog inputs. I/O pins configured as analog inputs
always read ‘0’.
11.3.3
OPEN-DRAIN CONTROL
The ODCONB register (Register 11-14) controls the
open-drain feature of the port. Open-drain operation is
independently selected for each pin. When an
ODCONB bit is set, the corresponding port output
becomes an open-drain driver, capable of sinking
current only. When an ODCONB bit is cleared, the
corresponding port output pin is the standard push-pull
drive, capable of sourcing and sinking current.
11.3.4
SLEW RATE CONTROL
The SLRCONB register (Register 11-15) controls the
slew rate option for each port pin. Slew rate control is
independently selectable for each port pin. When an
SLRCONB bit is set, the corresponding port pin drive is
slew rate limited. When an SLRCONB bit is cleared,
the corresponding port pin drive slews at the maximum
rate possible.
DS40001775B-page 146
11.3.5
INPUT THRESHOLD CONTROL
The INLVLB register (Register 11-16) controls the input
voltage threshold for each of the available PORTB input
pins. A selection between the Schmitt Trigger CMOS or
the TTL compatible thresholds is available. The input
threshold is important in determining the value of a read
of the PORTB register and also the level at which an
Interrupt-On-Change occurs, if that feature is enabled.
See Table 36-4 for more information on threshold
levels.
Note:
11.3.6
Changing the input threshold selection
should be performed while all peripheral
modules are disabled. Changing the
threshold level during the time a module is
active may inadvertently generate a
transition associated with an input pin,
regardless of the actual voltage level on
that pin.
ANALOG CONTROL
The ANSELB register (Register 11-12) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELB bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELB bits has no effect on digital output functions. A pin with TRIS clear and the ANSELB bit
set will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing Read-Modify-Write instructions on the
affected port.
Note:
11.3.7
The ANSELB bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSELx bits
must be initialized to ‘0’ by user software.
PORTB FUNCTIONS AND OUTPUT
PRIORITIES
Each pin defaults to the PORT latch data after Reset.
Other functions are selected with the Peripheral Pin
Select logic. See Section 12.0 “Peripheral Pin Select
(PPS) Module” for more information. Analog input
functions, such as ADC and op amp inputs, are not
shown in the Peripheral Pin Select lists. These inputs
are active when the I/O pin is set for Analog mode using
the ANSELB register. Digital output functions may
continue to control the pin when it is in Analog mode.
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
11.4
Register Definitions: PORTB
REGISTER 11-9:
R/W-x/u
PORTB: PORTB REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
RB<7:4>(1)
U-0
U-0
U-0
U-0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
RB<7:4>: PORTB General Purpose I/O Pin bits(1)
1 = Port pin is > VIH
0 = Port pin is < VIL
bit 3-0
Unimplemented: Read as ‘0’
Note 1:
Writes to PORTB are actually written to the corresponding LATB register. Reads from PORTB register are
the return of the actual I/O pin values.
REGISTER 11-10: TRISB: PORTB TRI-STATE REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
TRISB<7:4>
U-0
U-0
U-0
U-0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
TRISB<7:4>: PORTB Tri-State Control bits
1 = PORTB pin is configured as an input (tri-stated)
0 = PORTB pin is configured as an output
bit 3-0
Unimplemented: Read as ‘0’
 2014-2015 Microchip Technology Inc.
DS40001775B-page 147
PIC16(L)F1764/5/8/9
REGISTER 11-11: LATB: PORTB DATA LATCH REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LATB<7:4>(1)
U-0
U-0
U-0
U-0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
LATB<7:4>: PORTB Output Latch Value bits(1)
bit 3-0
Unimplemented: Read as ‘0’
Note 1:
Writes to PORTB are actually written to the corresponding LATB register. Reads from PORTB register are
the return of the actual I/O pin values.
REGISTER 11-12: ANSELB: PORTB ANALOG SELECT REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
ANSB<7:4>
U-0
U-0
U-0
U-0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
ANSB<7:4>: Analog Select Between Analog or Digital Function on RB<7:4> Pins bits
1 = Analog input; pin is assigned as an analog input, digital input buffer is disabled(1)
0 = Digital I/O; pin is assigned to port or digital special function
bit 3-0
Unimplemented: Read as ‘0’
Note 1:
When setting a pin to an analog input, the corresponding TRISx bit must be set to Input mode in order to
allow external control of the voltage on the pin.
DS40001775B-page 148
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
REGISTER 11-13: WPUB: WEAK PULL-UP PORTB REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
WPUB<7:4>(1,2)
U-0
U-0
U-0
U-0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
WPUB<7:4>: Weak Pull-up PORTB Register bits(1,2)
1 = Pull-up is enabled
0 = Pull-up is disabled
bit 3-0
Unimplemented: Read as ‘0’
Note 1:
2:
The global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is configured as an output.
REGISTER 11-14: ODCONB: PORTB OPEN-DRAIN CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ODB<7:4>
U-0
U-0
U-0
U-0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
ODB<7:4>: PORTB Open-Drain Enable bits
For RB<7:4> Pins:
1 = Port pin operates as an open-drain drive (sink current only)
0 = Port pin operates as a standard push-pull drive (source and sink current)
bit 3-0
Unimplemented: Read as ‘0’
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REGISTER 11-15: SLRCONB: PORTB SLEW RATE CONTROL REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
SLRB<7:4>
U-0
U-0
U-0
U-0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
SLRB<7:4>: PORTB Slew Rate Enable bits
For RB<7:4> Pins:
1 = Port pin slew rate is limited
0 = Port pin slews at maximum rate
bit 3-0
Unimplemented: Read as ‘0’
REGISTER 11-16: INLVLB: PORTB INPUT LEVEL CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
INLVLB<7:4>
U-0
U-0
U-0
U-0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
INLVLB<7:4>: PORTB Input Level Select bits
For RB<7:4> Pins:
1 = Port pin digital input operates with ST thresholds
0 = Port pin digital input operates with TTL thresholds
bit 3-0
Unimplemented: Read as ‘0’
TABLE 11-4:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSB<7:4>
—
—
—
—
148
INLVLB<7:4>
—
—
—
—
150
LATB
LATB<7:4>
—
—
—
—
148
ODCONB
ODB<7:4>
—
—
—
—
149
ANSELB
INLVLB
RB<7:4>
—
—
—
—
147
SLRB<7:4>
—
—
—
—
150
TRISB
TRISB<7:4>
—
—
—
—
150
WPUB
WPUB<7:4>
—
—
—
—
149
PORTB
SLRCONB
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by PORTB.
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11.5
11.5.1
PORTC Registers
DATA REGISTER
PORTC is a 6-bit wide bidirectional port in the
PIC16(L)F1764/5 devices and 8-bit wide bidirectional
port in the PIC16(L)F1768/9 devices. The corresponding
Data Direction register is TRISC (Register 11-18).
Setting a TRISC bit (= 1) will make the corresponding
PORTC pin an input (i.e., put the corresponding output
driver in a High-Impedance mode). Clearing a TRISC bit
(= 0) will make the corresponding PORTC pin an output
(i.e., enable the output driver and put the contents of the
output latch on the selected pin). Example 11-1 shows
how to initialize an I/O port.
Reading the PORTC register (Register 11-17) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are Read-Modify-Write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORTC Data Latch (LATC).
11.5.2
DIRECTION CONTROL
The TRISC register (Register 11-18) controls the
PORTC pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits in
the TRISC register are maintained set when using them
as analog inputs. I/O pins configured as analog inputs
always read ‘0’.
11.5.3
INPUT THRESHOLD CONTROL
The INLVLC register (Register 11-24) controls the input
voltage threshold for each of the available PORTC
input pins. A selection between the Schmitt Trigger
CMOS or the TTL compatible thresholds is available.
The input threshold is important in determining the
value of a read of the PORTC register and also the
level at which an Interrupt-On-Change occurs, if that
feature is enabled. See Table 36-4 for more information
on threshold levels.
Note:
Changing the input threshold selection
should be performed while all peripheral
modules are disabled. Changing the
threshold level during the time a module is
active may inadvertently generate a
transition associated with an input pin,
regardless of the actual voltage level on
that pin.
11.5.4
OPEN-DRAIN CONTROL
The ODCONC register (Register 11-22) controls the
open-drain feature of the port. Open-drain operation is
independently selected for each pin. When an
ODCONC bit is set, the corresponding port output
becomes an open-drain driver capable of sinking
current only. When an ODCONC bit is cleared, the
corresponding port output pin is the standard push-pull
drive capable of sourcing and sinking current.
11.5.5
SLEW RATE CONTROL
The SLRCONC register (Register 11-23) controls the
slew rate option for each port pin. Slew rate control is
independently selectable for each port pin. When an
SLRCONC bit is set, the corresponding port pin drive is
slew rate limited. When an SLRCONC bit is cleared,
the corresponding port pin drive slews at the maximum
rate possible.
11.5.6
ANALOG CONTROL
The ANSELC register (Register 11-20) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELC bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELC bits has no effect on digital output functions. A pin with TRISx clear and ANSELC set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing Read-Modify-Write instructions on the
affected port.
Note:
11.5.7
The ANSELC bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSELx bits
must be initialized to ‘0’ by user software.
PORTC FUNCTIONS AND OUTPUT
PRIORITIES
Each pin defaults to the PORT latch data after Reset.
Other functions are selected with the Peripheral Pin
Select logic. See Section 12.0 “Peripheral Pin Select
(PPS) Module” for more information.
Analog input functions, such as ADC and comparator
inputs, are not shown in the Peripheral Pin Select lists.
These inputs are active when the I/O pin is set for
Analog mode using the ANSELC register. Digital output
functions may continue to control the pin when it is in
Analog mode.
11.5.8
HIGH-CURRENT DRIVE CONTROL
The output drivers on RC4 and RC5 are capable of
sourcing and sinking up to 100 mA. This extra drive
capacity can be enabled and disabled with the control
bits in the HIDRVC register (Register 11-25).
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11.6
Register Definitions: PORTC
REGISTER 11-17: PORTC: PORTC REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
RC<7:0>(1,2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
RC<7:0>: PORTC General Purpose I/O Pin bits(1,2)
1 = Port pin is > VIH
0 = Port pin is < VIL
bit 7-0
Note 1:
2:
Writes to PORTC are actually written to corresponding LATC register. Reads from the PORTC register are
the return of actual I/O pin values.
RC<7:6> are available on PIC16(L)F1768/9 only.
REGISTER 11-18: TRISC: PORTC TRI-STATE REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
TRISC<7:0>(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
Note 1:
TRISC<7:0>: PORTC Tri-State Control bits(1)
1 = PORTC pin is configured as an input (tri-stated)
0 = PORTC pin is configured as an output
TRISC<7:6> are available on PIC16(L)F1768/9 only.
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REGISTER 11-19: LATC: PORTC DATA LATCH REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LATC<7:0>(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
LATC<7:0>: PORTC Output Latch Value bits(1)
bit 7-0
Note 1:
LATC<7:6> are available on PIC16(L)F1768/9 only.
REGISTER 11-20: ANSELC: PORTC ANALOG SELECT REGISTER
R/W-1/1
R/W-1/1
U-0
U-0
—
—
ANSC<7:6>(2)
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
ANSC<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
ANSC<7:6>: Analog Select Between Analog or Digital Function on RC<7:6> Pins bits(2)
1 = Analog input; pin is assigned as an analog input, digital input buffer is disabled(1)
0 = Digital I/O; pin is assigned to port or digital special function
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
ANSC<3:0>: Analog Select Between Analog or Digital Function on RC<3:0> Pins bits
1 = Analog input; pin is assigned as an analog input, digital input buffer is disabled(1)
0 = Digital I/O; pin is assigned to port or digital special function
Note 1:
2:
When setting a pin to an analog input, the corresponding TRISx bit must be set to Input mode in order to
allow external control of the voltage on the pin.
ANSC<7:6> are available on PIC16(L)F1768/9 only.
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REGISTER 11-21: WPUC: WEAK PULL-UP PORTC REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
WPUC<7:0>(1,2,3)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
WPUC<7:0>: Weak Pull-up PORTC Register bits(1,2,3)
1 = Pull-up is enabled
0 = Pull-up is disabled
bit 7-0
Note 1:
2:
3:
The global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is configured as an output.
WPUC<7:6> are available on PIC16(L)F1768/9 only.
REGISTER 11-22: ODCONC: PORTC OPEN-DRAIN CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
(1)
ODC<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
Note 1:
ODC<7:0>: PORTC Open-Drain Enable bits(1)
For RC<7:0> Pins:
1 = Port pin operates as an open-drain drive (sink current only)
0 = Port pin operates as a standard push-pull drive (source and sink current)
ODC<7:6> are available on PIC16(L)F1768/9 only.
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REGISTER 11-23: SLRCONC: PORTC SLEW RATE CONTROL REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
SLRC<7:0>(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
SLRC<7:0>: PORTC Slew Rate Enable bits(1)
For RC<7:0> Pins:
1 = Port pin slew rate is limited
0 = Port pin slews at maximum rate
bit 7-0
Note 1:
SLRC<7:6> are available on PIC16(L)F1768/9 only.
REGISTER 11-24: INLVLC: PORTC INPUT LEVEL CONTROL REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
INLVLC>7:0>(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
Note 1:
INLVLC<7:0>: PORTC Input Level Select bits(1)
For RC<7:0> Pins:
1 = Port pin digital input operates with ST thresholds
0 = Port pin digital input operates with TTL thresholds
INLVLC<7:6> are available on PIC16(L)F1768/9 only.
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REGISTER 11-25: HIDRVC: PORTC HIGH DRIVE CONTROL REGISTER
U-0
U-0
—
—
R/W-0/0
R/W-0/0
HIDC<5:4>
U-0
U-0
U-0
U-0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
HIDC<5:4>: PORTC High Drive Enable bits
For RC<5:4> Pins:
1 = High-current source and sink are enabled
0 = Standard current source and sink
bit 3-0
Unimplemented: Read as ‘0’
TABLE 11-5:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7
Bit 6
ANSELC
ANSC<7:6>(1)
HIDRVC
—
—
Bit 5
Bit 4
—
—
Bit 3
Bit 2
—
—
Bit 1
Bit 0
Register
on Page
—
156
ANSC<3:0>
HIDC<5:4>
—
153
INLVLC<7:0>(1)
155
LATC
LATC<7:0>(1)
153
ODCONC
ODC<7:0>(1)
154
RC<7:0>(1)
152
SLRC<7:0>(1)
155
INLVLC
PORTC
SLRCONC
TRISC
TRISC<7:0>
(1)
152
WPUC
WPUC<7:0>(1)
154
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by PORTC.
Note 1: Bits<7:6> are available on PIC16(L)F1768/9 only.
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12.0
PERIPHERAL PIN SELECT
(PPS) MODULE
The Peripheral Pin Select (PPS) module connects
peripheral inputs and outputs to the device I/O pins. Only
digital signals are included in the selections. All analog
inputs and outputs remain fixed to their assigned pins.
Input and output selections are independent, as shown
in the simplified block diagram (Figure 12-1).
The peripheral input is selected with the xxxPPS register
(Register 12-1) and the peripheral output is selected
with the RxyPPS register (Register 12-2). For example,
to select PORTB, bit 7 (RB7) as the EUSART RX input,
set RxyPPS<4:0> to ‘01111” and to select PORTB, bit 6
(RB6) as the TX output, set RxyPPS<4:0> to ‘10110’.
12.2
Each I/O pin has a PPS register with which the pin output
source is selected. With few exceptions, the port TRISx
control associated with that pin retains control over the
pin output driver. Peripherals that control the pin output
driver as part of the peripheral operation will override the
TRISx control as needed. These peripherals include:
• EUSART (synchronous operation)
• MSSP (I2C)
• COG (auto-shutdown)
Although every pin has its own PPS Peripheral
Selection register, the selections are identical for every
pin, as shown in Register 12-2.
Note:
12.1
PPS Outputs
PPS Inputs
Each peripheral has a PPS register with which the
inputs to the peripheral are selected. Inputs include the
device pins.
The notation, “Rxy”, is a placeholder for
the pin port and bit identifiers. For
example, x and y for PORTA, bit 0 would
be A and 0, respectively, resulting in the
PPS Pin Output Source Selection
register, RA0PPS.
Multiple peripherals can operate from the same source
simultaneously. Port reads always return the pin level,
regardless of the peripheral PPS selection. If a pin also
has associated analog functions, the ANSELx bit for that
pin must be cleared to enable the digital input buffer.
Although every peripheral has its own PPS Input Selection register, the selections are identical for every
peripheral, as shown in Register 12-1.
Note:
The notation, “xxx”, in the register name is
a placeholder for the peripheral identifier.
For example, CLC1PPS represents the
PPS Input Selection register for the CLC1
peripheral.
FIGURE 12-1:
SIMPLIFIED PPS BLOCK DIAGRAM
PPS Outputs
RA0PPS
PPS Inputs
RA0
abcPPS
RA0
Peripheral abc
RxyPPS
Rxy
Peripheral xyz
RC7
xyzPPS
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RC7
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12.3
Bidirectional Pins
PPS selections for peripherals with bidirectional
signals on a single pin must be made so that the PPS
input and PPS output select the same pin. Peripherals
that have bidirectional signals include:
• EUSART (synchronous operation)
• MSSP (I2C)
Note:
The I2C default input pins are I2C and
SMBus compatible, and are the only pins
on the device with this compatibility.
12.5
The PPS can be permanently locked by setting the
PPS1WAY Configuration bit. When this bit is set, the
PPSLOCKED bit can only be cleared and set one time
after a device Reset. This allows for clearing the
PPSLOCKED bit so that the input and output selections can be made during initialization. When the
PPSLOCKED bit is set, after all selections have been
made, it will remain set and cannot be cleared until after
the next device Reset event.
12.6
12.4
PPS Lock
The PPS includes a mode in which all input and output
selections can be locked to prevent inadvertent
changes. PPS selections are locked by setting the
PPSLOCKED bit of the PPSLOCK register. Setting and
clearing this bit requires a special sequence as an extra
precaution against inadvertent changes. Examples of
setting and clearing the PPSLOCKED bit are shown in
Example 12-1.
EXAMPLE 12-1:
PPS Permanent Lock
Operation During Sleep
PPS input and output selections are unaffected by
Sleep.
12.7
Effects of a Reset
A device Power-on Reset (POR) clears all PPS input
and output selections to their default values. All other
Resets leave the selections unchanged. Default input
selections are shown in Table 12-1.
PPS LOCK/UNLOCK
SEQUENCE
; suspend interrupts
bcf
INTCON,GIE
;
BANKSEL PPSLOCK
; set bank
; required sequence, next 5 instructions
movlw
0x55
movwf
PPSLOCK
movlw
0xAA
movwf
PPSLOCK
; Set PPSLOCKED bit to disable writes or
; Clear PPSLOCKED bit to enable writes
bsf
PPSLOCK,PPSLOCKED
; restore interrupts
bsf
INTCON,GIE
DS40001775B-page 158
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12.8
Register Definitions: PPS Input and Output Selections
REGISTER 12-1:
xxxPPS: PERIPHERAL xxx INPUT SELECTION
U-0
U-0
U-0
—
—
—
R/W-q/u
R/W-q/u
R/W-q/u
R/W-q/u
R/W-q/u
xxxPPS<2:0>(1)
xxxPPS<4:3>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = value depends on peripheral
bit 7-5
Unimplemented: Read as ‘0’
bit 4-3
xxxPPS<4:3>: Peripheral xxx Input PORT Selection bits
11 = Reserved; do not use
10 = Peripheral input is PORTC
01 = Peripheral input is PORTB(2)
00 = Peripheral input is PORTA
bit 2-0
xxxPPS<2:0>: Peripheral xxx Input Bit Selection bits(1)
111 = Peripheral input is from PORTx, bit 7 (Rx7)
110 = Peripheral input is from PORTx, bit 6 (Rx6)
101 = Peripheral input is from PORTx, bit 5 (Rx5)
100 = Peripheral input is from PORTx, bit 4 (Rx4)
011 = Peripheral input is from PORTx, bit 3 (Rx3)
010 = Peripheral input is from PORTx, bit 2 (Rx2)
001 = Peripheral input is from PORTx, bit 1 (Rx1)
000 = Peripheral input is from PORTx, bit 0 (Rx0)
Note 1:
2:
See Table 12-1 for xxxPPS register list and Reset values.
PIC16(L)F1768/9 only.
REGISTER 12-2:
RxyPPS: PIN Rxy OUTPUT SOURCE SELECTION REGISTER
U-0
U-0
U-0
—
—
—
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
RxyPPS<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RxyPPS<4:0>: Pin Rxy Output Source Selection bits
Selection code determines the output signal on the port pin. See Table 12-2 for the selection codes.
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REGISTER 12-3:
PPSLOCK: PPS LOCK REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0/0
—
—
—
—
—
—
—
PPSLOCKED
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-1
Unimplemented: Read as ‘0’
bit 0
PPSLOCKED: PPS Locked bit
1 = PPS is locked; PPS selections cannot be changed
0 = PPS is not locked; PPS selections can be changed
DS40001775B-page 160
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
TABLE 12-1:
PPS INPUT REGISTER RESET VALUES
Peripheral
xxxPPS
Register
(Register 12-1)
Default Pin Selection
Reset Value (xxxPPS<4:0>)
PIC16(L)F1768/9
PIC16(L)F1764/5
PIC16(L)F1768/9
PIC16(L)F1764/5
Interrupt-On-Change INTPPS
RA2
RA2
00010
00010
Timer0 Clock
T0CKIPPS
RA2
RA2
00010
00010
Timer1 Clock
T1CKIPPS
RA5
RA5
00101
00101
Timer1 Gate
T1GPPS
RA4
RA4
00100
00100
Timer2 Clock
T2CKIPPS
RA5
RA5
0101
0101
Timer3 Clock
T3CKIPPS
RC5
RC5
10101
10101
Timer3 Gate
T3GPPS
RC4
RC4
10100
10100
Timer4 Clock
T4CKIPPS
RC1
RC1
10001
10001
Timer5 Clock
T5CKIPPS
RC0
RC0
10000
10000
Timer5 Gate
T5GPPS
RC3
RC3
10011
10011
Timer6 Clock
T6CKIPPS
RA3
RA3
00011
00011
CCP1
CCP1PPS
RC5
RC5
10101
10101
CCP2
CCP2PPS
(1)
RC3
—
10011
—
COG1
COG1INPPS
RA2
RA2
00010
00010
COG2
COG2INPPS(1)
RA2
—
00010
—
2
SPI and I C Clock
SSPCLKPPS
RB6
RC0
01110
10000
SPI and I2C Data
SSPDATPPS
RB4
RC1
01100
10001
SPI Slave Select
SSPSSPPS
RC6
RC3
10110
10011
EUSART RX
RXPPS
RB5
RC5
01101
10101
EUSART CK
CKPPS
RB7
RC4
01111
10100
All CLCs
CLCIN0PPS
RC3
RC3
10011
10011
All CLCs
CLCIN1PPS
RC4
RC4
10100
10100
All CLCs
CLCIN2PPS
RC1
RC1
10001
10001
All CLCs
CLCIN3PPS
RA5
RA5
00101
00101
PRG1 Set Rising
PRG1RPPS
RC4
RC4
10100
10100
PRG1 Set Falling
PRG1FPPS
RC5
RC5
10101
10101
PRG2 Set Rising
PRG2RPPS
(1)
RC4
—
10100
—
PRG2 Set Falling
PRG2FPPS(1)
RC5
—
10101
—
DSM1 High Carrier
MD1CHPPS
RA3
RA3
00011
00011
DSM1 Low Carrier
MD1CLPPS
RA4
RA4
00100
00100
DSM1 Modulation
MD1MODPPS
RA5
RA5
00101
00101
DSM2 High Carrier
MD2CHPPS
(1)
RA3
—
00011
—
DSM2 Low Carrier
MD2CLPPS(1)
RA4
—
00100
—
DSM2 Modulation
MD2MODPPS(1)
RA5
—
00101
—
Example: CCP1PPS = 0x13 selects RC3 as the CCP1 input.
Note 1: PIC16(L)F1768/9 only.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 161
PIC16(L)F1764/5/8/9
TABLE 12-2:
AVAILABLE PORTS FOR OUTPUT BY PERIPHERAL(2)
PIC16(L)F1768/9
RxyPPS<4:0>
1111x
PIC16(L)F1764/5
Output Signal
Reserved
PORTA
PORTB
PORTC
PORTA
PORTC
—
—
—
—
—
11101
MD2_out
●
●
●
—
—
11100
MD1_out
●
●
●
●
●
11011
sync_C4OUT
●
●
●
—
—
11010
sync_C3OUT
●
●
●
—
—
11001
sync_C2OUT
●
●
●
●
●
11000
sync_C1OUT
●
●
●
●
●
(1)
●
●
●
●
●
10110
TX/CK(1)
●
●
●
●
●
10101
Reserved
—
—
—
—
—
10100
SDO
●
●
●
●
●
10011
SDA
●
●
●
●
●
10010
SCK/SCL(1)
●
●
●
●
●
10111
DT
10001
PWM6_out
●
●
●
—
—
10000
PWM5_out
●
●
●
●
●
01111
PWM4_out
●
●
●
—
—
01110
PWM3_out
●
●
●
●
●
01101
CCP2_out
●
●
●
●
●
01100
CCP1_out
●
●
●
●
●
01011
(1)
COG2D
●
●
●
—
—
01010
COG2C(1)
●
●
●
—
—
01001
COG2B(1)
●
●
●
—
—
01000
COG2A(1)
●
●
●
—
—
00111
COG1D(1)
●
●
●
●
●
00110
COG1C(1)
●
●
●
●
●
00101
COG1B
(1)
●
●
●
●
●
00100
COG1A(1)
●
●
●
●
●
00011
LC3_out
●
●
●
●
●
00010
LC2_out
●
●
●
●
●
00001
LC1_out
●
●
●
●
●
00000
LATxy
●
●
●
●
●
Note 1:
2:
TRISx control is overridden by the peripheral as required.
Unsupported peripherals will output a 0.
DS40001775B-page 162
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
TABLE 12-3:
SUMMARY OF REGISTERS ASSOCIATED WITH THE PPS MODULE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
PPSLOCK
—
—
—
—
—
—
—
PPSLOCKED
160
INTPPS
—
—
—
INTPPS<4:0>
159
T0CKIPPS
—
—
—
T0CKIPPS<4:0>
159
T1CKIPPS
—
—
—
T1CKIPPS<4:0>
159
T1GPPS
—
—
—
T1GPPS<4:0>
159
T2CKIPPS
—
—
—
T2CKIPPS<4:0>
159
T3CKIPPS
—
—
—
T3CKIPPS<4:0>
159
T3GPPS
—
—
—
T3GPPS<4:0>
159
T4CKIPPS
—
—
—
T4CKIPPS<4:0>
159
T5CKIPPS
—
—
—
T5CKIPPS<4:0>
159
T5GPPS
—
—
—
T5GPPS<4:0>
159
T6CKIPPS
—
—
—
T6CKIPPS<4:0>
159
CCP1PPS
—
—
—
CCP1PPS<4:0>
159
(1)
—
—
—
CCP2PPS<4:0>
159
COG1INPPS
—
—
—
COG1INPPS<4:0>
159
COG2INPPS(1)
—
—
—
COG2INPPS<4:0>
159
SSPCLKPPS
—
—
—
SSPCLKPPS<4:0>
159
SSPDATPPS
—
—
—
SSPDATPPS<4:0>
159
SSPSSPPS
—
—
—
SSPSSPPS<4:0>
159
RXPPS
—
—
—
RXPPS<4:0>
159
CKPPS
—
—
—
CKPPS<4:0>
159
CLCIN0PPS
—
—
—
CLCIN0PPS<4:0>
159
CLCIN1PPS
—
—
—
CLCIN1PPS<4:0>
159
CLCIN2PPS
—
—
—
CLCIN2PPS<4:0>
159
CLCIN3PPS
—
—
—
CLCIN3PPS<4:0>
159
PRG1RPPS
—
—
—
PRG1RPPS<4:0>
159
PRG1FPPS
—
—
—
PRG1FPPS<4:0>
159
PRG2RPPS(1)
—
—
—
PRG2RPPS<4:0>
159
PRG2FPPS(1)
—
—
—
PRG2FPPS<4:0>
159
MD1CHPPS
—
—
—
MD1CHPPS<4:0>
159
MD1CLPPS
—
—
—
MD1CLPPS<4:0>
159
MD1MODPPS
—
—
—
MD1MODPPS<4:0>
159
MD2CHPPS(1)
—
—
—
MD2CHPPS<4:0>
159
MD2CLPPS(1)
—
—
—
MD2CLPPS<4:0>
159
MD2MODPPS(1)
—
—
—
MD2MODPPS<4:0>
159
RA0PPS
—
—
—
RA0PPS<4:0>
159
RA1PPS
—
—
—
RA1PPS<4:0>
159
RA2PPS
—
—
—
RA2PPS<4:0>
159
RA4PPS
—
—
—
RA4PPS<4:0>
159
RA5PPS
—
—
—
RA5PPS<4:0>
159
RB4PPS(1)
—
—
—
RB4PPS<4:0>
159
Name
CCP2PPS
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the PPS module.
Note 1: PIC16(L)F1768/9 only.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 163
PIC16(L)F1764/5/8/9
TABLE 12-3:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH THE PPS MODULE (CONTINUED)
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
Bit 7
Bit 6
Bit 5
RB5PPS(1)
—
—
—
RB5PPS<4:0>
159
(1)
RB6PPS
—
—
—
RB6PPS<4:0>
159
RB7PPS(1)
—
—
—
RB7PPS<4:0>
159
RC0PPS
—
—
—
RC0PPS<4:0>
159
RC1PPS
—
—
—
RC1PPS<4:0>
159
RC2PPS
—
—
—
RC2PPS<4:0>
159
RC3PPS
—
—
—
RC3PPS<4:0>
159
RC4PPS
—
—
—
RC4PPS<4:0>
159
RC5PPS
—
—
—
RC5PPS<4:0>
159
RC6PPS(1)
—
—
—
RC6PPS<4:0>
159
RC7PPS(1)
—
—
—
RC7PPS<4:0>
159
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the PPS module.
Note 1: PIC16(L)F1768/9 only.
DS40001775B-page 164
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
13.0
INTERRUPT-ON-CHANGE
All pins on all ports can be configured to operate as
Interrupt-On-Change (IOC) pins. An interrupt can be
generated by detecting a signal that has either a rising
edge or a falling edge. Any individual pin, or combination
of pins, can be configured to generate an interrupt. The
Interrupt-On-Change module has the following features:
•
•
•
•
Interrupt-On-Change enable (Master Switch)
Individual pin configuration
Rising and falling edge detection
Individual pin interrupt flags
Figure 13-1 is a block diagram of the IOC module.
13.1
Enabling the Module
13.3
Interrupt Flags
The bits located in the IOCxF registers are status flags
that correspond to the Interrupt-On-Change pins of
each port. If an expected edge is detected on an
appropriately enabled pin, then the status flag for that pin
will be set and an interrupt will be generated if the IOCIE
bit is set. The IOCIF bit of the INTCON register reflects
the status of all IOCxF bits.
13.4
Clearing Interrupt Flags
The individual status flags (IOCxF register bits) can be
cleared by resetting them to zero. If another edge is
detected during this clearing operation, the associated
status flag will be set at the end of the sequence,
regardless of the value actually being written.
To allow individual pins to generate an interrupt, the
IOCIE bit of the INTCON register must be set. If the
IOCIE bit is disabled, the edge detection on the pin will
still occur, but an interrupt will not be generated.
In order to ensure that no detected edge is lost while
clearing flags, only AND operations masking out known
changed bits should be performed. The following
sequence is an example of what should be performed.
13.2
EXAMPLE 13-1:
Individual Pin Configuration
For each pin, a rising edge detector and a falling edge
detector are present. To enable a pin to detect a rising
edge, the associated bit of the IOCxP register is set. To
enable a pin to detect a falling edge, the associated bit
of the IOCxN register is set.
A pin can be configured to detect rising and falling
edges simultaneously by setting the associated bits in
both of the IOCxP and IOCxN registers.
MOVLW
XORWF
ANDWF
13.5
CLEARING INTERRUPT
FLAGS (PORTA EXAMPLE)
0xff
IOCAF, W
IOCAF, F
Operation in Sleep
The Interrupt-On-Change interrupt sequence will wake
the device from Sleep mode if the IOCIE bit is set.
If an edge is detected while in Sleep mode, the affected
IOCxF register will be updated prior to the first instruction
executed out of Sleep.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 165
PIC16(L)F1764/5/8/9
FIGURE 13-1:
INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE)
Rev. 10-000 037A
6/2/201 4
IOCANx
D
Q
R
Q4Q1
edge
detect
RAx
IOCAPx
D
data bus =
0 or 1
Q
D
S
to data bus
IOCAFx
Q
write IOCAFx
R
IOCIE
Q2
IOC interrupt
to CPU core
from all other
IOCnFx individual
pin detectors
FOSC
Q1
Q1
Q3
Q2
Q3
Q4
Q4Q1
Q1
Q2
Q2
Q3
Q4
Q4Q1
DS40001775B-page 166
Q4
Q4Q1
Q4Q1
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
13.6
Register Definitions: Interrupt-On-Change Control
REGISTER 13-1:
IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER
U-0
U-0
—
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCAP<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
IOCAP<5:0>: Interrupt-On-Change PORTA Positive Edge Enable bits
1 = Interrupt-On-Change is enabled on the pin for a positive going edge; IOCAFx bit and IOCIF flag
will be set upon edge detection
0 = Interrupt-On-Change is disabled for the associated pin
REGISTER 13-2:
IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER
U-0
U-0
—
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCAN<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
IOCAN<5:0>: Interrupt-On-Change PORTA Negative Edge Enable bits
1 = Interrupt-On-Change is enabled on the pin for a negative going edge; IOCAFx bit and IOCIF flag
will be set upon edge detection
0 = Interrupt-On-Change is disabled for the associated pin
 2014-2015 Microchip Technology Inc.
DS40001775B-page 167
PIC16(L)F1764/5/8/9
REGISTER 13-3:
IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER
U-0
U-0
—
—
R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
IOCAF<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HS = Hardware Settable bit
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
IOCAF<5:0>: Interrupt-On-Change PORTA Flag bits
1 = An enabled change was detected on the associated pin
Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling
edge was detected on RAx.
0 = No change was detected or the user cleared the detected change
REGISTER 13-4:
R/W-0/0
IOCBP: INTERRUPT-ON-CHANGE PORTB POSITIVE EDGE REGISTER(1)
R/W-0/0
R/W-0/0
R/W-0/0
IOCBP<7:4>
U-0
U-0
U-0
U-0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
IOCBP<7:4>: Interrupt-On-Change PORTB Positive Edge Enable bits
1 = Interrupt-On-Change is enabled on the pin for a positive going edge; IOCBFx bit and IOCIF flag
will be set upon edge detection
0 = Interrupt-On-Change is disabled for the associated pin
bit 3-0
Unimplemented: Read as ‘0’
Note 1:
PIC16(L)F1768/9 only.
DS40001775B-page 168
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
REGISTER 13-5:
R/W-0/0
IOCBN: INTERRUPT-ON-CHANGE PORTB NEGATIVE EDGE REGISTER(1)
R/W-0/0
R/W-0/0
R/W-0/0
IOCBN<7:4>
U-0
U-0
U-0
U-0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
IOCBN<7:4>: Interrupt-On-Change PORTB Negative Edge Enable bits
1 = Interrupt-On-Change is enabled on the pin for a negative going edge; IOCBFx bit and IOCIF flag
will be set upon edge detection
0 = Interrupt-On-Change is disabled for the associated pin
bit 3-0
Unimplemented: Read as ‘0’
Note 1:
PIC16(L)F1768/9 only.
REGISTER 13-6:
R/W/HS-0/0
IOCBF: INTERRUPT-ON-CHANGE PORTB FLAG REGISTER(1)
R/W/HS-0/0
R/W/HS-0/0 R/W/HS-0/0
IOCBF<7:4>
U-0
U-0
U-0
U-0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HS = Hardware Settable bit
bit 7-4
IOCBF<7:4>: Interrupt-On-Change PORTB Flag bits
1 = An enabled change was detected on the associated pin
Set when IOCBPx = 1 and a rising edge was detected on RBx, or when IOCBNx = 1 and a falling
edge was detected on RBx.
0 = No change was detected or the user cleared the detected change
bit 3-0
Unimplemented: Read as ‘0’
Note 1:
PIC16(L)F1768/9 only.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 169
PIC16(L)F1764/5/8/9
REGISTER 13-7:
R/W-0/0
IOCCP: INTERRUPT-ON-CHANGE PORTC POSITIVE EDGE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCCP<7:0>(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
IOCCP<7:0>: Interrupt-On-Change PORTC Positive Edge Enable bits(1)
1 = Interrupt-On-Change is enabled on the pin for a positive going edge; IOCCFx bit and IOCIF flag
will be set upon edge detection
0 = Interrupt-On-Change is disabled for the associated pin
bit 7-0
Note 1:
Bits<7:6> are available on PIC16(L)F1768/9 only.
REGISTER 13-8:
R/W-0/0
IOCCN: INTERRUPT-ON-CHANGE PORTC NEGATIVE EDGE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCCN<7:0>(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
Note 1:
IOCCN<7:0>: Interrupt-On-Change PORTC Negative Edge Enable bits(1)
1 = Interrupt-On-Change is enabled on the pin for a negative going edge; IOCCFx bit and IOCIF flag
will be set upon edge detection
0 = Interrupt-On-Change is disabled for the associated pin
Bits<7:6> are available on PIC16(L)F1768/9 only.
DS40001775B-page 170
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
REGISTER 13-9:
R/W/HS-0/0
IOCCF: INTERRUPT-ON-CHANGE PORTC FLAG REGISTER
R/W/HS-0/0
R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
IOCCF<7:0>(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HS = Hardware Settable bit
IOCCF<7:0>: Interrupt-On-Change PORTC Flag bits(1)
1 = An enabled change was detected on the associated pin
Set when IOCCPx = 1 and a rising edge was detected on RCx, or when IOCCNx = 1 and a falling
edge was detected on RCx
0 = No change was detected or the user cleared the detected change
bit 7-0
Note 1:
Bits<7:6> are available on PIC16(L)F1768/9 only.
TABLE 13-1:
Name
ANSELA
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
—
—
—
ANSA4
—
ANSELB(1)
ANSELC
INTCON
ANSB<7:4>
ANSC<7:6>(1)
—
—
—
TMR0IE
INTE
Bit 2
Bit 1
Bit 0
ANSA<2:0>
—
—
142
—
ANSC<3:0>
IOCIE
TMR0IF
INTF
Register
on Page
148
153
IOCIF
104
GIE
PEIE
IOCAF
—
—
IOCAF<5:0>
168
IOCAN
—
—
IOCAN<5:0>
167
IOCAP
—
—
IOCAP<5:0>
167
IOCBF(1)
IOCBF<7:4>
—
—
—
—
169
IOCBN(1)
IOCBN<7:4>
—
—
—
—
169
(1)
IOCBP
IOCBP<7:4>
—
—
—
—
168
IOCCF
(1)
IOCCF<7:6>
IOCCF<5:0>
IOCCN
IOCCN<7:6>(1)
IOCCN<5:0>
170
IOCCP
IOCCP<7:6>(1)
IOCCP<5:0>
170
TRISA
—
TRISB(1)
TRISC
—
TRISA<5:4>
TRISB<7:4>
TRISC<7:6>(1)
—(2)
—
171
TRISA<2:0>
—
—
141
—
TRISC<5:0>
147
152
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupt-On-Change.
Note 1: PIC16(L)F1768/9 only.
2: Unimplemented, read as ‘1’.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 171
PIC16(L)F1764/5/8/9
NOTES:
DS40001775B-page 172
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
14.0
FIXED VOLTAGE REFERENCE
(FVR)
The Fixed Voltage Reference, or FVR, is a stable
voltage reference, independent of VDD, with 1.024V,
2.048V or 4.096V selectable output levels. The output
of the FVR can be configured to supply a reference
voltage to the following:
•
•
•
•
ADC input channel
ADC positive reference
Comparator positive input
Digital-to-Analog Converter (DAC)
The FVR can be enabled by setting the FVREN bit of
the FVRCON register.
14.1
Independent Gain Amplifiers
The output of the FVR supplied to the ADC,
Comparators and DAC is routed through two
independent Programmable Gain Amplifiers (PGAs).
Each amplifier can be programmed for a gain of 1x, 2x
or 4x, to produce the three possible voltage levels.
The CDAFVR<1:0> bits of the FVRCON register are used
to enable and configure the gain amplifier settings for the
reference supplied to the DAC and comparator module.
Reference Section 17.0 “5-Bit Digital-to-Analog Converter (DAC) Module” and Section 19.0 “Comparator
Module” for additional information.
14.2
FVR Stabilization Period
When the Fixed Voltage Reference module is enabled, it
requires time for the reference and amplifier circuits to
stabilize. Once the circuits stabilize and are ready for
use, the FVRRDY bit of the FVRCON register will be
set. See Figure 37-19 in Section 37.0 “DC and AC
Characteristics Graphs and Charts”.
14.3
FVR Buffer Stabilization Period
When either FVR Buffer1 or Buffer2 is enabled, then
the buffer amplifier circuits require 30 s to stabilize.
This stabilization time is required even when the FVR
is already operating and stable.
The ADFVR<1:0> bits of the FVRCON register are used
to enable and configure the gain amplifier settings for the
reference supplied to the ADC module. Reference
Section 16.0 “Analog-to-Digital Converter (ADC)
Module” for additional information.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 173
PIC16(L)F1764/5/8/9
FIGURE 14-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
ADFVR<1:0>
CDAFVR<1:0>
2
X1
X2
X4
FVR Buffer1
(To ADC Module)
X1
X2
X4
FVR Buffer2
(To Comparators, DAC)
2
HFINTOSC Enable
HFINTOSC
To BOR, LDO
FVREN
+
_
FVRRDY
Any Peripheral Requiring
the Fixed Reference
(see Table 14-1)
TABLE 14-1:
PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR)
Peripheral
Conditions
Description
HFINTOSC
FOSC<2:0> = 100 and
IRCF<3:0>  000x
BOR
BOREN<1:0> = 11
BOR is always enabled
BOREN<1:0> = 10 and BORFS = 1
BOR is disabled in Sleep mode, BOR fast start is enabled
BOREN<1:0> = 01 and BORFS = 1
BOR under software control, BOR fast start is enabled
All PIC16F1764/5/8/9 devices when
VREGPM = 1 and not in Sleep
The device runs off of the ULP regulator when in Sleep mode
LDO
DS40001775B-page 174
INTOSC is active and device is not in Sleep
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
14.4
Register Definitions: FVR Control
REGISTER 14-1:
FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER
R/W-0/0
R-q/q
R/W-0/0
R/W-0/0
FVREN
FVRRDY(1)
TSEN(3)
TSRNG(3)
R/W-0/0
R/W-0/0
R/W-0/0
CDAFVR<1:0>
R/W-0/0
ADFVR<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
FVREN: Fixed Voltage Reference Enable bit
1 = Fixed Voltage Reference is enabled
0 = Fixed Voltage Reference is disabled
bit 6
FVRRDY: Fixed Voltage Reference Ready Flag bit(1)
1 = Fixed Voltage Reference output is ready for use
0 = Fixed Voltage Reference output is not ready or not enabled
bit 5
TSEN: Temperature Indicator Enable bit(3)
1 = Temperature indicator is enabled
0 = Temperature indicator is disabled
bit 4
TSRNG: Temperature Indicator Range Selection bit(3)
1 = VOUT = VDD – 4 VT (High Range)
0 = VOUT = VDD – 2 VT (Low Range)
bit 3-2
CDAFVR<1:0>: Comparator/DAC FVR Buffer Gain Selection bits
11 = Comparator/DAC FVR buffer gain is 4x with output, VCDAFVR = 4x VFVR(2)
10 = Comparator/DAC FVR buffer gain is 2x with output, VCDAFVR = 2x VFVR(2)
01 = Comparator/DAC FVR buffer gain is 1x with output, VCDAFVR = 1x VFVR
00 = Comparator/DAC FVR buffer is off
bit 1-0
ADFVR<1:0>: ADC FVR Buffer Gain Selection bits
11 = ADC FVR buffer gain is 4x with output, VADFVR = 4x VFVR(2)
10 = ADC FVR buffer gain is 2x with output, VADFVR = 2x VFVR(2)
01 = ADC FVR buffer gain is 1x with output, VADFVR = 1x VFVR
00 = ADC FVR buffer is off
Note 1:
2:
3:
FVRRDY is always ‘1’ on PIC16F1764/5/8/9 only.
Fixed Voltage Reference output cannot exceed VDD.
See Section 15.0 “Temperature Indicator Module” for additional information.
TABLE 14-2:
Name
FVRCON
SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE
Bit 7
Bit 6
Bit 5
Bit 4
FVREN
FVRRDY
TSEN
TSRNG
 2014-2015 Microchip Technology Inc.
Bit 3
Bit 2
CDAFVR<1:0>
Bit 1
Bit 0
ADFVR<1:0>
Register
on Page
175
DS40001775B-page 175
PIC16(L)F1764/5/8/9
NOTES:
DS40001775B-page 176
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
15.0
TEMPERATURE INDICATOR
MODULE
This family of devices is equipped with a temperature
circuit designed to measure the operating temperature
of the silicon die. The circuit’s range of operating
temperature falls between -40°C and +85°C. The
output is a voltage that is proportional to the device
temperature. The output of the temperature indicator is
internally connected to the device ADC.
The low range is selected by clearing the TSRNG bit
of the FVRCON register. The low range generates a
lower voltage drop and thus, a lower bias voltage is
needed to operate the circuit. The low range is
provided for low-voltage operation.
FIGURE 15-1:
Rev. 10-000069A
7/31/2013
VDD
The circuit may be used as a temperature threshold
detector or a more accurate temperature indicator,
depending on the level of calibration performed. A onepoint calibration allows the circuit to indicate a
temperature closely surrounding that point. A two-point
calibration allows the circuit to sense the entire range
of temperature more accurately. Reference Application
Note AN1333, “Use and Calibration of the Internal
Temperature Indicator” (DS00001333) for more details
regarding the calibration process.
15.1
TEMPERATURE CIRCUIT
DIAGRAM
TSEN
TSRNG
Circuit Operation
VOUT
Figure 15-1 shows a simplified block diagram of the
temperature circuit. The proportional voltage output is
achieved by measuring the forward voltage drop across
multiple silicon junctions.
Temp. Indicator
To ADC
Equation 15-1 describes the output characteristics of
the temperature indicator.
15.2
EQUATION 15-1:
VOUT RANGES
High Range: VOUT = VDD – 4VT
Low Range: VOUT = VDD – 2VT
The temperature sense circuit is integrated with the
Fixed Voltage Reference (FVR) module. See
Section 14.0 “Fixed Voltage Reference (FVR)” for
more information.
The circuit is enabled by setting the TSEN bit of the
FVRCON register. When disabled, the circuit draws no
current.
The circuit operates in either high or low range. The high
range, selected by setting the TSRNG bit of the
FVRCON register, provides a wider output voltage. This
provides more resolution over the temperature range,
but may be less consistent from part to part. This range
requires a higher bias voltage to operate and thus, a
higher VDD is needed.
 2014-2015 Microchip Technology Inc.
Minimum Operating VDD
When the temperature circuit is operated in low range,
the device may be operated at any operating voltage
that is within specifications.
When the temperature circuit is operated in high range,
the device operating voltage, VDD, must be high
enough to ensure that the temperature circuit is
correctly biased.
Table 15-1 shows the recommended minimum VDD vs.
range setting.
TABLE 15-1:
RECOMMENDED VDD VS.
RANGE
Min. VDD, TSRNG = 1
Min. VDD, TSRNG = 0
3.6V
1.8V
DS40001775B-page 177
PIC16(L)F1764/5/8/9
15.3
Temperature Output
15.4
The output of the circuit is measured using the internal
Analog-to-Digital Converter. A channel is reserved for
the temperature circuit output. Refer to Section 16.0
“Analog-to-Digital Converter (ADC) Module” for
detailed information.
TABLE 15-2:
Name
FVRCON
ADC Acquisition Time
To ensure accurate temperature measurements, the
user must wait at least 200 s after the ADC input
multiplexer is connected to the temperature indicator
output before the conversion is performed. In addition,
the user must wait 200 s between sequential
conversions of the temperature indicator output.
SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR
Bit 7
Bit 6
Bit 5
Bit 4
FVREN
FVRRDY
TSEN
TSRNG
Bit 3
Bit 2
CDFVR<1:0>
Bit 1
Bit 0
ADFVR<1:0>
Register
on Page
175
Legend: Shaded cells are unused by the temperature indicator module.
DS40001775B-page 178
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
16.0
The ADC voltage reference is software-selectable to be
either internally generated or externally supplied.
ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single
Sample-and-Hold (S&H) circuit. The output of the
Sample-and-Hold is connected to the input of the converter. The converter generates a 10-bit binary result via
successive approximation and stores the conversion
result into the ADC Result registers (ADRESH:ADRESL
register pair). Figure 16-1 shows the block diagram of
the ADC.
FIGURE 16-1:
ADC BLOCK DIAGRAM
VDD
ADPREF<1:0> = 00
VREF+
ADPREF<1:0> = 11
FVR_buffer1
ADPREF<1:0> = 10
VREF-
ADNREF = 1
ADNREF = 0
AN0
00000
VREF+/AN1
00001
AN2
00010
AN3
00011
AN4
00100
AN5
00101
AN6
00110
AN7
00111
AN8(2)
01000
(2)
01001
AN10(2)
01010
AN11(2)
01011
AN9
VSS
Ref-
Ref+
ADC
10
GO/DONE
ADFM
DAC4_output(2)
11010
DAC3_output
11011
(2)
11100
Temp Indicator
11101
DAC2_output
DAC1_output
11110
FVR_buffer1
11111
0 = Left Justify
1 = Right Justify
16
ADON(1)
VSS
ADRESH
ADRESL
CHS<4:0>
Note 1:
2:
When ADON = 0, all multiplexer inputs are disconnected.
PIC16(L)F1768/9 only
 2014-2015 Microchip Technology Inc.
DS40001775B-page 179
PIC16(L)F1764/5/8/9
16.1
ADC Configuration
When configuring and using the ADC the following
functions must be considered:
•
•
•
•
•
•
Port configuration
Channel selection
ADC voltage reference selection
ADC conversion clock source
Interrupt control
Result formatting
16.1.1
PORT CONFIGURATION
The ADC can be used to convert both analog and
digital signals. When converting analog signals, the I/O
pin should be configured for analog by setting the
associated TRISx and ANSELx bits. Refer to
Section 11.0 “I/O Ports” for more information.
Note:
16.1.2
Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.
CHANNEL SELECTION
There are up to 18 channel selections available:
•
•
•
•
•
AN<7:0> pins
AN<11:8> pins (PIC16(L)F1768/9 only)
Temperature indicator
DAC1_output and DAC3_output
DAC2_output and DAC4_output
(PIC16(L)F1768/9 only)
• FVR_buffer1
The CHS<4:0> bits of the ADCON0 register
(Register 16-1) determine which channel is connected
to the Sample-and-Hold circuit.
16.1.4
ADC NEGATIVE VOLTAGE
REFERENCE
The ADNREF bit of the ADCON1 register provides
control of the negative voltage reference. The negative
voltage reference can be:
• VREF- pin
• VSS
16.1.5
CONVERSION CLOCK
The source of the conversion clock is software-selectable
via the ADCS<2:0> bits of the ADCON1 register. There
are seven possible clock options:
•
•
•
•
•
•
•
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC (internal RC oscillator)
The time to complete one bit conversion is defined as
TAD. One full 10-bit conversion requires 11.5 TAD
periods, as shown in Figure 16-2.
For correct conversion, the appropriate TAD specification
must be met. Refer to Table 36-16: ADC Conversion
Requirements for more information. Table 16-1 gives
examples of appropriate ADC clock selections.
Note:
Unless using the FRC, any changes in the
system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 16.2
“ADC Operation” for more information.
16.1.3
ADC POSITIVE VOLTAGE
REFERENCE
The ADPREF<1:0> bits of the ADCON1 register
provide control of the positive voltage reference. The
positive voltage reference can be:
•
•
•
•
•
VREF+ pin
VDD
FVR 2.048V
FVR 4.096V (not available on LF devices)
VSS
See Section 16.0 “Analog-to-Digital Converter
(ADC) Module” for more details on the Fixed Voltage
Reference.
DS40001775B-page 180
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
TABLE 16-1:
ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
ADC Clock Period (TAD)
Device Frequency (FOSC)
ADC Clock
ADCS<2:0>
Source
32 MHz
20 MHz
16 MHz
8 MHz
4 MHz
1 MHz
FOSC/2
000
62.5ns(2)
100 ns(2)
125 ns(2)
250 ns(2)
500 ns(2)
2.0 s
100
125 ns
(2)
200 ns
(2)
(2)
250 ns
(2)
1.0 s
4.0 s
FOSC/8
001
0.5 s
400 ns
(2)
0.5 s
1.0 s
2.0 s
8.0 s(3)
FOSC/16
101
800 ns
800 ns
1.0 s
2.0 s
4.0 s
16.0 s(2)
FOSC/32
010
1.0 s
1.6 s
2.0 s
4.0 s
8.0 s(3)
32.0 s(2)
FOSC/64
110
2.0 s
3.2 s
4.0 s
16.0 s
64.0 s(2)
FRC
x11
FOSC/4
Legend:
Note 1:
2:
3:
4:
(2)
500 ns
(2)
8.0 s
(3)
(2)
1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4)
Shaded cells are outside of the recommended range.
See the TAD parameter for FRC source typical TAD value.
These values violate the required TAD time.
Outside the recommended TAD time.
The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is
derived from the system clock, FOSC. However, the FRC oscillator source must be used when conversions
are to be performed with the device in Sleep mode.
FIGURE 16-2:
ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
Rev. 10-000035A
7/30/2013
TAD1
TAD2
TAD3
TAD4
TAD5
TAD6
TAD7
TAD8
TAD9
TAD10
TAD11
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
THCD
Conversion Starts
TACQ
Holding capacitor disconnected
from analog input (THCD).
Set GO bit
On the following cycle:
ADRESH:ADRESL is loaded,
GO bit is cleared,
ADIF bit is set,
holding capacitor is reconnected to analog input.
Enable ADC (ADON bit)
and
Select channel (ACS bits)
 2014-2015 Microchip Technology Inc.
DS40001775B-page 181
PIC16(L)F1764/5/8/9
16.1.6
INTERRUPTS
16.1.7
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC Interrupt Flag is the ADIF bit in
the PIR1 register. The ADC Interrupt Enable bit is the
ADIE bit in the PIE1 register. The ADIF bit must be
cleared in software.
RESULT FORMATTING
The 10-bit ADC conversion result can be supplied in
two formats, left justified or right justified. The ADFM bit
of the ADCON1 register controls the output format.
Figure 16-3 shows the two output formats.
Note 1: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
2: The ADC operates during Sleep only
when the FRC oscillator is selected.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the ADIE bit of the PIE1 register and the
PEIE bit of the INTCON register must both be set, and
the GIE bit of the INTCON register must be cleared. If
all three of these bits are set, the execution will switch
to the Interrupt Service Routine.
FIGURE 16-3:
10-BIT ADC CONVERSION RESULT FORMAT
Rev. 10-000054A
7/30/2013
ADRESH
ADRESL
(ADFM = 0) MSB
LSB
bit 7
bit 0
bit 7
10-bit ADC Result
(ADFM = 1)
bit 0
Unimplemented: Read as ‘0’
MSB
bit 7
Unimplemented: Read as ‘0’
DS40001775B-page 182
LSB
bit 0
bit 7
bit 0
10-bit ADC Result
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
16.2
16.2.1
ADC Operation
STARTING A CONVERSION
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the
GO/DONE bit of the ADCON0 register to a ‘1’ will start
the Analog-to-Digital conversion.
Note:
16.2.2
16.2.5
AUTO-CONVERSION TRIGGER
The auto-conversion trigger allows periodic ADC
measurements without software intervention. When a
rising edge of the selected source occurs, the
GO/DONE bit is set by hardware.
The auto-conversion trigger source is selected with the
TRIGSEL<4:0> bits of the ADCON2 register.
The GO/DONE bit should not be set in the
same instruction that turns on the ADC.
Refer to Section 16.2.6 “ADC Conversion
Procedure”.
Using the auto-conversion trigger does not assure
proper ADC timing. It is the user’s responsibility to
ensure that the ADC timing requirements are met.
COMPLETION OF A CONVERSION
TABLE 16-2:
See Table 16-2 for auto-conversion sources.
When the conversion is complete, the ADC module will:
• Clear the GO/DONE bit
• Set the ADIF interrupt flag bit
• Update the ADRESH and ADRESL registers with
the new conversion result
16.2.3
TERMINATING A CONVERSION
If a conversion must be terminated before completion,
the GO/DONE bit can be cleared in software. The
ADRESH and ADRESL registers will be updated with
the partially complete Analog-to-Digital conversion
sample. Incomplete bits will match the last bit
converted.
Note:
16.2.4
A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the FRC
option. When the FRC oscillator source is selected, the
ADC waits one additional instruction before starting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
AUTO-CONVERSION
SOURCES
Source Peripheral
Signal Name
CCP1
CCP1_trigger
CCP2(1)
CCP2_trigger
Timer0
T0_overflow
Timer1
T1_overflow
Timer3
T3_overflow
Timer5
T5_overflow
Timer2
T2_postscaled
Timer4
T4_postscaled
Timer6
T6_postscaled
Comparator C1
sync_C1OUT
Comparator C2
sync_C2OUT
Comparator C3(1)
sync_C3OUT
(1)
sync_C4OUT
Comparator C4
CLC1
LC1_out
CLC2
LC2_out
CLC3
LC3_out
PWM3
PWM3OUT
PWM4(1)
PWM4OUT
PWM5
PR/PH/OF/DC5_match
PWM6(1)
PR/PH/OF/DC6_match
Note 1:
PIC16(L)F1768/9 only
When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off,
although the ADON bit remains set.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 183
PIC16(L)F1764/5/8/9
16.2.6
ADC CONVERSION PROCEDURE
This is an example procedure for using the ADC to
perform an Analog-to-Digital conversion:
1.
2.
3.
4.
5.
6.
7.
8.
Configure the PORT:
• Disable the pin output driver (refer to the
TRISx register)
• Configure pin as an analog (refer to the
ANSELx register)
Configure the ADC module:
• Select ADC conversion clock
• Configure voltage reference
• Select ADC input channel
• Turn on ADC module
Configure ADC interrupt (optional):
• Clear ADC interrupt flag
• Enable ADC interrupt
• Enable peripheral interrupt
• Enable global interrupt(1)
Wait the required acquisition time.(2)
Start conversion by setting the GO/DONE bit.
Wait for ADC conversion to complete by one of
the following:
• Polling the GO/DONE bit
• Waiting for the ADC interrupt (interrupts
enabled)
Read ADC result.
Clear the ADC interrupt flag (required if interrupt
is enabled).
EXAMPLE 16-1:
ADC CONVERSION
;This code block configures the ADC
;for polling, Vdd and Vss references, FRC
;oscillator and AN0 input.
;
;Conversion start & polling for completion
; are included.
;
BANKSEL
ADCON1
;
MOVLW
B’11110000’ ;Right justify, FRC
;oscillator
MOVWF
ADCON1
;Vdd and Vss Vref
BANKSEL
TRISA
;
BSF
TRISA,0
;Set RA0 to input
BANKSEL
ANSEL
;
BSF
ANSEL,0
;Set RA0 to analog
BANKSEL
ADCON0
;
MOVLW
B’00000001’ ;Select channel AN0
MOVWF
ADCON0
;Turn ADC On
CALL
SampleTime
;Acquisiton delay
BSF
ADCON0,ADGO ;Start conversion
BTFSC
ADCON0,ADGO ;Is conversion done?
GOTO
$-1
;No, test again
BANKSEL
ADRESH
;
MOVF
ADRESH,W
;Read upper 2 bits
MOVWF
RESULTHI
;store in GPR space
BANKSEL
ADRESL
;
MOVF
ADRESL,W
;Read lower 8 bits
MOVWF
RESULTLO
;Store in GPR space
Note 1: The global interrupt can be disabled if the
user is attempting to wake-up from Sleep
and resume in-line code execution.
2: Refer to Section 16.4 “ADC Acquisition
Requirements”.
DS40001775B-page 184
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
16.3
Register Definitions: ADC Control
REGISTER 16-1:
U-0
ADCON0: ADC CONTROL REGISTER 0
R/W-0/0
R/W-0/0
—
R/W-0/0
R/W-0/0
CHS<4:0>
R/W-0/0
R/W-0/0
R/W-0/0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
Unimplemented: Read as ‘0’
bit 6-2
CHS<4:0>: Analog Channel Select bits
11111 = FVR (Fixed Voltage Reference) Buffer1 Output(2)
11110 = DAC1_output(1)
11101 = Temperature indicator(3)
11100 = DAC2_output(1,5)
11011 = DAC3_output(4)
11010 = DAC4_output(4,5)
11001 = Reserved; no channel connected
•
•
•
01111 = Switched AN7(5,6)
01110 = Switched AN6(6)
01101 = Reserved; no channel connected.
01100 = Reserved; no channel connected.
01011 = AN11(5)
01010 = AN10(5)
01001 = AN9(5)
01000 = AN8(5)
00111 = AN7
00110 = AN6
00101 = AN5
00100 = AN4
00011 = AN3
00010 = AN2
00001 = AN1
00000 = AN0
bit 1
GO/DONE: ADC Conversion Status bit
1 = ADC conversion cycle in progress; setting this bit starts an ADC conversion cycle
This bit is automatically cleared by hardware when the ADC conversion has completed.
0 = ADC conversion completed/not in progress
bit 0
ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current
Note 1:
2:
3:
4:
5:
6:
See Section 17.0 “5-Bit Digital-to-Analog Converter (DAC) Module” for more information.
See Section 14.0 “Fixed Voltage Reference (FVR)” for more information.
See Section 15.0 “Temperature Indicator Module” for more information.
See Section 18.0 “10-Bit Digital-to-Analog Converter (DAC) Module” for more information.
PIC16(L)F1768/9 only.
Input source is switched off when op amp override is forced tri-state. See Section 29.3 “Override Control”.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 185
PIC16(L)F1764/5/8/9
REGISTER 16-2:
R/W-0/0
ADCON1: ADC CONTROL REGISTER 1
R/W-0/0
ADFM
R/W-0/0
R/W-0/0
ADCS<2:0>
U-0
R/W-0/0
—
ADNREF
R/W-0/0
R/W-0/0
ADPREF<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
ADFM: ADC Result Format Select bit
1 = Right justified; six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is
loaded
0 = Left justified; six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is
loaded
bit 6-4
ADCS<2:0>: ADC Conversion Clock Select bits
111 = FRC (clock supplied from an internal RC oscillator)
110 = FOSC/64
101 = FOSC/16
100 = FOSC/4
011 = FRC (clock supplied from an internal RC oscillator)
010 = FOSC/32
001 = FOSC/8
000 = FOSC/2
bit 3
Unimplemented: Read as ‘0’
bit 2
ADNREF: ADC Negative Voltage Reference Configuration bit
1 =VREF- is connected to external VREF- pin
0 =VREF- is connected to VSS
bit 1-0
ADPREF<1:0>: ADC Positive Voltage Reference Configuration bits
11 = VREF+ is connected to the internal Fixed Voltage Reference (FVR) module(1)
10 = VREF+ is connected to the external VREF+ pin(1)
01 = Reserved
00 = VREF+ is connected to VDD
Note 1:
When selecting the VREF+ pin as the source of the positive reference, be aware that a minimum voltage
specification exists. See Table 36-16 for details.
DS40001775B-page 186
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
REGISTER 16-3:
R/W-0/0
ADCON2: ADC CONTROL REGISTER 2
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TRIGSEL<4:0>(1)
U-0
U-0
U-0
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-3
TRIGSEL<4:0>: Auto-Conversion Trigger Selection bits(1)
11111 = Reserved
•
•
•
11011 = Reserved
11010 = PWM6 – OF6_match(2)
11001 = PWM6 – PH6_match(2)
11000 = PWM6 – PR6_match(2)
10111 = PWM6 – DC6_match(2)
10110 = PWM5 – OF5_match
10101 = PWM5 – PH5_match
10100 = PWM5 – PR5_match
10011 = PWM5 – DC5_match
10010 = PWM4 – PWM4OUT(2)
10001 = PWM3 – PWM3OUT
10000 = CCP2 – CCP2_trigger(2)
01111 = CCP1 – CCP1_trigger
01110 = CLC3 – LC3_out
01101 = CLC2 – LC2_out
01100 = CLC1 – LC1_out
01011 = Comparator C4 – sync_C4OUT(2)
01010 = Comparator C3 – sync_C3OUT(2)
01001 = Comparator C2 – sync_C2OUT
01000 = Comparator C1 – sync_C1OUT
00111 = Timer6 – T6_postscaled
00110 = Timer5 – T5_overflow
00101 = Timer4 – T4_postscaled
00100 = Timer3 – T3_overflow
00011 = Timer2 – T2_postscaled
00010 = Timer1 – T1_overflow
00001 = Timer0 – T0_overflow
00000 = No auto-conversion trigger selected
bit 3-0
Unimplemented: Read as ‘0’
Note 1:
2:
This is a rising edge-sensitive input for all sources.
PIC16(L)F1768/9 only; reserved otherwise.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 187
PIC16(L)F1764/5/8/9
REGISTER 16-4:
R/W-x/u
ADRESH: ADC RESULT REGISTER HIGH (ADFM = 0)
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES<9:2>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
ADRES<9:2>: ADC Result Register bits
Upper eight bits of 10-bit conversion result.
REGISTER 16-5:
R/W-x/u
ADRESL: ADC RESULT REGISTER LOW (ADFM = 0)
R/W-x/u
ADRES<1:0>
r-x/u
r-x/u
r-x/u
r-x/u
r-x/u
r-x/u
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
r = Reserved bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
ADRES<1:0>: ADC Result Register bits
Lower two bits of 10-bit conversion result.
bit 5-0
Reserved: Do not use.
DS40001775B-page 188
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
REGISTER 16-6:
ADRESH: ADC RESULT REGISTER HIGH (ADFM = 1)
r-x/u
r-x/u
r-x/u
r-x/u
r-x/u
r-x/u
—
—
—
—
—
—
R/W-x/u
R/W-x/u
ADRES<9:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
r = Reserved bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-2
Reserved: Do not use.
bit 1-0
ADRES<9:8>: ADC Result Register bits
Upper two bits of 10-bit conversion result.
REGISTER 16-7:
R/W-x/u
ADRESL: ADC RESULT REGISTER LOW (ADFM = 1)
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
ADRES<7:0>: ADC Result Register bits
Lower eight bits of 10-bit conversion result.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 189
PIC16(L)F1764/5/8/9
16.4
ADC Acquisition Requirements
For the ADC to meet its specified accuracy, the Charge
Holding Capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The analog
input model is shown in Figure 16-4. The Source
Impedance (RS) and the internal Sampling Switch
(RSS) impedance directly affect the time required to
charge the capacitor, CHOLD. The Sampling Switch
(RSS) impedance varies over the device voltage (VDD),
refer to Figure 16-4. The maximum recommended
impedance for analog sources is 10 k. As the
EQUATION 16-1:
Assumptions:
source impedance is decreased, the acquisition time
may be decreased. After the analog input channel is
selected (or changed), an ADC acquisition must be
done before the conversion can be started. To calculate
the minimum acquisition time, Equation 16-1 may be
used. This equation assumes that 1/2 LSb error is used
(1,024 steps for the ADC). The 1/2 LSb error is the
maximum error allowed for the ADC to meet its
specified resolution.
ACQUISITION TIME EXAMPLE
Temperature = 50°C and external impedance of 10k  5.0V V DD
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2µs + T C +   Temperature - 25°C   0.05µs/°C  
The value for TC can be approximated with the following equations:
1
 = V CHOLD
V AP P LI ED  1 – -------------------------n+1


2
–1
;[1] VCHOLD charged to within 1/2 lsb
–TC
----------

RC
V AP P LI ED  1 – e  = V CHOLD


;[2] VCHOLD charge response to VAPPLIED
– Tc
---------

1
RC
 ;combining [1] and [2]
V AP P LI ED  1 – e  = V A PP LIE D  1 – -------------------------n+1



2
–1
Note: Where n = number of bits of the ADC.
Solving for TC:
T C = – C HOLD  R IC + R SS + R S  ln(1/2047)
= – 10pF  1k  + 7k  + 10k   ln(0.0004885)
= 1.37 µs
Therefore:
T A CQ = 2µs + 892ns +   50°C- 25°C   0.05 µs/°C  
= 4.62µs
Note 1: The Reference Voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The Charge Holding Capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
DS40001775B-page 190
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
FIGURE 16-4:
ANALOG INPUT MODEL
Analog
Input
Pin
Rs
CPIN
5 pF
VA
VDD
VT  0.6V
RIC  1k
Sampling
Switch
SS RSS
I LEAKAGE(1)
VT  0.6V
CHOLD = 10 pF
Ref-
Legend: CHOLD
CPIN
= Sample/Hold Capacitance
= Input Capacitance
I LEAKAGE = Leakage Current at the pin due to
various junctions
= Interconnect Resistance
RIC
= Resistance of Sampling Switch
RSS
Note 1:
SS
= Sampling Switch
VT
= Threshold Voltage
6V
5V
VDD 4V
3V
2V
RSS
5 6 7 8 9 1011
Sampling Switch
(k)
Refer to Table 36-4 (Parameter D060).
FIGURE 16-5:
ADC TRANSFER FUNCTION
Full-Scale Range
3FFh
3FEh
ADC Output Code
3FDh
3FCh
3FBh
03h
02h
01h
00h
Analog Input Voltage
0.5 LSB
Ref-
 2014-2015 Microchip Technology Inc.
Zero-Scale
Transition
1.5 LSB
Full-Scale
Transition
Ref+
DS40001775B-page 191
PIC16(L)F1764/5/8/9
TABLE 16-3:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH ADC
Bit 7
ADCON0
—
ADCON1
ADFM
Bit 6
Bit 5
ADCS<2:0>
ADC Result Register High
ADRESL
ADC Result Register Low
—
—
ANSELB
ANSB<7:6>
ANSELC
ANSC<7:6>(1)
INTCON
—
TRIGSEL<4:0>
ADRESH
(1)
Bit 3
Bit 2
CHS<4:0>
ADCON2
ANSELA
Bit 4
ADNREF
—
Bit 1
Bit 0
Register
on Page
GO/DONE
ADON
185
ADPREF<1:0>
—
—
186
187
188, 189
188, 189
—
ANSA4
ANSB<5:4>
—
—
—
—
ANSA<2:0>
—
—
142
—
ANSC<3:0>
148
153
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
104
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
105
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
108
—
—
TRISA5
TRISA4
—(2)
TRISA
(1)
TRISB
TRISB<7:6>
TRISB<5:4>
TRISC
TRISC<7:6>(1)
TRISC<5:4>
FVRCON
DAC1CON0
—
TRISA<2:0>
—
—
141
—
TRISC<3:0>
147
152
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR<1:0>
ADFVR<1:0>
175
EN
FM
OE1
—
PSS<1:0>
NSS<1:0>
195
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the ADC module.
Note 1: PIC16(L)F1768/9 only.
2: Unimplemented, read as ‘1’.
DS40001775B-page 192
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
17.0
5-BIT DIGITAL-TO-ANALOG
CONVERTER (DAC) MODULE
TABLE 17-1:
AVAILABLE 5-BIT DACs
Device
The Digital-to-Analog Converter supplies a variable
voltage reference, ratiometric with the input source,
with 32 selectable output levels.
The input of the DAC can be connected to:
D3
D4
PIC16(L)F1764
●
PIC16(L)F1765
●
PIC16(L)F1768
●
●
PIC16(L)F1769
●
●
• External VREF pins
• VDD supply voltage
• FVR (Fixed Voltage Reference)
The Digital-to-Analog Converter (DAC) is enabled by
setting the EN bit of the DACxCON0 register.
The output of the DAC can be configured to supply a
reference voltage to the following:
17.1
• Comparator positive input
• Operational amplifier inverting and non-inverting
inputs
• ADC input channel
• DACxOUT1 pin
EQUATION 17-1:
Output Voltage Selection
The DAC has 32 voltage level ranges. The 32 levels
are set with the REF<4:0> bits of the DACxREF
register.
The DAC output voltage is determined by Equation 17-1.
DAC OUTPUT VOLTAGE
IF DACxEN = 1:
DACxR  4:0 
VOUT =   VSOURCE+ – VSOURCE-   ------------------------------- + VSOURCE5


2
VSOURCE+ = VDD, VREF, or FVR Buffer2
VSOURCE- = VSS
17.2
Ratiometric Output Level
The DAC output value is derived using a resistor ladder
with each end of the ladder tied to a positive and
negative voltage reference input source. If the voltage
of either input source fluctuates, a similar fluctuation will
result in the DAC output value.
The value of the individual resistors within the ladder
can be found in Table 36-20.
17.3
DAC Voltage Reference Output
The DAC voltage can be output to the DACxOUT1 pin
by setting the OE1 bit of the DACxCON0 register.
Selecting the DAC voltage for output on the
DACxOUT1 pin automatically overrides the digital
output buffer and digital input threshold detector
functions of that pin. Reading the DACxOUT1 pin when
it has been configured for DAC voltage output will
always return a ‘0’.
Due to the limited current drive capability, a buffer must
be used on the DAC voltage output for external
connections to the DACxOUT1 pin. Figure 17-2 shows
an example buffering technique.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 193
PIC16(L)F1764/5/8/9
FIGURE 17-1:
DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM
Digital-to-Analog Converter (DAC)
FVR_buffer2
VSOURCE+
VDD
R<4:0>
5
VREF+
R
R
PSS<1:0>
2
R
EN
R
32
Steps
R
32-to-1 MUX
R
DACX_Output
(To Comparator and
ADC Modules)
R
DACxOUT1
R
OE1
NSS
VSOURCE-
VREFVSS
FIGURE 17-2:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC® MCU
DAC
Module
R
Voltage
Reference
Output
Impedance
17.4
Operation During Sleep
The DAC continues to function during Sleep. When the
device wakes up from Sleep through an interrupt or a
Watchdog Timer time-out, the contents of the
DACxCON0 register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
DS40001775B-page 194
+
–
DACxOUT1
17.5
Buffered DAC Output
Effects of a Reset
A device Reset affects the following:
• DAC is disabled.
• DAC output voltage is removed from the
DACXOUT1 pin.
• The REF<4:0> voltage reference control bits are
cleared.
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
17.6
Register Definitions: DAC Control
Long bit name prefixes for the 5-bit DAC peripherals are
shown in Table 17-2. Refer to Section 1.1 “Register and
Bit Naming Conventions” for more information.
TABLE 17-2:
BIT NAME PREFIXES
Peripheral
Bit Name Prefix
DAC3
DAC3
DAC4(1)
DAC4
Note 1:
PIC16(L)F1768/9 devices only.
REGISTER 17-1:
DACxCON0: DACx CONTROL REGISTER 0
R/W-0/0
U-0
R/W-0/0
U-0
EN
—
OE1
—
R/W-0/0
R/W-0/0
U-0
R/W-0/0
—
NSS
PSS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
EN: DACx Enable bit
1 = DACx is enabled
0 = DACx is disabled
bit 6
Unimplemented: Read as ‘0’
bit 5
OE1: DACx Voltage Output Enable bit
1 = DACx voltage level is also an output on the DACxOUT1 pin
0 = DACx voltage level is disconnected from the DACxOUT1 pin
bit 4
Unimplemented: Read as ‘0’
bit 3-2
PSS<1:0>: DACx Positive Source Select bits
11 = Reserved, do not use
10 = FVR Buffer2 output
01 = VREF+ pin
00 = VDD
bit 1
Unimplemented: Read as ‘0’
bit 0
NSS: DACx Negative Source Select bit
1 = VREF- pin
0 = VSS
 2014-2015 Microchip Technology Inc.
DS40001775B-page 195
PIC16(L)F1764/5/8/9
REGISTER 17-2:
DACxREF: DACx REFERENCE VOLTAGE OUTPUT SELECT REGISTER
U-0
U-0
U-0
—
—
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
REF<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
REF<4:0>: DACx Reference Voltage Output Select bits (see Equation 17-1)
TABLE 17-3:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH THE DACx MODULE
Bit 3
Bit 2
Register
on Page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 1
Bit 0
DAC3CON0
EN
—
OE1
—
DAC4CON0(1)
EN
---
OE1
---
PSS<1:0>
—
NSS
195
PSS<1:0>
---
NSS
195
DAC3REF
---
---
---
REF<4:0>
196
DAC4REF(1)
---
---
---
REF<4:0>
196
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used with the DACx module.
Note 1: PIC16(L)F1768/9 only.
DS40001775B-page 196
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
18.0
10-BIT DIGITAL-TO-ANALOG
CONVERTER (DAC) MODULE
The 10-bit Digital-to-Analog Converter (DAC) supplies
a variable voltage reference, ratiometric with the input
source, with 1024 selectable output levels.
The input of the DAC can be connected to:
• External VREF pins
• VDD supply voltage
• FVR (Fixed Voltage Reference)
The output of the DAC can be configured to supply a
reference voltage to the following:
•
•
•
•
Comparator positive input
ADC input channel
DACxOUT1 pin
Op Amp
The Digital-to-Analog Converter is enabled by setting
the EN bit of the DACxCON0 register.
EQUATION 18-1:
TABLE 18-1:
AVAILABLE 10-BIT DACs
Device
D1
D2
PIC16(L)F1764
●
PIC16(L)F1765
●
PIC16(L)F1768
●
●
PIC16(L)F1769
●
●
18.1
Output Voltage Level Selection
The DAC has 1024 voltage levels that are set by the
10-bit reference selection word contained in the
DACxREFH and DACxREFL registers. This 10-bit
word can be left or right justified. See Section 18.4
“DAC Reference Selection Justification” for more
details.
The DAC output voltage can be determined with
Equation 18-1.
DAC OUTPUT VOLTAGE
If EN = 1:
DACxR  9:0 
DACx_output =   VSOURCE + – VSOURCE -   ------------------------------- + VSOURCE 10


2
VSOURCE+ = VDD, VREF+, or FVR_buffer2
VSOURCE- = VSS OR VREF-
18.2
Ratiometric Output Voltage
The DAC output voltage is derived using a resistor
ladder with each end of the ladder tied to a positive and
negative voltage source. If the voltage of either input
source fluctuates, a similar fluctuation will result in the
DAC output value.
The value of the individual resistors within the ladder
can be found in Table 36-20.
18.3
DAC Output
The DAC voltage is always available to the internal
peripherals that use it. The DAC voltage can be output
to the DACxOUT1 pin by setting the OE1 bit of the
DACxCON0 register. Selecting the DAC voltage for
output on the DACxOUT1 pin automatically overrides
the digital output buffer and digital input threshold
detector functions of that pin. Reading the DACXOUT1
pin when it has been configured for DAC voltage output
will always return a ‘0’.
18.4
DAC Reference Selection
Justification
The DAC reference selection can be configured to be left
or right justified. When the FM bit of the DACxCON0
register is set, the 10-bit word is left justified, such that
the eight Most Significant bits fill the DACxREFH register
and the two Least Significant bits are left justified in the
DACxREFL register. When the FM bit is cleared, the
10-bit word is right justified, such that the eight Least
Significant bits fill the DACxREFL register and the two
Most Significant bits are right justified in the DACxREFH
register. Refer to Figure 18-1.
The DACxREFL and DACxREFH registers are
double-buffered. Writing to either register does not take
effect immediately. Writing a ‘1’ to the DACxLD bit of
the DACLD register transfers the contents of the
DACxREFH and DACxREFL registers to the buffers,
thereby changing all 10 bits of the DAC reference
selection simultaneously.
Due to the limited current drive capability, a buffer must
be used on the DAC voltage output for external
connections to either DACXOUT1 pin. Figure 18-3
shows a buffering technique example.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 197
PIC16(L)F1764/5/8/9
FIGURE 18-1:
DAC JUSTIFICATION
R1 R0 0
7
FM = 1 R9 R8 R7 R6 R5 R4 R3 R2
7
0
DACxREFH
0
7
0
0
0
0
0 R9 R8
0
0
0
0
0
0
Rev. 10-000 225A
4/29/201 4
DACxREFL
R7 R6 R5 R4 R3 R2 R1 R0
7
0
DACxREFH
0
FM = 0
DACxREFL
R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
DACxREF
FIGURE 18-2:
DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM
Rev. 10-000 219A
5/8/201 4
DACxREFH DACxREFL
10-bit Latch
(not visible to user)
Reserved
FVR_buffer2
VSOURCE+
write 1 to
DACxL D bit
VDD
VREF+
10
R
PSS<1:0>
R
2
EN
R
1024
Steps
R
R
1024-to-1 MUX
R
DACx_output
To Peripherals
DACxOUT1
OE
R
VREF-
VSOURCEVSS
NSS
DS40001775B-page 198
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
FIGURE 18-3:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC® MCU
DAC
Module
R
Voltage
Reference
Output
Impedance
18.5
Operation During Sleep
When the device wakes up from Sleep as the result of
an interrupt or a Watchdog Timer time-out, the contents
of the DACxCON0 register are not affected. To
minimize current consumption in Sleep mode, the
voltage reference should be disabled.
 2014-2015 Microchip Technology Inc.
+
–
DACxOUT1
18.6
Buffered DAC Output
Effects of a Reset
A device Reset affects the following:
• DAC is disabled
• DAC output voltage is removed from the
DACxOUT1 pin
• The REF<9:0> reference selection bits are
cleared
DS40001775B-page 199
PIC16(L)F1764/5/8/9
18.7
Register Definitions: DAC Control
Long bit name prefixes for the 10-bit DAC peripherals are
shown in Table 18-2. Refer to Section 1.1 “Register
and Bit Naming Conventions” for more information.
TABLE 18-2:
BIT NAME PREFIXES
Peripheral
Bit Name Prefix
DAC1
DAC1
DAC2(1)
DAC2
Note 1:
PIC16(L)F1768/9 devices only.
REGISTER 18-1:
DACxCON0: DACx CONTROL REGISTER 0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
EN
FM
OE1
—
R/W-0/0
R/W-0/0
U-0
R/W-0/0
—
NSS
PSS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
EN: DACx Enable bit
1 = DACx is enabled
0 = DACx is disabled
bit 6
FM: DACx Reference Format bit
1 = DACx reference selection is left justified
0 = DACx reference selection is right justified
bit 5
OE1: DACx Voltage Output Enable bit
1 = DACx voltage level is also an output on the DACxOUT1 pin
0 = DACx voltage level is disconnected from the DACxOUT1 pin
bit 4
Unimplemented: Read as ‘0’
bit 3-2
PSS<1:0>: DACx Positive Source Select bits
11 = Reserved; do not use.
10 = FVR_buffer2
01 = VREF+ pin
00 = VDD
bit 1
Unimplemented: Read as ‘0’
bit 0
NSS: DACx Negative Source Select bit
1 = VREF- pin
0 = VSS
DS40001775B-page 200
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
REGISTER 18-2:
R/W-0/0
DACxREFH: DACx REFERENCE VOLTAGE SELECT HIGH REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
REF<9:x> (x Depends on FM bit)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
When FM = 1 (left justified):
bit 7-0
REF<9:2>: DAC Reference Voltage Output Select bits
DACxOUT1 = f(REF<9:0>) (see Equation 18-1).
When FM = 0 (right justified):
bit 7-2
Unimplemented: Read as ‘0’
bit 1-0
REF<9:8>: DAC Reference Voltage Output Select bits
DACxOUT1 = f(REF<9:0>) (see Equation 18-1).
REGISTER 18-3:
R/W-0/0
DACxREFL: DACx REFERENCE VOLTAGE SELECT LOW REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
REF<x-1:0> (x Depends on FM bit)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
When FM = 1 (left justified):
bit 7-6
REF<1:0>: DAC Reference Voltage Output Select bits
DACxOUT1 = f(REF<9:0>) (see Equation 18-1).
bit 5-0
Unimplemented: Read as ‘0’
When FM = 0 (right justified):
bit 7-0
REF<7:0>: DAC Reference Voltage Output Select bits
DACxOUT1 = f(REF<9:0>) (see Equation 18-1).
 2014-2015 Microchip Technology Inc.
DS40001775B-page 201
PIC16(L)F1764/5/8/9
REGISTER 18-4:
DACLD: DAC BUFFER LOAD REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
—
—
—
—
—
—
DAC2LD(1)
DAC1LD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = value depends on configuration bits
bit 7-2
Unimplemented: Read as ‘0’
bit 1
DAC2LD: DAC2 Double-Buffer Load bit(1)
1 = DAC2REFH:DAC2REFL values are transfered to the double-buffer; bit is cleared automatically
by hardware
0 = DAC2REFH:DAC2REFL double-buffers remain unchanged
bit 0
DAC1LD: DAC1 Double-Buffer Load bit
1 = DAC1REFH:DAC1REFL values are transfered to the double-buffer; bit is cleared automatically
by hardware
0 = DAC1REFH:DAC1REFL double-buffers remain unchanged
Note 1:
PIC16(L)F1768/9 only
TABLE 18-3:
Name
DAC1CON0
(1)
DAC2CON0
SUMMARY OF REGISTERS ASSOCIATED WITH THE DACx MODULE
Bit 7
Bit 6
Bit 5
Bit 4
EN
FM
OE1
—
EN
FM
OE1
—
DAC1REFH
(1)
Register
on Page
PSS<1:0>
—
NSS
200
PSS<1:0>
—
NSS
200
201
REF<9:x> (x Depends on FM bit)
201
REF<x-1:0> (x Depends on FM bit)
201
REF<x-1:0> (x Depends on FM bit)
DAC2REFL
DACLD
Bit 0
Bit 2
REF<9:x> (x Depends on FM bit)
DAC2REFH(1)
DAC1REFL
Bit 1
Bit 3
—
—
—
—
—
—
201
DAC2LD(1)
DAC1LD
202
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used with the DACx module.
Note 1: PIC16(L)F1768/9 only
DS40001775B-page 202
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
19.0
COMPARATOR MODULE
FIGURE 19-1:
Comparators are used to interface analog circuits to a
digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes.
Comparators are very useful mixed-signal building
blocks because they provide analog functionality
independent of program execution. The analog
comparator module includes the following features:
•
•
•
•
•
•
•
•
•
Independent comparator control
Programmable input selection
Comparator output is available internally/externally
Programmable output polarity
Interrupt-On-Change
Wake-up from Sleep
Programmable speed/power optimization
PWM shutdown
Programmable and Fixed Voltage Reference (FVR)
19.1
Comparator Overview
SINGLE COMPARATOR
VIN+
+
VIN-
–
Output
VINVIN+
Output
Note:
The black areas of the output of the
comparator represent the uncertainty
due to input offsets and response time.
A single comparator is shown in Figure 19-1 along with
the relationship between the analog input levels and
the digital output. When the analog voltage at VIN+ is
less than the analog voltage at VIN-, the output of the
comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-,
the output of the comparator is a digital high level.
The comparators available for this device are located in
Table 19-1.
TABLE 19-1:
Device
AVAILABLE COMPARATORS
C1
C2
C3
C4
PIC16(L)F1764
●
●
PIC16(L)F1765
●
●
PIC16(L)F1768
●
PIC16(L)F1769
●
●
●
●
●
●
●
 2014-2015 Microchip Technology Inc.
DS40001775B-page 203
PIC16(L)F1764/5/8/9
FIGURE 19-2:
COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM
CxNCH<2:0>
CxON(1)
3
CxINTP
Interrupt
det
CxIN0-
0
CxIN1-
1
CxIN2-
2
MUX(2)
3
CxIN3PRG1_output
4
(3)
5
FVR Buffer2
6
PRG2_output
AGND
Set CxIF
CxINTN
Interrupt
det
CxPOL
CxVN
–
0
D
Cx
CxVP
ZLF
+
7
1
Q1
CxHYS
To CMxCON0 (CXOUT)
and CM2CON1 (MCxOUT)
Q
EN
CxZLF
CxSYNC
CxIN0+
0
(3)
1
CxIN1+
PPS
D
From Timer1
tmr1_clk
MUX(2)
7
PRG1_output
PRG2_output(3)
DAC1_output
Q
1
CxOUT
sync_CxOUT
To ADC, PRG, CLC,
Timer1/3/5 Gate,
Timer2/4/6 Reset,
COG, DSM
8
9
10
DAC2_output(3)
DAC3_output
11
DAC4_output(3)
FVR Buffer2
13
AGND
TRISx bit
0
2
Reserved
RxyPPS
12
14
15
CxON
CxPCH<3:0>
4
Note 1:
2:
3:
When CxON = 0, the comparator will produce a ‘0’ at the output.
When CxON = 0, all multiplexer inputs are disconnected.
Only on PIC16(L)F1768/9
DS40001775B-page 204
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
19.2
Comparator Control
Each comparator has two control registers: CMxCON0
and CMxCON1.
The CMxCON0 register (see Register 19-1) contains
control and status bits for the following:
•
•
•
•
•
•
•
Enable
Output
Output polarity
Zero latency filter
Speed/power selection
Hysteresis enable
Output synchronization
19.2.3
COMPARATOR OUTPUT POLARITY
Inverting the output of the comparator is functionally
equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
setting the POL bit of the CMxCON0 register. Clearing
the POL bit results in a non-inverted output.
Table 19-2 shows the output state versus input
conditions, including polarity control.
TABLE 19-2:
COMPARATOR OUTPUT
STATE vs. INPUT
CONDITIONS
Input Condition
CxPOL
CxOUT
The CMxCON1 register (see Register 19-2) contains
control bits for the following:
CxVN > CxVP
0
0
CxVN < CxVP
0
1
•
•
•
•
CxVN > CxVP
1
1
CxVN < CxVP
1
0
Interrupt enable
Interrupt edge polarity
Positive input channel selection
Negative input channel selection
19.2.1
COMPARATOR ENABLE
Setting the ON bit of the CMxCON0 register enables the
comparator for operation. Clearing the ON bit disables the
comparator, resulting in minimum current consumption.
19.2.2
COMPARATOR OUTPUT
SELECTION
The output of the comparator can be monitored by
reading either the OUT bit of the CMxCON0 register or
the MCxOUT bit of the CMOUT register. In order to
make the output available for an external connection,
the following conditions must be true:
• Desired pin PPS control
• Corresponding TRISx bit must be cleared
• ON bit of the CMxCON0 register must be set
Note 1: The internal output of the comparator is
latched with each instruction cycle.
Unless otherwise specified, external
outputs are not latched.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 205
PIC16(L)F1764/5/8/9
19.3
Comparator Hysteresis
A selectable amount of separation voltage can be
added to the input pins of each comparator to provide a
hysteresis function to the overall operation. Hysteresis
is enabled by setting the HYS bit of the CMxCON0
register.
The associated interrupt flag bit, CxIF bit of the PIR2
register, must be cleared in software. If another edge is
detected while this flag is being cleared, the flag will still
be set at the end of the sequence.
Note:
See Comparator Specifications in Table 36-19:
Comparator Specifications for more information.
19.4
Timer1 Gate Operation
The output resulting from a comparator operation can
be used as a source for gate control of Timer1. See
Section 22.6 “Timer1 Gate” for more information.
This feature is useful for timing the duration or interval
of an analog event.
It is recommended that the comparator output be
synchronized to Timer1. This ensures that Timer1 does
not increment while a change in the comparator is
occurring.
19.4.1
COMPARATOR OUTPUT
SYNCHRONIZATION
The output from a comparator can be synchronized
with Timer1 by setting the SYNC bit of the CMxCON0
register.
Once enabled, the comparator output is latched on the
falling edge of the Timer1 source clock. If a prescaler is
used with Timer1, the comparator output is latched after
the prescaling function. To prevent a race condition, the
comparator output is latched on the falling edge of the
Timer1 clock source and Timer1 increments on the
rising edge of its clock source. See the Comparator
Block Diagram (Figure 19-2) and the Timer1 Block
Diagram (Figure 22-1) for more information.
19.5
Comparator Interrupt
An interrupt can be generated upon a change in the
output value of the comparator for each comparator, a
rising edge detector and a falling edge detector are
present.
When either edge detector is triggered and its associated enable bit is set (INTP and/or INTN bits of the
CMxCON1 register), the corresponding interrupt flag
bit (CxIF bit of the PIR2 register) will be set.
To enable the interrupt, you must set the following bits:
• ON and POL bits of the CMxCON0 register
• CxIE bit of the PIE2 register
• INTP bit of the CMxCON1 register (for a rising
edge detection)
• INTN bit of the CMxCON1 register (for a falling
edge detection)
• PEIE and GIE bits of the INTCON register
DS40001775B-page 206
19.6
Although a comparator is disabled, an
interrupt can be generated by changing
the output polarity with the POL bit of the
CMxCON0 register, or by switching the
comparator on or off with the ON bit of the
CMxCON0 register.
Comparator Positive Input
Selection
Configuring the PCH<3:0> bits of the CMxPSEL
register directs an internal voltage reference or an
analog pin to the non-inverting input of the comparator:
•
•
•
•
•
CxIN+ analog pin
Programmable Ramp Generator (PRG) output
DAC output
FVR (Fixed Voltage Reference)
VSS (Ground)
See Section 14.0 “Fixed Voltage Reference (FVR)”
for more information on the Fixed Voltage Reference
module.
See Section 17.0 “5-Bit Digital-to-Analog Converter
(DAC) Module” for more information on the DAC input
signal.
Any time the comparator is disabled (CxON = 0), all
comparator inputs are disabled.
19.7
Comparator Negative Input
Selection
The NCH<2:0> bits of the CMxNSEL register direct an
analog input pin and internal reference voltage or
analog ground to the inverting input of the comparator:
• CxIN- pin
• FVR (Fixed Voltage Reference)
• Analog ground
Some inverting input selections share a pin with the
operational amplifier output function. Enabling both
functions at the same time will direct the operational
amplifier output to the comparator inverting input.
Note:
To use CxINy+ and CxINy- pins as analog
inputs, the appropriate bits must be set in
the ANSELx register and the corresponding TRISx bits must also be set to disable
the output drivers.
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
19.8
the hardware and software relying on this signal.
Therefore, a digital filter has been added to the
comparator output to suppress the comparator output
oscillation. Once the comparator output changes, the
output is prevented from reversing the change for a
nominal time of 20 ns. This allows the comparator
output to stabilize without affecting other dependent
devices. Refer to Figure 19-3.
Comparator Response Time
The comparator output is indeterminate for a period of
time after the change of an input source or the selection
of a new reference voltage. This period is referred to as
the response time. The response time of the comparator
differs from the settling time of the voltage reference.
Therefore, both of these times must be considered when
determining the total response time to a comparator
input change. See the Comparator and Voltage
Reference Specifications in Table 36-19: Comparator
Specifications for more details.
19.9
Zero Latency Filter
In high-speed operation, and under proper circuit
conditions, it is possible for the comparator output to
oscillate. This oscillation can have adverse effects on
FIGURE 19-3:
COMPARATOR ZERO LATENCY FILTER OPERATION
CxOUT from Comparator
CxOUT from ZLF
TZLF
Output waiting for TZLF to expire before an output change is allowed.
TZLF has expired so output change of ZLF is immediate based on
comparator output change.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 207
PIC16(L)F1764/5/8/9
19.10 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 19-4. Since the analog input pins share their
connection with a digital input, they have reverse
biased ESD protection diodes to VDD and VSS. The
analog input, therefore, must be between VSS and VDD.
If the input voltage deviates from this range by more
than 0.6V in either direction, one of the diodes is
forward biased and a latch-up may occur.
Note 1: When reading a PORT register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert as an analog input, according to
the input specification.
2: Analog levels on any pin defined as a
digital input, may cause the input buffer to
consume more current than is specified.
A maximum source impedance of 10 k is recommended
for the analog sources. Also, any external component
connected to an analog input pin, such as a capacitor or
a Zener diode, should have very little leakage current to
minimize inaccuracies introduced.
FIGURE 19-4:
ANALOG INPUT MODEL
Rev. 10-000071A
8/2/2013
VDD
RS < 10K
Analog
Input pin
VT § 0.6V
RIC
To Comparator
ILEAKAGE(1)
VA
CPIN
5pF
VT § 0.6V
VSS
Legend: CPIN
ILEAKAGE
RIC
RS
VA
VT
= Input Capacitance
= Leakage Current at the pin due to various junctions
= Interconnect Resistance
= Source Impedance
= Analog Voltage
= Threshold Voltage
Note 1: See I/O Ports in Table 36-4: I/O Ports.
DS40001775B-page 208
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
19.11 Register Definitions: Comparator Control
Long bit name prefixes for the DSM peripherals are
shown in Table 19-3. Refer to Section 1.1.2.2 “Long
Bit Names” for more information
TABLE 19-3:
BIT NAME PREFIXES
Peripheral
Bit Name Prefix
Comparator 1
C1
Comparator 2(1)
C2
Note 1:
PIC16(L)F1768/9 devices only.
REGISTER 19-1:
CMxCON0: COMPARATOR Cx CONTROL REGISTER 0
R/W-0/0
R-0/0
U-0
R/W-0/0
R/W-0/0
R/W-1/1
R/W-0/0
R/W-0/0
ON
OUT
—
POL
ZLF
r
HYS
SYNC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
r = Reserved bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
ON: Comparator Enable bit
1 = Comparator is enabled
0 = Comparator is disabled and consumes no active power
bit 6
OUT: Comparator Output bit
If POL = 1 (inverted polarity):
1 = CxVP < CxVN
0 = CxVP > CxVN
If POL = 0 (non-inverted polarity):
1 = CxVP > CxVN
0 = CxVP < CxVN
bit 5
Unimplemented: Read as ‘0’
bit 4
POL: Comparator Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 3
ZLF: Comparator Zero Latency Filter Enable bit
1 = Comparator output is filtered
0 = Comparator output is unfiltered
bit 2
Reserved: Read as ‘1’; maintain this bit set
bit 1
HYS: Comparator Hysteresis Enable bit
1 = Comparator hysteresis is enabled
0 = Comparator hysteresis is disabled
bit 0
SYNC: Comparator Output Synchronous Mode bit
1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source;
output updated on the falling edge of Timer1 clock source
0 = Comparator output to Timer1 and I/O pin is asynchronous
 2014-2015 Microchip Technology Inc.
DS40001775B-page 209
PIC16(L)F1764/5/8/9
REGISTER 19-2:
CMxCON1: COMPARATOR Cx CONTROL REGISTER 1
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
—
—
—
—
—
—
INTP
INTN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-2
Unimplemented: Read as ‘0’
bit 1
INTP: Comparator Interrupt on Positive Going Edge Enable bit
1 = The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit
0 = No interrupt flag will be set on a positive going edge of the CxOUT bit
bit 0
INTN: Comparator Interrupt on Negative Going Edge Enable bit
1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit
0 = No interrupt flag will be set on a negative going edge of the CxOUT bit
REGISTER 19-3:
CMxNSEL: COMPARATOR Cx NEGATIVE CHANNEL SELECT REGISTER
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0/0
R/W-0/0
R/W-0/0
NCH<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-3
Unimplemented: Read as ‘0’
bit 2-0
NCH<2:0>: Comparator Negative Input Channel Select bits
111 = CxVN connects to AGND
110 = CxVN connects to FVR Buffer2
101 = CxVN connects to PRG2_output(1)
100 = CxVN connects to PRG1_output
011 = CxVN connects to CxIN3- pin
010 = CxVN connects to CxIN2- pin
001 = CxVN connects to CxIN1- pin
000 = CxVN connects to CxIN0- pin
Note 1:
PIC16(L)F1768/9 only.
DS40001775B-page 210
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
REGISTER 19-4:
CMxPSEL: COMPARATOR Cx POSITIVE CHANNEL SELECT REGISTER 1
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PCH<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
PCH<3:0>: Comparator Positive Input Channel Select bits
1111 = CxVP connects to AGND
1110 = CxVP connects to FVR Buffer2
1101 = CxVP connects to DAC4_output(1)
1100 = CxVP connects to DAC3_output
1011 = CxVP connects to DAC2_output(1)
1010 = CxVP connects to DAC1_output
1001 = CxVP connects to PRG2_output(1)
1000 = CxVP connects to PRG1_output
0111 = CxVP unconnected, input floating
0110 = CxVP unconnected, input floating
0101 = CxVP unconnected, input floating
0100 = CxVP unconnected, input floating
0011 = CxVP unconnected, input floating
0010 = CxVP unconnected, input floating
0001 = CxVP connects to CxIN1+ pin
0000 = CxVP connects to CxIN0+ pin
Note 1:
Note:
PIC16(L)F1768/9 only.
There are no long and short bit name variants for the following mirror register.
REGISTER 19-5:
U-0
CMOUT: COMPARATOR OUTPUT REGISTER
U-0
—
U-0
—
—
U-0
—
R-0/0
MC4OUT
R-0/0
(1)
MC3OUT
(1)
R-0/0
R-0/0
MC2OUT
MC1OUT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-2
Unimplemented: Read as ‘0’
bit 3
MC4OUT: Mirror Copy of C4OUT bit(1)
bit 2
MC3OUT: Mirror Copy of C3OUT bit(1)
bit 1
MC2OUT: Mirror Copy of C2OUT bit
bit 0
MC1OUT: Mirror Copy of C1OUT bit
Note 1:
PIC16(L)F1768/9 only.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 211
PIC16(L)F1764/5/8/9
TABLE 19-4:
Name
ANSELA
ANSELB(1)
SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
—
—
—
ANSA4
—
ANSA2
—
—
ANSB<7:6>
ANSB<5:4>
Bit 1
Bit 0
ANSA<1:0>
Register
on Page
142
—
—
148
ANSC7(1)
ANSC6(1)
—
—
CM1CON0
ON
OUT
—
POL
ZLF
Reserved
HYS
SYNC
209
CM2CON0
ON
OUT
—
POL
ZLF
Reserved
HYS
SYNC
209
CM3CON0(1)
ON
OUT
—
POL
ZLF
Reserved
HYS
SYNC
209
CM4CON0(1)
ON
OUT
—
POL
ZLF
Reserved
HYS
SYNC
209
CM1CON1
—
—
—
—
—
—
INTP
INTN
210
CM2CON1
—
—
—
—
—
—
INTP
INTN
210
CM3CON1(1)
—
—
—
—
—
—
INTP
INTN
210
CM4CON1(1)
—
—
—
—
—
—
INTP
INTN
210
CM1NSEL
—
—
—
—
—
NCH<2:0>
210
CM2NSEL
—
—
—
—
—
NCH<2:0>
210
CM3NSEL(1)
—
—
—
—
—
NCH<2:0>
210
CM4NSEL(1)
—
—
—
—
—
NCH<2:0>
210
CM1PSEL
—
—
—
—
PCH<3:0>
211
CM2PSEL
—
—
—
—
PCH<3:0>
211
CM3PSEL(1)
—
—
—
—
PCH<3:0>
211
CM4PSEL(1)
—
—
—
—
PCH<3:0>
CMOUT
—
—
—
—
MC4OUT(1) MC3OUT(1)
FVRCON
ANSELC
ANSC<3:0>
153
211
MC2OUT
MC1OUT
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR<1:0>
DAC1CON0
EN
FM
OE1
—
PSS<1:0>
—
NSS
200
DAC2CON0(1)
EN
FM
OE1
—
PSS<1:0>
—
NSS
200
DAC3CON0
EN
—
OE1
—
PSS<1:0>
—
NSS
195
DAC4CON0
EN
—
OE1
—
PSS<1:0>
—
NSS
195
DAC3REF
---
---
---
REF<4:0>
196
DAC4REF(1)
---
---
---
REF<4:0>
196
(1)
DAC1REFH
ADFVR<1:0>
211
175
REF<9:x> (x Depends on FM bit)
201
DAC2REFH
REF<9:x> (x Depends on FM bit)
201
DAC1REFL
REF<x-1:0> (x Depends on FM bit)
201
DAC2REFL(1)
REF<x-1:0> (x Depends on FM bit)
201
(1)
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
104
C3IE(1)
CCP2IE(1)
106
C3IF(1)
CCP2IF(1)
109
PIE2
OSFIE
C2IE
C1IE
—
BCL1IE
C4IE(1)
PIR2
OSFIF
C2IF
C1IF
—
BCL1IF
C4IF(1)
—
—
TRISA<5:4>
—(2)
TRISA2
TRISB<5:4>
—
—
TRISA
TRISB(1)
TRISB<7:6>
(1)
TRISC
TRISC<7:6>
TRISC<5:4>
TRISA<1:0>
—
TRISC<3:0>
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module.
Note
1:
PIC16(L)F1768/9 only.
2:
Unimplemented, read as ‘1’.
DS40001775B-page 212
—
141
147
152
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
20.0
ZERO-CROSS DETECTION
(ZCD) MODULE
20.1
The ZCD module detects when an A/C signal crosses
through the ground potential. The actual zero-crossing
threshold is the zero-crossing reference voltage,
ZCPINV, which is typically 0.75V above ground.
The connection to the signal to be detected is through
a series current-limiting resistor. The module applies a
current source or sink to the ZCD pin to maintain a
constant voltage on the pin, thereby preventing the pin
voltage from forward biasing the ESD protection
diodes. When the applied voltage is greater than the
reference voltage, the module sinks current. When the
applied voltage is less than the reference voltage, the
module sources current. The current source and sink
action keeps the pin voltage constant over the full
range of the applied voltage. The ZCD module is
shown in the simplified block diagram (Figure 20-2).
The ZCD module requires a current-limiting resistor in
series with the external voltage source. The impedance
and rating of this resistor depends on the external
source peak voltage. Select a resistor value that will
drop all of the peak voltage when the current through
the resistor is nominally 300 A. Refer to Equation 20-1
and Figure 20-1. Make sure that the ZCD I/O pin
internal weak pull-up is disabled so it doesn’t interfere
with the current source and sink.
EQUATION 20-1:
R
EXTERNAL VOLTAGE
maxpeak
minpeak
ZCPINV
SIMPLIFIED ZCD BLOCK DIAGRAM
Optional
VDD
Vpullup
Rpullup
–
ZCPINV
V
peak
= -----------------series
–4
3 10
Vpeak
A/C period measurement
Accurate long term time measurement
Dimmer phase delayed drive
Low EMI cycle switching
FIGURE 20-2:
EXTERNAL RESISTOR
FIGURE 20-1:
The ZCD module is useful when monitoring an AC
waveform for, but not limited to, the following purposes:
•
•
•
•
External Resistor Selection
+
External
Current-Limiting
Resistor
Rseries
ZCD Pin
Rpulldown
External
Voltage
Source
Optional
ZCDx_output
D
POL
Q1
Q
OUT
LE
Interrupt
det
INTP
Sets
ZCDIF Flag
INTN
Interrupt
det
 2014-2015 Microchip Technology Inc.
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20.2
ZCD Logic Output
The ZCD module includes a status bit, which can be
read to determine whether the current source or sink is
active. The OUT bit of the ZCDCON register is set
when the current sink is active, and cleared when the
current source is active. The OUT bit is affected by the
polarity bit.
20.3
ZCD Logic Polarity
The POL bit of the ZCDxCON register inverts the OUT
bit relative to the current source and sink output. When
the POL bit is set, a OUT high indicates that the current
source is active, and a low output indicates that the
current sink is active.
The POL bit affects the ZCD interrupts. See
Section 20.4 “ZCD Interrupts”.
20.4
20.5
Correcting for ZCPINV Offset
The actual voltage at which the ZCD switches is the
reference voltage at the non-inverting input of the ZCD
op amp. For external voltage source waveforms other
than square waves, this voltage offset from zero
causes the zero-cross event to occur either too early or
too late. When the waveform is varying relative to Vss,
then the zero cross is detected too early as the
waveform falls and too late as the waveform rises.
When the waveform is varying relative to VDD, then the
zero cross is detected too late as the waveform rises
and too early as the waveform falls. The actual offset
time can be determined for sinusoidal waveforms with
the corresponding equations shown in Equation 20-2.
EQUATION 20-2:
When External Voltage Source is Relative to Vss:
ZCD Interrupts
An interrupt will be generated upon a change in the
ZCD logic output when the appropriate interrupt
enables are set. A rising edge detector and a falling
edge detector are present in the ZCD for this purpose.
The ZCDIF bit of the PIR3 register will be set when
either edge detector is triggered and its associated
enable bit is set. The INTP enables rising edge interrupts and the INTN bit enables falling edge interrupts.
Both are located in the ZCDxCON register.
To fully enable the interrupt, the following bits must
be set:
• ZCDIE bit of the PIE3 register
• INTP bit of the ZCDxCON register
(for a rising edge detection)
• INTN bit of the ZCDxCON register
(for a falling edge detection)
• PEIE and GIE bits of the INTCON register
Changing the POL bit will cause an interrupt,
regardless of the level of the EN bit.
The ZCDIF bit of the PIR3 register must be cleared in
software as part of the interrupt service. If another edge
is detected while this flag is being cleared, the flag will
still be set at the end of the sequence.
ZCD EVENT OFFSET
 Z cpinv
asin  -----------------
 V peak 
T
= ---------------------------------offset
2  Freq
When External Voltage Source is Relative to VDD:
 V DD – Z cpinv
asin  --------------------------------
 V peak 
= ------------------------------------------------T
offset
2  Freq
This offset time can be compensated for by adding a
pull-up or pull-down biasing resistor to the ZCD pin. A
pull-up resistor is used when the external voltage
source is varying relative to Vss. A pull-down resistor is
used when the voltage is varying relative to VDD.The
resistor adds a bias to the ZCD pin so that the target
external voltage source must go to zero to pull the pin
voltage to the ZCPINV switching voltage. The pull-up or
pull-down value can be determined with the equations
shown in Equation 20-3.
EQUATION 20-3:
ZCD PULL-UP/DOWN
When External Signal is relative to Vss:
R
R series  V pullup – Z cpinv 
= --------------------------------------------------------------------pullup
Z
cpinv
When External Signal is Relative to VDD:
R
DS40001775B-page 214
pulldown
R
Z

series cpinv
= ----------------------------------------- V DD – Z

cpinv
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
The pull-up and pull-down resistor values are
significantly affected by small variations of ZCPINV.
Measuring ZCPINV can be difficult, especially when the
waveform is relative to VDD. However, by combining
Equation 20-2 and Equation 20-3 the resistor value
can be determined from the time difference between
the ZCDOUT high and low periods. Note that the time
difference, ∆T, is 4*Toffset. The equation for determining
the pull-up and pull-down resistor values from the high
and low ZCDOUT periods is shown in Equation 20-4.
The ZCDOUT signal can be directly observed on a pin
by routing the ZCDOUT signal through one of the
CLCs.
EQUATION 20-4:
R = R


V bias


---------------------------------------------------------------- – 1

series 
 T  

 
 Vpeak  sin  Freq ----------
2 
20.6
If the peak amplitude of the external voltage is
expected to vary then the series resistor must be
selected to keep the ZCD current source and sink
below the design maximum range of ± 600 A for the
maximum expected voltage and high enough to be
detected accurately at the minimum peak voltage. A
general rule of thumb is that the maximum peak voltage
can be no more than six times the minimum peak
voltage. To ensure that the maximum current does not
exceed ± 600 A and the minimum is at least ± 100 A,
compute the series resistance as shown in
Equation 20-5. The compensating pull-up for this series
resistance can be determined with Equation 20-3
because the pull-up value is independent from the peak
voltage.
EQUATION 20-5:
SERIES R FOR V RANGE
V
+V
maxpeak
minpeak
Rseries = -----------------------------------------------------------–4
7 10
R is pull-up or pull-down resistor.
Vbias is Vpullup when R is pull-up or VDD when R is
pull-down.
∆T is the ZCDOUT high and low period difference.
Handling VPEAK variations
20.7
Operation During Sleep
The ZCD current sources and interrupts are unaffected
by Sleep.
20.8
Effects of a Reset
The ZCD circuit can be configured to default to the active
or inactive state on Power-on Reset (POR). When the
ZCD Configuration bit is cleared, the ZCD circuit will be
active at POR. When the ZCD Configuration bit is set,
the EN bit of the ZCDxCON register must be set to
enable the ZCD module.
 2014-2015 Microchip Technology Inc.
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20.9
Register Definitions: ZCD Control
Long bit name prefixes for the Zero-Cross Detect peripheral are shown in Table 20-1. Refer to Section 1.1.2.2
“Long Bit Names” for more information
TABLE 20-1:
BIT NAME PREFIXES
Peripheral
Bit Name Prefix
ZCD1
ZCD1
REGISTER 20-1:
R/W-0/0
(1)
EN
ZCDxCON: ZERO-CROSS DETECTION x CONTROL REGISTER
U-0
R-x/x
R/W-0/0
U-0
U-0
R/W-0/0
R/W-0/0
—
OUT
POL
—
—
INTP
INTN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = value depends on configuration bits
bit 7
EN: Zero-Cross Detection Enable bit(1)
1 = Zero-Cross Detect is enabled; ZCD pin is forced to output to source and sink current
0 = Zero-Cross Detect is disabled; ZCD pin operates according to PPS and TRISx controls
bit 6
Unimplemented: Read as ‘0’
bit 5
OUT: Zero-Cross Detection Logic Level bit
POL bit = 0:
1 = ZCD pin is sinking current
0 = ZCD pin is sourcing current
POL bit = 1:
1 = ZCD pin is sourcing current
0 = ZCD pin is sinking current
bit 4
POL: Zero-Cross Detection Logic Output Polarity bit
1 = ZCD logic output is inverted
0 = ZCD logic output is not inverted
bit 3-2
Unimplemented: Read as ‘0’
bit 1
INTP: Zero-Cross Positive Edge Interrupt Enable bit
1 = ZCDIF bit is set on low-to-high OUT transition
0 = ZCDIF bit is unaffected by low-to-high OUT transition
bit 0
INTN: Zero-Cross Negative Edge Interrupt Enable bit
1 = ZCDIF bit is set on high-to-low OUT transition
0 = ZCDIF bit is unaffected by high-to-low OUT transition
Note 1:
The EN bit has no effect when the ZCD Configuration bit is cleared.
DS40001775B-page 216
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
TABLE 20-2:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH THE ZCD MODULE
Bit 7
Bit 6
Bit 5
Bit 4
PIE3
PWM6IE(1)
PWM5IE
COG1IE
ZCDIE
PIR3
(1)
PWM6IF
ZCD1CON
EN
PWM5IF
COG1IF
ZCDIF
—
OUT
POL
Bit 3
Bit 1
Bit 0
Register
on page
CLC2IE
CLC1IE
107
CLC3IF
CLC2IF
CLC1IF
110
—
INTP
INTN
216
Register
on Page
Bit 2
COG2IE(1) CLC3IE
(1)
COG2IF
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the ZCD module.
Note 1: PIC16(L)F1768/9 only.
TABLE 20-3:
Name
CONFIG2
SUMMARY OF CONFIGURATION WORD WITH THE ZCD MODULE
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
13:8
—
—
LVP
DEBUG
LPBOR
BORV
STVREN
PLLEN
7:0
ZCD
—
—
—
—
PPS1WAY
WRT<1:0>
66
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the ZCD module.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 217
PIC16(L)F1764/5/8/9
NOTES:
DS40001775B-page 218
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
21.0
21.1.2
TIMER0 MODULE
8-BIT COUNTER MODE
The Timer0 module is an 8-bit timer/counter with the
following features:
In 8-Bit Counter mode, the Timer0 module will increment
on every rising or falling edge of the T0CKI pin.
•
•
•
•
•
•
8-Bit Counter mode using the T0CKI pin is selected by
setting the TMR0CS bit in the OPTION_REG register to
‘1’.
8-bit timer/counter register (TMR0)
8-bit prescaler (independent of Watchdog Timer)
Programmable internal or external clock source
Programmable external clock edge selection
Interrupt-on-overflow
TMR0 can be used to gate Timer1
The rising or falling transition of the incrementing edge
for either input source is determined by the TMR0SE bit
in the OPTION_REG register.
Figure 21-1 is a block diagram of the Timer0 module.
21.1
Timer0 Operation
The Timer0 module can be used as either an 8-bit timer
or an 8-bit counter.
21.1.1
8-BIT TIMER MODE
The Timer0 module will increment every instruction
cycle if used without a prescaler. 8-Bit Timer mode is
selected by clearing the TMR0CS bit of the
OPTION_REG register.
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
The value written to the TMR0 register
can be adjusted, in order to account for
the two instruction cycle delay when
TMR0 is written.
Note:
FIGURE 21-1:
BLOCK DIAGRAM OF TIMER0
FOSC/4
T0CKIPPS
Data Bus
0
Set TMR0IF
8
T0CKI
1
PPS
Sync
2 TCY
1
0
TMR0SE
TMR0CS
8-Bit
Prescaler
TMR0
Timer0
Overflow
PSA
8
PS<2:0>
 2014-2015 Microchip Technology Inc.
DS40001775B-page 219
PIC16(L)F1764/5/8/9
21.1.3
SOFTWARE PROGRAMMABLE
PRESCALER
A software programmable prescaler is available for
exclusive use with Timer0. The prescaler is enabled by
clearing the PSA bit of the OPTION_REG register.
Note:
The Watchdog Timer (WDT) uses its own
independent prescaler.
There are eight prescaler options for the Timer0 module,
ranging from 1:2 to 1:256. The prescale values are
selectable via the PS<2:0> bits of the OPTION_REG
register. In order to have a 1:1 prescaler value for the
Timer0 module, the prescaler must be disabled by
setting the PSA bit of the OPTION_REG register.
The prescaler is not readable or writable. All instructions
writing to the TMR0 register will clear the prescaler.
21.1.4
21.1.5
8-BIT COUNTER MODE
SYNCHRONIZATION
When in 8-Bit Counter mode, the incrementing edge on
the T0CKI pin must be synchronized to the instruction
clock. Synchronization can be accomplished by
sampling the prescaler output on the Q2 and Q4 cycles
of the instruction clock. The high and low periods of the
external clocking source must meet the timing
requirements as shown in Table 36-12: Timer0 and
Timer1 External Clock Requirements.
21.1.6
OPERATION DURING SLEEP
Timer0 cannot operate while the processor is in Sleep
mode. The contents of the TMR0 register will remain
unchanged while the processor is in Sleep mode.
TIMER0 INTERRUPT
Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The TMR0IF
interrupt flag bit of the INTCON register is set every
time the TMR0 register overflows, regardless of
whether or not the Timer0 interrupt is enabled. The
TMR0IF bit can only be cleared in software. The Timer0
interrupt enable is the TMR0IE bit of the INTCON
register.
Note:
The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
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21.2
Register Definitions: Option Register
REGISTER 21-1:
OPTION_REG: OPTION REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
R/W-1/1
R/W-1/1
R/W-1/1
PS<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
WPUEN: Weak Pull-Up Enable bit
1 = All weak pull-ups are disabled (except MCLR, if it is enabled)
0 = Weak pull-ups are enabled by individual WPUx latch values
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5
TMR0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4
TMR0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is not assigned to the Timer0 module
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS<2:0>: Prescaler Rate Select bits
TABLE 21-1:
Name
INTCON
TRISA
Timer0 Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
104
OPTION_REG WPUEN
TMR0
Bit Value
INTEDG
TMR0CS TMR0SE
PSA
PS<2:0>
221
Timer0 Module Register
—
—
219*
TRISA<5:4>
—(1)
TRISA2
TRISA<1:0>
141
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module.
* Page provides register information.
Note 1: Unimplemented, read as ‘1’.
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22.0
•
•
•
•
•
TIMER1/3/5 MODULE WITH
GATE CONTROL
The Timer1 module is a 16-bit timer/counter with the
following features:
•
•
•
•
•
•
•
•
16-Bit Timer/Counter register pair (TMR1H:TMR1L)
Programmable internal or external clock source
2-bit prescaler
Dedicated 32 kHz oscillator circuit
Optionally synchronized comparator out
Multiple Timer1 gate (count enable) sources
Interrupt-on-overflow
Wake-up on overflow (external clock,
Asynchronous mode only)
• Time base for the capture/compare function
• Auto-conversion trigger (with CCP)
FIGURE 22-1:
Selectable gate source polarity
Gate Toggle mode
Gate Single-Pulse mode
Gate value status
Gate event interrupt
Figure 22-1 is a block diagram of the Timer1 module.
This device has three instances of Timer1 type
modules. They include:
• Timer1
• Timer3
• Timer5
All references to Timer1 and Timer1 gate apply equally
to Timer3 and Timer5.
TIMER1 BLOCK DIAGRAM
T1GSS<1:0>
T1GPPS
T1G
PPS
00
T1GSPM
Timer0 Overflow
01
sync_C1OUT
10
0
t1g_in
sync_C2OUT
T1GVAL
0
Single-Pulse
11
TMR1ON
T1GTM
T1GPOL
D
Q
CK
R
Q
1
Acq. Control
1
Q1
D
Data Bus
Q
RD
T1GCON
EN
Interrupt
T1GGO/DONE
Set
TMR1GIF
det
TMR1GE
Set Flag bit
TMR1IF on
Overflow
To ADC Auto-Conversion
TMR1ON
To Comparator Module
TMR1(2)
TMR1H
EN
TMR1L
Q
D
T1CLK
Synchronized
Clock Input
0
1
TMR1CS<1:0>
SOSCO
LFINTOSC
SOSC
SOSCI
11
1
Synchronize(3)
Prescaler
1, 2, 4, 8
det
10
EN
0
T1OSCEN
T1CKIPPS
(1)
T1CKI
T1SYNC
OUT
PPS
FOSC
Internal
Clock
01
FOSC/4
Internal
Clock
00
2
T1CKPS<1:0>
FOSC/2
Internal
Clock
Sleep input
To Clock Switching Modules
Note 1: ST Buffer is high-speed type when using T1CKI.
2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
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22.1
Timer1 Operation
22.2
The Timer1 module is a 16-bit incrementing counter
which is accessed through the TMR1H:TMR1L register
pair. Writes to TMR1H or TMR1L directly update the
counter.
When used with an internal clock source, the module is
a timer and increments on every instruction cycle.
When used with an external clock source, the module
can be used as either a timer or counter and
increments on every selected edge of the external
source.
Timer1 is enabled by configuring the ON and GE bits in
the T1CON and T1GCON registers, respectively.
Table 22-1 displays the Timer1 enable selections.
TABLE 22-1:
TIMER1 ENABLE
SELECTIONS
Clock Source Selection
The CS<1:0> and OSCEN bits of the T1CON register
are used to select the clock source for Timer1.
Table 22-2 displays the clock source selections.
22.2.1
INTERNAL CLOCK SOURCE
When the internal clock source is selected, the
TMR1H:TMR1L register pair will increment on multiples
of FOSC, as determined by the Timer1 prescaler.
When the FOSC internal clock source is selected, the
Timer1 register value will increment by four counts every
instruction clock cycle. Due to this condition, a 2 LSB
error in resolution will occur when reading the Timer1
value. To utilize the full resolution of Timer1, an
asynchronous input signal must be used to gate the
Timer1 clock input.
The following asynchronous sources may be used:
Timer1
Operation
• Asynchronous event on the T1G pin to Timer1 gate
• C1 or C2 comparator input to Timer1 gate
TMR1ON
TMR1GE
0
0
Off
22.2.2
0
1
Off
1
0
Always On
When the external clock source is selected, the Timer1
module may work as a timer or a counter.
1
1
Count Enabled
EXTERNAL CLOCK SOURCE
When enabled to count, Timer1 is incremented on the
rising edge of the external clock input T1CKI, which can
be synchronized to the microcontroller system clock or
can run asynchronously.
When used as a timer with a clock oscillator, an
external 32.768 kHz crystal can be used in conjunction
with the dedicated internal oscillator circuit.
Note:
In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge after any one or
more of the following conditions:
•
•
•
•
TABLE 22-2:
Timer1 enabled after POR
Write to TMR1H or TMR1L
Timer1 is disabled
Timer1 is disabled (TMR1ON = 0) when
T1CKI is high then Timer1 is enabled
(TMR1ON = 1) when T1CKI is low
CLOCK SOURCE SELECTIONS
TMR1CS<1:0>
T1OSCEN
Clock Source
11
x
LFINTOSC
10
0
External Clocking on T1CKI Pin
01
x
System Clock (FOSC)
00
x
Instruction Clock (FOSC/4)
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22.3
Timer1 Prescaler
Timer1 has four prescaler options, allowing 1, 2, 4 or 8
divisions of the clock input. The CKPS<1:0> bits of the
T1CON register control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write to
TMR1H or TMR1L.
22.4
Timer1 (Secondary) Oscillator
A dedicated low-power 32.768 kHz oscillator circuit is
built in between pins, SOSCI (input) and SOSCO
(amplifier output). This internal circuit is to be used in
conjunction with an external 32.768 kHz crystal.
The oscillator circuit is enabled by setting the OSCEN
bit of the T1CON register. The oscillator will continue to
run during Sleep.
Note:
22.5
The oscillator requires a start-up and
stabilization time before use. Thus,
OSCEN should be set and a suitable
delay observed prior to using Timer1. A
suitable delay similar to the OST delay
can be implemented in software by
clearing the TMR1IF bit then presetting
the TMR1H:TMR1L register pair to
FC00h. The TMR1IF flag will be set when
1024 clock cycles have elapsed, thereby
indicating that the oscillator is running and
reasonably stable.
Timer1 Operation in
Asynchronous Counter Mode
If the control bit, SYNC of the T1CON register, is set,
the external clock input is not synchronized. The timer
increments asynchronously to the internal phase
clocks. If the external clock source is selected then the
timer will continue to run during Sleep and can
generate an interrupt-on-overflow, which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer (see
Section 22.5.1 “Reading and Writing Timer1 in
Asynchronous Counter Mode”).
Note:
22.5.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER MODE
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the TMR1H:TMR1L register pair.
22.6
Timer1 Gate
Timer1 can be configured to count freely or the count
can be enabled and disabled using Timer1 gate
circuitry. This is also referred to as Timer1 Gate Enable.
Timer1 gate can also be driven by multiple selectable
sources.
22.6.1
TIMER1 GATE ENABLE
The Timer1 Gate Enable mode is enabled by setting
the GE bit of the T1GCON register. The polarity of the
Timer1 Gate Enable mode is configured using the
GPOL bit of the T1GCON register.
When Timer1 Gate Enable mode is enabled, Timer1
will increment on the rising edge of the Timer1 clock
source. When Timer1 Gate Enable mode is disabled,
no incrementing will occur and Timer1 will hold the
current count. See Figure 22-3 for timing details.
TABLE 22-3:
TIMER1 GATE ENABLE
SELECTIONS
T1CLK
T1GPOL
T1G
Timer1 Operation

0
0
Counts

0
1
Holds Count

1
0
Holds Count

1
1
Counts
When switching from synchronous to
asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce an additional
increment.
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22.6.2
TIMER1 GATE SOURCE
SELECTION
Timer1 gate source selections are shown in Table 22-4.
Source selection is controlled by the T1GSS bits of the
T1GCON register. The polarity for each available source
is also selectable. Polarity selection is controlled by the
T1GPOL bit of the T1GCON register.
TABLE 22-4:
T1GSS<1:0>
TIMER1 GATE SOURCES
Timer1 Gate Source
00
Timer1 Gate Pin
01
Overflow of Timer0
(TMR0 increments from FFh to 00h)
10
Comparator 1 Output sync_C1OUT
(optionally Timer1 synchronized output)
11
Comparator 2 Output sync_C2OUT
(optionally Timer1 synchronized output)
22.6.2.1
T1G Pin Gate Operation
The T1G pin is one source for Timer1 gate control. It
can be used to supply an external source to the Timer1
gate circuitry.
22.6.2.2
Timer0 Overflow Gate Operation
When Timer0 increments from FFh to 00h, a
low-to-high pulse will automatically be generated and
internally supplied to the Timer1 gate circuitry.
22.6.2.3
Comparator C1 Gate Operation
The output resulting from a Comparator 1 operation can
be selected as a source for Timer1 gate control. The
Comparator 1 output (sync_C1OUT) can be
synchronized to the Timer1 clock or left asynchronous.
For more information, see Section 19.4.1 “Comparator
Output Synchronization”.
22.6.2.4
Comparator C2 Gate Operation
The output resulting from a Comparator 2 operation
can be selected as a source for Timer1 gate control.
The Comparator 2 output (sync_C2OUT) can be
synchronized to the Timer1 clock or left asynchronous.
For more information, see Section 19.4.1 “Comparator
Output Synchronization”.
22.6.3
TIMER1 GATE TOGGLE MODE
When Timer1 Gate Toggle mode is enabled, it is
possible to measure the full-cycle length of a Timer1
gate signal, as opposed to the duration of a single level
pulse.
Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
Note:
22.6.4
Enabling Toggle mode at the same time
as changing the gate polarity may result in
indeterminate operation.
TIMER1 GATE SINGLE-PULSE
MODE
When Timer1 Gate Single-Pulse mode is enabled, it is
possible to capture a single-pulse gate event. Timer1
Gate Single-Pulse mode is first enabled by setting the
T1GSPM bit in the T1GCON register. Next, the
T1GGO/DONE bit in the T1GCON register must be set.
The Timer1 will be fully enabled on the next
incrementing edge. On the next trailing edge of the
pulse, the T1GGO/DONE bit will automatically be
cleared. No other gate events will be allowed to
increment Timer1 until the T1GGO/DONE bit is once
again set in software. See Figure 22-5 for timing details.
If the Single-Pulse Gate mode is disabled by clearing the
T1GSPM bit in the T1GCON register, the T1GGO/DONE
bit should also be cleared.
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
together. This allows the cycle times on the Timer1 gate
source to be measured. See Figure 22-6 for timing
details.
22.6.5
TIMER1 GATE VALUE STATUS
When Timer1 gate value status is utilized, it is possible
to read the most current level of the gate control value.
The value is stored in the T1GVAL bit in the T1GCON
register. The T1GVAL bit is valid even when the Timer1
gate is not enabled (TMR1GE bit is cleared).
22.6.6
TIMER1 GATE EVENT INTERRUPT
When Timer1 Gate Event Interrupt is enabled, it is
possible to generate an interrupt upon the completion
of a gate event. When the falling edge of T1GVAL
occurs, the TMR1GIF flag bit in the PIR1 register will be
set. If the TMR1GIE bit in the PIE1 register is set, then
an interrupt will be recognized.
The TMR1GIF flag bit operates even when the Timer1
gate is not enabled (TMR1GE bit is cleared).
The Timer1 gate source is routed through a flip-flop that
changes state on every incrementing edge of the
signal. See Figure 22-4 for timing details.
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22.7
Timer1 Interrupt
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit of the PIR1 register is
set. To enable the interrupt-on-rollover, you must set
these bits:
•
•
•
•
ON bit of the T1CON register
TMR1IE bit of the PIE1 register
PEIE bit of the INTCON register
GIE bit of the INTCON register
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.
Note:
22.8
The TMR1H:TMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device:
•
•
•
•
•
ON bit of the T1CON register must be set
TMR1IE bit of the PIE1 register must be set
PEIE bit of the INTCON register must be set
SYNC bit of the T1CON register must be set
CS<1:0> bits of the T1CON register must be
configured
• OSCEN bit of the T1CON register must be
configured
The device will wake-up on an overflow and execute
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine.
22.9
CCP Capture/Compare Time Base
The CCP modules use the TMR1H:TMR1L register
pair as the time base when operating in Capture or
Compare mode.
In Capture mode, the value in the TMR1H:TMR1L
register pair is copied into the CCPR1H:CCPR1L
register pair on a configured event.
In Compare mode, an event is triggered when the value
CCPR1H:CCPR1L register pair matches the value in
the TMR1H:TMR1L register pair. This event can be an
Auto-conversion Trigger.
For
more
information,
see
Section 24.0
“Capture/Compare/PWM Modules”.
22.10 CCP Auto-Conversion Trigger
When any of the CCPs are configured to trigger an
auto-conversion, the trigger will clear the
TMR1H:TMR1L register pair. This auto-conversion
does not cause a Timer1 interrupt. The CCP module
may still be configured to generate a CCP interrupt.
In this mode of operation, the CCPR1H:CCPR1L
register pair becomes the period register for Timer1.
Timer1 should be synchronized and FOSC/4 should be
selected as the clock source in order to utilize the
Auto-conversion Trigger. Asynchronous operation of
Timer1 can cause an Auto-conversion Trigger to be
missed.
In the event that a write to TMR1H or TMR1L coincides
with an Auto-conversion Trigger from the CCP, the
write will take precedence.
For
more
information,
see
“Auto-Conversion Trigger”.
Section 24.2.1
The secondary oscillator will continue to operate in
Sleep regardless of the SYNC bit setting.
FIGURE 22-2:
TIMER1 INCREMENTING EDGE
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1:
2:
Arrows indicate counter increments.
In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge
of the clock.
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FIGURE 22-3:
TIMER1 GATE ENABLE MODE
TMR1GE
T1GPOL
t1g_in
T1CKI
T1GVAL
Timer1
N
FIGURE 22-4:
N+1
N+2
N+3
N+4
TIMER1 GATE TOGGLE MODE
TMR1GE
T1GPOL
T1GTM
t1g_in
T1CKI
T1GVAL
Timer1
N
 2014-2015 Microchip Technology Inc.
N+1 N+2 N+3
N+4
N+5 N+6 N+7
N+8
DS40001775B-page 227
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FIGURE 22-5:
TIMER1 GATE SINGLE-PULSE MODE
TMR1GE
T1GPOL
T1GSPM
T1GGO/
DONE
Cleared by Hardware on
Falling Edge of T1GVAL
Set by Software
Counting Enabled on
Rising Edge of T1G
t1g_in
T1CKI
T1GVAL
Timer1
TMR1GIF
DS40001775B-page 228
N
Cleared by Software
N+1
N+2
Set by Hardware on
Falling Edge of T1GVAL
Cleared by
Software
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FIGURE 22-6:
TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
TMR1GE
T1GPOL
T1GSPM
T1GTM
T1GGO/
DONE
Cleared by Hardware on
Falling Edge of T1GVAL
Set by Software
Counting Enabled on
Rising Edge of T1G
t1g_in
T1CKI
T1GVAL
Timer1
TMR1GIF
N
Cleared by Software
 2014-2015 Microchip Technology Inc.
N+1
N+2
N+3
Set by Hardware on
Falling Edge of T1GVAL
N+4
Cleared by
Software
DS40001775B-page 229
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22.11 Register Definitions: Timer1 Control
Long bit name prefixes for the Timer1 peripherals are
shown in Table 22-5. Refer to Section 1.1.2.2 “Long
Bit Names” for more information.
TABLE 22-5:
BIT NAME PREFIXES
Peripheral
Bit Name Prefix
Timer1
T1
Timer3
T3
Timer5
T5
REGISTER 22-1:
R/W-0/u
T1CON: TIMER1 CONTROL REGISTER
R/W-0/u
CS<1:0>
R/W-0/u
R/W-0/u
CKPS<1:0>
R/W-0/u
(1)
OSCEN
R/W-0/u
U-0
R/W-0/u
SYNC
—
ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
CS<1:0>: Timer1 Clock Source Select bits
11 = Reserved, do not use
10 = Timer1 clock source is a pin or oscillator:(1)
If T1OSCEN = 0:
External clock from T1CKI pin (on the rising edge).
If T1OSCEN = 1:
Crystal oscillator on SOSCI/SOSCO pins.
01 = Timer1 clock source is the system clock (FOSC)
00 = Timer1 clock source is the instruction clock (FOSC/4)
bit 5-4
CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3
OSCEN: LP Oscillator Enable Control bit(1)
1 = Dedicated secondary oscillator circuit is enabled
0 = Dedicated secondary oscillator circuit is disabled
bit 2
SYNC: Timer1 Synchronization Control bit
1 = Does not synchronize asynchronous clock input
0 = Synchronizes asynchronous clock input with system clock (FOSC)
bit 1
Unimplemented: Read as ‘0’
bit 0
ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1 and clears Timer1 gate flip-flop
Note 1:
Timer1 only. Reserved, do not use for Timer3 and Timer5.
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REGISTER 22-2:
T1GCON: TIMER1 GATE CONTROL REGISTER
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W/HC-0/u
R-x/x
GE
GPOL
GTM
GSPM
GGO/
DONE
GVAL
R/W-0/u
R/W-0/u
GSS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HC = Hardware Clearable bit
bit 7
GE: Timer1 Gate Enable bit
If TMR1ON = 0:
This bit is ignored.
If TMR1ON = 1:
1 = Timer1 counting is controlled by the Timer1 gate function
0 = Timer1 counts regardless of Timer1 gate function
bit 6
GPOL: Timer1 Gate Polarity bit
1 = Timer1 gate is active-high (Timer1 counts when gate is high)
0 = Timer1 gate is active-low (Timer1 counts when gate is low)
bit 5
GTM: Timer1 Gate Toggle Mode bit
1 = Timer1 Gate Toggle mode is enabled
0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared
Timer1 gate flip-flop toggles on every rising edge.
bit 4
GSPM: Timer1 Gate Single-Pulse Mode bit
1 = Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate
0 = Timer1 Gate Single-Pulse mode is disabled
bit 3
GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit
1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge
0 = Timer1 gate single-pulse acquisition has completed or has not been started
bit 2
GVAL: Timer1 Gate Value Status bit
Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L. Unaffected by
Timer1 Gate Enable bit (TMR1GE).
bit 1-0
GSS<1:0>: Timer1 Gate Source Select bits
11 = Comparator 2 optionally synchronized output (sync_C2OUT)
10 = Comparator 1 optionally synchronized output (sync_C1OUT)
01 = Timer0 overflow output
00 = Timer1 gate pin
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TABLE 22-6:
Name
ANSELA
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
—
—
—
ANSA4
—
Bit 2
Bit 1
Bit 0
ANSA<2:0>
Register
on Page
142
CCPxCON
EN
OE
OUT
FMT
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
MODE<3:0>
INTF
IOCIF
261
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
105
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
108
104
TMRxH
Holding Register for the Most Significant Byte of the 16-bit TMR1/3/5 Register
222*
TMRxL
Holding Register for the Least Significant Byte of the 16-bit TMR1/3/5 Register
222*
TRISA
TxCON
TxGCON
Legend:
*
Note 1:
2:
—
—
CS<1:0>
GE
GPOL
TRISA<5:4>
CKPS<1:0>
GTM
GSPM
(1)
—
TRISA<2:0>
OSCEN
SYNC
GGO/
DONE
GVAL
—
141
ON
GSS<1:0>
230
231
— = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module.
Page provides register information.
Unimplemented, read as ‘1’.
PIC16(L)F1768/9 only.
DS40001775B-page 232
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
23.0
• Three modes of operation:
- Free-Running Period
- One-Shot
- Monostable
TIMER2/4/6 MODULE
The Timer2/4/6 modules are 8-bit timers that can operate as free-running period counters or in conjunction
with external signals that control Start, Run, Freeze and
Reset operation in One-Shot and Monostable modes of
operation. Sophisticated waveform control, such as
pulse density modulation, are possible by combining
the operation of these timers with other internal peripherals, such as the comparators and CCP modules.
Features of the timer include:
•
•
•
•
•
•
•
•
See Figure 23-1 for a block diagram of Timer2. See
Figure 23-2 for the clock source block diagram.
Note:
8-Bit Timer register
8-Bit Period register
Selectable external hardware timer Resets
Programmable prescaler (1:1 to 1:128)
Programmable postscaler (1:1 to 1:16)
Selectable synchronous/asynchronous operation
Alternate clock sources
Interrupt-on-period
FIGURE 23-1:
TIMER2 BLOCK DIAGRAM
RSEL
TxINPPS
TxIN
PPS
External Reset
Sources
(Table 23-4)
Three identical Timer2 modules are
implemented on this device. The timers are
named Timer2, Timer4 and Timer6. All
references to Timer2 apply as well to
Timer4 and Timer6. All references to T2PR
apply as well to T4PR and T6PR.
Rev. 10-000 168B
5/29/201 4
MODE<4:0>
TMRx_ers
Edg e Detecto r
Level Dete ctor
Mode Control
(2 clock Sync)
MODE<3>
reset
CCP_pset
MODE<4:3>=01
enable
D
MODE<4:1>=1011
Q
Clear ON
CKPOL
0
Pre scaler
TMRx_clk
TMRx
3
CKPS<2:0>
Sync
1
Fosc/4
PSYNC
R
Set flag bi t
TMRxIF
Comparator
Postscaler
TMRx_postscaled
4
ON
Sync
(2 Clocks)
1
PRx
OUTPS<3:0>
0
CKSYNC
Note 1:
2:
Signal to the CCP to trigger the PWM pulse
See Section 22.5 for description of CCP interaction in the different TMR modes
 2014-2015 Microchip Technology Inc.
DS40001775B-page 233
PIC16(L)F1764/5/8/9
FIGURE 23-2:
TIMER2 CLOCK SOURCE
BLOCK DIAGRAM
TxCLKCON
Rev. 10-000 169B
5/29/201 4
TXINPPS
TXIN
the OUTPS<4:0> bits of the TMRxCON1 register then a
one clock period wide pulse occurs on the
TMR2_postscaled output, and the postscaler count is
cleared.
23.1.2
PPS
Timer Clock Sources
(See Table 23-3)
TMR2_clk
ONE-SHOT MODE
The One-Shot mode is identical to the Free-Running
Period mode except that the ON bit is cleared and the
timer is stopped when TMR2 matches T2PR, and will
not restart until the T2ON bit is cycled off and on.
Postscaler OUTPS<4:0> values other than 0 are
meaningless in this mode because the timer is stopped
at the first period event and the postscaler is reset
when the timer is restarted.
23.1.3
MONOSTABLE MODE
Monostable modes are similar to One-Shot modes
except that the ON bit is not cleared and the timer can
be restarted by an external Reset event.
23.1
Timer2 Operation
Timer2 operates in three major modes:
23.2
• Free-Running Period
• One-Shot
• Monostable
The
Timer2
module’s
primary
output
is
TMR2_postscaled, which pulses for a single TMR2_clk
period when the postscaler counter matches the value
in the OUTPS bits of the TMR2xCON register. The
T2PR postscaler is incremented each time the TMR2
value matches the T2PR value. This signal can be
selected as an input to several other input modules:
Within each mode, there are several options for starting,
stopping and resetting. Table 23-1 lists the options.
In all modes, the TMR2 Count register is incremented
on the rising edge of the clock signal from the programmable prescaler. When TMR2 equals T2PR, a high
level is output to the postscaler counter. TMR2 is
cleared on the next clock input.
An external signal from hardware can also be configured to gate the timer operation or force a TMR2 count
Reset. In Gate modes the counter stops when the gate
is disabled and resumes when the gate is enabled. In
Reset modes the TMR2 count is reset on either the
level or edge from the external source.
The TMR2 and T2PR registers are both directly readable and writable. The TMR2 register is cleared and the
T2PR register initializes to FFh on any device Reset.
Both the prescaler and postscaler counters are cleared
on the following events:
•
•
•
•
A write to the TMR2 register
A write to the T2CON register
Any device Reset
External Reset source event that resets the timer.
Note:
23.1.1
TMR2 is not cleared when T2CON is
written.
FREE-RUNNING PERIOD MODE
The value of TMR2 is compared to that of the Period register, T2PR, on each clock cycle. When the two values
match, the comparator resets the value of TMR2 to 00h
on the next cycle and increments the output postscaler
counter. When the postscaler count equals the value in
DS40001775B-page 234
Timer2 Output
• The ADC module as an auto-conversion trigger
• COG as an auto-shutdown source
In addition, the Timer2 is also used by the CCP module
for pulse generation in PWM mode. Both the actual
TMR2 value as well as other internal signals are sent to
the CCP module to properly clock both the period and
pulse width of the PWM signal. See Section 24.6
“CCP/PWM Clock Selection” for more details on
setting up Timer2 for use with the CCP, as well as
the timing diagrams in Section 23.6 “Operation
Examples” for examples of how the varying Timer2
modes affect CCP PWM output.
23.3
External Reset Sources
In addition to the clock source, the Timer2 also takes in
an external Reset source. This external Reset source
is selected for Timer2, Timer4 and Timer6, with the
T2RST, T4RST and T6RST registers, respectively.
This source can control starting and stopping of the
timer, as well as resetting the timer, depending on
which mode the timer is in. The mode of the timer is
controlled by the MODE<4:0> bits of the TMRxHLT
register. Edge-Triggered modes require six timer clock
periods between external triggers. Level-Triggered
modes require the triggering level to be at least three
timer clock periods long. External triggers are ignored
while in Debug Freeze mode.
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
23.4
Operating Modes
TABLE 23-1:
TIMER2 OPERATING MODES
MODE<4:0>
Mode
<4:3> <2:0>
Output
Operation
ON = 1
—
ON = 0
001
ON = 1 and
TMRx_ers = 1
—
ON = 0 or
TMRx_ers = 0
Hardware gate, active-low
ON = 1 and
TMRx_ers = 0
—
ON = 0 or
TMRx_ers = 1
Period Pulse
011
Rising or falling edge Reset
TMRx_ers ↕
100
Rising edge Reset (Figure 23-6)
TMRx_ers ↑
Falling edge Reset
TMRx_ers ↓
110
Period
Pulse
with
Hardware
Reset
000
001
010
One-Shot
EdgeTriggered
Start
(Note 1)
011
01
100
101
110
111
EdgeTriggered
Start
and
Hardware
Reset
(Note 1)
010
Reserved
111
Reserved
Note 1:
11
ON = 0 or
TMRx_ers = 1
ON = 1
—
Rising edge start (Figure 23-9)
—
Falling edge start
ON = 1 and
TMRx_ers ↓
—
Any edge start
ON = 1 and
TMRx_ers ↕
—
Rising edge start and
rising edge Reset (Figure 23-10)
ON = 1 and
TMRx_ers ↑
TMRx_ers ↑
Falling edge start and
falling edge Reset
ON = 1 and
TMRx_ers ↓
TMRx_ers ↓
Rising edge start and
low-level Reset (Figure 23-11)
ON = 1 and
TMRx_ers ↑
TMRx_ers = 0
Falling edge start and
high-level Reset
ON = 1 and
TMRx_ers ↓
TMRx_ers = 1
EdgeTriggered
Start
(Note 1)
Rising edge start
(Figure 23-12)
ON = 1 and
TMRx_ers ↑
—
Falling edge start
ON = 1 and
TMRx_ers ↓
—
Any edge start
ON = 1 and
TMRx_ers ↕
—
ON = 0
or
next clock after
TMRx = PRx
(Note 2)
ON = 0
or
next clock after
TMRx = PRx
(Note 3)
Reserved
100
One-shot
TMRx_ers = 1
ON = 1 and
TMRx_ers ↑
Reserved
101
110
ON = 0 or
TMRx_ers = 0
Reserved
011
10
ON = 0
TMRx_ers = 0
Software start (Figure 23-8)
000
001
ON = 1
Low-level Reset
High-level Reset (Figure 23-7)
111
Reserved
Stop
Hardware gate, active-high
(Figure 23-5)
00
Mono-stable
Reset
Software gate (Figure 23-4)
101
One-Shot
Start
000
010
Free-Running
Period
Timer Control
Operation
LevelTriggered
Start
and
Hardware
Reset
xxx
High-level start and
low-level Reset (Figure 23-13)
ON = 1 and
TMRx_ers = 1
TMRx_ers = 0
Low-level start and
high-level Reset
ON = 1 and
TMRx_ers = 0
TMRx_ers = 1
ON = 0 or
held in Reset
(Note 2)
Reserved
If ON = 0, then an edge is required to restart the timer after ON = 1.
2:
When TMRx = PRx, then the next clock clears ON and stops TMRx at 00h.
3:
When TMRx = PRx, then the next clock stops TMRx at 00h but does not clear ON.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 235
PIC16(L)F1764/5/8/9
23.5
Timer2 Interrupt
Timer2 can also generate a device interrupt. The
interrupt is generated when the postscaler counter
matches one of 16 postscale options (from 1:1 through
1:16), which are selected with the postscaler control
bits, OUTPS<3:0> of the T2CON register. The interrupt
is enabled by setting the TMR2IE interrupt enable bit of
the PIE1 register. Interrupt timing is illustrated in
Figure 23-3.
FIGURE 23-3:
TIMER2 PRESCALER, POSTSCALER AND INTERRUPT TIMING DIAGRAM
CKPS
0b010
PRx
1
OUTPS
2
TMRx_clk
TMRx
0
1
0
1
0
1
0
TMRx_postscaled
(1)
TMRxIF
Note 1:
Setting the interrupt flag is synchronized with the instruction clock.
Synchronization may take as many as 2 instruction cycles
DS40001775B-page 236
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
23.6
23.6.1
Operation Examples
This mode corresponds to legacy Timer2 operation.
The timer increments with each clock input when
ON = 1 and does not increment when ON = 0. When
the TMRx count equals the PRx period count, the timer
resets on the next clock and continues counting from 0.
Operation with the ON bit software controlled is illustrated in Figure 23-4. With PRx = 5, the counter
advances until TMRx = 5, and goes to zero with the
next clock.
Unless otherwise specified, the following notes apply to
the following timing diagrams:
- Both the prescaler and postscaler are set to
1:1 (both the CKPSx and OUTPSx bits in the
TxCON register are cleared).
- The diagrams illustrate any clock except
FOSC/4 and show clock-sync delays of at
least two full cycles for both ON and
Timer2_ers. When using FOSC/4, the
clock-sync delay is at least one instruction
period for Timer2_ers; ON applies in the next
instruction period.
- The PWM duty cycle and PWM output are
illustrated assuming that the timer is used for
the PWM function of the CCP module, as
described in Section 24.6 “CCP/PWM Clock
Selection”. The signals are not a part of the
Timer2 module.
FIGURE 23-4:
SOFTWARE GATE MODE
SOFTWARE GATE MODE TIMING DIAGRAM (MODE<4:0> = 00000)
Rev. 10-000195B
5/30/2014
0b00000
MODE
TMRx_clk
Instruction(1)
BSF
BCF
BSF
ON
PRx
TMRx
5
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
5
0
1
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note
1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 237
PIC16(L)F1764/5/8/9
23.6.2
HARDWARE GATE MODE
When MODE<4:0> = 00001, then the timer is stopped
when the external signal is high. When
MODE<4:0> = 00010, then the timer is stopped when
the external signal is low.
The Hardware Gate modes operate the same as the
Software Gate mode, except the TMRx_ers external
signal can also gate the timer. When used with the
CCP, the gating extends the PWM period. If the timer is
stopped when the PWM output is high, then the duty
cycle is also extended.
FIGURE 23-5:
Figure 23-5 illustrates the Hardware Gating mode for
MODE<4:0> = 00001 in which a high input level starts
the counter.
HARDWARE GATE MODE TIMING DIAGRAM (MODE<4:0> = 00001)
Rev. 10-000 196B
5/30/201 4
MODE
0b00001
TMRx_clk
TMRx_ers
5
PRx
TMRx
0
1
2
3
4
5
0
1
2
3
4
5
0
1
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
DS40001775B-page 238
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
23.6.3
EDGE-TRIGGERED HARDWARE
LIMIT MODE
When the timer is used in conjunction with the CCP in
PWM mode, then an early Reset shortens the period
and restarts the PWM pulse after a two-clock delay.
Refer to Figure 23-6.
In Hardware Limit mode, the timer can be reset by the
TMRx_ers external signal before the timer reaches the
period count. Three types of Resets are possible:
• Reset on rising or falling edge
(MODE<4:0>= 00011)
• Reset on rising edge (MODE<4:0> = 00100)
• Reset on falling edge (MODE<4:0> = 00101)
FIGURE 23-6:
EDGE-TRIGGERED HARDWARE LIMIT MODE TIMING DIAGRAM
(MODE<4:0> = 00100)
Rev. 10-000 197B
5/30/201 4
0b00100
MODE
TMRx_clk
PRx
5
Instruction(1)
BSF
BCF
BSF
ON
TMRx_ers
TMRx
0
1
2
0
1
2
3
4
5
0
1
2
3
4
5
0
1
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note
1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 239
PIC16(L)F1764/5/8/9
23.6.4
LEVEL-TRIGGERED HARDWARE
LIMIT MODE
When the CCP uses the timer as the PWM time base,
then the PWM output will be set high when the timer
starts counting and then set low only when the timer
count matches the CCPRx value. The timer is reset
when either the timer count matches the PRx value or
two clock periods after the external Reset signal goes
true and stays true.
In the Level-Triggered Hardware Limit Timer modes,
the counter is reset by high or low levels of the external
signal, TMRx_ers, as shown in Figure 23-7. Selecting
MODE<4:0> = 00110 will cause the timer to reset on a
low-level external signal. Selecting MODE<4:0> = 00111
will cause the timer to reset on a high-level external
signal. In the example, the counter is reset while
TMRx_ers = 1. ON is controlled by BSF and BCF
instructions. When ON = 0, the external signal is
ignored.
FIGURE 23-7:
The timer starts counting, and the PWM output is set
high, on either the clock following the PRx match or two
clocks after the external Reset signal relinquishes the
Reset. The PWM output will remain high until the timer
counts up to match the CCPRx pulse-width value. If the
external Reset signal goes true while the PWM output
is high then the PWM output will remain high until the
Reset signal is released allowing the timer to count up
to match the CCPRx value.
LEVEL-TRIGGERED HARDWARE LIMIT MODE TIMING DIAGRAM
(MODE<4:0> = 00111)
Rev. 10-000198B
5/30/2014
0b00111
MODE
TMRx_clk
5
PRx
Instruction(1)
BSF
BCF
BSF
ON
TMRx_ers
0
TMRx
1
2
0
1
2
3
4
5
0
0
1
2
3
4
5
0
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note
1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
DS40001775B-page 240
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
23.6.5
SOFTWARE START ONE-SHOT
MODE
When One-Shot mode is used in conjunction with the
CCP PWM operation, the PWM pulse drive starts concurrent with setting the ON bit. Clearing the ON bit
while the PWM drive is active will extend the PWM
drive. The PWM drive will terminate when the timer
value matches the CCPRx pulse-width value. The
PWM drive will remain off until software sets the ON bit
to start another cycle. If software clears the ON bit after
the CCPRx match, but before the PRx match, then the
PWM drive will be extended by the length of time the
ON bit remains cleared. Another timing cycle can only
be initiated by setting the ON bit after it has been
cleared by a PRx period count match.
In One-Shot mode, the timer resets and the ON bit is
cleared when the timer value matches the PRx period
value. The ON bit must be set by software to start
another timer cycle. Setting MODE<4:0> = 01000
selects One-Shot mode, which is illustrated in
Figure 23-8. In the example, ON is controlled by the
BSF and BCF instructions. In the first case, a BSF
instruction sets ON and the counter runs to completion
and clears ON. In the second case, a BSF instruction
starts the cycle, BCF/BSF instructions turn the counter
off and on during the cycle, and then it runs to
completion.
FIGURE 23-8:
SOFTWARE START ONE-SHOT MODE TIMING DIAGRAM (MODE<4:0> = 01000)
Rev. 10-000198B
5/30/2014
0b00111
MODE
TMRx_clk
5
PRx
Instruction(1)
BSF
BCF
BSF
ON
TMRx_ers
TMRx
0
1
2
0
1
2
3
4
5
0
0
1
2
3
4
5
0
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note
1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 241
PIC16(L)F1764/5/8/9
23.6.6
EDGE-TRIGGERED ONE-SHOT
MODE
If the timer is halted by clearing the ON bit, then another
TMRx_ers edge is required after the ON bit is set to
resume counting. Figure 23-9 illustrates operation in
the rising edge One-Shot mode.
The Edge-Triggered One-Shot modes start the timer
on an edge from the external signal input, after the ON
bit is set, and clear the ON bit when the timer matches
the PRx period value. The following edges will start the
timer:
• Rising edge (MODE<4:0> = 01001)
• Falling edge (MODE<4:0> = 01010)
• Rising or falling edge (MODE<4:0> = 01011)
FIGURE 23-9:
When Edge-Triggered One-Shot mode is used in
conjunction with the CCP, then the edge-trigger will
activate the PWM drive and the PWM drive will
deactivate when the timer matches the CCPRx
pulse-width value and stay deactivated when the timer
halts at the PRx period count match.
EDGE-TRIGGERED ONE-SHOT MODE TIMING DIAGRAM (MODE<4:0> = 01001)
Rev. 10-000200B
5/30/2014
0b01001
MODE
TMRx_clk
5
PRx
Instruction(1)
BSF
BSF
BCF
ON
TMRx_ers
TMRx
0
1
2
3
4
5
0
1
2
TMRx_out
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note
DS40001775B-page 242
1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
23.6.7
EDGE-TRIGGERED HARDWARE
LIMIT ONE-SHOT MODE
In Edge-Triggered Hardware Limit One-Shot modes,
the timer starts on the first external signal edge after the
ON bit is set and resets on all subsequent edges. Only
the first edge after the ON bit is set is needed to start
the timer. The counter will resume counting automatically, two clocks after all subsequent external Reset
edges. Edge triggers are as follows:
• Rising edge start and Reset
(MODE<4:0> = 01100)
• Falling edge start and Reset
(MODE<4:0> = 01101)
FIGURE 23-10:
The timer resets and clears the ON bit when the timer
value matches the PRx period value. External signal
edges will have no effect until after software sets the
ON bit. Figure 23-10 illustrates the rising edge hardware limit one-shot operation.
When this mode is used in conjunction with the CCP
then the first starting edge trigger, and all subsequent
Reset edges, will activate the PWM drive. The PWM
drive will deactivate when the timer matches the
CCPRx pulse-width value and stay deactivated until
the timer halts at the PRx period match unless an external signal edge resets the timer before the match
occurs.
EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM
(MODE<4:0> = 01100)
Rev. 10-000 201B
5/30/201 4
0b01100
MODE
TMRx_clk
5
PRx
Instruction(1)
BSF
BSF
ON
TMRx_ers
0
TMRx
1
2
3
4
5
0
1
2
0
1
2
3
4
5
0
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note
1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 243
PIC16(L)F1764/5/8/9
23.6.8
LEVEL RESET, EDGE-TRIGGERED
HARDWARE LIMIT ONE-SHOT
MODES
When the timer count matches the PRx period count,
the timer is reset and the ON bit is cleared. When the
ON bit is cleared by either a PRx match or by software
control, a new external signal edge is required after the
ON bit is set to start the counter.
In Level-Triggered One-Shot mode, the timer count is
reset on the external signal level and starts counting on
the rising/falling edge of the transition from Reset level
to the active level while the ON bit is set. Reset levels
are selected as follows:
When Level-Triggered Reset One-Shot mode is used
in conjunction with the CCP PWM operation, the PWM
drive goes active with the external signal edge that
starts the timer. The PWM drive goes inactive when the
timer count equals the CCPRx pulse-width count. The
PWM drive does not go active when the timer count
clears at the PRx period count match.
• Low Reset level (MODE<4:0> = 01110)
• High Reset level (MODE<4:0> = 01111)
FIGURE 23-11:
LOW-LEVEL RESET, EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE
TIMING DIAGRAM (MODE<4:0> = 01110)
Rev. 10-000 202B
5/30/201 4
MODE
0b01110
TMRx_clk
PRx
Instruction(1)
5
BSF
BSF
ON
TMRx_ers
TMRx
0
1
2
3
4
5
0
1
0
1
2
3
4
5
0
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note
DS40001775B-page 244
1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
23.6.9
EDGE-TRIGGERED MONOSTABLE
MODES
When an Edge-Triggered Monostable mode is used in
conjunction with the CCP PWM operation, the PWM
drive goes active with the external Reset signal edge
that starts the timer, but will not go active when the
timer matches the PRx value. While the timer is incrementing, additional edges on the external Reset signal
will not affect the CCP PWM.
The Edge-Triggered Monostable modes start the timer
on an edge from the external Reset signal input, after
the ON bit is set, and stop incrementing the timer when
the timer matches the PRx period value. The following
edges will start the timer:
• Rising edge (MODE<4:0> = 10001)
• Falling edge (MODE<4:0> = 10010)
• Rising or falling edge (MODE<4:0> = 10011)
FIGURE 23-12:
RISING EDGE-TRIGGERED MONOSTABLE MODE TIMING DIAGRAM
(MODE<4:0> = 10001)
Rev. 10-000203A
5/29/2014
0b10001
MODE
TMRx_clk
5
PRx
(1)
Instruction
BSF
BCF
BSF
BCF
BSF
ON
TMRx_ers
TMRx
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
5
0
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note
1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 245
PIC16(L)F1764/5/8/9
23.6.10
LEVEL-TRIGGERED HARDWARE
LIMIT ONE-SHOT MODES
When the timer count matches the PRx period count,
the timer is reset and the ON bit is cleared. When the
ON bit is cleared by either a PRx match or by software
control, the timer will stay in Reset until both the ON bit
is set and the external signal is not at the Reset level.
The Level-Triggered Hardware Limit One-Shot modes
hold the timer in Reset on an external Reset level, and
start counting when both the ON bit is set and the external signal is not at the Reset level. If one of either of the
external signals is not in Reset, or the ON bit is set,
then the other signal being set/made active will start the
timer. Reset levels are selected as follows:
When Level-Triggered Hardware Limit One-Shot
modes are used in conjunction with the CCP PWM
operation, the PWM drive goes active with either the
external signal edge or the setting of the ON bit,
whichever of the two starts the timer.
• Low Reset level (MODE<4:0> = 10110)
• High Reset level (MODE<4:0> = 10111)
FIGURE 23-13:
LEVEL-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM
(MODE<4:0> = 10110)
Rev. 10-000 204A
5/30/201 4
0b10110
MODE
TMR2_clk
5
PRx
Instruction
(1)
BSF
BSF
BCF
BSF
ON
TMR2_ers
0
TMRx
1
2
3
4
5
0
1
2
3
0
1
2
3
4
5
0
TMR2_postscaled
PWM Duty
Cycle
‘D3
PWM Output
Note
1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
DS40001775B-page 246
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
23.7
PR2 Period Register
The T2PR Period register is double-buffered. Software
reads and writes the T2PR register. However, the timer
uses a buffered T2PR register for operation. Software
does not have direct access to the buffered T2PR
register. The contents of the T2PR register are
transferred to the buffer by any of the following events:
• A write to the TMR2 register
• A write to the TMR2CON register
• When TMR2 = T2PR buffer and the prescaler
rolls over
• An external Reset event
 2014-2015 Microchip Technology Inc.
23.8
Timer2 Operation During Sleep
When PSYNC = 1, Timer2 cannot be operated while
the processor is in Sleep mode. The contents of the
TMR2 and T2PR registers will remain unchanged while
the processor is in Sleep mode.
When PSYNC = 0, Timer2 will operate in Sleep as long
as the clock source selected is also still running.
Selecting the LFINTOSC, MFINTOSC or HFINTOSC
oscillator as the timer clock source will keep the
selected oscillator running during Sleep.
DS40001775B-page 247
PIC16(L)F1764/5/8/9
23.9
Register Definitions: Timer2/4/6 Control
Long bit name prefixes for the Timer2/4/6 peripherals
are shown in Table 23-2. Refer to Section 1.1.2.2
“Long Bit Names” for more information.
TABLE 23-2:
BIT NAME PREFIXES
Peripheral
Bit Name Prefix
Timer2
T2
Timer4
T4
Timer6
T6
REGISTER 23-1:
TxCLKCON: TIMERx CLOCK SELECTION REGISTER
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
CS<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
CS<3:0>: Timerx Clock Selection bits
See Table 23-3.
TABLE 23-3:
TIMERx CLOCK SOURCES
CS<3:0>
Timer2
Timer4
Timer6
1011-1111
Reserved
Reserved
Reserved
1010
LC3_out
LC3_out
LC3_out
1001
LC2_out
LC2_out
LC2_out
1000
LC1_out
LC1_out
LC1_out
0111
ZCD_out
ZCD_out
ZCD_out
0110
SOSC
SOSC
SOSC
0101
MFINTOSC
MFINTOSC
MFINTOSC
0100
LFINTOSC
LFINTOSC
LFINTOSC
0011
HFINTOSC
HFINTOSC
HFINTOSC
0010
FOSC
FOSC
FOSC
0001
FOSC/4
FOSC/4
FOSC/4
0000
Pin selected by T2INPPS
Pin selected by T4INPPS
Pin selected by T6INPPS
DS40001775B-page 248
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
REGISTER 23-2:
R/W/HC-0/0
TxCON: TIMERx CONTROL REGISTER
R/W-0/0
ON(1)
R/W-0/0
R/W-0/0
R/W-0/0
CKPS<2:0>
R/W-0/0
R/W-0/0
R/W-0/0
OUTPS<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HC = Hardware Clearable bit
bit 7
ON: Timerx On bit
1 = Timerx is on
0 = Timerx is off; all counters and state machines are reset
bit 6-4
CKPS<2:0>: Timer2 Type Clock Prescale Select bits
111 = 1:128 Prescaler
110 = 1:64 Prescaler
101 = 1:32 Prescaler
100 = 1:16 Prescaler
011 = 1:8 Prescaler
010 = 1:4 Prescaler
001 = 1:2 Prescaler
000 = 1:1 Prescaler
bit 3-0
OUTPS<3:0>: Timerx Output Postscaler Select bits
1111 = 1:16 Postscaler
1110 = 1:15 Postscaler
1101 = 1:14 Postscaler
1100 = 1:13 Postscaler
1011 = 1:12 Postscaler
1010 = 1:11 Postscaler
1001 = 1:10 Postscaler
1000 = 1:9 Postscaler
0111 = 1:8 Postscaler
0110 = 1:7 Postscaler
0101 = 1:6 Postscaler
0100 = 1:5 Postscaler
0011 = 1:4 Postscaler
0010 = 1:3 Postscaler
0001 = 1:2 Postscaler
0000 = 1:1 Postscaler
Note 1:
In certain modes, the ON bit will be auto-cleared by hardware. See Section 23.6 “Operation Examples”.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 249
PIC16(L)F1764/5/8/9
REGISTER 23-3:
TxHLT: TIMERx HARDWARE LIMIT CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
PSYNC(1,2)
CKPOL(3)
CKSYNC(4,5)
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
MODE<4:0>(6,7)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
PSYNC: Timerx Prescaler Synchronization Enable bit(1,2)
1 = TMRx prescaler output is synchronized to FOSC/4
0 = TMRx prescaler output is not synchronized to FOSC/4
bit 6
CKPOL: Timerx Clock Polarity Selection bit(3)
1 = Falling edge of input clock clocks timer/prescaler
0 = Rising edge of input clock clocks timer/prescaler
bit 5
CKSYNC: Timerx Clock Synchronization Enable bit(4,5)
1 = ON register bit is synchronized to TMR2_clk input
0 = ON register bit is not synchronized to TMR2_clk input
bit 4-0
MODE<4:0>: Timerx Control Mode Selection bits(6,7)
See Table 23-1.
Note 1:
2:
3:
4:
5:
6:
7:
Setting this bit ensures that reading TMRx will return a valid value.
When this bit is ‘1’, Timer2 cannot operate in Sleep mode.
CKPOL should not be changed while ON = 1.
Setting this bit ensures glitch-free operation when the ON bit is enabled or disabled.
When this bit is set, then the timer operation will be delayed by two TMRx input clocks after the ON bit is
set.
Unless otherwise indicated, all modes start upon ON = 1 and stop upon ON = 0 (stops occur without
affecting the value of TMRx).
When TMRx = PRx, the next clock clears TMRx, regardless of the operating mode.
DS40001775B-page 250
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
REGISTER 23-4:
TxRST: TIMERx EXTERNAL RESET SIGNAL SELECTION REGISTER
U-0
U-0
U-0
—
—
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
RSEL<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RSEL<4:0>: Timerx External Reset Signal Source Selection bits
See Table 23-4.
TABLE 23-4:
EXTERNAL RESET SOURCES
RSEL<4:0>
Timer2
Timer4
Timer6
10010-11111
Reserved
Reserved
Reserved
10001
LC3_out
LC3_out
LC3_out
10000
LC2_out
LC2_out
LC2_out
01111
LC1_out
LC1_out
LC1_out
Note 1:
01110
ZCD_out
ZCD_out
ZCD_out
01101
sync_C4OUT(1)
sync_C4OUT(1)
sync_C4OUT(1)
01100
sync_C3OUT(1)
sync_C3OUT(1)
sync_C3OUT(1)
01011
sync_C2OUT
sync_C2OUT
sync_C2OUT
01010
sync_C1OUT
sync_C1OUT
sync_C1OUT
01001
PWM6_out(1)
PWM6_out(1)
PWM6_out(1)
01000
PWM5_out
PWM5_out
PWM5_out
00111
PWM4_out(1)
PWM4_out(1)
PWM4_out(1)
00110
PWM3_out
PWM3_out
PWM3_out
00101
CCP2_out(1)
CCP2_out(1)
CCP2_out(1)
00100
CCP1_out
CCP1_out
CCP1_out
00011
TMR6_postscaled
TMR6_postscaled
Reserved
00010
TMR4_postscaled
Reserved
TMR4_postscaled
00001
Reserved
TMR2_postscaled
TMR2_postscaled
00000
Pin selected byT2INPPS
Pin selected by T4INPPS
Pin selected by T6INPPS
PIC16(L)F1768/9 devices only.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 251
PIC16(L)F1764/5/8/9
TABLE 23-5:
Name
CCP1CON
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2
Bit 7
Bit 6
Bit 5
Bit 4
EN
OE
OUT
FMT
Bit 3
Bit 2
Bit 1
Bit 0
MODE<3:0>
Register
on Page
261
CCP2CON(2)
EN
OE
OUT
FMT
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
105
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
108
MODE<3:0>
261
104
T2PR
Timer2 Module Period Register
234*
TMR2
Holding Register for the 8-Bit TMR2 Register
234*
T2CON
ON
T2CLKCON
—
CKPS<2:0>
—
—
—
—
T2RST
—
—
—
T2HLT
PSYNC
CKPOL
CKSYNC
OUTPS<3:0>
249
CS<3:0>
248
RSEL<3:0>
251
MODE<4:0>
250
T4PR
Timer4 Module Period Register
234*
TMR4
Holding Register for the 8-Bit TMR4 Register
234*
T4CON
ON
T4CLKCON
—
CKPS<2:0>
—
—
—
—
T4RST
—
—
—
T4HLT
PSYNC
CKPOL
CKSYNC
OUTPS<3:0>
249
CS<3:0>
248
RSEL<3:0>
251
MODE<4:0>
250
T6PR
Timer6 Module Period Register
234*
TMR6
Holding Register for the 8-Bit TMR6 Register
234*
T6CON
ON
T6CLKCON
—
CKPS<2:0>
—
—
—
—
T6RST
—
—
—
T6HLT
PSYNC
CKPOL
CKSYNC
Legend:
*
Note 1:
OUTPS<3:0>
249
CS<3:0>
248
RSEL<3:0>
251
MODE<4:0>
250
— = unimplemented location, read as ‘0’. Shaded cells are not used for the Timer2 module.
Page provides register information.
PIC16(L)F1768/9 only.
DS40001775B-page 252
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
24.0
CAPTURE/COMPARE/PWM
MODULES
The Capture/Compare/PWM module is a peripheral
which allows the user to time and control different
events, and to generate Pulse-Width Modulation
(PWM) signals. In Capture mode, the peripheral allows
the timing of the duration of an event. The Compare
mode allows the user to trigger an external event when
a predetermined amount of time has expired. The
PWM mode can generate Pulse-Width Modulated
signals of varying frequency and duty cycle.
TABLE 24-1:
AVAILABLE CCP MODULES
Device
CCP1
CCP2
PIC16(L)F1764
●
●
PIC16(L)F1765
●
●
PIC16(L)F1768
●
●
PIC16(L)F1769
●
●
Note 1: In devices with more than one CCP
module, it is very important to pay close
attention to the register names used. A
number placed after the module acronym
is used to distinguish between separate
modules. For example, the CCP1CON
and CCP2CON control the same
operational aspects of two completely
different CCP modules.
2: Throughout
this
section,
generic
references to a CCP module in any of its
operating modes may be interpreted as
being equally applicable to the CCPx
module. Register names, module signals,
I/O pins and bit names may use the
generic designator, ‘x’, to indicate the use
of a numeral to distinguish a particular
module when required.
24.1
Capture Mode
The Capture mode function described in this section is
available and identical for all CCP modules.
Capture mode makes use of the 16-bit Timer1
resource. When an event occurs on the CCPx input,
the 16-bit CCPRxH:CCPRxL register pair captures and
stores the 16-bit value of the TMR1H:TMR1L register
pair, respectively. An event is defined as one of the
following and is configured by the MODE<3:0> bits of
the CCPxCON register:
•
•
•
•
•
Every edge (rising or falling)
Every falling edge
Every rising edge
Every 4th rising edge
Every 16th rising edge
The CCPx capture input signal is configured by the
CTS<2:0> bits of the CCPxCAP register with the
following options:
•
•
•
•
•
•
•
•
CCPx pin
Comparator 1 output (C1_OUT_sync)
Comparator 2 output (C2_OUT_sync)
Comparator 3 output (C3_OUT_sync)
Comparator 4 output (C4_OUT_sync)
LC2_output
LC3_output
Interrupt-On-Change interrupt trigger
(IOC_interrupt)
When a capture is made, the CCPx Interrupt Flag bit,
CCPxIF of the PIRx register, is set. The interrupt flag
must be cleared in software. If another capture occurs
before the value in the CCPRxH:CCPRxL register pair
is read, the old captured value is overwritten by the new
captured value.
Figure 24-1 shows a simplified diagram of the capture
operation.
24.1.1
CCP PIN CONFIGURATION
In Capture mode, select the interrupt source using the
CTSx bits of the CCPxCAP register. If the CCPx pin is
chosen, it should be configured as an input by setting
the associated TRISx control bit.
Note:
 2014-2015 Microchip Technology Inc.
If the CCPx pin is configured as an output,
a write to the port can cause a capture
condition.
DS40001775B-page 253
PIC16(L)F1764/5/8/9
FIGURE 24-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
Rev. 10-000 158E
9/5/201 4
RxyPPS
CTS<2:0>
CCPx
PPS
TRIS Control
CCPRxH
CCPRxL
16
Prescaler
1,4,16
set CCPxIF
and
Edge Detect
16
CCPx
PPS
MODE <3:0>
TMR1H
TMR1L
CCPxPPS
Note:
24.1.2
Capture sources. See Register 24-5.
TIMER1 MODE RESOURCE
24.1.5
CAPTURE DURING SLEEP
Timer1 must be running in Timer mode or Synchronized
Counter mode for the CCP module to use the capture
feature. In Asynchronous Counter mode, the capture
operation may not work.
Capture mode depends upon the Timer1 module for
proper operation. There are two options for driving the
Timer1 module in Capture mode. It can be driven by the
instruction clock (FOSC/4), or by an external clock source.
See Section 22.0 “Timer1/3/5 Module with Gate
Control” for more information on configuring Timer1.
When Timer1 is clocked by FOSC/4, Timer1 will not
increment during Sleep. When the device wakes from
Sleep, Timer1 will continue from its previous state.
24.1.3
SOFTWARE INTERRUPT MODE
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit of the PIEx register clear to
avoid false interrupts. Additionally, the user should
clear the CCPxIF interrupt flag bit of the PIRx register
following any change in operating mode.
Note:
24.1.4
Clocking Timer1 from the system clock
(FOSC) should not be used in Capture
mode. In order for Capture mode to
recognize the trigger event on the CCPx
pin, Timer1 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.
CCP PRESCALER
There are four prescaler settings specified by the
MODE<3:0> bits of the CCPxCON register. Whenever
the CCP module is turned off, or the CCP module is not
in Capture mode, the prescaler counter is cleared. Any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another does not
clear the prescaler and may generate a false interrupt. To
avoid this unexpected operation, turn the module off by
clearing the EN bit of the CCPxCON register before
changing the prescaler.
DS40001775B-page 254
Capture mode will operate during Sleep when Timer1
is clocked by an external clock source.
24.1.6
ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the PPS controls. See
Section 12.0 “Peripheral Pin Select (PPS) Module”
for more details.
24.1.7
CAPTURE OUTPUT
Whenever a capture occurs, the output of the CCP will
go high for a period equal to one system clock period
(1/FOSC). This output is available as an input signal to
the following peripherals:
•
•
•
•
•
•
•
•
ADC trigger
COG
PRG
DSM
CLC
Op amp override
Timer2/4/6 Reset
Any device pins
In addition, the CCP output can be output to any pin
with that pin’s PPS control.
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
24.2
Compare Mode
The Compare mode function described in this section
is available and identical for all CCP modules.
Compare mode makes use of the 16-bit Timer1
resource. The 16-bit value of the CCPRxH:CCPRxL
register pair is constantly compared against the 16-bit
value of the TMR1H:TMR1L register pair. When a
match occurs, one of the following events can occur:
•
•
•
•
•
•
Toggle the CCPx output
Set the CCPx output
Clear the CCPx output
Pulse the CCPx output
Generate a software interrupt
Auto-conversion trigger
register pair. The TMR1H, TMR1L register pair is not
reset until the next rising edge of the Timer1 clock. The
auto-conversion trigger output starts an ADC conversion (if the ADC module is enabled). This allows the
CCPRxH, CCPRxL register pair to effectively provide a
16-bit programmable period register for Timer1.
Refer to Section 16.2.5 “Auto-Conversion Trigger”
for more information.
Note 1: The auto-conversion trigger from the
CCP module does not set interrupt flag
bit, TMR1IF of the PIR1 register.
2: Removing the match condition by
changing the contents of the CCPRxH
and CCPRxL register pair, between the
clock
edge that
generates
the
auto-conversion trigger and the clock
edge that generates the Timer1 Reset,
will preclude the Reset from occurring.
The action on the pin is based on the value of the
MODE<3:0> control bits of the CCPxCON register. At
the same time, the interrupt flag CCPxIF bit is set.
All Compare modes can generate an interrupt.
24.2.2
Figure 24-2 shows a simplified diagram of the compare
operation.
The user must configure the CCPx pin as an output by
clearing the associated TRISx bit.
24.2.1
The CCPx pin function can be moved to alternate pins
using the PPS controls. See Section 12.0 “Peripheral
Pin Select (PPS) Module” for more detail.
AUTO-CONVERSION TRIGGER
When Auto-Conversion Trigger mode is chosen
(CCPxM<3:0> = 1011), the CCPx module does the
following:
CCPx PIN CONFIGURATION
Clearing the CCPxCON register will force
the CCPx compare output latch to the
default low level. This is not the PORT I/O
data latch.
Note:
• Resets Timer1
• Starts an ADC conversion if ADC is enabled
The CCPx module does not assert control of the CCPx
pin in this mode.
The auto-conversion trigger output of the CCP occurs
immediately upon a match between the TMR1H,
TMR1L register pair and the CCPRxH, CCPRxL
FIGURE 24-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
Rev. 10-000 159B
9/5/201 4
To Peripherals
CCPRxH
CCPRxL
set CCPxIF
Comparator
Output
Logic
4
TMR1H
TMR1L
 2014-2015 Microchip Technology Inc.
S
Q
PPS
CCP x
TRIS Control
R
RxyPPS
MODE<3:0>
DS40001775B-page 255
PIC16(L)F1764/5/8/9
24.2.3
TIMER1 MODE RESOURCE
In Compare mode, Timer1 must be running in either
Timer mode or Synchronized Counter mode. The
compare operation may not work in Asynchronous
Counter mode.
See Section 22.0 “Timer1/3/5 Module with Gate
Control” for more information on configuring Timer1.
Note:
24.2.4
Clocking Timer1 from the system clock
(FOSC) should not be used in Compare
mode. In order for Compare mode to
recognize the trigger event on the CCPx
pin, TImer1 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.
SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen
(MODE<3:0> = 1010), the CCPx module does not
assert control of the CCPx pin (see the CCPxCON
register).
24.2.5
COMPARE DURING SLEEP
The Compare mode is dependent upon the system
clock (FOSC) for proper operation. Since FOSC is shut
down during Sleep mode, the Compare mode will not
function properly during Sleep.
24.2.6
24.2.7
CAPTURE OUTPUT
When in Compare mode, the CCP will provide an
output upon the 16-bit value of the CCPRxH:CCPRxL
register pair matching the TMR1H:TMR1L register pair.
The compare output depends on which Compare mode
the CCP is configured as. If the MODEx bits of the
CCPxCON register are equal to ‘1011’ or ‘1010’, the
CCP module will output high, while TMR1 is equal to
the CCPRxH:CCPRxL register pair. This means that
the pulse width is determined by the TMR1 prescaler. If
the MODEx bits of CCPxCON are equal to ‘0001’ or
‘0010’, the output will toggle upon a match, going from
‘0’ to ‘1’ or vice-versa. If the MODEx bits of CCPxCON
are equal to ‘1001’, the output is cleared on a match,
and if the MODEx bits are equal to ‘1000’, the output is
set on a match. This output is available to the following
peripherals:
•
•
•
•
•
•
•
•
ADC trigger
COG
PRG
DSM
CLC
Op amp override
Timer2/4/6 Reset
Any device pins
ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the PPS controls. See
Section 12.0 “Peripheral Pin Select (PPS) Module”
for more detail.
DS40001775B-page 256
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
24.3
PWM resolution defines the maximum number of steps
that can be present in a single PWM period. A higher
resolution allows for more precise control of the
pulse-width time, and in turn, the power that is applied
to the load.
PWM Overview
Pulse-Width Modulation (PWM) is a scheme that
provides power to a load by switching quickly between
fully on and fully off states. The PWM signal resembles
a square wave where the high portion of the signal is
considered the on state and the low portion of the signal
is considered the off state. The high portion, also known
as the pulse width, can vary in time and is defined in
steps. A larger number of steps applied, which
lengthens the pulse width, also supplies more power to
the load. Lowering the number of steps applied, which
shortens the pulse width, supplies less power. The
PWM period is defined as the duration of one complete
cycle or the total amount of on and off time combined.
FIGURE 24-3:
The term duty cycle describes the proportion of the on
time to the off time and is expressed in percentages,
where 0% is fully off and 100% is fully on. A lower duty
cycle corresponds to less power applied and a higher
duty cycle corresponds to more power applied.
Figure 24-3 shows a typical waveform of the PWM
signal.
SIMPLIFIED PWM BLOCK DIAGRAM
Rev. 10-000 157C
9/5/201 4
Duty cycle registers
CCPRxH
CCPRxL
CCPx_out
set CCPIF
10-bit Latch(2)
(Not accessible by user)
Comparator
R
S
TMR2 Module
R
TMR2
To Peripherals
Q
PPS
RxyPPS
CCPx
TRIS Control
(1)
ERS logic
Comparator
CCPx_pset
PR2
Notes:
1. 8-bit timer is concatenated with two bits generated by Fosc or two bits of the internal prescaler to
create 10-bit time-base.
2. The alignment of the 10 bits from the CCPR register is determined by the CCPxFMT bit.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 257
PIC16(L)F1764/5/8/9
24.3.1
STANDARD PWM OPERATION
24.3.2
SETUP FOR PWM OPERATION
The standard PWM function described in this section is
available and identical for all CCP modules.
The following steps should be taken when configuring
the CCP module for standard PWM operation:
The standard PWM mode generates a Pulse-Width
Modulation (PWM) signal on the CCPx pin with up to
10 bits of resolution. The period, duty cycle and
resolution are controlled by the following registers:
1.
• T2PR/T4PR/T6PR registers
• T2CON/T4CON/T6CON registers
• CCPRxH:CCPRxL register pair
3.
Figure 24-3 shows a simplified block diagram of PWM
operation.
Note 1: The corresponding TRISx bit must be
cleared to enable the PWM output on the
CCPx pin.
2.
4.
5.
6.
2: Clearing the CCPxCON register will
relinquish control of the CCPx pin.
7.
Disable the CCPx pin output driver by setting the
associated TRISx bit.
Select the timer associated with the PWM by
setting the CCPTMRS register.
Load the associated T2PR/T4PR/T6PR register
with the PWM period value.
Configure the CCP module for the PWM mode
by loading the CCPxCON register with the
appropriate values.
Load the CCPRxH:CCPRxL register pair with
the PWM duty cycle value.
Configure and start the timer selected in Step 2:
• Clear the timer interrupt flag bit of the PIRx
register. See Note below.
• Configure the CKPSx bits of the TxCON
register with the timer prescale value.
• Enable the timer by setting the ON bit of the
TxCON register.
Enable PWM output pin:
• Wait until the timer overflows and the timer
interrupt bit of the PIRx register is set. See
Note below.
• Enable the CCPx pin output driver by clearing
the associated TRISx bit.
Note:
DS40001775B-page 258
In order to send a complete duty cycle and
period on the first PWM output, the above
steps must be included in the setup
sequence. If it is not critical to start with a
complete PWM signal on the first output,
then Step 6 may be ignored.
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
24.4
CCP/PWM Clock Selection
The PIC16(L)F1764/5/8/9 allows each individual CCP
and PWM module to select the timer source that controls the module. Each module has an independent
selection.
As there are up to three 8-bit timers with auto-reload
(Timer2/4/6), the PWM mode on the CCP and PWM
modules can use any of these timers.
The CCPTMRS register is used to select which timer is
used.
24.4.1
USING THE TMR2/4/6 WITH THE
CCP MODULE
This device has a new version of the TMR2 module that
has many new modes, which allow for greater customization and control of the PWM signals than older parts.
Refer to Section 23.6 “Operation Examples” for
examples of PWM signal generation using the different
modes of Timer2. The CCP operation requires that the
timer used as the PWM time base has the FOSC/4 clock
source selected.
24.4.2
PWM PERIOD
The PWM period is specified by the T2PR/T4PR/T6PR
register of Timer2/4/6. The PWM period can be
calculated using the formula of Equation 24-1.
EQUATION 24-1:
PWM PERIOD
PWM Period =   PR2  + 1   4  T OSC 
(TMR2 Prescale Value)
Note 1:
TOSC = 1/FOSC.
When TMR2/4/6 is equal to its respective
T2PR/T4PR/T6PR register, the following three events
occur on the next increment cycle:
• TMR2/4/6 is cleared
• The CCPx pin is set. (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
• The PWM duty cycle is latched from the
CCPRxH:CCPRxL pair into the internal 10-bit
latch.
Note:
The Timer postscaler (see Figure 24-1) is
not used in the determination of the PWM
frequency.
24.4.3
PWM DUTY CYCLE
The PWM duty cycle is specified by writing a 10-bit value
to two registers: the CCPRxH:CCPRxL register pair.
Where the particular bits go is determined by the FMT bit
of the CCPxCON register. If FMT = 0, the two Most
Significant bits of the duty cycle value should be written to
bits<1:0> of the CCPRxH register and the remaining eight
bits to the CCPRxL register. If FMT = 1, the Least
Significant two bits of the duty cycle should be written to
bits<7:6> of the CCPRxL register and the Most Significant
eight bits to the CCPRxH register. This is illustrated in
Figure 24-4. These bits can be written at any time. The
duty cycle value is not latched into the internal latch until
after the period completes (i.e., a match between
T2PR/T4PR/T6PR and TMR2/4/6 registers occurs).
Equation 24-2 is used to calculate the PWM pulse
width. Equation 24-3 is used to calculate the PWM duty
cycle ratio.
EQUATION 24-2:
PULSE WIDTH
Pulse Width = CCPRxH:CCPRxL  T OSC
 (TMR2 Prescale Value)
EQUATION 24-3:
DUTY CYCLE RATIO
 CCPRxH:CCPRxL 
Duty Cycle Ratio = -------------------------------------------------4  PRx + 1 
The PWM Duty Cycle registers are double-buffered for
glitchless PWM operation.
The 8-bit timer TMR2/4/6 register is concatenated with
either the 2-bit internal system clock (FOSC), or two bits of
the prescaler, to create the 10-bit time base. The system
clock is used if the Timer2/4/6 prescaler is set to 1:1.
When the 10-bit time base matches the internal buffer
register, then the CCPx pin is cleared (see Figure 24-3).
FIGURE 24-4:
CCPx DUTY CYCLE
ALIGNMENT
Rev. 10-000 160A
12/9/201 3
CCPRxH
CCPRxL
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
FMT = 1
FMT = 0
CCPRxH
CCPRxL
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
10-bit Duty Cycle
9 8 7 6 5 4 3 2 1 0
 2014-2015 Microchip Technology Inc.
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PIC16(L)F1764/5/8/9
24.4.4
PWM RESOLUTION
EQUATION 24-4:
The resolution determines the number of available duty
cycles for a given period. For example, a 10-bit resolution
will result in 1024 discrete duty cycles, whereas an 8-bit
resolution will result in 256 discrete duty cycles.
log  4  PR2 + 1  
Resolution = ------------------------------------------ bits
log  2 
The maximum PWM resolution is 10 bits when
T2PR/T4PR/T6PR is 255. The resolution is a function
of the T2PR/T4PR/T6PR register value as shown by
Equation 24-4.
TABLE 24-2:
1.22 kHz
Timer Prescale
T2PR Value
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
16
4
1
1
1
1
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
8
7
6
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
PWM Frequency
1.22 kHz
Timer Prescale
T2PR Value
4.90 kHz
76.92 kHz
153.85 kHz
200.0 kHz
16
4
1
1
1
1
0x65
0x65
0x19
0x0C
0x09
8
8
8
6
5
5
CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 5.0 “Oscillator Module (with Fail-Safe
Clock Monitor)” for additional details.
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
DS40001775B-page 260
19.61 kHz
0x65
Maximum Resolution (bits)
24.4.6
If the pulse-width value is greater than the
period, the assigned PWM pin(s) will
remain unchanged.
0xFF
Maximum Resolution (bits)
24.4.5
Note:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency
TABLE 24-3:
PWM RESOLUTION
24.4.7
PWM OUTPUT
The output of the CCP in PWM mode is the PWM signal
generated by the module and described above. This
output is available to the following peripherals:
•
•
•
•
•
•
•
•
ADC trigger
COG
PRG
DSM
CLC
Op amp override
Timer2/4/6 Reset
Any device pins
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
24.5
Register Definitions: CCP Control
REGISTER 24-1:
CCPxCON: CCPx CONTROL REGISTER
R/W-0/0
U-0
R-x
R/W-0/0
EN
—
OUT
FMT
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
MODE<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Reset
bit 7
EN: CCPx Module Enable bit
1 = CCPx is enabled
0 = CCPx is disabled
bit 6
Unimplemented: Read as ‘0’
bit 5
OUT: CCPx Output Data bit (read-only)
bit 4
FMT: CCPW (Pulse-Width) Alignment bit
If MODE<3:0> = PWM Mode:
1 = Left-aligned format, CCPRxH<7> is the MSB of the PWM duty cycle
0 = Right-aligned format, CCPRxL<0> is the LSB of the PWM duty cycle
bit 3-0
MODE<3:0>: CCPx Mode Selection bits
11xx = PWM mode
1011 =
1010 =
1001 =
1000 =
Compare mode: Pulse output, clear TMR1
Compare mode: Pulse output (0 - 1 - 0)
Compare mode: Clear output on compare match; output is set upon selection of this mode
Compare mode: Set output on compare match; output is set upon selection of this mode
0111 =
0110 =
0101 =
0100 =
Capture mode: Every 16th rising edge
Capture mode: Every 4th rising edge
Capture mode: Every rising edge
Capture mode: Every falling edge
0011 =
0010 =
0001 =
0000 =
Capture mode: Every rising or falling edge
Compare mode: Toggle output on match
Compare mode: Toggle output and clear TMR1 on match
Capture/Compare/PWM off (resets CCPx module) (reserved for backwards compatibility)
 2014-2015 Microchip Technology Inc.
DS40001775B-page 261
PIC16(L)F1764/5/8/9
REGISTER 24-2:
R/W-0/0
CCPTMRS: PWM TIMER SELECTION CONTROL REGISTER
R/W-0/0
P4TSEL<1:0>(1)
R/W-0/0
R/W-0/0
R/W-0/0
P3TSEL<1:0>
R/W-0/0
R/W-0/0
C2TSEL<1:0>
R/W-0/0
C1TSEL<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
P4TSEL<1:0>: PWM4 Timer Selection bits(1)
11 = Reserved
10 = PWM4 is based off Timer6 in PWM mode
01 = PWM4 is based off Timer4 in PWM mode
00 = PWM4 is based off Timer2 in PWM mode
bit 5-4
P3TSEL<1:0>: PWM3 Timer Selection bits
11 = Reserved
10 = PWM3 is based off Timer6 in PWM mode
01 = PWM3 is based off Timer4 in PWM mode
00 = PWM3 is based off Timer2 in PWM mode
bit 3-2
C2TSEL<1:0>: CCP2 (PWM2) Timer Selection bits
11 = Reserved
10 = CCP2 is based off Timer6 in PWM mode
01 = CCP2 is based off Timer4 in PWM mode
00 = CCP2 is based off Timer2 in PWM mode
bit 1-0
C1TSEL<1:0>: CCP1 (PWM1) Timer Selection bits
11 = Reserved
10 = CCP1 is based off Timer6 in PWM mode
01 = CCP1 is based off Timer4 in PWM mode
00 = CCP1 is based off Timer2 in PWM mode
DS40001775B-page 262
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
REGISTER 24-3:
R/W-0/0
CCPRxL: CCPx LOW BYTE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
CCPR<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
MODE<3:0> = Capture Mode:
CCPRxL<7:0>: LSB of captured TMR1 value.
MODE<3:0> = Compare Mode:
CCPRxL<7:0>: LSB compared to TMR1 value.
MODE<3:0> = PWM Mode && FMT = 0:
CCPRxL<7:0>: CCPW<7:0> – Pulse-width Least Significant eight bits.
MODE<3:0> = PWM Mode and FMT = 1:
CCPRxL<7:6>: CCPW<1:0> – Pulse-width Least Significant two bits.
CCPRxL<5:0>: Not used.
REGISTER 24-4:
R/W-0/0
CCPRxH: CCPx HIGH BYTE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
CCPR<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
MODE<3:0> = Capture Mode:
CCPRxH<7:0>: MSB of captured TMR1 value.
MODE<3:0> = Compare Mode:
CCPRxH<7:0>: MSB compared to TMR1 value.
MODE<3:0> = PWM Mode && FMT = 0:
CCPRxH<7:2>: Not used.
CCPRxH<1:0>: CCPW<9:8> – Pulse-width Most Significant two bits.
MODE<3:0> = PWM Mode and FMT = 1:
CCPRxH<7:0>: CCPW<9:2> – Pulse-width Most Significant eight bits.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 263
PIC16(L)F1764/5/8/9
REGISTER 24-5:
CCPxCAP: CCPx CAPTURE INPUT SELECTION REGISTER
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0/0
R/W-0/0
R/W-0/0
CTS<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Reset
bit 7-3
Unimplemented: Read as ‘0’
bit 2-0
CTS<2:0>: Capture Trigger Input Selection bits
111 = IOC_event
110 = LC3_output
101 = LC2_output
100 = C4_sync_out(1)
011 = C3_sync_out(1)
010 = C2_sync_out
001 = C1_sync_out
000 = Pin selected with the CCPxPPS register
Note 1:
PIC16(L)F1768/9 only. Unimplemented on PIC16(L)F1764/5.
DS40001775B-page 264
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
TABLE 24-4:
SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
CCPxCAP
—
—
—
—
—
EN
OE
OUT
FMT
CCPxCON
CCPRxL
Capture/Compare/PWM Register x (LSB)
CCPRxH
Capture/Compare/PWM Register x (MSB)
CCPTMRS
P4TSEL<1:0>
P3TSEL<1:0>
Bit 2
Bit 1
Bit 0
CTS<2:0>
Register
on Page
264
MODE<3:0>
261
263
263
C2TSEL<1:0>
C1TSEL<1:0>
262
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
104
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
105
PIE2
OSFIE
C2IE
C1IE
—
BCL1IE
C4IE(1)
C3IE(1)
CCP2IE(1)
INTCON
T2PR
T2CON
Timer2 Period Register
ON
CKPS<2:0>
TMR2
Timer2 Module Register
T4PR
Timer4 Period Register
T4CON
ON
106
234*
OUTPS<3:0>
249
234
234*
CKPS<2:0>
OUTPS<3:0>
249
TMR4
Timer4 Module Register
234
T6PR
Timer6 Period Register
234*
T6CON
TMR6
ON
CKPS<2:0>
OUTPS<3:0>
Timer6 Module Register
249
234
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the PWM.
* Page provides register information.
Note 1: PIC16(L)F1768/9 only.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 265
PIC16(L)F1764/5/8/9
NOTES:
DS40001775B-page 266
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
25.0
Figure 25-1 shows a simplified block diagram of PWM
operation.
10-BIT PULSE-WIDTH
MODULATION (PWM) MODULE
Figure 25-2 shows a typical waveform of the PWM
signal.
The 10-bit PWM module generates a Pulse-Width
Modulated signal determined by the duty cycle, period
and resolution that are configured by the following
registers:
•
•
•
•
•
T2PR
T2CON
PWMxDCH
PWMxDCL
PWMxCON
FIGURE 25-1:
SIMPLIFIED PWM BLOCK DIAGRAM
Duty Cycle Registers
PWMxDCL<7:6>
PWMxDCH
Latched
(not visible to user)
Comparator
PWMxOUT
To Other Peripherals: ADC, COG, CLC,
PRG, DSM, Op Amp Override
R
Q
0
PWMx
PPS
S
Q
1
RXYPPS
TRISx
TMR2 Module
TMR2
(1)
Output Polarity (PWMxPOL)
Comparator
T2PR
Note
1:
Clear Timer,
PWMx Pin and
Latch Duty Cycle
The 8-bit timer is concatenated with the two Least Significant bits of 1/FOSC, adjusted by the Timer2
prescaler to create a 10-bit time base.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 267
PIC16(L)F1764/5/8/9
For a step-by-step procedure on how to set up this module for PWM operation, refer to Section 25.10.1 “Setup
for PWM Operation Using PWMx Output Pins”.
FIGURE 25-2:
EQUATION 25-1:
PWM PERIOD
PWM Period =  T2PR + 1   4  T OSC 
(TMR2 Prescale Value)
PWM OUTPUT
Note:
TOSC = 1/FOSC.
Period
Pulse Width
TMR2 = T2PR
TMR2 =
PWMxDCH<7:0>:PWMxDCL<7:6>
TMR2 = 0
25.1
PWMx Pin Configuration
All PWM outputs are multiplexed with the PORT data
latch. The user must configure the pins as outputs by
clearing the associated TRISx bits.
25.2
Fundamental Operation
The PWM module produces a 10-bit resolution output.
Timer2 and T2PR set the period of the PWM. The
PWMxDCL and PWMxDCH registers configure the
duty cycle. The period is common to all PWM modules,
whereas the duty cycle is independently controlled.
Note: The Timer2 postscaler is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than the
PWM output.
All PWM outputs associated with Timer2 are set when
TMR2 is cleared. Each PWMx is cleared when TMR2
is equal to the value specified in the corresponding
PWMxDCH (8 MSbs) and PWMxDCL<7:6> (2 LSbs)
registers. When the value is greater than or equal to
T2PR, the PWM output is never cleared (100% duty
cycle).
Note: The PWMxDCH and PWMxDCL registers
are double-buffered. The buffers are
updated when Timer2 matches T2PR. Care
should be taken to update both registers
before the timer match occurs.
When TMR2 is equal to T2PR, the following three
events occur on the next increment cycle:
• TMR2 is cleared
• The PWM output is active. (Exception: When the
PWM duty cycle = 0%, the PWM output will
remain inactive.)
• The PWMxDCH and PWMxDCL register values
are latched into the buffers.
Note:
25.5
The Timer2 postscaler has no effect on the
PWM operation.
PWM Duty Cycle
The PWM duty cycle is specified by writing a 10-bit value
to the PWMxDCH and PWMxDCL register pair. The
PWMxDCH register contains the eight MSbs and the
PWMxDCL<7:6>, the two LSbs. The PWMxDCH and
PWMxDCL registers can be written to at any time.
Equation 25-2 is used to calculate the PWM pulse
width.
Equation 25-3 is used to calculate the PWM duty cycle
ratio.
EQUATION 25-2:
PULSE WIDTH
Pulse Width =  PWMxDCH:PWMxDCL<7:6>  
T OS C  (TMR2 Prescale Value)
Note: TOSC = 1/FOSC.
EQUATION 25-3:
DUTY CYCLE RATIO
 PWMxDCH:PWMxDCL<7:6> 
Duty Cycle Ratio = ----------------------------------------------------------------------------------4  T2PR + 1 
The output polarity is inverted by setting the PWMxPOL
bit of the PWMxCON register.
The 8-bit timer TMR2 register is concatenated with the
two Least Significant bits of 1/FOSC, adjusted by the
Timer2 prescaler to create the 10-bit time base. The
system clock is used if the Timer2 prescaler is set to 1:1.
25.4
25.6
25.3
PWM Output Polarity
PWM Period
The PWM period is specified by the T2PR register of
Timer2. The PWM period can be calculated using the
formula of Equation 25-1.
DS40001775B-page 268
PWM Resolution
The resolution determines the number of available duty
cycles for a given period. For example, a 10-bit resolution
will result in 1024 discrete duty cycles, whereas an 8-bit
resolution will result in 256 discrete duty cycles.
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
The maximum PWM resolution is ten bits when T2PR
is 255. The resolution is a function of the T2PR register
value as shown by Equation 25-4.
EQUATION 25-4:
Note:
If the pulse-width value is greater than the
period the assigned PWM pin(s) will
remain unchanged.
PWM RESOLUTION
log  4  T2PR + 1  
Resolution = ---------------------------------------------- bits
log  2 
TABLE 25-1:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency
0.31 kHz
Timer Prescale
T2PR Value
Maximum Resolution (bits)
TABLE 25-2:
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
64
4
1
1
1
1
0xFF
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
8
7
6.6
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
PWM Frequency
0.31 kHz
Timer Prescale
T2PR Value
Maximum Resolution (bits)
25.7
4.88 kHz
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz
200.0 kHz
64
4
1
1
1
1
0x65
0x65
0x65
0x19
0x0C
0x09
8
8
8
6
5
5
Operation in Sleep Mode
In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the
PWMx pin is driving a value, it will continue to drive that
value. When the device wakes up, TMR2 will continue
from its previous state.
25.8
Changes in System Clock
Frequency
The PWM frequency is derived from the system clock
frequency (FOSC). Any changes in the system clock
frequency will result in changes to the PWM frequency.
Refer to Section 5.0 “Oscillator Module (with
Fail-Safe Clock Monitor)” for additional details.
25.9
Effects of Reset
Any Reset will force all ports to Input mode and the
PWM registers to their Reset states.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 269
PIC16(L)F1764/5/8/9
25.10 Set-up Procedures
25.10.1
SETUP FOR PWM OPERATION
USING PWMx OUTPUT PINS
The following steps should be taken when configuring
the module for PWM operation using the PWMx output
pins:
1.
2.
3.
4.
5.
6.
7.
8.
Disable the PWMx pin output driver(s) by setting
the associated TRISx bit(s).
Clear the PWMxCON register.
Load the T2PR register with the PWM period
value.
Load the PWMxDCH register and bits<7:6> of
the PWMxDCL register with the PWM duty cycle
value.
Configure and start Timer2:
• Clear the TMR2IF interrupt flag bit of the PIR1
register. See Note below.
• Configure the CKPSx bits of the T2CON
register with the Timer2 prescale value.
• Enable Timer2 by setting the ON bit of the
T2CON register.
Enable the PWM output pin and wait until
Timer2 overflows. TMR2IF bit of the PIR1
register is set. See Note below.
Enable the PWMx pin output driver(s) by clearing the associated TRISx bit(s) and setting the
desired pin PPS control bits.
Configure the PWM module by loading the
PWMxCON register with the appropriate values.
Note 1: In order to send a complete duty cycle
and period on the first PWM output, the
above steps must be followed in the order
given. If it is not critical to start with a
complete PWM signal, then move Step 8
to replace Step 4.
25.10.2
SETUP FOR PWM OPERATION TO
OTHER DEVICE PERIPHERALS
The following steps should be taken when configuring
the module for PWM operation to be used by other
device peripherals:
1.
2.
3.
4.
5.
6.
7.
Disable the PWMx pin output driver(s) by setting
the associated TRISx bit(s).
Clear the PWMxCON register.
Load the T2PR register with the PWM period
value.
Load the PWMxDCH register and bits<7:6> of
the PWMxDCL register with the PWM duty cycle
value.
Configure and start Timer2:
• Clear the TMR2IF interrupt flag bit of the PIR1
register. See Note below.
• Configure the CKPSx bits of the T2CON
register with the Timer2 prescale value.
• Enable Timer2 by setting the ON bit of the
T2CON register.
Enable PWM output pin:
• Wait until Timer2 overflows, TMR2IF bit of the
PIR1 register is set. See Note below.
Configure the PWM module by loading the
PWMxCON register with the appropriate values.
Note:
In order to send a complete duty cycle and
period on the first PWM output, the above
steps must be included in the setup
sequence. If it is not critical to start with a
complete PWM signal on the first output,
then Step 6 may be ignored.
2: For operation with other peripherals only,
disable PWMx pin outputs.
DS40001775B-page 270
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
25.11 Register Definitions: 10-Bit PWM Control
Long bit name prefixes for the PWM peripherals are
shown in Table 25-3. Refer to Section 1.1.2.2 “Long
Bit Names” for more information.
TABLE 25-3:
BIT NAME PREFIXES
Peripheral
Note 1:
Bit Name Prefix
PWM3
PWM3
PWM4(1)
PWM4
PIC16(L)F1768/9 devices only.
REGISTER 25-1:
PWMxCON: PWMx CONTROL REGISTER
R/W-0/0
U-0
R-0/0
R/W-0/0
U-0
U-0
U-0
U-0
EN
—
OUT
POL
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
EN: PWMx Module Enable bit
1 = PWMx module is enabled
0 = PWMx module is disabled
bit 6
Unimplemented: Read as ‘0’
bit 5
OUT: PWMx Module Output Level When Read bit
bit 4
POL: PWMx Output Polarity Select bit
1 = PWMx output is active-low
0 = PWMx output is active-high
bit 3-0
Unimplemented: Read as ‘0’
 2014-2015 Microchip Technology Inc.
DS40001775B-page 271
PIC16(L)F1764/5/8/9
REGISTER 25-2:
R/W-x/u
PWMxDCH: PWMx DUTY CYCLE REGISTER HIGH BITS
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
DC<9:2>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
DC<9:2>: PWM Duty Cycle Most Significant bits
These bits are the MSbs of the PWM duty cycle. The two LSbs are found in the PWMxDCL register.
REGISTER 25-3:
R/W-x/u
PWMxDCL: PWMx DUTY CYCLE REGISTER LOW BITS
R/W-x/u
DC<1:0>
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
DC<1:0>: PWM Duty Cycle Least Significant bits
These bits are the LSbs of the PWM duty cycle. The MSbs are found in the PWMxDCH register.
bit 5-0
Unimplemented: Read as ‘0’
TABLE 25-4:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH 10-BIT PWM
Bit 7
Bit 6
CCPTMRS
P4TSEL<1:0>
PWMxCON
EN
Bit 5
Bit 4
OUT
POL
—
—
PWMxDCH
DC<1:0>
RxyPPS
—
TxCON
ON
TxPR
TRISA
Bit 0
—
—
C1TSEL<1:0>
264
—
—
271
—
—
—
272
272
—
—
—
RxyPPS<4:0>
CKPS<2:0>
—
—
—
159
OUTPS<3:0>
—
249
CS<3:0>
248
234
TRISA<5:4>
TRISB<7:4>
TRISC7(2)
(2)
TRISC6
Register
on Page
MODE<1:0>
TMRx Period Register
TRISB(2)
TRISC
Bit 1
DC<9:2>
PWMxDCL
TxCLKCON
Bit 2
C2TSEL<1:0>(1)
P3TSEL<1:0>
—
Bit 3
TRISC5
TRISC4
—(1)
TRISA<2:0>
141
—
—
—
—
147
TRISC3
TRISC2
TRISC1
TRISC0
152
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM.
Note 1: Unimplemented, read as ‘1’.
2: PIC16(L)F1768/9 only.
DS40001775B-page 272
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
26.0
Each PWM module has four Offset modes:
16-BIT PULSE-WIDTH
MODULATION (PWM) MODULE
•
•
•
•
The Pulse-Width Modulation (PWM) module generates
a Pulse-Width Modulated signal determined by the
phase, duty cycle, period and offset event counts that
are contained in the following registers:
•
•
•
•
Using the Offset modes, each PWM module can offset
its waveform relative to any other PWM module in the
same device. For a more detailed description of the
Offset modes, refer to Section 26.3 “Offset Modes”.
PWMxPH registers
PWMxDC registers
PWMxPR registers
PWMxOF registers
Every PWM module has a configurable reload
operation to ensure all event count buffers change at
the end of a period, thereby avoiding signal glitches.
Figure 26-2 shows a simplified block diagram of the
reload operation. For a more detailed description of
the reload operation, refer to Section 26.4 “Reload
Operation”.
Figure 26-1 shows a simplified block diagram of the
PWM operation.
Each PWM module has four modes of operation:
•
•
•
•
Independent Run
Slave Run with Synchronous Start
One-Shot Slave with Synchronous Start
Continuous Run Slave with Synchronous Start
and Timer Reset
Standard
Set On Match
Toggle On Match
Center-Aligned
For a more detailed description of each PWM mode,
refer to Section 26.2 “PWM Modes”.
FIGURE 26-1:
16-BIT PWMx BLOCK DIAGRAM
MODE<1:0>
EN
PHx_match
Rev. 10-000 152B
4/22/201 4
PWM Control
Unit
DCx_match
D
Q4
PWMxOUT
Q
CK
PWMxPOL
OF6_match (1)
OF5_match
(1)
PWMx_output
1
0
Offset
Control
PRx_match
PPS
OFM<1:0>
OFS
E
PWM_clock
Comparator
PRx_match
set PRIF
16-bt Latch LDx_trigger
PWMxPR
Comparator
R
U/D
PHx_match
set PHIF
Comparator
OFx_match
set OFIF
16-bt Latch LDx_trigger
PWMxOF
PWMx
TRIS Control
RxyPPS
PWMxTMR
16-bt Latch LDx_trigger
PWMxPH
Note 1:
To Peripherals
OF_match
Comparator
DCx_match
set DCIF
16-bt Latch LDx_trigger
PWMxDC
A PWM module cannot trigger from its own offset match event.
The input corresponding to a PWM module’s own offset match is reserved.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 273
PIC16(L)F1764/5/8/9
FIGURE 26-2:
LOAD TRIGGER BLOCK DIAGRAM
Rev. 10-000 153B
7/9/201 5
LDx_trigger(1)
LDy_trigger
1
PWMxLDS
0
PRx_match
PWMxLDT
Note
26.1
D
PWMxLDA(2)
LDx_trigger
PWM_clock
1. The input corresponding to a PWM module’s own load trigger is reserved.
2. PWMxLDA is cleared by hardware upon LDx_trigger.
Fundamental Operation
FIGURE 26-3:
The PWM module produces a 16-bit resolution
Pulse-Width Modulated output.
PWMxCS<1:0>
Each PWM module can be enabled individually using
the EN bit of the PWMxCON register, or several PWM
modules can be enabled simultaneously using the
MPWMxEN bits of the PWMEN register.
The current state of the PWM output can be read using
the OUT bit of the PWMxCON register. In some modes,
this bit can be set and cleared by software, giving
additional software control over the PWM waveform.
This bit is synchronized to FOSC/4 and therefore, does
not change in real time with respect to the PWM_clock.
If PWM_clock > FOSC/4, the OUT bit may
not accurately represent the output state of
the PWM.
PWMx CLOCK SOURCE
BLOCK DIAGRAM
Rev. 10-000156A
1/7/2015
Each PWM module has an independent timer driven by
a selection of clock sources determined by the
PWMxCLKCON register (Register 26-4). The timer
value is compared to Event Count registers to generate
the various events of a the PWM waveform, such as the
period and duty cycle. For a block diagram describing
the clock sources, refer to Figure 26-3.
Note:
Q
26.1.1
FOSC
00
HFINTOSC
01
LFINTOSC
10
Reserved
11
PWMxPS<2:0>
Prescaler
PWMx_clock
PWMx PIN CONFIGURATION
This device uses the PPS control circuitry to route
peripherals to any device I/O pin. Select the desired
pin, or pins, for PWM output with the device pin, using
the RxyPPS control register (Register 12-2).
All PWM outputs are multiplexed with the PORT data
latch, so the pins must also be configured as outputs by
clearing the associated PORT TRISx bits.
The slew rate feature may be configured to optimize
the rate to be used in conjunction with the PWM _outputs. High-speed output switching is attained by
clearing the associated PORT SLRCONx bits.
The PWM outputs can be configured to be open-drain
outputs by setting the associated PORT ODCONx bits.
26.1.2
PWMx Output Polarity
The output polarity is inverted by setting the POL bit of
the PWMxCON register. The polarity control affects the
PWM output even when the module is not enabled.
DS40001775B-page 274
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
26.2
26.2.3
PWM Modes
PWM modes are selected with the MODE<1:0> bits of
the PWMxCON register (Register 26-1).
In all PWM modes, an offset match event can also be
used to synchronize the PWMxTMR in three Offset
modes. See Section 26.3 “Offset Modes” for more
information.
26.2.1
STANDARD MODE
The Standard mode (MODE<1:0> = 00) selects a
single-phase PWM output. The PWM output in this mode
is determined by when the period, duty cycle and phase
counts match the PWMxTMR value. The start of the duty
cycle occurs on the phase match and the end of the duty
cycle occurs on the duty cycle match. The period match
resets the timer. The offset match can also be used to
synchronize the PWMxTMR in the Offset modes. See
Section 26.3 “Offset Modes” for more information.
Equation 26-1 is used to calculate the PWM period in
Standard mode.
Equation 26-2 is used to calculate the PWM duty cycle
ratio in Standard mode.
EQUATION 26-1:
PWM PERIOD IN
STANDARD MODE
 PWMxPR + 1   Prescale
Period = ---------------------------------------------------------------------PWM _clock
TOGGLE ON MATCH MODE
The Toggle On Match mode (MODE<1:0> = 10) generates a 50% duty cycle PWM with a period twice as long
as that computed for the Standard PWM mode. Duty
cycle count has no effect in this mode. The phase count
determines how many PWMxTMR periods, after a
period event, the output will toggle.
Writes to the OUT bit of the PWMxCON register will
have no effect in this mode.
A detailed timing diagram for Toggle On Match mode is
shown in Figure 26-6.
26.2.4
CENTER-ALIGNED MODE
The Center-Aligned mode (MODE<1:0> = 11)
generates a PWM waveform that is centered in the
period. In this mode, the period is two times the
PWMxPR count. The PWMxTMR counts up to the
period value, then counts back down to 0. The duty
cycle count determines both the start and end of the
active PWM output. The start of the duty cycle occurs
at the match event when PWMxTMR is incrementing,
and the duty cycle ends at the match event when
PWMxTMR is decrementing. The incrementing match
value is the period count minus the duty cycle count.
The decrementing match value is the incrementing
match value plus 1.
Equation 26-3 is used to calculate the PWM period in
Center-Aligned mode.
EQUATION 26-3:
EQUATION 26-2:
PWM DUTY CYCLE IN
STANDARD MODE
 PWMxDC – PWMx PH 
Duty Cycle = -----------------------------------------------------------------
PWMxPR + 1
A detailed timing diagram for Standard mode is shown
in Figure 26-4.
26.2.2
SET ON MATCH MODE
The Set On Match mode (MODE<1:0> = 01) generates
an active output when the phase count matches the
PWMxTMR value. The output stays active until the
OUT bit of the PWMxCON register is cleared or the
PWM module is disabled. The duty cycle count has no
effect in this mode. The period count only determines
the maximum PWMxTMR value above which no phase
matches can occur.
PWM PERIOD IN
CENTER-ALIGNED MODE
 PWMxPR + 1   2  Prescale
Period = -----------------------------------------------------------------------------PWM _clock
Equation 26-4 is used to calculate the PWM duty cycle
ratio in Center-Aligned mode
EQUATION 26-4:
PWM DUTY CYCLE IN
CENTER-ALIGNED MODE
PWMxDC  2
Duty Cycle = ------------------------------------------------ PWMx PR + 1   2
Writes to PWMxOUT will have no effect in this mode.
A detailed timing diagram for Center-Aligned mode is
shown in Figure 26-7.
The PWMxOUT bit can be used to set or clear the output of the PWM in this mode. Writes to this bit will take
place on the next rising edge of the PWM_clock after
the bit is written.
A detailed timing diagram for Set On Match mode is
shown in Figure 26-5.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 275
STANDARD PWMx MODE TIMING DIAGRAM
Rev. 10-000142A
9/5/2013
Period
Duty Cycle
Phase
PWMxCLK
PWMxPR
10
PWMxPH
4
PWMxDC
9
PWMxTMR
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
PWMxOUT
FIGURE 26-5:
SET ON MATCH PWMx MODE TIMING DIAGRAM
Rev. 10-000143A
9/5/2013
Period
Phase
 2014-2015 Microchip Technology Inc.
PWMxCLK
PWMxPR
10
PWMxPH
4
PWMxTMR
PWMxOUT
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
PIC16(L)F1764/5/8/9
DS40001775B-page 276
FIGURE 26-4:
 2014-2015 Microchip Technology Inc.
FIGURE 26-6:
TOGGLE ON MATCH PWMx MODE TIMING DIAGRAM
Rev. 10-000144A
9/5/2013
Period
Phase
PWMxCLK
PWMxPR
10
PWMxPH
4
PWMxTMR
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
PWMxOUT
FIGURE 26-7:
CENTER-ALIGNED PWMx MODE TIMING DIAGRAM
Period
Duty Cycle
PWMxCLK
DS40001775B-page 277
PWMxPR
6
PWMxDC
4
PWMxTMR
PWMxOUT
0
1
2
3
4
5
6
6
5
4
3
2
1
0
0
1
2
3
PIC16(L)F1764/5/8/9
Rev. 10-000 145A
4/22/201 4
PIC16(L)F1764/5/8/9
26.3
Offset Modes
The Offset modes provide the means to adjust the waveform of a slave PWM module relative to the waveform of
a master PWM module in the same device.
26.3.1
INDEPENDENT RUN MODE
In Independent Run mode (OFM<1:0> = 00), the PWM
module is unaffected by the other PWM modules in the
device. The PWMxTMR associated with the PWM
module in this mode starts counting as soon as the EN bit
associated with this PWM module is set, and continues
counting until the EN bit is cleared. Period events reset
the PWMxTMR to zero, after which, the timer continues
to count.
A detailed timing diagram of this mode used with
Standard PWM mode is shown in Figure 26-8.
26.3.2
SLAVE RUN MODE WITH SYNC
START
In Slave Run mode with Sync Start (OFM<1:0> = 01),
the slave PWMxTMR waits for the master’s OF_match
event. When this event occurs, if the EN bit is set, the
PWMxTMR begins counting and continues to count
until software clears the EN bit. Slave period events
reset the PWMxTMR to zero, after which, the timer
continues to count.
26.3.4
In Continuous Run Slave mode with Synchronous Start
and Timer Reset (OFM<1:0> = 11), the slave PWMxTMR
is inhibited from counting after the slave PWM enable is
set. The first master OF_match event starts the slave
PWMxTMR. Subsequent master OF_match events reset
the slave PWMxTMR timer value back to 1, after which,
the slave PWMxTMR continues to count. The next master
OF_match event resets the slave PWMxTMR back to 1 to
repeat the cycle. Slave period events that occur before
the master’s OF_match event will reset the slave
PWMxTMR to zero, after which, the timer will continue to
count. Slaves operating in this mode must have a
PWMxPH register pair value equal to, or greater than, 1;
otherwise, the phase match event will not occur
precluding the start of the PWM output duty cycle.
The offset timing will persist if both the master and
slave PWMxPR values are the same and the Slave
Offset mode is changed to Independent Run mode
while the PWM module is operating.
A detailed timing diagram of this mode used in
Standard PWM mode is shown in Figure 26-11.
Note:
A detailed timing diagram of this mode used with
Standard PWM mode is shown in Figure 26-9.
26.3.3
ONE-SHOT SLAVE MODE WITH
SYNC START
In One-Shot Slave mode with Synchronous Start
(OFM<1:0> = 10), the slave PWMxTMR waits until the
master’s OF_match event. The timer then begins counting, starting from the value that is already in the timer, and
continues to count until the period match event. When the
period event occurs, the timer resets to zero and stops
counting. The timer then waits until the next master
OF_match event, after which, it begins counting again to
repeat the cycle. An OF_match event that occurs before
the slave PWM has completed the triggered period will be
ignored. A slave period that is greater than the master
period, but less that twice the master period, will result in
a slave output every other master period.
Note:
During the time the slave timers are
resetting to zero, if another offset match
event is received, it is possible that the slave
PWM would not recognize this match event
and the slave timers would fail to begin
counting again. This would result in missing
duty cycles in the output of the slave PWM.
To prevent this from happening, avoid using
the same period for both the master and
slave PWMs.
CONTINUOUS RUN SLAVE MODE
WITH SYNC START AND TIMER
RESET
26.3.5
Unexpected results will occur if the slave
PWM_clock is a higher frequency than the
master PWM_clock.
OFFSET MATCH IN
CENTER-ALIGNED MODE
When a master is operating in Center-Aligned mode,
the offset match event depends on which direction the
PWMxTMR is counting. Clearing the OFO bit of the
PWMxOFCON register will cause the OF_match event
to occur when the timer is counting up. Setting the OFO
bit of the PWMxOFCON register will cause the
OF_match event to occur when the timer is counting
down. The OFO bit is ignored in Non-Center-Aligned
modes.
The OFO bit is double-buffered and requires setting the
LDA bit to take effect when the PWM module is
operating.
Detailed timing diagrams of Center-Aligned mode
using offset match control in Independent Slave with
Sync Start mode can be seen in Figure 26-12 and
Figure 26-13.
A detailed timing diagram of this mode used with
Standard PWM mode is shown in Figure 26-10.
DS40001775B-page 278
 2014-2015 Microchip Technology Inc.
 2014-2015 Microchip Technology Inc.
FIGURE 26-8:
INDEPENDENT RUN MODE TIMING DIAGRAM
Rev. 10-000 146B
7/8/201 5
Period
Duty Cycle
Phase
Offset
PWMxCLK
PWMxPR
10
PWMxPH
3
PWMxDC
5
PWMxOF
2
PWMxTMR
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
0
1
2
PWMxOUT
OFx_match
PHx_match
PRx_match
PWMyTMR
DS40001775B-page 279
PWMyPR
4
PWMyPH
0
PWMyDC
1
PWMyOUT
Note: PWMx = Master, PWMy = Slave
PIC16(L)F1764/5/8/9
DCx_match
SLAVE RUN MODE WITH SYNC START TIMING DIAGRAM
Rev. 10-000 147B
7/8/201 5
Period
Duty Cycle
Phase
Offset
PWMxCLK
PWMxPR
10
PWMxPH
3
PWMxDC
5
PWMxOF
2
PWMxTMR
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
1
2
3
4
0
1
2
3
4
0
1
2
3
4
0
PWMxOUT
OFx_match
PWMyTMR
0
PWMyPR
4
PWMyPH
0
PWMyDC
1
 2014-2015 Microchip Technology Inc.
PWMyOUT
Note: Master = PWMx, Slave = PWMy
PIC16(L)F1764/5/8/9
DS40001775B-page 280
FIGURE 26-9:
 2014-2015 Microchip Technology Inc.
FIGURE 26-10:
ONE-SHOT SLAVE RUN MODE WITH SYNC START TIMING DIAGRAM
Rev. 10-000 148B
7/8/201 5
Period
Duty Cycle
Phase
Offset
PWMxCLK
PWMxPR
10
PWMxPH
3
PWMxDC
5
PWMxOF
2
PWMxTMR
0
1
2
3
4
5
6
1
2
3
4
7
8
9
10
0
1
2
3
4
5
6
1
2
3
4
PWMxOUT
OFx_match
PWMyTMR
0
0
4
PWMyPH
0
PWMyDC
1
PWMyOUT
Note: Master = PWMx, Slave = PWMy
DS40001775B-page 281
PIC16(L)F1764/5/8/9
PWMyPR
CONTINUOUS SLAVE RUN MODE WITH IMMEDIATE RESET AND SYNC START TIMING DIAGRAM
Rev. 10-000 149B
7/8/201 5
Period
Duty Cycle
Phase
Offset
PWMxCLK
PWMxPR
10
PWMxPH
3
PWMxDC
5
PWMxOF
2
PWMxTMR
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
1
2
3
4
0
1
2
3
4
0
1
1
2
3
4
PWMxOUT
OFx_match
PWMyTMR
0
PWMyPR
4
PWMyPH
1
PWMyDC
2
 2014-2015 Microchip Technology Inc.
PWMyOUT
Note: Master= PWMx, Slave=PWMy
PIC16(L)F1764/5/8/9
DS40001775B-page 282
FIGURE 26-11:
 2014-2015 Microchip Technology Inc.
FIGURE 26-12:
OFFSET MATCH ON INCREMENTING TIMER TIMING DIAGRAM
Rev. 10-000 150B
7/9/201 5
Period
Duty Cycle
Offset
PWMxCLK
PWMxPR
6
PWMxDC
2
PWMxOF
2
PWMxTMR
0
1
2
3
4
5
6
6
5
4
3
2
0
1
2
3
4
4
3
2
1
0
1
0
0
1
2
3
0
1
PWMxOUT
OFx_match
PHx_match
DCx_match
PWMyTMR
0
PWMyPR
4
PWMyDC
1
PWMyOUT
Note: Master = PWMx, Slave = PWMy
0
DS40001775B-page 283
PIC16(L)F1764/5/8/9
PRx_match
OFFSET MATCH ON DECREMENTING TIMER TIMING DIAGRAM
Rev. 10-000 151B
7/9/201 5
Period
Duty Cycle
Offset
PWMxCLK
PWMxPR
6
PWMxDC
2
PWMxOF
2
PWMxTMR
0
1
2
3
4
5
6
6
5
4
3
2
1
0
0
1
2
3
0
1
2
3
4
4
3
PWMxOUT
OF5_match
PH5_match
DC5_match
PR5_match
PWMyTMR
0
 2014-2015 Microchip Technology Inc.
PWMyPR
4
PWMyDC
1
PWMyOUT
Note: Master = PWMx, Slave = PWMy
PIC16(L)F1764/5/8/9
DS40001775B-page 284
FIGURE 26-13:
PIC16(L)F1764/5/8/9
26.4
Reload Operation
Four of the PWM module control register pairs and one
control bit are double-buffered so that all can be
updated simultaneously. These include:
•
•
•
•
•
PWMxPHH:PWMxPHL register pair
PWMxDCH:PWMxDCL register pair
PWMxPRH:PWMxPRL register pair
PWMxOFH:PWMxOFL register pair
ODO control bit
When written to, these registers do not immediately
affect the operation of the PWM. By default, writes to
these registers will not be loaded into the PWM operating buffer registers until after the arming conditions are
met. The arming control has two methods of operation:
26.4.2
When the LDT bit is set, then the Triggered mode is
selected and a trigger event is required for the LDA bit to
take effect. The trigger source is the buffer load event of
one of the other PWM modules in the device. The triggering source is selected by the LDS bit of the PWMxLDCON
register. The buffers will be loaded at the first period event
following the trigger event. Triggered reloading is used
when a PWM module is operating as a slave to another
PWM and it is necessary to synchronize the buffer
reloads in both modules.
Note 1: The buffer load operation clears the LDA
bit.
2: If the LDA bit is set at the same time as
PWMxTMR = PWMxPR, the LDA bit is
ignored until the next period event. Such is
the case when triggered reload is selected
and the triggering event occurs
simultaneously with the target’s period
event.
• Immediate
• Triggered
The LDT bit of the PWMxLDCON register controls the
arming method. Both methods require the LDA bit to be
set. All four buffer pairs will load simultaneously at the
loading event.
26.4.1
IMMEDIATE RELOAD
When the LDT bit is clear, then the Immediate mode is
selected and the buffers will be loaded at the first period
event after the LDA bit is set. Immediate reloading is
used when a PWM module is operating stand-alone or
when the PWM module is operating as a master to
other slave PWM modules.
 2014-2015 Microchip Technology Inc.
TRIGGERED RELOAD
26.5
Operation in Sleep Mode
Each PWM module will continue to operate in Sleep
mode when either the HFINTOSC or LFINTOSC is
selected as the clock source by PWMxCLKCON<1:0>.
26.6
Interrupts
Each PWM module has four independent interrupts
based on the phase, duty cycle, period and offset match
events. The interrupt flag is set on the rising edge of each
of these signals. Refer to Figures 26-12 and 26-13 for
detailed timing diagrams of the match signals.
DS40001775B-page 285
PIC16(L)F1764/5/8/9
26.7
Register Definitions: PWM Control
Long bit name prefixes for the 16-bit PWM peripherals
are shown in Table 26-1. Refer to Section 1.1 “Register
and Bit Naming Conventions” for more information.
TABLE 26-1:
BIT NAME PREFIXES
Peripheral
Bit Name Prefix
PWM5
PWM5
PWM6(1)
PWM6
Note 1:
PIC16(L)F1768/9 devices only.
REGISTER 26-1:
PWMxCON: PWMx CONTROL REGISTER
R/W-0/0
U-0
R/HS/HC-0/0
R/W-0/0
EN
—
OUT
POL
R/W-0/0
R/W-0/0
U-0
U-0
—
—
MODE<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
HC = Hardware Clearable bit
HS = Hardware Settable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
EN: PWMx Module Enable bit
1 = Module is enabled
0 = Module is disabled
bit 6
Unimplemented: Read as ‘0’
bit 5
OUT: Output State of the PWMx Module bit
bit 4
POL: PWMx Output Polarity Control bit
1 = PWMx output active state is low
0 = PWMx output active state is high
bit 3-2
MODE<1:0>: PWMx Mode Control bits
11 = Center-Aligned mode
10 = Toggle On Match mode
01 = Set On Match mode
00 = Standard PWM mode
bit 1-0
Unimplemented: Read as ‘0’
DS40001775B-page 286
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
REGISTER 26-2:
PWMxINTE: PWMx INTERRUPT ENABLE REGISTER
U-0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
—
—
—
—
OFIE
PHIE
DCIE
PRIE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
Unimplemented: Read as ‘0’
bit 3
OFIE: Offset Interrupt Enable bit
1 = Interrupts CPU on offset match
0 = Does not interrupt CPU on offset match
bit 2
PHIE: Phase Interrupt Enable bit
1 = Interrupts CPU on phase match
0 = Does not interrupt CPU on phase match
bit 1
DCIE: Duty Cycle Interrupt Enable bit
1 = Interrupts CPU on duty cycle match
0 = Does not interrupt CPU on duty cycle match
bit 0
PRIE: Period Interrupt Enable bit
1 = Interrupts CPU on period match
0 = Does not interrupt CPU on period match
 2014-2015 Microchip Technology Inc.
DS40001775B-page 287
PIC16(L)F1764/5/8/9
REGISTER 26-3:
PWMxINTF: PWMx INTERRUPT REQUEST REGISTER
U-0
U-0
U-0
U-0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
—
—
—
—
OFIF(1)
PHIF(1)
DCIF(1)
PRIF(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
HS = Hardware Settable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
Unimplemented: Read as ‘0’
bit 3
OFIF: Offset Interrupt Flag bit(1)
1 = Offset match event occurred
0 = Offset match event did not occur
bit 2
PHIF: Phase Interrupt Flag bit(1)
1 = Phase match event occurred
0 = Phase match event did not occur
bit 1
DCIF: Duty Cycle Interrupt Flag bit(1)
1 = Duty cycle match event occurred
0 = Duty cycle match event did not occur
bit 0
PRIF: Period Interrupt Flag bit(1)
1 = Period match event occurred
0 = Period match event did not occur
Note 1:
Bit is forced clear by hardware while module is disabled (EN = 0).
DS40001775B-page 288
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
REGISTER 26-4:
U-0
PWMxCLKCON: PWMx CLOCK CONTROL REGISTER
R/W-0/0
—
R/W-0/0
R/W-0/0
PS<2:0>
U-0
U-0
—
—
R/W-0/0
bit 7
R/W-0/0
CS<1:0>
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
Unimplemented: Read as ‘0’
bit 6-4
PS<2:0>: Clock Source Prescaler Select bits
111 = Divide clock source by 128
110 = Divide clock source by 64
101 = Divide clock source by 32
100 = Divide clock source by 16
011 = Divide clock source by 8
010 = Divide clock source by 4
001 = Divide clock source by 2
000 = No Prescaler
bit 3-2
Unimplemented: Read as ‘0’
bit 1-0
CS<1:0>: Clock Source Select bits
11 = Reserved
10 = LFINTOSC (continues to operate during Sleep)
01 = HFINTOSC (continues to operate during Sleep)
00 = FOSC
 2014-2015 Microchip Technology Inc.
DS40001775B-page 289
PIC16(L)F1764/5/8/9
REGISTER 26-5:
R/W/HC-0/0
PWMxLDCON: PWMx RELOAD TRIGGER SOURCE SELECT REGISTER
R/W-0/0
(1)
LDA
LDT
(3)
U-0
U-0
U-0
U-0
U-0
R/W-0/0
—
—
—
—
—
LDS(2,3)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
HC = Hardware Clearable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
LDA: Load Buffer Armed bit(1)
If LDT = 1:
1 = Loads the ODO bit, and OFx, PHx, DCx and PRx buffers at the end of the period in which the
selected trigger occurs
0 = Does not load buffers, load has completed
If LDT = 0:
1 = Loads the ODO bit, and OFx, PHx, DCx and PRx buffers at the end of the current period
0 = Does not load buffers, load has completed
bit 6
LDT: Load Buffer on Trigger bit(3)
1 = Waits for trigger selected by the LDS<1:0> bits to occur before enabling the LDA bit
0 = Load triggering is disabled; buffer loads are controlled by the LDA bit alone
bit 5-1
Unimplemented: Read as ‘0’
bit 0
LDS: Load Trigger Source Select bit(2,3)
1 = LD6_trigger
0 = LD5_trigger
Note 1:
2:
3:
This bit is cleared by the module after a reload operation. It can be cleared in software to clear an existing
arming event.
The source corresponding to a PWM module’s own LDx_trigger is reserved.
PIC16(L)F1768/9 only.
DS40001775B-page 290
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
REGISTER 26-6:
U-0
PWMxOFCON: PWMx OFFSET TRIGGER SOURCE SELECT REGISTER
R/W-0/0
—
R/W-0/0
OFM<1:0>
R/W-0/0
(2)
(1)
OFO
U-0
U-0
U-0
R/W-0/0
—
—
—
OFS(1,2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
Unimplemented: Read as ‘0’
bit 6-5
OFM<1:0>: Offset Mode Select bits(2)
11 = Continuous Slave Run mode with offset triggered timer Reset and synchronized start
10 = One-Shot Slave Run mode with offset triggered synchronized start
01 = Slave Run mode with offset triggered synchronized start
00 = Independent Run mode
bit 4
OFO: Offset Match Output Control bit(1)
If MODE<1:0> = 11 (PWM Center-Aligned mode):
1 = OFx_match occurs when the PWMxTMR is counting up
0 = OFx_match occurs when the PWMxTMR is counting down
If MODE<1:0> = 00, 01 or 10 (All Other modes):
This bit is ignored.
bit 3-1
Unimplemented: Read as ‘0’
bit 0
OFS: Offset Trigger Source Select bit(1,2)
1 = OF6_match
0 = OF5_match
Note 1:
2:
The source corresponding to the PWM module’s own OFx_match is reserved.
PIC16(L)F1768/9 only.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 291
PIC16(L)F1764/5/8/9
REGISTER 26-7:
R/W-x/u
PWMxPHH: PWMx PHASE COUNT HIGH REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PH<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
PH<15:8>: PWMx Phase High bits
Upper eight bits of PWMx phase count.
REGISTER 26-8:
R/W-x/u
PWMxPHL: PWMx PHASE COUNT LOW REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PH<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
PH<7:0>: PWMx Phase Low bits
Lower eight bits of PWMx phase count.
DS40001775B-page 292
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
REGISTER 26-9:
R/W-x/u
PWMxDCH: PWMx DUTY CYCLE COUNT HIGH REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
DC<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
DC<15:8>: PWMx Duty Cycle High bits
Upper eight bits of PWMx duty cycle count.
REGISTER 26-10: PWMxDCL: PWMx DUTY CYCLE COUNT LOW REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
DC<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
DC<7:0>: PWMx Duty Cycle Low bits
Lower eight bits of PWMx duty cycle count.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 293
PIC16(L)F1764/5/8/9
REGISTER 26-11: PWMxPRH: PWMx PERIOD COUNT HIGH REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PR<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
PR<15:8>: PWMx Period High bits
Upper eight bits of PWMx period count.
REGISTER 26-12: PWMxPRL: PWMx PERIOD COUNT LOW REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PR<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
PR<7:0>: PWMx Period Low bits
Lower eight bits of PWMx period count.
DS40001775B-page 294
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
REGISTER 26-13: PWMxOFH: PWMx OFFSET COUNT HIGH REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
OF<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
OF<15:8>: PWMx Offset High bits
Upper eight bits of PWMx offset count.
REGISTER 26-14: PWMxOFL: PWMx OFFSET COUNT LOW REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
OF<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
OF<7:0>: PWMx Offset Low bits
Lower eight bits of PWMx offset count.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 295
PIC16(L)F1764/5/8/9
REGISTER 26-15: PWMxTMRH: PWMx TIMER HIGH REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TMR<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
TMR<15:8>: PWMx Timer High bits
Upper eight bits of PWMx timer counter.
REGISTER 26-16: PWMxTMRL: PWMx TIMER LOW REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TMR<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
TMR<7:0>: PWMx Timer Low bits
Lower eight bits of PWMx timer counter.
DS40001775B-page 296
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
Note:
There are no long and short bit name variants for the following three mirror registers.
REGISTER 26-17: PWMEN: PWMEN BIT MIRROR REGISTER
U-0
—
U-0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
U-0
—
MPWM6EN(1)
MPWM5EN
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
MPWMxEN: PWM6(1)/PWM5 Enable bits
Mirror copy of each PWMx module’s PWMxCON<7> bit.
bit 3-0
Unimplemented: Read as ‘0’
Note 1:
PIC16(L)F1768/9 only. (Applies also to Register 26-18 and Register 26-19.)
REGISTER 26-18: PWMLD: LDA BIT MIRROR REGISTER
U-0
—
U-0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
U-0
—
MPWM6LD(1)
MPWM5LD
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
MPWMxLDA: PWM6(1)/PWM5 LDA bits
Mirror copy of each PWMx module’s PWMxLDCON<7> bit.
bit 3-0
Unimplemented: Read as ‘0’
REGISTER 26-19: PWMOUT: PWMOUT BIT MIRROR REGISTER
U-0
—
U-0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
U-0
—
MPWM6OUT(1)
MPWM5OUT
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
MPWMxOUT: PWM6(1)/PWM5 OUT bits
Mirror copy of each PWMx module’s PWMxCON<5> bit.
bit 3-0
Unimplemented: Read as ‘0’
 2014-2015 Microchip Technology Inc.
DS40001775B-page 297
PIC16(L)F1764/5/8/9
TABLE 26-2:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PWMx
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
—
IRCF<3:0>
Bit 1
Bit 0
SCS<1:0>
Register
on Page
85
OSCCON
SPLLEN
PWMEN
—
—
MPWM6EN(1)
MPWM5EN
—
—
—
—
297
PWMLD
—
—
MPWM6LD(1)
MPWM5LD
—
—
—
—
297
PWMOUT
—
—
—
—
—
—
297
MPWM6OUT(1) MPWM5OUT
PWM5PHL
PH<7:0>
292
PWM5PHH
PH<15:8>
292
PWM5DCL
DC<7:0>
293
PWM5DCH
DC<15:8>
293
PWM5PRH
PR<15:8>
294
PWM5PRL
PR<7:0>
294
PWM5OFH
OF<15:8>
295
PWM5OFL
OF<7:0>
295
TMR<15:8>
296
PWM5TMRH
PWM5TMRL
TMR<7:0>
296
PWM5CON
EN
—
OUT
POL
PWM5INTE
—
—
—
—
OFIE
PWM5INTF
—
—
—
—
OFIF
PWM5CLKCON
—
—
—
PWM5LDCON
LDA
PWM5OFCON
MODE<1:0>
PS<2:0>
LDT(1)
—
—
—
286
PHIE
DCIE
PRIE
287
PHIF
DCIF
PRIF
CS<1:0>
—
—
—
—
—
LDS(1)
(1)
OFO
—
—
—
OFS(1)
OFM<1:0>
288
289
290
291
PWM6PHL(1)
PH<7:0>
PWM6PHH(1)
PH<15:8>
292
PWM6DCL(1)
DC<7:0>
293
PWM6DCH(1)
DC<15:8>
293
PWM6PRL(1)
PR<7:0>
294
PWM6PRH(1)
PR<15:8>
294
PWM6OFL(1)
OF<7:0>
295
PWM6OFH(1)
OF<15:8>
295
PWM6TMRL(1)
TMR<7:0>
296
(1)
292
TMR<15:8>
PWM6TMRH
296
PWM6CON(1)
EN
—
OUT
POL
PWM6INTE(1)
—
—
—
—
OFIE
PWM6INTF(1)
—
—
—
—
OFIF
PWM6CLKCON(1)
—
—
—
PWM6LDCON(1)
(1)
PWM6OFCON
Legend:
Note 1:
CONFIG1
—
PS<2:0>
LDT(1)
—
—
286
PHIE
DCIE
PRIE
287
PHIF
DCIF
PRIF
CS<1:0>
288
289
—
—
—
—
—
LDS(1)
290
(1)
OFO
—
—
—
OFS(1)
291
Bit 8/0
Register
on Page
OFM<1:0>
— = unimplemented location, read as ‘0’. Shaded cells are not used by PWM.
PIC16(L)F1768/9 only
TABLE 26-3:
Name
LDA
MODE<1:0>
Bits
SUMMARY OF CONFIGURATION WORDS WITH CLOCK SOURCES
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
IESO
CLKOUTEN
13:8
—
—
FCMEN
7:0
CP
MCLRE
PWRTE
WDTE<1:0>
Bit 10/2
Bit 9/1
BOREN<1:0>
FOSC<2:0>
—
64
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
DS40001775B-page 298
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
27.0
COMPLEMENTARY OUTPUT
GENERATOR (COG) MODULE
The primary purpose of the Complementary Output
Generator (COG) is to convert a single output PWM
signal into a two-output complementary PWM signal.
The COG can also convert two separate input events
into a single or complementary PWM output.
The COG PWM frequency and duty cycle are
determined by a rising event input and a falling event
input. The rising event and falling event may be the
same source. Sources may be synchronous or
asynchronous to the COG_clock.
The rate at which the rising event occurs determines
the PWM frequency. The time from the rising event to
the falling event determines the duty cycle.
A selectable clock input is used to generate the phase
delay, blanking and dead-band times. Dead-band time
can also be generated with a programmable delay
chain, which is independent from all clock sources.
Simplified block diagrams of the various COG modes
are shown in Figure 27-2 through Figure 27-6.
The COG module has the following features:
• Six modes of operation:
- Steered PWM mode
- Synchronous Steered PWM mode
- Forward Full-Bridge mode
- Reverse Full-Bridge mode
- Half-Bridge mode
- Push-Pull mode
• Selectable COG_clock clock source
• Independently selectable rising event sources
• Independently selectable falling event sources
• Independently selectable edge or level event
sensitivity
• Independent output polarity selection
• Phase delay with independent rising and falling
delay times
• Dead-band control with:
- independent rising and falling event
dead-band times
- Synchronous and asynchronous timing
• Blanking control with independent rising and
falling event blanking times
• Auto-shutdown control with:
- Independently selectable shutdown sources
- Auto-restart enable
- Auto-shutdown pin override control
(high, low, off and High-Z)
 2014-2015 Microchip Technology Inc.
27.1
Output to Pins (all modes)
The COG peripheral has four outputs: COGA, COGB,
COGC and COGD.
The operating mode, selected with the MD<2:0> bits of
the COGxCON0 register, determines the waveform
available at each output. An individual peripheral
source control for each device pin selects the pin or
pins at which the outputs will appear. Please refer to the
RxyPPS register (Register 12-2) for more information.
27.2
Event-Driven PWM (All Modes)
Besides generating PWM and complementary outputs
from a single PWM input, the COG can also generate
PWM waveforms from a periodic rising event and a
separate falling event. In this case, the falling event is
usually derived from analog feedback within the
external PWM driver circuit. In this configuration,
high-power switching transients may trigger a false
falling event that needs to be blanked out. The COG
can be configured to blank falling (and rising) event
inputs for a period of time immediately following the
rising (and falling) event drive output. This is referred to
as input blanking and is covered in Section 27.8
“Blanking Control”.
It may be necessary to guard against the possibility of
external circuit Faults. In this case, the active drive
must be terminated before the Fault condition causes
damage. This is referred to as auto-shutdown and is
covered in Section 27.10 “Auto-Shutdown Control”.
The COG can be configured to operate in phase
delayed conjunction with another PWM. The active
drive cycle is delayed from the rising event by a phase
delay timer. Phase delay is covered in more detail in
Section 27.9 “Phase Delay”.
A typical operating waveform, with phase delay and
dead band, generated from a single CCP1 input is
shown in Figure 27-10.
DS40001775B-page 299
PIC16(L)F1764/5/8/9
27.3
27.3.1
27.3.2
Modes of Operation
STEERED PWM MODES
In Steered PWM mode, the PWM signal derived from
the input event sources is output as a single-phase
PWM which can be steered to any combination of the
four COG outputs. Output steering takes effect on the
instruction cycle following the write to the COGxSTR
register.
Synchronous Steered PWM mode is identical to the
Steered PWM mode except that changes to the output
steering take effect on the first rising event after the
COGxSTR register write. Static output data is not
synchronized.
Steering mode configurations are shown in Figure 27-2
and Figure 27-3.
Steered PWM and Synchronous Steered PWM modes
are selected by setting the MD<2:0> bits of the
COGxCON0 register (Register 27-1) to ‘000’ and
‘001’, respectively.
FIGURE 27-1:
FULL-BRIDGE MODES
In both Forward and Reverse Full-Bridge modes, two of
the four COG outputs are active and the other two are
inactive. Of the two active outputs, one is modulated by
the PWM input signal and the other is on at 100% duty
cycle. When the direction is changed, the dead-band
time is inserted to delay the modulated output. This
gives the unmodulated driver time to shut down,
thereby, preventing shoot-through current in the series
connected power devices.
In Forward Full-Bridge mode, the PWM input
modulates the COGxD output and drives the COGA
output at 100%.
In Reverse Full-Bridge mode, the PWM input
modulates the COGxB output and drives the COGxC
output at 100%.
The full-bridge configuration is shown in Figure 27-4.
Typical full-bridge waveforms are shown in
Figure 27-12 and Figure 27-13.
Full-Bridge Forward and Full-Bridge Reverse modes
are selected by setting the MD<2:0> bits of the
COGxCON0 register to ‘010’ and ‘011’, respectively.
EXAMPLE OF FULL-BRIDGE APPLICATION
V+
FET
Driver
QC
QA
FET
Driver
COGxA
Load
COGxB
FET
Driver
COGxC
FET
Driver
QD
QB
VCOGxD
DS40001775B-page 300
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
27.3.3
HALF-BRIDGE MODE
In Half-Bridge mode, the COG generates a two-output
complementary PWM waveform from rising and falling
event sources. In the simplest configuration, the rising
and falling event sources are the same signal, which is
a PWM signal with the desired period and duty cycle.
The COG converts this single PWM input into a dual
complementary PWM output. The frequency and duty
cycle of the dual PWM output match those of the single
input PWM signal. The off-to-on transition of each
output can be delayed from the on-to-off transition of
the other output, thereby, creating a time immediately
after the PWM transition where neither output is driven.
This is referred to as dead-band time and is covered in
Section 27.7 “Dead-Band Control”.
The Half-Bridge configuration is shown in Figure 27-5. A
typical operating waveform, with dead band, generated
from a single CCP1 input is shown in Figure 27-9.
27.3.4
PUSH-PULL MODE
In Push-Pull mode, the COG generates a single PWM
output that alternates between the two pairs of the
COG outputs at every PWM period. COGxA has the
same signal as COGxC. COGxB has the same signal
as COGxD. The output drive activates with the rising
input event and terminates with the falling event input.
Each rising event starts a new period and causes the
output to switch to the COG pair not used in the
previous period.
The Push-Pull mode configuration is shown in
Figure 27-6. A typical Push-Pull mode waveform
generated from a single CCP1 input is shown in
Figure 27-11.
Push-Pull mode is selected by setting the MD<2:0> bits
of the COGxCON0 register to ‘101’.
The primary output is available on either, or both, COGxA
and COGxC. The complementary output is available on
either, or both, COGxB and COGxD.
Half-Bridge mode is selected by setting the MD<2:0>
bits of the COGxCON0 register to ‘100’.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 301
 2014-2015 Microchip Technology Inc.
FIGURE 27-2:
SIMPLIFIED COG BLOCK DIAGRAM (STEERED PWM MODE, MD<2:0> = 0)
ASDAC<1:0>
Reserved
11
HFINTOSC
10
FOSC
01
FOSC/4
CS<1:0>
1
0
Hi-Z
COG_clock
1
1
00
POLA
SDATA
ASDBD<1:0>
Clock
src15
1
0
Hi-Z
Reset Dominates
rising_event
S Q
count_en
0
POLB
SDATB
0
STRB
ASDAC<1:0>
1
0
Hi-Z
Clock
src15
11
10
01
00
1
falling_event
COGxC
1
POLC
count_en
SDATC
0
STRC
ASDBD<1:0>
1
0
Hi-Z
EN
Source 7
AS7E
11
10
01
00
1
COGxD
1
0
POLD
Auto-Shutdown Source
DS40001775B-page 302
Source 0
AS0E
SDATD
0
STRD
S Q
ARSEN
Write ASE Low
R
Set Dominates
ASE
S
D Q
PIC16(L)F1764/5/8/9
0
src0
Write ASE High
COGxB
1
Falling Input Block
Shutdown Sources,
See Register 27-12.
11
10
01
00
1
R Q
src0
Falling Event Sources,
See Register 27-7 and
Register 27-8.
COGxA
0
0
STRA
Rising Input Block
Rising Event Sources,
See Register 27-3 and
Register 27-4.
11
10
01
00
SIMPLIFIED COG BLOCK DIAGRAM (SYNCHRONOUS STEERED PWM MODE, MD<2:0> = 1)
ASDAC<1:0>
Reserved
HFINTOSC
11
10
FOSC
01
FOSC/4
CS<1:0>
1
0
High-Z
COG_clock
1
1
00
POLA
STRA
Rising Input Block
src15
Rising Event Sources,
See Register 27-3 and
Register 27-4.
SDATA
D Q
ASDBD<1:0>
1
0
High-Z
Reset Dominates
S Q
rising_event
11
10
01
00
COGxB
1
0
POLB
STRB
Falling Input Block
src15
1
R Q
count_en
SDATB
0
D Q
ASDAC<1:0>
1
0
High-Z
Clock
11
10
01
00
1
falling_event
COGxC
1
src0
0
POLC
count_en
STRC
SDATC
0
D Q
ASDBD<1:0>
1
0
High-Z
EN
 2014-2015 Microchip Technology Inc.
Source 7
AS7E
Shutdown sources
See Register 27-12.
COGxA
0
0
Clock
src0
Falling Event Sources,
See Register 27-7 and
Register 27-8.
11
10
01
00
11
10
01
00
1
COGxD
1
0
Auto-Shutdown Source
POLD
STRD
SDATD
0
D Q
Source 0
AS0E
ASE
S Q
Write ASE High
ARSEN
Write ASE Low
R
Set Dominates
S
D Q
PIC16(L)F1764/5/8/9
DS40001775B-page 303
FIGURE 27-3:
 2014-2015 Microchip Technology Inc.
FIGURE 27-4:
SIMPLIFIED COG BLOCK DIAGRAM (FULL-BRIDGE MODES, FORWARD: MD<2:0> = 2, REVERSE: MD<2:0> = 3)
ASDAC<1:0>
Reserved
HFINTOSC
11
10
FOSC
01
FOSC/4
CS<1:0>
1
0
High-Z
11
10
01
00
COG_clock
1
COGxA
0
00
Rising Dead-Band Block
Rising Input Block
src15
Rising Event Sources,
See Register 27-3 and
Register 27-4.
Clock
Clock
Reset Dominates
POLA
ASDBD<1:0>
signal_out
signal_in
1
0
High-Z
S Q
rising_event
11
10
01
00
R Q
src0
COGxB
1
0
count_en
Falling Input Block
Falling Event Sources,
See Register 27-7 and
Register 27-8.
src15
Falling Dead-Band Block
ASDAC<1:0>
POLB
1
0
High-Z
Clock
Clock
signal_out
signal_in
11
10
01
00
1
src0
COGxC
0
count_en
Forward/Reverse
MD0
ASDBD<1:0>
1
0
High-Z
D Q
EN
Q
Source 7
AS7E
Shutdown Sources,
See Register 27-12.
POLC
1
COGxD
0
Auto-Shutdown Source
DS40001775B-page 304
POLD
Source 0
AS0E
ASE
S Q
Write ASE High
11
10
01
00
ARSEN
Write ASE Low
R
Set Dominates
S
D Q
PIC16(L)F1764/5/8/9
falling_event
SIMPLIFIED COG BLOCK DIAGRAM (HALF-BRIDGE MODE, MD<2:0> = 4)
ASDAC<1:0>
Reserved
HFINTOSC
11
10
FOSC
01
FOSC/4
CS<1:0>
1
0
High-Z
11
10
01
00
COG_clock
1
00
Rising Input Block
src15
Rising Event Sources,
See Register 27-3
and Register 27-4.
COGxA
0
Rising Dead-Band Block
Clock
Reset Dominates
S Q
rising_event
POLA
ASDBD<1:0>
1
0
High-Z
Clock
signal_out
signal_in
11
10
01
00
1
R Q
src0
COGxB
0
count_en
Falling Input Block
Falling Event Sources,
See Register 27-7 and
Register 27-8.
src15
Falling Dead-Band Block
ASDAC<1:0>
POLB
1
0
High-Z
Clock
Clock
signal_out
signal_in
11
10
01
00
1
falling_event
src0
COGxC
0
count_en
POLC
ASDBD<1:0>
 2014-2015 Microchip Technology Inc.
1
0
High-Z
EN
Source 7
AS7E
Shutdown Sources,
See Register 27-12.
1
COGxD
0
Auto-Shutdown Source
POLD
Source 0
AS0E
ASE
S Q
Write ASE High
11
10
01
00
ARSEN
Write ASE Low
R
Set Dominates
S
D Q
PIC16(L)F1764/5/8/9
DS40001775B-page 305
FIGURE 27-5:
 2014-2015 Microchip Technology Inc.
FIGURE 27-6:
SIMPLIFIED COG BLOCK DIAGRAM (PUSH-PULL MODE, MD<2:0> = 5)
ASDAC<1:0>
Reserved
HFINTOSC
11
10
FOSC
FOSC/4
01
CS<1:0>
1
0
High-Z
11
10
01
00
COG_clock
1
00
Rising Input Block
src15
Rising Event Sources,
See Register 27-3
and Register 27-4.
POLA
ASDBD<1:0>
Push-Pull
Clock
Reset Dominates
rising_event
S Q
1
0
High-Z
D Q
R
Q
11
10
01
00
R Q
src0
src15
ASDAC<1:0>
POLB
Falling Input Block
COGxB
1
0
count_en
Falling Event Sources,
See Register 27-7 and
Register 27-8.
COGxA
0
1
0
High-Z
Clock
11
10
01
00
1
src0
COGxC
0
count_en
POLC
ASDBD<1:0>
1
0
High-Z
EN
Source 7
AS7E
Shutdown Sources,
See Register 27-12.
1
COGxD
0
Auto-Shutdown Source
DS40001775B-page 306
POLD
Source 0
AS0E
ASE
S Q
Write ASE High
11
10
01
00
ARSEN
Write ASE Low
R
Set Dominates
S
D Q
PIC16(L)F1764/5/8/9
falling_event
PIC16(L)F1764/5/8/9
FIGURE 27-7:
COG (RISING/FALLING) INPUT BLOCK
Clock
PH(R/F)<3:0>
Blanking
=
Cnt/Clr
count_en
Phase
Delay
BLK(F/R)<3:0>
src15
(R/F)IS15
(R/F)SIM15
D Q
1
LE
0
D Q
1
LE
0
(rising/falling)_event
src1 through src14
(R/F)IS1 through (R/F)IS14
(R/F)SIM1 through (R/F)SIM14
src0
(R/F)IS0
(R/F)SIM0
FIGURE 27-8:
COG (RISING/FALLING) DEAD-BAND BLOCK
(R/F)DBTS
Synchronous
Delay
=
Cnt/Clr
Clock
0
1
0
DBR<3:0>
1
Asynchronous
Delay Chain
signal_in
 2014-2015 Microchip Technology Inc.
signal_out
DS40001775B-page 307
PIC16(L)F1764/5/8/9
FIGURE 27-9:
TYPICAL HALF-BRIDGE MODE COG OPERATION WITH CCP1
COG_clock
Source
CCP1
COGxA
Rising Event Dead-Band
Falling Event Dead-Band
Falling Event Dead-Band
COGxB
FIGURE 27-10:
HALF-BRIDGE MODE COG OPERATION WITH CCP1 AND PHASE DELAY
COG_clock
Source
CCP1
COGxA
Falling Event Dead-Band
Phase Delay
Rising Event
Dead-Band
COGxB
FIGURE 27-11:
Falling Event
Dead-Band
PUSH-PULL MODE COG OPERATION WITH CCP1
CCP1
COGxA
COGxB
DS40001775B-page 308
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FIGURE 27-12:
FULL-BRIDGE FORWARD MODE COG OPERATION WITH CCP1
CCP1
COGxA
COGxB
COGxC
COGxD
FIGURE 27-13:
FULL-BRIDGE MODE COG OPERATION WITH CCP1 AND DIRECTION CHANGE
CCP1
COGxA
Falling Event Dead-Band
COGxB
COGxC
COGxD
MD0
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27.4
Clock Sources
The COG_clock is used as the reference clock to the
various timers in the peripheral. Timers that use the
COG_clock include:
• Rising and falling dead-band time
• Rising and falling blanking time
• Rising and falling event phase delay
Clock sources available for selection include:
• 16 MHz HFINTOSC (active during Sleep)
• Instruction clock (FOSC/4)
• System clock (FOSC)
The clock source is selected with the CS<1:0> bits of
the COGxCON0 register (Register 27-1).
27.5
Selectable Event Sources
The COG uses any combination of independently selectable event sources to generate the complementary
waveform. Sources fall into two categories:
• Rising event sources
• Falling event sources
The rising event sources are selected by setting bits in
the COGxRIS0 and COGxRIS1 registers (Register 27-3
and Register 27-4). The falling event sources are
selected by setting bits in the COGxFIS0 and COGxF1
registers (Register 27-7 and Register 27-8). All selected
sources are OR’d together to generate the
corresponding event signal. Refer to Figure 27-7.
27.5.1
EDGE vs. LEVEL SENSING
Event input detection may be selected as level or
edge-sensitive. The Detection mode is individually selectable for every source. Rising Source Detection modes are
selected with the COGxRSIM0 and COGxRSIM1
registers (Register 27-5 and Register 27-6). Falling
Source Detection modes are selected with the
COGxFSIM0 and COGxFSIM1 registers (Register 27-9
and Register 27-10). A set bit selects edge detection for
the corresponding event source. A cleared bit selects
level detection.
In general, events that are driven from a periodic source
should be edge-detected and events that are derived from
voltage thresholds at the target circuit should be
level-sensitive. Consider the following two examples:
1. The first example is an application in which the
period is determined by a 50% duty cycle clock on the
rising event input and the COG output duty cycle is
determined by a voltage level fed back through a comparator on the falling event input. If the clock input is
level-sensitive, duty cycles less than 50% will exhibit
erratic operation because the level-sensitive clock will
suppress the comparator feedback.
2. The second example is similar to the first except
that the duty cycle is close to 100%. The feedback
comparator high-to-low transition trips the COG drive off,
but almost immediately the period source turns the drive
back on. If the off cycle is short enough, the comparator
input may not reach the low side of the hysteresis band
precluding an output change. The comparator output
stays low and without a high-to-low transition to trigger
the edge sense, the drive of the COG output will be stuck
in a constant drive-on condition. See Figure 27-14.
FIGURE 27-14:
EDGE vs. LEVEL SENSE
Rising (CCP1)
Falling (C1OUT)
C1IN-
hyst
COGOUT
Edge-Sensitive
Rising (CCP1)
Falling (C1OUT)
C1IN-
hyst
COGOUT
Level-Sensitive
DS40001775B-page 310
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27.5.2
RISING EVENT
The rising event starts the PWM output active duty
cycle period. The rising event is the low-to-high
transition of the rising_event output. When the rising
event phase delay and dead-band time values are zero,
the primary output starts immediately. Otherwise, the
primary output is delayed. The rising event source
causes all the following actions:
•
•
•
•
•
Start rising event phase delay counter (if enabled)
Clear complementary output after phase delay
Start falling event input blanking (if enabled)
Start dead-band delay (if enabled)
Set primary output after dead-band delay expires
27.5.3
FALLING EVENT
The falling event terminates the PWM output active duty
cycle period. The falling event is the high-to-low
transition of the falling_event output. When the falling
event phase delay and dead-band time values are zero,
the complementary output starts immediately. Otherwise,
the complementary output is delayed. The falling event
source causes all the following actions:
• Start falling event phase delay counter (if
enabled)
• Clear primary output
• Start rising event input blanking (if enabled)
• Start falling event dead-band delay (if enabled)
• Set complementary output after dead-band delay
expires
27.6
Output Control
Upon disabling, or immediately after enabling the COG
module, the primary COG outputs are inactive and
complementary COG outputs are active.
27.6.1
OUTPUT ENABLES
There are no output enable controls in the COG
module. Instead, each device pin has an individual
output selection control called the PPS register. All
four COG outputs are available for selection in the
PPS register of every pin.
When a COG output is enabled by PPS selection, the
output on the pin has several possibilities which depend
on the mode, steering control, EN bit and shutdown
state, as shown in Table 27-1 and Table 27-2.
.
TABLE 27-1:
EN Bit
PIN OUTPUT STATES
MD<2:0> = 00x
STR Bit Shutdown
Output
x
0
Inactive
Static Steering Data
x
1
Active
Shutdown Override
0
1
Inactive
Inactive State
1
1
Inactive
Active PWM Signal
 2014-2015 Microchip Technology Inc.
TABLE 27-2:
EN Bit
PIN OUTPUT STATES
MD<2:0> > 001
STR Bit Shutdown
Inactive
Output
Inactive State
x
x
x
x
Active
Shutdown Override
1
x
Inactive
Active PWM Signal
27.6.2
POLARITY CONTROL
The polarity of each COG output can be selected
independently. When the output polarity bit is set, the
corresponding output is active-low. Clearing the output
polarity bit configures the corresponding output as
active-high. However, polarity affects the outputs in
only one of the four Shutdown Override modes. See
Section 27.10 “Auto-Shutdown Control” for more
details.
Output polarity is selected with the POLA through POLD
bits of the COGxCON1 register (Register 27-2).
27.7
Dead-Band Control
The dead-band control provides for non-overlapping
PWM output signals to prevent shoot-through current
in the external power switches. Dead-band time
affects the output only in the Half-Bridge mode and
when changing direction in the Full-Bridge mode.
The COG contains two dead-band timers. One
dead-band timer is used for rising event dead-band
control. The other is used for falling event dead-band
control. Timer modes are selectable as either:
• Asynchronous delay chain
• Synchronous counter
The Dead-Band Timer mode is selected for the rising
event and falling event dead-band times, with the
respective RDBS and FDBS bits of the COGxCON1
register (Register 27-2).
In Half-Bridge mode, the rising event dead-band time
delays all selected primary outputs from going active
for the selected dead-band time after the rising event.
COGxA and COGxC are the primary outputs in
Half-Bridge mode.
In Half-Bridge mode, the falling event dead-band time
delays all selected complementary outputs from going
active for the selected dead-band time after the falling
event. COGxB and COGxD are the complementary
outputs in Half-Bridge mode.
In Full-Bridge mode, the dead-band delay occurs only
during direction changes. The modulated output is
delayed for the falling event dead-band time after a
direction change from forward to reverse. The modulated
output is delayed for the rising event dead-band time after
a direction change from reverse to forward.
DS40001775B-page 311
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27.7.1
ASYNCHRONOUS DELAY CHAIN
DEAD-BAND DELAY
Asynchronous dead-band delay is determined by the
time it takes the input to propagate through a series of
delay elements. Each delay element is a nominal five
nanoseconds.
For rising event asynchronous dead-band delay, set
the RDBS bit of the COGxCON0 register and set the
COGxDBR register (Register 27-14) value to the
desired number of delay elements in the rising event
dead-band time.
For falling event asynchronous dead-band delay, set
the FDBS bit of the COGxCON0 register and set the
COGxDBF register (Register 27-15) value to the
desired number of delay elements in the falling event
dead-band time.
Setting the value to zero disables dead-band delay.
27.7.2
SYNCHRONOUS COUNTER
DEAD-BAND DELAY
Synchronous counter dead-band is timed by counting
COG_clock periods from zero, up to the value in the
Dead-Band Count register. Use Equation 27-1 to
calculate dead-band times.
For rising event synchronous dead-band delay, clear
the RDBS bit of the COGxCON0 register and set the
COGxDBR register value to the number of COG_clock
periods in the rising event dead-band time.
For falling event synchronous dead-band delay, clear
the FDBS bit of the COGxCON0 register and set the
COGxDBF register value to the number of COG_clock
periods in the falling event dead-band time.
When the value is zero, dead-band delay is disabled.
27.7.3
SYNCHRONOUS COUNTER
DEAD-BAND TIME UNCERTAINTY
When the rising and falling events that trigger the
dead-band counters come from asynchronous inputs,
it creates uncertainty in the synchronous counter
dead-band time. The maximum uncertainty is equal to
one COG_clock period. Refer to Example 27-1 for
more detail.
When event input sources are asynchronous with no
phase delay, use the Asynchronous Delay Chain
Dead-Band mode to avoid the dead-band time
uncertainty.
27.7.4
RISING EVENT DEAD-BAND
Rising event dead-band delays the turn-on of the
primary outputs from when complementary outputs are
turned off. The rising event dead-band time starts
when the rising_ event output goes true.
DS40001775B-page 312
See Section 27.7.1 “Asynchronous Delay Chain
Dead-Band Delay” and Section 27.7.2 “Synchronous
Counter Dead-Band Delay” for more information on
setting the rising edge dead-band time.
27.7.5
FALLING EVENT DEAD-BAND
Falling event dead-band delays the turn-on of
complementary outputs from when the primary outputs
are turned off. The falling event dead-band time starts
when the falling_event output goes true.
See Section 27.7.1 “Asynchronous Delay Chain
Dead-Band Delay” and Section 27.7.2 “Synchronous
Counter Dead-Band Delay” for more information on
setting the rising edge dead-band time.
27.7.6
DEAD-BAND OVERLAP
There are two cases of potential dead-band overlap:
• Rising-to-falling
• Falling-to-rising
27.7.6.1
Rising-to-Falling Overlap
In this case, the falling event occurs while the rising
event dead-band counter is still counting. When this
happens, the primary drives are suppressed and the
dead-band extends by the falling event dead-band
time. At the termination of the extended dead-band
time, the complementary drive goes true.
27.7.6.2
Falling-to-Rising Overlap
In this case, the rising event occurs while the falling
event dead-band counter is still counting. When this
happens, the complementary drive is suppressed and
the dead-band extends by the rising event dead-band
time. At the termination of the extended dead-band
time, the primary drive goes true.
27.8
Blanking Control
Input blanking is a function whereby the event inputs
can be masked or blanked for a short period of time.
This is to prevent electrical transients caused by the
turn-on/off of power components from generating a
false input event.
The COG contains two blanking counters: one
triggered by the rising event and the other triggered by
the falling_event. The counters are cross coupled with
the events they are blanking. The falling event
blanking counter is used to blank rising input events
and the rising event blanking counter is used to blank
falling input events. Once started, blanking extends for
the time specified by the corresponding blanking
counter.
Blanking is timed by counting COG_clock periods from
zero, up to the value in the Blanking Count register. Use
Equation 27-1 to calculate blanking times.
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27.8.1
FALLING EVENT BLANKING OF
RISING EVENT INPUTS
The falling event blanking counter inhibits rising event
inputs from triggering a rising event. The falling event
blanking time starts when the rising_event output drive
goes false.
The falling event blanking time is set by the value
contained in the COGxBLKF register (Register 27-17).
Blanking times are calculated using the formula shown
in Equation 27-1.
When the COGxBLKF value is zero, falling event
blanking is disabled and the blanking counter output is
true, thereby, allowing the event signal to pass straight
through to the event trigger circuit.
27.8.2
27.9.1
It is not possible to create more than one COG_clock of
uncertainty by successive stages. Consider that the
phase-delay stage comes after the blanking stage, the
dead-band stage comes after either the blanking or
phase-delay stages, and the blanking stage comes
after the dead-band stage. When the preceding stage
is enabled, the output of that stage is necessarily
synchronous with the COG_clock, which removes any
possibility of uncertainty in the succeeding stage.
EQUATION 27-1:
RISING EVENT BLANKING OF
FALLING EVENT INPUTS
When the COGxBLKR value is zero, rising event
blanking is disabled and the blanking counter output is
true, thereby, allowing the event signal to pass straight
through to the event trigger circuit.
27.8.3
BLANKING TIME UNCERTAINTY
When the rising and falling sources that trigger the
blanking counters are asynchronous to the
COG_clock, it creates uncertainty in the blanking time.
The maximum uncertainty is equal to one COG_clock
period. Refer to Equation 27-1 and Example 27-1 for
more detail.
27.9
Phase Delay
PHASE, DEAD-BAND
AND BLANKING TIME
CALCULATION
Count
T min = --------------------------------F
COG_clock
The rising event blanking counter inhibits falling event
inputs from triggering a falling event. The rising event
blanking time starts when the falling_event output
drive goes false.
The rising event blanking time is set by the value
contained in the COGxBLKR register (Register 27-16).
CUMULATIVE UNCERTAINTY
T
T
max
Count + 1
= --------------------------------FCOG_clock
uncertainty
= T
max
–T
min
Also:
T
uncertainty
1
= --------------------------------F
COG_clock
Where:
T
Rising Phase Delay
Count
COGxPHR
Falling Phase Delay
COGxPHF
Rising Dead-Band
COGxDBR
Falling Dead-Band
COGxDBF
Rising Event Blanking
COGxBLKR
Falling Event Blanking
COGxBLKF
It is possible to delay the assertion of either, or both,
the rising event and falling events. This is accomplished by placing a non-zero value in COGxPHR or
COGxPHF phase-delay count registers, respectively
(Register 27-18 and Register 27-19). Refer to
Figure 27-10 for COG operation with CCP1 and phase
delay. The delay from the input rising event signal
switching to the actual assertion of the events is calculated the same as the dead-band and blanking delays.
Refer to Equation 27-1.
When the phase-delay count value is zero, phase
delay is disabled and the phase-delay counter output
is true, thereby, allowing the event signal to pass
straight through to the complementary output driver
flop.
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DS40001775B-page 313
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EXAMPLE 27-1:
TIMER UNCERTAINTY
Given:
When auto-restart is enabled, the ASE bit will clear
automatically and resume operation on the first rising
event after the shutdown input clears. See
Figure 27-15 and Section 27.10.3.2 “Auto-Restart”.
Count = Ah = 10d
FCOG_Clock = 8MHz
Therefore:
T
uncertainty
1
= --------------------------------F
COG_clock
1
= --------------8MHz
= 125ns
Proof:
T
min
Count
= --------------------------------F
COG_clock
= 125ns  10d
= 1.25s
Count + 1
T
= --------------------------------max
F
COG_clock
= 125ns   10d + 1 
= 1.375s
Therefore:
T
uncertainty
= T
max
When auto-restart is disabled, the shutdown state will
persist until the first rising event after the ASE bit is
cleared by software.
–T
min
27.10.1.2
External Shutdown Source
External shutdown inputs provide the fastest way to
safely suspend COG operation in the event of a Fault
condition. When any of the selected shutdown inputs
go true, the output drive latches are reset and the
COG outputs immediately go to the selected override
levels without software delay.
Any combination of the input sources can be selected
to cause a shutdown condition. Shutdown occurs
when the selected source is low. Shutdown input
sources include:
• Any input pin selected with the COGxINPPS
control
• Comparator 1
• Comparator 2
• Comparator 3
• Comparator 4
• CLC2 output
• Timer2 output
• Timer4 output
Shutdown inputs are selected independently with bits
of the COGxASD1 register (Register 27-12).
Note:
= 1.375s – 1.25s
= 125ns
Shutdown inputs are level-sensitive, not
edge-sensitive. The shutdown state
cannot be cleared as long as the
shutdown input level persists, except by
disabling auto-shutdown,
27.10 Auto-Shutdown Control
Auto-shutdown is a method to immediately override
the COG output levels with specific overrides that
allow for safe shutdown of the circuit.
The shutdown state can be either cleared automatically or held until cleared by software. In either case,
the shutdown overrides remain in effect until the first
rising event after the shutdown is cleared.
27.10.1
SHUTDOWN
The shutdown state can be entered by either of the
following two mechanisms:
• Software generated
• External input
27.10.2
The levels driven to the output pins, while the
shutdown is active, are controlled by the ASDAC<1:0>
and ASDBC<1:0> bits of the COGxASD0 register
(Register 27-11). ASDAC<1:0> controls the COGxA
and COGxC override levels, and ASDBC<1:0>
controls the COGxB and COGxD override levels.
There are four override options for each output pair:
•
•
•
•
Forced low
Forced high
Tri-state
PWM inactive state (same state as that caused by
a falling event)
Note:
27.10.1.1
Software Generated Shutdown
Setting the ASE bit of the COGxASD0 register
(Register 27-11) will force the COG into the shutdown
state.
DS40001775B-page 314
PIN OVERRIDE LEVELS
The polarity control does not apply to the
forced low and high override levels but
does apply to the PWM inactive state.
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27.10.3
AUTO-SHUTDOWN RESTART
After an auto-shutdown event has occurred, there are
two ways to resume operation:
The COG will resume operation on the first rising
event after the ASE bit is cleared. Clearing the
shutdown state requires all selected shutdown inputs
to be false; otherwise, the ASE bit will remain set.
• Software controlled
• Auto-restart
27.10.3.2
The restart method is selected with the ARSEN bit of
the COGxASD0 register. Waveforms of a software
controlled automatic restart are shown in Figure 27-15.
When the ARSEN bit of the COGxASD0 register is
set, the COG will restart from the auto-shutdown state
automatically.
27.10.3.1
The ASE bit will clear automatically and the COG will
resume operation on the first rising event after all
selected shutdown inputs go false.
Software Controlled Restart
When the ARSEN bit of the COGxASD0 register is
cleared, software must clear the ASE bit to restart
COG operation after an auto-shutdown event.
 2014-2015 Microchip Technology Inc.
Auto-Restart
DS40001775B-page 315
 2014-2015 Microchip Technology Inc.
FIGURE 27-15: AUTO-SHUTDOWN WAVEFORM – CCP1 AS RISING AND FALLING EVENT INPUT SOURCE
1
2
3
4
5
CCP1
ARSEN
Next Rising Event
Shutdown Input
Next Rising Event
ASE
Cleared in Hardware
Cleared in Software
ASDAC
2b00
ASDBD
2b00
2b00
COGxB
Operating State
NORMAL OUTPUT
SHUTDOWN
NORMAL OUTPUT
SOFTWARE CONTROLLED RESTART
SHUTDOWN
NORMAL OUTPUT
AUTO-RESTART
DS40001775B-page 316
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COGxA
PIC16(L)F1764/5/8/9
27.11 Buffer Updates
3.
Changes to the Phase, Dead-Band and Blanking
Count registers need to occur simultaneously during
COG operation to avoid unintended operation that
may occur as a result of delays between each register
write. This is accomplished with the LD bit of the
COGxCON0 register and double-buffering of the
Phase, Blanking and Dead-Band Count registers.
4.
5.
Before the COG module is enabled, writing the Count
registers loads the count buffers without need of the
LD bit. However, when the COG is enabled, the count
buffer updates are suspended after writing the Count
registers until after the LD bit is set. When the LD bit is
set, the Phase, Dead-Band and Blanking register
values are transferred to the corresponding buffers
synchronous with COG operation. The LD bit is
cleared by hardware when the transfer is complete.
6.
7.
8.
9.
27.12 Input and Output Pin Selection
The COG has one selection for an input from a device
pin. That one input can be used as rising and falling
event source or a Fault source. The COGxINPPS register is used to select the pin. Refer to registers,
xxxPPS (Register 12-1) and RxyPPS (Register 12-2).
The Pin PPS Control registers are used to enable the
COG outputs. Any combination of outputs to pins is
possible including multiple pins for the same output.
See the RxyPPS control register and Section 12.2
“PPS Outputs” for more details.
10.
11.
12.
27.13 Operation During Sleep
The COG continues to operate in Sleep provided that
the COG_clock, rising event, and falling event sources
remain active.
The HFINTSOC remains active during Sleep when the
COG is enabled and the HFINTOSC is selected as the
COG_clock source.
13.
14.
27.14 Configuring the COG
The following steps illustrate how to properly configure
the COG to ensure a synchronous start with the rising
event input:
1.
2.
If a pin is to be used for the COG Fault or event
input, use the COGxINPPS register to configure
the desired pin.
Clear all ANSELx register bits associated with
pins that are used for COG functions.
 2014-2015 Microchip Technology Inc.
15.
16.
17.
Ensure that the TRISx control bits corresponding to the COG outputs to be used are set so that
all are configured as inputs. The COG module
will enable the output drivers as needed later.
Clear the EN bit, if not already cleared.
Set desired dead-band times with the
COGxDBR and COGxDBF registers, and select
the source with the RDBS and FDBS bits of the
COGxCON1 register.
Set desired blanking times with the COGxBLKR
and COGxBLKF registers.
Set desired phase delay with the COGxPHR
and COGxPHF registers.
Select the desired shutdown sources with the
COGxASD1 register.
Setup the following controls in the COGxASD0
Auto-Shutdown register:
• Select both output override controls to the
desired levels (this is necessary, even if not
using auto-shutdown because start-up will be
from a shutdown state).
• Set the ASE bit and clear the ARSEN bit.
Select the desired rising and falling event
sources with the COGxRIS0, COGxRIS1,
COGxFIS0 and COGxFIS1 registers.
Select the desired Rising and Falling Event
modes with the COGxRSIM0, COGxRSIMI1,
COGxFSIM0 and COGxFSIM1 registers.
Configure the following controls in the
COGxCON1 register:
• Set the polarity for each output
• Select the desired dead-band timing sources
Configure the following controls in the
COGxCON0 register:
• Set the desired operating mode
• Select the desired clock source
If one of the Steering modes is selected, then
configure the following controls in the
COGxSTR register:
• Set the steering bits of the outputs to be
used.
• Set the desired static levels.
Set the EN bit.
Set the pin PPS controls to direct the COG
outputs to the desired pins.
If auto-restart is to be used, set the ARSEN bit
and the ASE will be cleared automatically;
otherwise, clear the ASE bit to start the COG.
DS40001775B-page 317
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27.15 Register Definitions: COG Control
Long bit name prefixes for the COG peripherals are
shown in Table 27-3. Refer to Section 1.1 “Register
and Bit Naming Conventions” for more information.
TABLE 27-3:
BIT NAME PREFIXES
Peripheral
Bit Name Prefix
COG1
G1
COG2(1)
G2
Note 1:
PIC16(L)F1768/9 devices only.
REGISTER 27-1:
COGxCON0: COGx CONTROL REGISTER 0
R/W-0/0
R/W-0/0
U-0
EN
LD
—
R/W-0/0
R/W-0/0
R/W-0/0
CS<1:0>
R/W-0/0
R/W-0/0
MD<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
EN: COGx Enable bit
1 = Module is enabled
0 = Module is disabled
bit 6
LD: COGx Load Buffers bit
1 = Phase, blanking and dead-band buffers to be loaded with register values on next input events
0 = Register to buffer transfer is complete
bit 5
Unimplemented: Read as ‘0’
bit 4-3
CS<1:0>: COGx Clock Selection bits
11 = Reserved; do not use
10 = COG_clock is HFINTOSC (stays active during Sleep)
01 = COG_clock is FOSC
00 = COG_clock is FOSC/4
bit 2-0
MD<2:0>: COGx Mode Selection bits
11x = Reserved; do not use
101 = COG outputs operate in Push-Pull mode
100 = COG outputs operate in Half-Bridge mode
011 = COG outputs operate in Reverse Full-Bridge mode
010 = COG outputs operate in Forward Full-Bridge mode
001 = COG outputs operate in Synchronous Steered PWM mode
000 = COG outputs operate in Steered PWM mode
DS40001775B-page 318
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PIC16(L)F1764/5/8/9
REGISTER 27-2:
COGxCON1: COGx CONTROL REGISTER 1
R/W-0/0
R/W-0/0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
RDBS
FDBS
—
—
POLD
POLC
POLB
POLA
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
RDBS: COGx Rising Event Dead-Band Timing Source Select bit
1 = Delay chain and COGxDBR are used for dead-band timing generation
0 = COGx_clock and COGxDBR are used for dead-band timing generation
bit 6
FDBS: COGx Falling Event Dead-band Timing Source select bit
1 = Delay chain and COGxDBF are used for dead-band timing generation
0 = COGx_clock and COGxDBF are used for dead-band timing generation
bit 5-4
Unimplemented: Read as ‘0’
bit 3
POLD: COGxD Output Polarity Control bit
1 = Active level of COGxD output is low
0 = Active level of COGxD output is high
bit 2
POLC: COGxC Output Polarity Control bit
1 = Active level of COGxC output is low
0 = Active level of COGxC output is high
bit 1
POLB: COGxB Output Polarity Control bit
1 = Active level of COGxB output is low
0 = Active level of COGxB output is high
bit 0
POLA: COGxA Output Polarity Control bit
1 = Active level of COGxA output is low
0 = Active level of COGxA output is high
 2014-2015 Microchip Technology Inc.
DS40001775B-page 319
PIC16(L)F1764/5/8/9
REGISTER 27-3:
COGxRIS0: COGx RISING EVENT INPUT SELECTION REGISTER 0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
RIS7
RIS6
RIS5
RIS4
RIS3
RIS2
RIS1
RIS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
RIS7: COGx Rising Event Input Source 7 Enable bit
1 = PWM3 output is enabled as a rising event input
0 = PWM3 output has no effect on the rising event
bit 6
RIS6: COGx Rising Event Input Source 6 Enable bit
1 = CCP2 output is enabled as a rising event input
0 = CCP2 output has no effect on the rising event
bit 5
RIS5: COGx Rising Event Input Source 5 Enable bit
1 = CCP1 output is enabled as a rising event input
0 = CCP1 output has no effect on the rising event
bit 4
RIS4: COGx Rising Event Input Source 4 Enable bit
1 = Comparator 4 output is enabled as a rising event input
0 = Comparator 4 output has no effect on the rising event
bit 3
RIS3: COGx Rising Event Input Source 3 Enable bit
1 = Comparator 3 output is enabled as a rising event input
0 = Comparator 3 output has no effect on the rising event
bit 2
RIS2: COGx Rising Event Input Source 2 Enable bit
1 = Comparator 2 output is enabled as a rising event input
0 = Comparator 2 output has no effect on the rising event
bit 1
RIS1: COGx Rising Event Input Source 1 Enable bit
1 = Comparator 1 output is enabled as a rising event input
0 = Comparator 1 output has no effect on the rising event
bit 0
RIS0: COGx Rising Event Input Source 0 Enable bit
1 = Pin selected with COGxINPPS register is enabled as rising event input
0 = Pin selected with COGxINPPS register has no effect on the rising event
DS40001775B-page 320
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PIC16(L)F1764/5/8/9
REGISTER 27-4:
COGxRIS1: COGx RISING EVENT INPUT SELECTION REGISTER 1
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
RIS15(1)
RIS14
RIS13
RIS12
RIS11
RIS10
RIS9
RIS8
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
RIS15: COGx Rising Event Input Source 15 Enable bit(1)
1 = DSM2 MD2_out is enabled as a rising event input
0 = DSM2 MD2_out has no effect on the rising event
bit 6
RIS14: COGx Rising Event Input Source 14 Enable bit
1 = DSM1 MD1_out output is enabled as a rising event input
0 = DSM1 MD1_out has no effect on the rising event
bit 5
RIS13: COGx Rising Event Input Source 13 Enable bit
1 = CLC3 output is enabled as a rising event input
0 = CLC3 output has no effect on the rising event
bit 4
RIS12: COGx Rising Event Input Source 12 Enable bit
1 = CLC2 output is enabled as a rising event input
0 = CLC2 output has no effect on the rising event
bit 3
RIS11: COGx Rising Event Input Source 11 Enable bit
1 = CLC1 output is enabled as a rising event input
0 = CLC1 output has no effect on the rising event
bit 2
RIS10: COGx Rising Event Input Source 10 Enable bit
1 = PWM6 output is enabled as a rising event input
0 = PWM6 output has no effect on the rising event
bit 1
RIS9: COGx Rising Event Input Source 9 Enable bit
1 = PWM5 output is enabled as a rising event input
0 = PWM5 output has no effect on the rising event
bit 0
RIS8: COGx Rising Event Input Source 8 Enable bit
1 = PWM4 output is enabled as rising event input
0 = PWM4 output has no effect on the rising event
Note 1:
PIC16(L)F1768/9 only. Otherwise unimplemented, read as ‘0’.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 321
PIC16(L)F1764/5/8/9
REGISTER 27-5:
COGxRSIM0: COGx RISING EVENT SOURCE INPUT MODE
REGISTER 0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
RSIM7
RSIM6
RSIM5
RSIM4
RSIM3
RSIM2
RSIM1
RSIM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
RSIM7: COGx Rising Event Input Source 7 Mode bit
RIS7 = 1:
1 = PWM3 output low-to-high transition will cause a rising event after rising event phase delay
0 = PWM3 output high level will cause an immediate rising event
RIS7 = 0:
PWM3 output has no effect on rising event.
bit 6
RSIM6: COGx Rising Event Input Source 6 Mode bit
RIS6 = 1:
1 = CCP2 output low-to-high transition will cause a rising event after rising event phase delay
0 = CCP2 output high level will cause an immediate rising event
RIS6 = 0:
CCP2 output has no effect on rising event.
bit 5
RSIM5: COGx Rising Event Input Source 5 Mode bit
RIS5 = 1:
1 = CCP1 output low-to-high transition will cause a rising event after rising event phase delay
0 = CCP1 output high level will cause an immediate rising event
RIS5 = 0:
CCP1 output has no effect on rising event.
bit 4
RSIM4: COGx Rising Event Input Source 4 Mode bit
RIS4 = 1:
1 = Comparator 4 output low-to-high transition will cause a rising event after rising event phase delay
0 = Comparator 4 output high level will cause an immediate rising event
RIS4 = 0:
Comparator 4 has no effect on rising event.
bit 3
RSIM3: COGx Rising Event Input Source 3 Mode bit
RIS3 = 1:
1 = Comparator 3 output low-to-high transition will cause a rising event after rising event phase delay
0 = Comparator 3 output high level will cause an immediate rising event
RIS3 = 0:
Comparator 3 output has no effect on rising event.
bit 2
RSIM2: COGx Rising Event Input Source 2 Mode bit
RIS2 = 1:
1 = Comparator 2 output low-to-high transition will cause a rising event after rising event phase delay
0 = Comparator 2 output high level will cause an immediate rising event
RIS2 = 0:
Comparator 2 has no effect on rising event.
DS40001775B-page 322
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PIC16(L)F1764/5/8/9
REGISTER 27-5:
COGxRSIM0: COGx RISING EVENT SOURCE INPUT MODE
REGISTER 0 (CONTINUED)
bit 1
RSIM1: COGx Rising Event Input Source 1 Mode bit
RIS1 = 1:
1 = Comparator 1 low-to-high transition will cause a rising event after rising event phase delay
0 = Comparator 1 high level will cause an immediate rising event
RIS1 = 0:
Comparator 1 has no effect on rising event.
bit 0
RSIM0: COGx Rising Event Input Source 0 Mode bit
RIS0 = 1:
1 = Pin selected with COGxINPPS register low-to-high transition will cause a rising event after rising
event phase delay
0 = Pin selected with COGxINPPS register high level will cause an immediate rising event
RIS0 = 0:
Pin selected with COGxINPPS register has no effect on rising event.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 323
PIC16(L)F1764/5/8/9
REGISTER 27-6:
R/W-0/0
(1)
RSIM15
COGxRSIM1: COGx RISING EVENT SOURCE INPUT MODE
REGISTER 1
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
RSIM14
RSIM13
RSIM12
RSIM11
RSIM10
RSIM9
RSIM8
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
RSIM15: COGx Rising Event Input Source 15 Mode bit(1)
RIS15 = 1:
1 = DSM2 MD2_out output low-to-high transition will cause a rising event after rising event phase delay
0 = DSM2 MD2_out output high level will cause an immediate rising event
RIS15 = 0:
DSM2 MD2_out output has no effect on rising event.
bit 6
RSIM14: COGx Rising Event Input Source 14 Mode bit
RIS14 = 1:
1 = DSM1 MD1_out output low-to-high transition will cause a rising event after rising event phase delay
0 = DSM1 MD1_out output high level will cause an immediate rising event
RIS14 = 0:
DSM1 MD1_out output has no effect on rising event.
bit 7-6
Unimplemented: Read as ‘0’
bit 5
RSIM13: COGx Rising Event Input Source 13 Mode bit
RIS13 = 1:
1 = CLC3 output low-to-high transition will cause a rising event after rising event phase delay
0 = CLC3 output high level will cause an immediate rising event
RIS13 = 0:
CLC3 output has no effect on rising event.
bit 4
RSIM12: COGx Rising Event Input Source 12 Mode bit
RIS12 = 1:
1 = CLC2 output low-to-high transition will cause a rising event after rising event phase delay
0 = CLC2 output high level will cause an immediate rising event
RIS12 = 0:
CLC2 output has no effect on rising event.
bit 3
RSIM11: COGx Rising Event Input Source 11 Mode bit
RIS11 = 1:
1 = CLC1 output low-to-high transition will cause a rising event after rising event phase delay
0 = CLC1 output high level will cause an immediate rising event
RIS11 = 0:
CLC1 output has no effect on rising event.
bit 2
RSIM10: COGx Rising Event Input Source 10 Mode bit
RIS10 = 1:
1 = PWM6 output low-to-high transition will cause a rising event after rising event phase delay
0 = PWM6 output high level will cause an immediate rising event
RIS10 = 0:
PWM6 output has no effect on rising event.
Note 1:
PIC16(L)F1768/9 only. Otherwise unimplemented, read as ‘0’.
DS40001775B-page 324
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
REGISTER 27-6:
COGxRSIM1: COGx RISING EVENT SOURCE INPUT MODE
REGISTER 1 (CONTINUED)
bit 1
RSIM9: COGx Rising Event Input Source 9 Mode bit
RIS9 = 1:
1 = PWM5 output low-to-high transition will cause a rising event after rising event phase delay
0 = PWM5 output high level will cause an immediate rising event
RIS9 = 0:
PWM5 output has no effect on rising event.
bit 0
RSIM8: COGx Rising Event Input Source 8 Mode bit
RIS8 = 1:
1 = PWM4 output low-to-high transition will cause a rising event after rising event phase delay
0 = PWM4 output high level will cause an immediate rising event
RIS8 = 0:
PWM4 output has no effect on rising event.
Note 1:
PIC16(L)F1768/9 only. Otherwise unimplemented, read as ‘0’.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 325
PIC16(L)F1764/5/8/9
REGISTER 27-7:
COGxFIS0: COGx FALLING EVENT INPUT SELECTION REGISTER 0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
FIS7
FIS6
FIS5
FIS4
FIS3
FIS2
FIS1
FIS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
FIS7: COGx Falling Event Input Source 7 Enable bit
1 = PWM3 output is enabled as a falling event input
0 = PWM3 output has no effect on the falling event
bit 6
FIS6: COGx Falling Event Input Source 6 Enable bit
1 = CCP2 output is enabled as a falling event input
0 = CCP2 output has no effect on the falling event
bit 5
FIS5: COGx Falling Event Input Source 5 Enable bit
1 = CCP1 output is enabled as a falling event input
0 = CCP1 output has no effect on the falling event
bit 4
FIS4: COGx Falling Event Input Source 4 Enable bit
1 = Comparator 4 output is enabled as a falling event input
0 = Comparator 4 output has no effect on the falling event
bit 3
FIS3: COGx Falling Event Input Source 3 Enable bit
1 = Comparator 3 output is enabled as a falling event input
0 = Comparator 3 output has no effect on the falling event
bit 2
FIS2: COGx Falling Event Input Source 2 Enable bit
1 = Comparator 2 output is enabled as a falling event input
0 = Comparator 2 output has no effect on the falling event
bit 1
FIS1: COGx Falling Event Input Source 1 Enable bit
1 = Comparator 1 output is enabled as a falling event input
0 = Comparator 1 output has no effect on the falling event
bit 0
FIS0: COGx Falling Event Input Source 0 Enable bit
1 = Pin selected with COGxINPPS register is enabled as falling event input
0 = Pin selected with COGxINPPS register has no effect on the falling event
DS40001775B-page 326
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PIC16(L)F1764/5/8/9
REGISTER 27-8:
COGxFIS1: COGx FALLING EVENT INPUT SELECTION REGISTER 1
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
FIS15(1)
FIS14
FIS13
FIS12
FIS11
FIS10
FIS9
FIS8
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
FIS15: COGx Falling Event Input Source 15 Mode bit(1)
1 = DSM2 MD2_out is enabled as a falling event input
0 = DSM2 MD2_out has no effect on the falling event
bit 6
FIS14: COGx Falling Event Input Source 14 Mode bit
1 = DSM1 MD1_out is enabled as a falling event input
0 = DSM1 MD1_out has no effect on the falling event
bit 5
FIS13: COGx Falling Event Input Source 13 Enable bit
1 = CLC3 output is enabled as a falling event input
0 = CLC3 output has no effect on the falling event
bit 4
FIS12: COGx Falling Event Input Source 12 Enable bit
1 = CLC2 output is enabled as a falling event input
0 = CLC2 output has no effect on the falling event
bit 3
FIS11: COGx Falling Event Input Source 11 Enable bit
1 = CLC1 output is enabled as a falling event input
0 = CLC1 output has no effect on the falling event
bit 2
FIS10: COGx Falling Event Input Source 10 Enable bit
1 = PWM6 output is enabled as a falling event input
0 = PWM6 output has no effect on the falling event
bit 1
FIS9: COGx Falling Event Input Source 9 Enable bit
1 = PWM5 output is enabled as a falling event input
0 = PWM5 output has no effect on the falling event
bit 0
FIS8: COGx Falling Event Input Source 8 Enable bit
1 = PWM4 output is enabled as falling event input
0 = PWM4 output has no effect on the falling event
Note 1:
PIC16(L)F1768/9 only. Otherwise unimplemented, read as ‘0’.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 327
PIC16(L)F1764/5/8/9
REGISTER 27-9:
COGxFSIM0: COGx FALLING EVENT SOURCE INPUT MODE
REGISTER 0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
FSIM7
FSIM6
FSIM5
FSIM4
FSIM3
FSIM2
FSIM1
FSIM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
FSIM7: COGx Falling Event Input Source 7 Mode bit
FIS7 = 1:
1 = PWM3 output high-to-low transition will cause a falling event after falling event phase delay
0 = PWM3output low level will cause an immediate falling event
FIS7 = 0:
PWM3 output has no effect on falling event.
bit 6
FSIM6: COGx Falling Event Input Source 6 Mode bit
FIS6 = 1:
1 = CCP2 output high-to-low transition will cause a falling event after falling event phase delay
0 = CCP2 output low level will cause an immediate falling event
FIS6 = 0:
CCP2 output has no effect on falling event.
bit 5
FSIM5: COGx Falling Event Input Source 5 Mode bit
FIS5 = 1:
1 = CCP1 output high-to-low transition will cause a falling event after falling event phase delay
0 = CCP1 output low level will cause an immediate falling event
FIS5 = 0:
CCP1 output has no effect on falling event.
bit 4
FSIM4: COGx Falling Event Input Source 4 Mode bit
FIS4 = 1:
1 = Comparator 4 high-to-low transition will cause a falling event after falling event phase delay
0 = Comparator 4 low level will cause an immediate falling event
FIS4 = 0:
Comparator 4 has no effect on falling event.
bit 3
FSIM3: COGx Falling Event Input Source 3 Mode bit
FIS3 = 1:
1 = Comparator 3 high-to-low transition will cause a falling event after falling event phase delay
0 = Comparator 3 low level will cause an immediate falling event
FIS3 = 0:
Comparator 3 has no effect on falling event.
bit 2
FSIM2: COGx Falling Event Input Source 2 Mode bit
FIS2 = 1:
1 = Comparator 2 high-to-low transition will cause a falling event after falling event phase delay
0 = Comparator 2 low level will cause an immediate falling event
FIS2 = 0:
Comparator 2 has no effect on falling event.
DS40001775B-page 328
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PIC16(L)F1764/5/8/9
REGISTER 27-9:
COGxFSIM0: COGx FALLING EVENT SOURCE INPUT MODE
REGISTER 0 (CONTINUED)
bit 1
FSIM1: COGx Falling Event Input Source 1 Mode bit
FIS1 = 1:
1 = Comparator 1 high-to-low transition will cause a falling event after falling event phase delay
0 = Comparator 1 low level will cause an immediate falling event
FIS1 = 0:
Comparator 1 has no effect on falling event.
bit 0
FSIM0: COGx Falling Event Input Source 0 Mode bit
FIS0 = 1:
1 = Pin selected with COGxINPPS control high-to-low transition will cause a falling event after falling
event phase delay
0 = Pin selected with COGxINPPS control low level will cause an immediate falling event
FIS0 = 0:
Pin selected with COGxINPPS control has no effect on falling event.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 329
PIC16(L)F1764/5/8/9
REGISTER 27-10: COGxFSIM1: COGx FALLING EVENT SOURCE INPUT MODE
REGISTER 1
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
FSIM15(1)
FSIM14
FSIM13
FSIM12
FSIM11
FSIM10
FSIM9
FSIM8
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
FSIM15: COGx Falling Event Input Source 15 Mode bit(1)
FIS15 = 1:
1 = DSM2 MD2_out output high-to-low transition will cause a falling event after falling event phase delay
0 = DSM2 MD2_out low level will cause an immediate falling event
FIS15 = 0:
DSM2 MD2_out output has no effect on falling event.
bit 6
FSIM14: COGx Falling Event Input Source 14 Mode bit
FIS14 = 1:
1 = DSM1 MD1_out output high-to-low transition will cause a falling event after falling event phase delay
0 = DSM1 MD1_out output low level will cause an immediate falling event
FIS14 = 0:
DSM1 MD1_out output has no effect on falling event.
bit 5
FSIM13: COGx Falling Event Input Source 13 Mode bit
FIS13 = 1:
1 = CLC3 output high-to-low transition will cause a falling event after falling event phase delay
0 = CLC3 output low level will cause an immediate falling event
FIS13 = 0:
CLC3 output has no effect on falling event.
bit 4
FSIM12: COGx Falling Event Input Source 12 Mode bit
FIS12 = 1:
1 = CLC2 output high-to-low transition will cause a falling event after falling event phase delay
0 = CLC2 output low level will cause an immediate falling event
FIS12 = 0:
CLC2 output has no effect on falling event.
bit 3
FSIM11: COGx Falling Event Input Source 11 Mode bit
FIS11 = 1:
1 = CLC1 output high-to-low transition will cause a falling event after falling event phase delay
0 = CLC1 output low level will cause an immediate falling event
FIS11 = 0:
CLC1 output has no effect on falling event.
bit 2
FSIM10: COGx Falling Event Input Source 10 Mode bit
FIS10 = 1:
1 = PWM6 output high-to-low transition will cause a falling event after falling event phase delay
0 = PWM6 output low level will cause an immediate falling event
FIS10 = 0:
Comparator 2 has no effect on falling event.
Note 1:
PIC16(L)F1768/9 only. Otherwise unimplemented, read as ‘0’.
DS40001775B-page 330
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PIC16(L)F1764/5/8/9
REGISTER 27-10: COGxFSIM1: COGx FALLING EVENT SOURCE INPUT MODE
REGISTER 1 (CONTINUED)
bit 1
FSIM9: COGx Falling Event Input Source 9 Mode bit
FIS9 = 1:
1 = PWM5 output high-to-low transition will cause a falling event after falling event phase delay
0 = PWM5 output low level will cause an immediate falling event
FIS9 = 0:
PWM5 output has no effect on falling event.
bit 0
FSIM8: COGx Falling Event Input Source 8 Mode bit
FIS8 = 1:
1 = PWM4 output high-to-low transition will cause a falling event after falling event phase delay
0 = PWM4 output low level will cause an immediate falling event
FIS8 = 0:
PWM4 output has no effect on falling event.
Note 1:
PIC16(L)F1768/9 only. Otherwise unimplemented, read as ‘0’.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 331
PIC16(L)F1764/5/8/9
REGISTER 27-11: COGxASD0: COGx AUTO-SHUTDOWN CONTROL REGISTER 0
R/W-0/0
R/W-0/0
ASE
ARSEN
R/W-0/0
R/W-0/0
ASDBD<1:0>
R/W-0/0
R/W-0/0
ASDAC<1:0>
bit 7
U-0
U-0
—
—
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
ASE: Auto-Shutdown Event Status bit
1 = COG is in the shutdown state
0 = COG is either not in the shutdown state or will exit the shutdown state on the next rising event
bit 6
ARSEN: Auto-Restart Enable bit
1 = Auto-restart is enabled
0 = Auto-restart is disabled
bit 5-4
ASDBD<1:0>: COGxB and COGxD Auto-shutdown Override Level Select bits
11 = A logic ‘1’ is placed on COGxB and COGxD when shutdown is active
10 = A logic ‘0’ is placed on COGxB and COGxD when shutdown is active
01 = COGxB and COGxD are tri-stated when shutdown is active
00 = The inactive state of the pin, including polarity, is placed on COGxB and COGxD when shutdown
is active
bit 3-2
ASDAC<1:0>: COGxA and COGxC Auto-shutdown Override Level Select bits
11 = A logic ‘1’ is placed on COGxA and COGxC when shutdown is active
10 = A logic ‘0’ is placed on COGxA and COGxC when shutdown is active
01 = COGxA and COGxC are tri-stated when shutdown is active
00 = The inactive state of the pin, including polarity, is placed on COGxA and COGxC when shutdown
is active
bit 1-0
Unimplemented: Read as ‘0’
DS40001775B-page 332
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REGISTER 27-12: COGxASD1: COGx AUTO-SHUTDOWN CONTROL REGISTER 1
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
AS7E
AS6E
AS5E
AS4E
AS3E
AS2E
AS1E
AS0E
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
AS7E: COGx Auto-shutdown Source Enable bit 7
1 = COGx is shutdown when Timer4_output is high
0 = Timer4_output has no effect on shutdown
bit 6
AS6E: COGx Auto-shutdown Source Enable bit 6
1 = COGx is shutdown when Timer2_output is high
0 = Timer2_output has no effect on shutdown
bit 5
AS5E: COGx Auto-shutdown Source Enable bit 5
1 = COGx is shutdown when CLC LC2_out is low
0 = CLC2 output has no effect on shutdown
bit 4
AS4E: COGx Auto-shutdown Source Enable bit 4
1 = COGx is shutdown when Comparator sync_C4OUT is low
0 = Comparator 4 output has no effect on shutdown
bit 3
AS3E: COGx Auto-shutdown Source Enable bit 3
1 = COGx is shutdown when Comparator sync_C3OUT is low
0 = Comparator 3 output has no effect on shutdown
bit 2
AS2E: COGx Auto-shutdown Source Enable bit 2
1 = COGx is shutdown when Comparator sync_C2OUT is low
0 = Comparator 2 output has no effect on shutdown
bit 1
AS1E: COGx Auto-shutdown Source Enable bit 1
1 = COGx is shutdown when comparator sync_C1OUT is low
0 = Comparator 1 output has no effect on shutdown
bit 0
AS0E: COGx Auto-shutdown Source Enable bit 0
1 = COGx is shutdown when pin selected with COGxINPPS register is low
0 = Pin selected with COGxINPPS register has no effect on shutdown
 2014-2015 Microchip Technology Inc.
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PIC16(L)F1764/5/8/9
REGISTER 27-13: COGxSTR: COGx STEERING CONTROL REGISTER 1(1)
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
SDATD
SDATC
SDATB
SDATA
STRD
STRC
STRB
STRA
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
SDATD: COGxD Static Output Data bit
1 = COGxD static data is high
0 = COGxD static data is low
bit 6
SDATC: COGxC Static Output Data bit
1 = COGxC static data is high
0 = COGxC static data is low
bit 5
SDATB: COGxB Static Output Data bit
1 = COGxB static data is high
0 = COGxB static data is low
bit 4
SDATA: COGxA Static Output Data bit
1 = COGxA static data is high
0 = COGxA static data is low
bit 3
STRD: COGxD Steering Control bit
1 = COGxD output has the COGxD waveform with polarity control from the POLD bit
0 = COGxD output is the static data level determined by the SDATD bit
bit 2
STRC: COGxC Steering Control bit
1 = COGxC output has the COGxC waveform with polarity control from the POLC bit
0 = COGxC output is the static data level determined by the SDATC bit
bit 1
STRB: COGxB Steering Control bit
1 = COGxB output has the COGxB waveform with polarity control from the POLB bit
0 = COGxB output is the static data level determined by the SDATB bit
bit 0
STRA: COGxA Steering Control bit
1 = COGxA output has the COGxA waveform with polarity control from the POLA bit
0 = COGxA output is the static data level determined by the SDATA bit
Note 1:
Steering is active only when the MD<2:0> bits of the COGxCON0 register = 00x (see Register 27-1).
DS40001775B-page 334
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REGISTER 27-14: COGxDBR: COGx RISING EVENT DEAD-BAND COUNT REGISTER
U-0
U-0
—
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
DBR<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
DBR<5:0>: Rising Event Dead-Band Count Value bits
RDBS = 0:
= Number of COGx clock periods to delay primary output after rising event
RDBS = 1:
= Number of delay chain element periods to delay primary output after rising event
REGISTER 27-15: COGxDBF: COGx FALLING EVENT DEAD-BAND COUNT REGISTER
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
DBF<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
DBF<5:0>: Falling Event Dead-Band Count Value bits
FDBS = 0:
= Number of COGx clock periods to delay complementary output after falling event input
FDBS = 1:
= Number of delay chain element periods to delay complementary output after falling event input
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REGISTER 27-16: COGxBLKR: COGx RISING EVENT BLANKING COUNT REGISTER
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
BLKR<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
BLKR<5:0>: Rising Event Blanking Count Value bits
= Number of COGx clock periods to inhibit falling event inputs
REGISTER 27-17: COGxBLKF: COGx FALLING EVENT BLANKING COUNT REGISTER
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
BLKF<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
BLKF<5:0>: Falling Event Blanking Count Value bits
= Number of COGx clock periods to inhibit rising event inputs
REGISTER 27-18: COGxPHR: COGx RISING EVENT PHASE DELAY COUNT REGISTER
U-0
U-0
—
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PHR<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
PHR<5:0>: Rising Event Phase Delay Count Value bits
= Number of COGx clock periods to delay rising event
DS40001775B-page 336
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REGISTER 27-19: COGxPHF: COGx FALLING EVENT PHASE DELAY COUNT REGISTER
U-0
U-0
—
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PHF<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
PHF<5:0>: Falling Event Phase Delay Count Value bits
= Number of COGx clock periods to delay falling event
TABLE 27-4:
Name
ANSELA
SUMMARY OF REGISTERS ASSOCIATED WITH COGx
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
—
—
—
ANSA4
—
ANSELB(1)
ANSB<7:4>
ANSC<7:6>(1)
ANSELC
Bit 2
Bit 0
ANSA<2:0>
—
—
Bit 1
—
—
—
142
—
148
—
—
332
AS1E
AS0E
333
ANSC<3:0>
ASDBD<1:0>
153
COGxASD0
ASE
ARSEN
COGxASD1
AS7E
AS6E
COGxBLKR
—
—
BLKR<5:0>
COGxBLKF
—
—
BLKF<5:0>
COGxCON0
EN
LD
—
COGxCON1
RDBS
FDBS
—
COGxDBR
—
—
DBR<5:0>
COGxDBF
—
—
DBF<5:0>
COGxFIS0
FIS7
FIS6
FIS5
FIS4
FIS3
FIS2
FIS1
FIS0
326
COGxFIS1
FIS15(1)
FIS14
FIS13
FIS12
FIS11
FIS10
FIS9
FIS8
327
AS5E
ASDAC<1:0>
Register
on Page
AS4E
AS3E
AS2E
CS<1:0>
—
336
336
MD<2:0>
POLD
POLC
POLB
318
POLA
319
335
335
COGxFSIM0
FSIM7
FSIM6
FSIM5
FSIM4
FSIM3
FSIM2
FSIM1
FSIM0
328
COGxFSIM1
FSIM15(1)
FSIM14
FSIM13
FSIM12
FSIM11
FSIM10
FSIM9
FSIM8
330
COGxPHR
—
—
PHR<5:0>
336
COGxPHF
—
—
PHF<5:0>
337
COGxPPS
—
—
—
COGxRIS0
RIS7
RIS6
RIS5
RIS4
RIS3
RIS2
RIS1
RIS0
320
COGxRIS1
RIS15(1)
RIS14
RIS13
RIS12
RIS11
RIS10
RIS9
RIS8
321
COGxRSIM0
RSIM7
RSIM6
RSIM5
RSIM4
RSIM3
RSIM2
RSIM1
RSIM0
322
COGxRSIM1
RSIM15(1)
RSIM14
RSIM13
RSIM12
RSIM11
RSIM10
RSIM9
RSIM8
324
SDATD
SDATC
SDATB
SDATA
STRD
STRC
STRB
STRA
334
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
104
RxyPPS
—
—
—
COGxSTR
COG1PPS<4:0>
RxyPPS<4:0>
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by COG.
Note 1:
PIC16(L)F1768/9 only.
 2014-2015 Microchip Technology Inc.
159, 161
159
DS40001775B-page 337
PIC16(L)F1764/5/8/9
NOTES:
DS40001775B-page 338
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
28.0
Refer to Figure 28-1 for a simplified diagram showing
signal flow through the CLCx.
CONFIGURABLE LOGIC CELL
(CLC)
Possible configurations include:
The Configurable Logic Cell (CLC) provides programmable logic that operates outside the speed limitations
of software execution. The logic cell takes up to
32 input signals, and through the use of configurable
gates, reduces the 32 inputs to four logic lines that drive
one of eight selectable single output logic functions.
• Combinatorial Logic:
- AND
- NAND
- AND-OR
- AND-OR-INVERT
- OR-XOR
- OR-XNOR
• Latches:
- S-R
- Clocked D with Set and Reset
- Transparent D with Set and Reset
- Clocked J-K with Reset
Input sources are a combination of the following:
•
•
•
•
I/O pins
Internal clocks
Peripherals
Register bits
The output can be directed internally to peripherals and
to an output pin.
FIGURE 28-1:
CLCx SIMPLIFIED BLOCK DIAGRAM
Rev. 10-000 025D
6/4/201 4
D
Q
LCxOUT
MLCxOUT
Q1
.
.
.
See Table 28-1.
LCx_in[35]
LCx_in[36]
LCx_in[37]
LCx_out
Input Data Selection Gates(1)
LCx_in[0]
LCx_in[1]
LCx_in[2]
EN
g1
g2
g3
Logic
Function
to Peripherals
CLCxPPS
q
PPS
CLCx
(2)
g4
POL
MODE<2:0>
TRIS
Interrupt
det
INTP
INTN
set bit
CLCxIF
Interrupt
det
Note 1:
2:
See Figure 28-2: Input Data Selection and Gating.
See Figure 28-3: Programmable Logic Functions.
 2014-2015 Microchip Technology Inc.
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28.1
CLCx Setup
Programming the CLCx module is performed by configuring the four stages in the logic signal flow. The four
stages are:
•
•
•
•
Data selection
Data gating
Logic function selection
Output polarity
Each stage is set up at run time by writing to the corresponding CLCx Special Function Registers. This has
the added advantage of permitting logic reconfiguration
on-the-fly during program execution.
28.1.1
DATA SELECTION
There are 32 signals available as inputs to the configurable logic. Four 32-input multiplexers are used to
select the inputs to pass on to the next stage.
Data selection is through four multiplexers, as indicated
on the left side of Figure 28-2. Data inputs in the figure
are identified by a generic numbered input name.
Table 28-1 correlates the generic input name to the
actual signal for each CLC module. The column labeled,
dy, indicates the MUX selection code for the selected
data input. DxS is an abbreviation for the MUX select
input codes: D1S<5:0> through D4S<5:0>.
Data inputs are selected with the CLCxSEL0 through
CLCxSEL3
registers
(Register 28-3
through
Register 28-6).
Note:
Data selections are undefined at power-up.
TABLE 28-1:
Data Input
dy
DxS<5:0>
LCx_in[38]
100110
LCx_in[37]
LCx_in[36]
LCx_in[35]
LCx_in[34]
100101
100100
100011
100010
MD1_out(1) or MD2_out(2) or
Reserved(3)
FOSC
HFINTOSC
LFINTOSC
FRC (ADC RC clock)
LCx_in[33]
LCx_in[32]
LCx_in[31]
LCx_in[30]
LCx_in[29]
100001
100000
011111
011110
011101
IOCIF Set
Timer6_postscaled
Timer4_postscaled
Timer2_postscaled
Timer5 Overflow
LCx_in[28]
LCx_in[27]
LCx_in[26]
LCx_in[25]
LCx_in[24]
LCx_in[23]
LCx_in[22]
LCx_in[21]
LCx_in[20]
LCx_in[19]
LCx_in[18]
LCx_in[17]
LCx_in[16]
LCx_in[15]
LCx_in[14]
LCx_in[13]
LCx_in[12]
LCx_in[11]
LCx_in[10]
LCx_in[9]
LCx_in[8]
LCx_in[7]
LCx_in[6]
LCx_in[5]
LCx_in[4]
LCx_in[3]
LCx_in[2]
LCx_in[1]
LCx_in[0]
Note 1:
2:
3:
DS40001775B-page 340
CLCx DATA INPUT SELECTION
CLCx
Timer3 Overflow
Timer1 Overflow
Timer0 Overflow
EUSART RX
EUSART TX
ZCD1_output
MSSP1 SDO/SDA
MSSP1 SCL/SCK
PWM6_out
PWM5_out
PWM4_out
PWM3_out
CCP2_out
CCP1_out
COG2B
COG2A
COG1B
COG1A
sync_C4OUT
sync_C3OUT
sync_C2OUT
sync_C1OUT
LC3_out from the CLC3
LC2_out from the CLC2
LC1_out from the CLC1
CLCIN3 Pin Input Selected in
CLCIN3PPS Register
000010 CLCIN2 Pin Input Selected in
CLCIN2PPS Register
000001 CLCIN1 Pin Input Selected in
CLCIN1PPS Register
000000 CLCIN0 Pin Input Selected in
CLCIN0PPS Register
CLCxSEL0 only.
PIC16(L)F1768/9 CLCxSEL1 only.
CLCxSEL2, CLCxSEL3 and
PIC16(L)F1764/5 CLCxSEL1 only.
011100
011011
011010
011001
011000
010111
010110
010101
010100
010011
010010
010001
010000
001111
001110
001101
001100
001011
001010
001001
001000
000111
000110
000101
000100
000011
 2014-2015 Microchip Technology Inc.
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28.1.2
DATA GATING
Outputs from the input multiplexers are directed to the
desired logic function input through the data gating
stage. Each data gate can direct any combination of the
four selected inputs.
Note:
Data gating is undefined at power-up.
The gate stage is more than just signal direction. The
gate can be configured to direct each input signal as
inverted or non-inverted data. Directed signals are
ANDed together in each gate. The output of each gate
can be inverted before going on to the logic function
stage.
The gating is, in essence, a 1-to-4 input
AND/NAND/OR/NOR gate. When every input is
inverted and the output is inverted, the gate is an OR of
all enabled data inputs. When the inputs and output are
not inverted, the gate is an AND or all enabled inputs.
Table 28-2 summarizes the basic logic that can be
obtained in Gate 1 by using the gate logic select bits.
The table shows the logic of four input variables, but
each gate can be configured to use less than four. If no
inputs are selected, the output will be zero or one,
depending on the gate output polarity bit.
TABLE 28-2:
DATA GATING LOGIC
CLCxGLS0
G1POL
Gate Logic
0x55
1
AND
0x55
0
NAND
0xAA
1
NOR
0xAA
0
OR
0x00
0
Logic ‘0’
0x00
1
Logic ‘1’
Data gating is indicated in the right side of Figure 28-2.
Only one gate is shown in detail. The remaining three
gates are configured identically with the exception that
the data enables correspond to the enables for that
gate.
28.1.3
LOGIC FUNCTION
There are eight available logic functions including:
•
•
•
•
•
•
•
•
AND-OR
OR-XOR
AND
S-R Latch
D Flip-Flop with Set and Reset
D Flip-Flop with Reset
J-K Flip-Flop with Reset
Transparent Latch with Set and Reset
Logic functions are shown in Figure 28-3. Each logic
function has four inputs and one output. The four inputs
are the four data gate outputs of the previous stage.
The output is fed to the inversion stage and from there
to other peripherals, an output pin, and back to the
CLCx itself.
28.1.4
OUTPUT POLARITY
The last stage in the Configurable Logic Cell is the
output polarity. Setting the POL bit of the CLCxCON
register inverts the output signal from the logic stage.
Changing the polarity while the interrupts are enabled
will cause an interrupt for the resulting output transition.
It is possible (but not recommended) to select both the
true and negated values of an input. When this is done,
the gate output is zero, regardless of the other inputs,
but may emit logic glitches (transient-induced pulses).
If the output of the channel must be zero or one, the
recommended method is to set all gate bits to zero and
use the gate polarity bit to set the desired level.
Data gating is configured with the Logic Gate Select
registers as follows:
•
•
•
•
Gate 1: CLCxGLS0 (Register 28-7)
Gate 2: CLCxGLS1 (Register 28-8)
Gate 3: CLCxGLS2 (Register 28-9)
Gate 4: CLCxGLS3 (Register 28-10)
Register number suffixes are different than the gate
numbers because other variations of this module have
multiple gate selections in the same register.
 2014-2015 Microchip Technology Inc.
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28.1.5
CLCx SETUP STEPS
The following steps should be followed when setting up
the CLCx:
• Disable CLCx by clearing the EN bit.
• Select desired inputs using CLCxSEL0 through
CLCxSEL3 registers (see Table 28-1).
• Clear any associated ANSELx bits.
• Set all TRISx bits associated with inputs.
• Clear all TRISx bits associated with outputs.
• Enable the chosen inputs through the four gates
using CLCxGLS0, CLCxGLS1, CLCxGLS2, and
CLCxGLS3 registers.
• Select the gate output polarities with the POLy
bits of the CLCxPOL register.
• Select the desired logic function with the
MODE<2:0> bits of the CLCxCON register.
• Select the desired polarity of the logic output with
the POL bit of the CLCxPOL register. (This step
may be combined with the previous gate output
polarity step).
• If driving a device pin, set the desired Pin PPS
Control register and also clear the TRISx bit
corresponding to that output.
• If interrupts are desired, configure the following
bits:
- Set the INTP bit in the CLCxCON register for
a rising event.
- Set the INTN bit in the CLCxCON register for
a falling event.
- Set the CLCxIE bit of the associated PIE
registers.
- Set the GIE and PEIE bits of the INTCON
register.
• Enable the CLCx by setting the EN bit of the
CLCxCON register.
28.2
CLCx Interrupts
An interrupt will be generated upon a change in the
output value of the CLCx when the appropriate interrupt
enables are set. A rising edge detector and a falling
edge detector are present in each CLC for this purpose.
To fully enable the interrupt, set the following bits:
• EN bit of the CLCxCON register
• CLCxIE bit of the associated PIE registers
• INTP bit of the CLCxCON register (for a rising
edge detection)
• INTN bit of the CLCxCON register (for a falling
edge detection)
• PEIE and GIE bits of the INTCON register
The CLCxIF bit of the associated PIR registers must be
cleared in software as part of the interrupt service. If
another edge is detected while this flag is being
cleared, the flag will still be set at the end of the
sequence.
28.3
Output Mirror Copies
Mirror copies of all CLCxCON output bits are contained
in the CLCxDATA register. Reading this register reads
the outputs of all CLCs simultaneously. This prevents
any reading skew introduced by testing or reading the
CLCxOUT bits in the individual CLCxCON registers.
28.4
Effects of a Reset
The CLCxCON register is cleared to zero as the result
of a Reset. All other selection and gating values remain
unchanged.
28.5
Operation During Sleep
The CLCx module operates independently from the
system clock and will continue to run during Sleep,
provided that the input sources selected remain active.
The HFINTOSC remains active during Sleep when the
CLCx module is enabled and the HFINTOSC is
selected as an input source, regardless of the system
clock source selected.
In other words, if the HFINTOSC is simultaneously
selected as the system clock and as a CLCx input
source when the CLCx is enabled, the CPU will go Idle
during Sleep, but the CLCx will continue to operate and
the HFINTOSC will remain active.
This will have a direct effect on the Sleep mode current.
The CLCxIF bit of the associated PIR registers will be
set when either edge detector is triggered and its associated enable bit is set. The INTP enables rising edge
interrupts and the INTN bit enables falling edge
interrupts. Both are located in the CLCxCON register.
DS40001775B-page 342
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FIGURE 28-2:
LCx_in[0]
INPUT DATA SELECTION AND GATING
Data Selection
Data GATE 1
See Table 28-1.
d1T
D1G1T
d1N
D1G1N
LCx_in[37]
D2G1T
D1S<5:0>
D2G1N
g1
LCx_in[0]
D3G1T
d2T
See Table 28-1.
G1POL
D3G1N
d2N
D4G1T
LCx_in[37]
D2S<5:0>
D4G1N
LCx_in[0]
Data GATE 2
g2
d3T
See Table 28-1.
(Same as Data GATE 1)
d3N
Data GATE 3
LCx_in[37]
g3
D3S<5:0>
(Same as Data GATE 1)
Data GATE 4
LCx_in[0]
g4
d4T
See Table 28-1.
(Same as Data GATE 1)
d4N
LCx_in[37]
D4S<5:0>
Note:
All controls are undefined at power-up.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 343
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FIGURE 28-3:
PROGRAMMABLE LOGIC FUNCTIONS
AND – OR
OR – XOR
g1
g1
g2
g2
q
g3
q
g3
g4
g4
MODE<2:0>= 000
MODE<2:0>= 001
4-Input AND
S-R Latch
g1
g1
g2
g2
q
g3
S
g3
g4
R
g4
MODE<2:0>= 010
q
Q
MODE<2:0>= 011
1-Input D Flip-Flop with S and R
2-Input D Flip-Flop with R
g4
g2
D
S
g4
Q
q
D
g2
g1
g1
Q
q
R
R
g3
g3
MODE<2:0>= 100
MODE<2:0>= 101
J-K Flip-Flop with R
1-Input Transparent Latch with S and R
g4
g2
J
Q
g1
g4
K
R
q
g2
D
g1
LE
g3
S
Q
q
R
g3
MODE<2:0>= 110
DS40001775B-page 344
MODE<2:0>= 111
 2014-2015 Microchip Technology Inc.
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28.6
Register Definitions: CLC Control
Long bit name prefixes for the CLC peripherals are
shown in Table 28-3. Refer to Section 1.1 “Register
and Bit Naming Conventions” for more information.
TABLE 28-3:
BIT NAME PREFIXES
Peripheral
Bit Name Prefix
CLC1
LC1
CLC2
LC2
REGISTER 28-1:
CLCxCON: CLCx CONTROL REGISTER
R/W-0/0
U-0
R-0/0
R/W-0/0
R/W-0/0
EN
—
OUT
INTP
INTN
R/W-0/0
R/W-0/0
R/W-0/0
MODE<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
EN: CLCx Enable bit
1 = CLCx is enabled and mixing input signals
0 = CLCx is disabled and has logic zero output
bit 6
Unimplemented: Read as ‘0’
bit 5
OUT: CLCx Data Output bit
Read-only: logic cell output data, after POL; sampled from lcx_out wire.
bit 4
INTP: CLCx Positive Edge Going Interrupt Enable bit
1 = CLCxIF will be set when a rising edge occurs on lcx_out
0 = CLCxIF will not be set
bit 3
INTN: CLCx Negative Edge Going Interrupt Enable bit
1 = CLCxIF will be set when a falling edge occurs on lcx_out
0 = CLCxIF will not be set
bit 2-0
MODE<2:0>: CLCx Functional Mode bits
111 = Cell is 1-Input Transparent Latch with S and R
110 = Cell is J-K Flip-Flop with R
101 = Cell is 2-Input D Flip-Flop with R
100 = Cell is 1-Input D Flip-Flop with S and R
011 = Cell is S-R Latch
010 = Cell is 4-Input AND
001 = Cell is OR-XOR
000 = Cell is AND-OR
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REGISTER 28-2:
CLCxPOL: CLCx SIGNAL POLARITY CONTROL REGISTER
R/W-0/0
U-0
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
POL
—
—
—
G4POL
G3POL
G2POL
G1POL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
POL: LCOUT Polarity Control bit
1 = The output of the logic cell is inverted
0 = The output of the logic cell is not inverted
bit 6-4
Unimplemented: Read as ‘0’
bit 3
G4POL: Gate 4 Output Polarity Control bit
1 = The output of Gate 4 is inverted when applied to the logic cell
0 = The output of Gate 4 is not inverted
bit 2
G3POL: Gate 3 Output Polarity Control bit
1 = The output of Gate 3 is inverted when applied to the logic cell
0 = The output of Gate 3 is not inverted
bit 1
G2POL: Gate 2 Output Polarity Control bit
1 = The output of Gate 2 is inverted when applied to the logic cell
0 = The output of Gate 2 is not inverted
bit 0
G1POL: Gate 1 Output Polarity Control bit
1 = The output of Gate 1 is inverted when applied to the logic cell
0 = The output of Gate 1 is not inverted
DS40001775B-page 346
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REGISTER 28-3:
CLCxSEL0: GENERIC CLCx DATA 1 SELECT REGISTER
U-0
U-0
—
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
D1S<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
D1S<5:0>: CLCx Data1 Input Selection bits
See Table 28-1.
REGISTER 28-4:
CLCxSEL1: GENERIC CLCx DATA 2 SELECT REGISTER
U-0
U-0
—
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
D2S<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
D2S<5:0>: CLCx Data 2 Input Selection bits
See Table 28-1.
REGISTER 28-5:
CLCxSEL2: GENERIC CLCx DATA 3 SELECT REGISTER
U-0
U-0
—
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
D3S<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
D3S<5:0>: CLCx Data 3 Input Selection bits
See Table 28-1.
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REGISTER 28-6:
CLCxSEL3: GENERIC CLCx DATA 4 SELECT REGISTER
U-0
U-0
—
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
D4S<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
D4S<5:0>: CLCx Data 4 Input Selection bits
See Table 28-1.
REGISTER 28-7:
CLCxGLS0: CLCx GATE 1 LOGIC SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
G1D4T
G1D4N
G1D3T
G1D3N
G1D2T
G1D2N
G1D1T
G1D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
G1D4T: Gate 1 Data 4 True (non-inverted) bit
1 = d4T is gated into g1
0 = d4T is not gated into g1
bit 6
G1D4N: Gate 1 Data 4 Negated (inverted) bit
1 = d4N is gated into g1
0 = d4N is not gated into g1
bit 5
G1D3T: Gate 1 Data 3 True (non-inverted) bit
1 = d3T is gated into g1
0 = d3T is not gated into g1
bit 4
G1D3N: Gate 1 Data 3 Negated (inverted) bit
1 = d3N is gated into g1
0 = d3N is not gated into g1
bit 3
G1D2T: Gate 1 Data 2 True (non-inverted) bit
1 = d2T is gated into g1
0 = d2T is not gated into g1
bit 2
G1D2N: Gate 1 Data 2 Negated (inverted) bit
1 = d2N is gated into g1
0 = d2N is not gated into g1
bit 1
G1D1T: Gate 1 Data 1 True (non-inverted) bit
1 = d1T is gated into g1
0 = d1T is not gated into g1
bit 0
G1D1N: Gate 1 Data 1 Negated (inverted) bit
1 = d1N is gated into g1
0 = d1N is not gated into g1
DS40001775B-page 348
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REGISTER 28-8:
CLCxGLS1: CLCx GATE 2 LOGIC SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
G2D4T
G2D4N
G2D3T
G2D3N
G2D2T
G2D2N
G2D1T
G2D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
G2D4T: Gate 2 Data 4 True (non-inverted) bit
1 = d4T is gated into g2
0 = d4T is not gated into g2
bit 6
G2D4N: Gate 2 Data 4 Negated (inverted) bit
1 = d4N is gated into g2
0 = d4N is not gated into g2
bit 5
G2D3T: Gate 2 Data 3 True (non-inverted) bit
1 = d3T is gated into g2
0 = d3T is not gated into g2
bit 4
G2D3N: Gate 2 Data 3 Negated (inverted) bit
1 = d3N is gated into g2
0 = d3N is not gated into g2
bit 3
G2D2T: Gate 2 Data 2 True (non-inverted) bit
1 = d2T is gated into g2
0 = d2T is not gated into g2
bit 2
G2D2N: Gate 2 Data 2 Negated (inverted) bit
1 = d2N is gated into g2
0 = d2N is not gated into g2
bit 1
G2D1T: Gate 2 Data 1 True (non-inverted) bit
1 = d1T is gated into g2
0 = d1T is not gated into g2
bit 0
G2D1N: Gate 2 Data 1 Negated (inverted) bit
1 = d1N is gated into g2
0 = d1N is not gated into g2
 2014-2015 Microchip Technology Inc.
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PIC16(L)F1764/5/8/9
REGISTER 28-9:
CLCxGLS2: CLCx GATE 3 LOGIC SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
G3D4T
G3D4N
G3D3T
G3D3N
G3D2T
G3D2N
G3D1T
G3D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
G3D4T: Gate 3 Data 4 True (non-inverted) bit
1 = d4T is gated into g3
0 = d4T is not gated into g3
bit 6
G3D4N: Gate 3 Data 4 Negated (inverted) bit
1 = d4N is gated into g3
0 = d4N is not gated into g3
bit 5
G3D3T: Gate 3 Data 3 True (non-inverted) bit
1 = d3T is gated into g3
0 = d3T is not gated into g3
bit 4
G3D3N: Gate 3 Data 3 Negated (inverted) bit
1 = d3N is gated into g3
0 = d3N is not gated into g3
bit 3
G3D2T: Gate 3 Data 2 True (non-inverted) bit
1 = d2T is gated into g3
0 = d2T is not gated into g3
bit 2
G3D2N: Gate 3 Data 2 Negated (inverted) bit
1 = d2N is gated into g3
0 = d2N is not gated into g3
bit 1
G3D1T: Gate 3 Data 1 True (non-inverted) bit
1 = d1T is gated into g3
0 = d1T is not gated into g3
bit 0
G3D1N: Gate 3 Data 1 Negated (inverted) bit
1 = d1N is gated into g3
0 = d1N is not gated into g3
DS40001775B-page 350
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REGISTER 28-10: CLCxGLS3: CLCx GATE 4 LOGIC SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
G4D4T
G4D4N
G4D3T
G4D3N
G4D2T
G4D2N
G4D1T
G4D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
G4D4T: Gate 4 Data 4 True (non-inverted) bit
1 = d4T is gated into g4
0 = d4T is not gated into g4
bit 6
G4D4N: Gate 4 Data 4 Negated (inverted) bit
1 = d4N is gated into g4
0 = d4N is not gated into g4
bit 5
G4D3T: Gate 4 Data 3 True (non-inverted) bit
1 = d3T is gated into g4
0 = d3T is not gated into g4
bit 4
G4D3N: Gate 4 Data 3 Negated (inverted) bit
1 = d3N is gated into g4
0 = d3N is not gated into g4
bit 3
G4D2T: Gate 4 Data 2 True (non-inverted) bit
1 = d2T is gated into g4
0 = d2T is not gated into g4
bit 2
G4D2N: Gate 4 Data 2 Negated (inverted) bit
1 = d2N is gated into g4
0 = d2N is not gated into g4
bit 1
G4D1T: Gate 4 Data 1 True (non-inverted) bit
1 = d1T is gated into g4
0 = d1T is not gated into g4
bit 0
G4D1N: Gate 4 Data 1 Negated (inverted) bit
1 = d1N is gated into g4
0 = d1N is not gated into g4
 2014-2015 Microchip Technology Inc.
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PIC16(L)F1764/5/8/9
REGISTER 28-11: CLCxDATA: CLCx DATA OUTPUT
U-0
U-0
U-0
U-0
U-0
R-0
R-0
R-0
—
—
—
—
—
MLC3OUT
MLC2OUT
MLC1OUT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-3
Unimplemented: Read as ‘0’
bit 2
MLC3OUT: Mirror copy of LC3OUT bit
bit 1
MLC2OUT: Mirror copy of LC2OUT bit
bit 0
MLC1OUT: Mirror copy of LC1OUT bit
TABLE 28-4:
Name
ANSELA
SUMMARY OF REGISTERS ASSOCIATED WITH CLCx
Bit7
Bit6
Bit5
Bit4
BIt3
—
—
—
ANSA4
—
ANSELB(1)
ANSELC
ANSB<7:4>
ANSC<7:6>(1)
Bit2
—
Bit0
Register
on Page
—
148
ANSA<2:0>
—
—
Bit1
—
—
142
ANSC<3:0>
153
CLCxCON
EN
—
OUT
INTP
INTN
CLCDATA
—
—
—
—
—
MLC3OUT
MODE<2:0>
MLC2OUT
MLC1OUT
352
345
CLCxGLS0
G1D4T
G1D4N
G1D3T
G1D3N
G1D2T
G1D2N
G1D1T
G1D1N
348
CLCxGLS1
G2D4T
G2D4N
G2D3T
G2D3N
G2D2T
G2D2N
G2D1T
G2D1N
349
CLCxGLS2
G3D4T
G3D4N
G3D3T
G3D3N
G3D2T
G3D2N
G3D1T
G3D1N
350
CLCxGLS3
G4D4T
G4D4N
G4D3T
G4D3N
G4D2T
G4D2N
G4D1T
G4D1N
351
CLCxPOL
POL
—
—
—
G4POL
G3POL
G2POL
G1POL
346
CLCxSEL0
—
—
D1S<5:0>
347
CLCxSEL1
—
—
D2S<5:0>
347
CLCxSEL2
—
—
D3S<5:0>
347
CLCxSEL3
—
—
D4S<5:0>
CLCxPPS
—
—
—
348
CLCxPPS<4:0>
159, 161
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
104
PIE3
PWM6IE(1)
PWM5IE
COG1IE
ZCDIE
COG2IE(1)
CLC3IE
CLC2IE
CLC1IE
107
PIR3
PWM6IF(1)
PWM5IF
COG1IF
ZCDIF
COG2IF(1)
CLC3IF
CLC2IF
CLC1IF
RxyPPS
—
—
—
TRISA
—
—
INTCON
(1)
TRISB<7:4>
TRISB
TRISC<7:6>(1)
TRISC
TRISA<5:4>
RxyPPS<4:0>
—(3)
—
TRISA<2:0>
—
—
TRISC<5:0>
141
—
147
152
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used for CLCx module.
Note 1:
PIC16(L)F1768/9 only.
2:
110
159
Unimplemented, read as ‘1’.
DS40001775B-page 352
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29.0
OPERATIONAL AMPLIFIER
(OPA) MODULES
The Operational Amplifier (OPA) is a standard threeterminal device requiring external feedback to operate.
The OPA module has the following features:
•
•
•
•
•
External connections to I/O ports
Low leakage inputs
Factory calibrated input offset voltage
Unity gain control
Programmable positive and negative source
selections
• Override controls:
- Forced tri-state output
- Forced unity gain
FIGURE 29-1:
OPAx MODULE BLOCK DIAGRAM
OPAxIN0+
EN
OPAxIN1+
Internal Analog Sources,
See Register 29-4.
0
OPAx_out
OPAXOUT
OPA
1
PCH<1:0>
OPAxIN0OPAxIN1Internal Analog Sources,
See Register 29-3.
UG
NCH<1:0>
ORM1
Internal Override Sources,
See Register 29-2.
ORS<1:0>
ORM0
ORPOL
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29.1
OPA Module Performance
Common AC and DC performance specifications for
the OPA module:
•
•
•
•
•
Common-Mode Voltage Range
Leakage Current
Input Offset Voltage
Open-Loop Gain
Gain Bandwidth Product
Common-mode voltage range is the specified
voltage range for the OPA+ and OPA- inputs, for which
the OPA module will perform to within its specifications.
The OPA module is designed to operate with input
voltages between VSS and VDD. Behavior for Commonmode voltages greater than VDD, or below VSS, are not
guaranteed.
Leakage current is a measure of the small source or
sink currents on the OPA+ and OPA- inputs. To
minimize the effect of leakage currents, the effective
impedances connected to the OPA+ and OPA- inputs
should be kept as small as possible and equal.
Input offset voltage is a measure of the voltage
difference between the OPA+ and OPA- inputs in a
closed loop circuit with the OPA in its linear region. The
offset voltage will appear as a DC offset in the output
equal to the input offset voltage, multiplied by the gain of
the circuit. The input offset voltage is also affected by the
Common-mode voltage. The OPA is factory calibrated to
minimize the input offset voltage of the module.
Open-loop gain is the ratio of the output voltage to the
differential input voltage, (OPA+) – (OPA-). The gain is
greatest at DC and falls off with frequency.
Gain Bandwidth Product or GBWP is the frequency
at which the open-loop gain falls off to 0 dB.
29.2
OPA Module Control
The OPA module is enabled by setting the OPAxEN bit
of the OPAxCON register (Register 29-1). When
enabled, the OPA forces the output driver of OPAxOUT
pin into tri-state to prevent contention between the
driver and the OPA output.
Note:
29.2.1
When the OPA module is enabled, the
OPAxOUT pin is driven by the op amp
output, not by the PORT digital driver.
Refer to Table 36-17: Operational Amplifier
(OPA) for the op amp output drive
capability.
29.2.2
PROGRAMMABLE SOURCE
SELECTIONS
The inverting and non-inverting sources are selected
with the OPAxNCHS (Register 29-3) and OPAxPCHS
(Register 29-4) registers, respectively. Sources include:
•
•
•
•
Internal DACs
Device pins
Internal slope compensation ramp generator
Other op amps in the device
29.3
29.3.1
Override Control
OVERRIDE MODE
The op amp operation can be overridden in two ways:
• Forced tri-state output
• Force unity gain
The Override mode is selected with the ORM<1:0> bits
of the OPxCON register (Register 29-1). The override
is in effect when the mode is selected and the override
source is true.
29.3.2
OVERRIDE SOURCES
The override source is selected with the OPAxORS
register (Register 29-2). Sources are from internal
peripherals including:
•
•
•
•
•
•
CCP outputs
PWM outputs
Comparator outputs
Zero-Cross Detect (ZCD) output
Configurable Logic Cell outputs
COG outputs
29.3.3
OVERRIDE SOURCE POLARITY
The override source polarity can be inverted so that the
override will occur on either the high or low level of the
selected source. Override polarity is controlled by the
ORPOL bit of the OPAxCON register (Register 29-1).
29.4
Effects of Reset
A device Reset forces all registers to their Reset state.
This disables the OPA module.
29.5
Effects of Sleep
The operational amplifier continues to operate when
the device is put in Sleep mode.
UNITY GAIN MODE
The OPAxUG bit of the OPAxCON register
(Register 29-1) selects the Unity Gain mode. When
unity gain is selected, the OPA output is connected to
the inverting input and the OPAxIN pin is relinquished,
releasing the pin for general purpose input and output.
DS40001775B-page 354
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
29.6
Register Definitions: Op Amp Control
Long bit name prefixes for the op amp peripherals are
shown in Table 29-1. Refer to Section 1.1 “Register
and Bit Naming Conventions” for more information.
TABLE 29-1:
BIT NAME PREFIXES
Peripheral
Bit Name Prefix
OPA1
OPA1
OPA2(1)
OPA2
Note 1:
PIC16(L)F1768/9 devices only.
REGISTER 29-1:
OPAxCON: OPERATIONAL AMPLIFIER x (OPAx) CONTROL REGISTER
R/W-0/0
U-0
U-0
R/W-0/0
U-0
R/W-0/0
EN
—
—
UG
—
ORPOL
R/W-0/0
R/W-0/0
ORM<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
EN: Op Amp Enable bit
1 = Op amp is enabled
0 = Op amp is disabled and consumes no active power
bit 6-5
Unimplemented: Read as ‘0’
bit 4
UG: Op Amp Unity Gain Select bit
1 = OPA output is connected to inverting input; OPAxIN- pin is available for general purpose I/O
0 = Inverting input is connected to the OPAxIN- pin
bit 3
Unimplemented: Read as ‘0’
bit 2
ORPOL: Op Amp Override Source Polarity bit
1 = Override source polarity is inverted; override occurs when source is high
0 = Override source polarity is not inverted; override occurs when source is low
bit 1-0
ORM<1:0>: Op Amp Override Mode Selection bits
11 = Reserved; do not use
10 = Op amp is forced to unity gain when override source is true
01 = Op amp output is tri-stated when override source is true
00 = Output override function is disabled
 2014-2015 Microchip Technology Inc.
DS40001775B-page 355
PIC16(L)F1764/5/8/9
REGISTER 29-2:
OPAxORS: OP AMP x OVERRIDE SOURCE SELECTION REGISTER
U-0
U-0
U-0
—
—
—
R/W-0/0
R/W-0/x
R/W-0/x
R/W-0/0
R/W-0/x
ORS<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
ORS<4:0>: Op Amp Output Override Source Selection bits
11111 = Reserved; do not use
•
•
•
10110 = Reserved; do not use
10101 = Override source is COG2D(1)
10100 = Override source is COG2C(1)
10011 = Override source is COG2B(1)
10010 = Override source is COG2A(1)
10001 = Override source is COG1C
10000 = Override source is COG1C
01111 = Override source is COG1B
01110 = Override source is COG1A
01101 = Override source is LC3_out
01100 = Override source is LC2_out
01011 = Override source is LC1_out
01010 = Override source is ZCD1_output
01001 = Override source is sync_C4OUT(1)
01000= Override source is sync_C3OUT(1)
00111 = Override source is sync_C2OUT
00110 = Override source is sync_C1OUT
00101 = Override source is PWM6_out(1)
00100 = Override source is PWM5_out
00011 = Override source is PWM4_out(1)
00010 = Override source is PWM3_out
00001 = Override source is CCP2_out(1)
00000 = Override source is CCP1_out
Note 1:
PIC16(L)F1768/9 only
DS40001775B-page 356
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
REGISTER 29-3:
OPAxNCHS: OP AMP x NEGATIVE CHANNEL SOURCE SELECT REGISTER
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
NCH<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
NCH<3:0>: Op Amp Inverting Input Channel Selection bits
1111 = Reserved; do not use
•
•
•
1010 = Reserved; do not use
1001 = Programmable Ramp Generator PRG2_out(1)
1000 = Programmable Ramp Generator PRG1_out
0111 = Reserved. Do not use.
0110 = FVR_Buffer2
0101 = DAC4_out(1)
0100 = DAC3_out
0011 = DAC2_out(1)
0010 = DAC1_out
0001 = OPAxIN1- pin(1)
0000 = OPAxIN0- pin
Note 1:
PIC16(L)F1768/9 only
 2014-2015 Microchip Technology Inc.
DS40001775B-page 357
PIC16(L)F1764/5/8/9
REGISTER 29-4:
OPAxPCHS: OP AMP x POSITIVE CHANNEL SOURCE SELECT REGISTER
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PCH<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
PCH<3:0>: Op Amp Non-Inverting Input Channel Selection bits
1111 = Reserved; do not use
•
•
•
1010 = Reserved; do not use
1001 = Programmable Ramp Generator PRG2_out(1)
1000 = Programmable Ramp Generator PRG1_out
0111 = Reserved. Do not use.
0110 = FVR_Buffer2
0101 = DAC4_out(1)
0100 = DAC3_out
0011 = DAC2_out(1)
0010 = DAC1_out
0001 = OPAxIN1+ pin(1)
0000 = OPAxIN0+ pin
Note 1:
PIC16(L)F1768/9 only
TABLE 29-2:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH OP AMPS
Bit 7
ANSELB(2)
Bit 6
ANSB<7:6>
(2)
(2)
ANSC<7:6>
Bit 5
Bit 4
ANSB<5:4>
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
—
—
—
—
148
—
—
ANSC<3:2>
ANSC<1:0>
153
DACxCON0
EN
FM
OE1
—
PSS<1:0>
NSS<1:0>
195
DACxREF
---
---
---
ANSELC
REF<4:0>
DACxREFL(2)
DACxREFH(2)
FVRCON
201
REF<15:8>
FVREN
FVRRDY
TSEN
TSRNG
OPAxCON
EN
—
—
UG
OPAxNCHS
—
—
—
—
OPAxPCHS
—
—
—
—
OPAxORS
—
—
—
TRISB(2)
TRISB<7:6>
TRISB<5:4>
TRISC(2)
TRISC<7:6>(2)
TRISC<5:4>
Legend:
Note 1:
2:
196
REF<7:0>
201
CDAFVR<1:0>
—
ORPOL
ADFVR<1:0>
175
ORM<1:0>
355
NCH<3:0>
357
PCH<3:0>
358
ORS<4:0>
—
—
356
—
TRISC<3:2>
—
TRISC<1:0>
147
152
— = unimplemented location, read as ‘0’. Shaded cells are not used by op amps.
Unimplemented, read as ‘1’.
PIC16(L)F1768/9 only
DS40001775B-page 358
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
30.0
PROGRAMMABLE RAMP
GENERATOR (PRG) MODULE
The Programmable Ramp Generator (PRG) module is
designed to provide rising and falling linear ramps.
Typical applications include slope compensation for
fixed frequency, continuous current and Current mode
switched power supplies. Slope compensation is a
necessary feature of these power supplies because it
prevents frequency instabilities at duty cycles greater
than 50%.
The PRG has the following features:
•
•
•
•
Linear positive and negative voltage ramp outputs
Programmable current source/sink
Internal and external reference voltage selection
Internal and external timing source selection
A simplified block diagram of the PRG is shown in
Figure 30-1.
30.1
Fundamental Operation
The PRG can be operated in three voltage ramp
generator modes:
30.1.1
SLOPE COMPENSATION
Slope compensation works by quickly discharging an
internal capacitor at the beginning of each PWM period.
One side of the internal capacitor is connected to the
voltage input source and the other side is connected to
the internal current sink. The internal current sink
charges this capacitor at a programmable rate. As the
capacitor charges, the capacitor voltage is subtracted
from the voltage source, producing a linear voltage
decay at the required rate (see Figure 30-2). The ramp
terminates and the capacitor is discharged when the
set_falling timing input goes true. The next ramp starts
when the set_rising timing input goes true.
Enabling the optional one-shot by setting the OS bit of
the PRGxCON0 register ensures that the capacitor is
fully discharged by overriding the set_rising timing input
and holding the shorting switch closed for at least the
one-shot period, typically 50 ns. Edge-sensitive timing
inputs that occur during the one-shot period will be
ignored. Level-sensitive timing inputs that occur during,
and extend beyond, the one-shot period will be
suspended until the end of the one-shot time.
30.1.2
RAMP GENERATION
• Falling Voltage (slope compensation)
• Rising Voltage
• Alternating Rising and Falling Voltage
Ramp generation is similar to slope compensation
except that the slope is either both rising and falling or
just rising.
In the Rising or Falling mode, an internal capacitor is
discharged when the set_falling timing input is true and
charged by an internally generated constant current
when the set_rising timing input is true. The resulting
linear ramp starts at the selected voltage input level
and resets back to that level when the ramp is terminated by the set_falling timing input. The set_falling
input dominates when both timing inputs are true.
30.1.2.1
To control the operation with a single-ended source,
select the same source for both the set_rising and
set_falling inputs and invert the polarity of one of them
with the corresponding polarity control bit.
In the Alternating mode, the capacitor is not discharged
but alternates between being charged in one direction
then the other.
Input selections are identical for all modes. The input
voltage is supplied by any of the following:
• The PRGxIN0 or PRGxIN1 pins
• The buffered output of the internal Fixed Voltage
Reference (FVR),
• Any of the internal DACs.
The timing sources are selected from the following:
• The synchronized output of any comparator
• Any PWM output
• Any I/O pin
The ramp output is available as an input to any of the
comparators or op amps.
 2014-2015 Microchip Technology Inc.
Alternating Rising/Falling Ramps
The alternating rising/falling ramp generation function
works by employing the built-in current source and sink,
and relying on the synchronous control of the internal
analog switches and timing sources to ramp the module’s
output voltage up, and then subsequently, down.
Once initialized, the output voltage is ramped up linearly
by the current source at a programmable rate until the
set_falling timing source goes true, at which point the
current source is disengaged. At the same time, the
current sink is engaged to linearly ramp down the output
voltage, also at a programmable rate, until the set_rising
timing input goes true thereby reversing the ramp slope.
The process then repeats to create a saw tooth like
waveform, as shown in Figure 30-3 and Figure 30-4.
The set_rising and set_falling timing inputs can be
either edge or level-sensitive, which is selected with the
respective REDG and FEDG bits of the PRGxCON0
register. Edge-sensitive operation is recommended for
periodic signals, such as clocks, and level-sensitive
operation is recommended for analog limit triggers,
such as comparator outputs.
When the one-shot is enabled (OS bit is set), then both
the falling and rising ramps will persist for a minimum of
the one-shot period. Edge-sensitive timing inputs that
occur during the one-shot period will be ignored.
Level-sensitive timing inputs that occur during, and
extend beyond, the one-shot period will be suspended
until the end of the one-shot time.
DS40001775B-page 359
PIC16(L)F1764/5/8/9
30.1.2.2
Rising Ramp
30.4
Level and Edge Timing Sensitivity
The Rising Ramp mode is identical to the Slope Compensation mode, except that the ramps have a rising
slope instead of a falling slope. One side of the internal
capacitor is connected to the voltage input source and
the other side is connected to the internal current
source. The internal current source charges this capacitor at a programmable rate. As the capacitor charges,
the capacitor voltage is added to the voltage source,
producing a linear voltage rise at the required rate (see
Figure 30-5). The ramp terminates and the capacitor is
discharged when the set_falling timing input goes true.
The next ramp starts when the set_rising timing input
goes true.
The set_rising and set_falling timing inputs can be
independently configured as either level or
edge-sensitive.
Enabling the optional one-shot by setting the OS bit of
the PRGxCON0 register ensures that the capacitor is
fully discharged by overriding the set_rising timing input
and holding the shorting switch closed for at least the
one-shot period, typically 50 ns. Edge-sensitive timing
inputs that occur during the one-shot period will be
ignored. Level-sensitive timing inputs that occur during,
and extend beyond, the one-shot period will be
suspended until the end of the one-shot time.
Edge-sensitive operation is useful for periodic timing
inputs, such as those generated by PWMs and clocks.
The duty cycle of a level-sensitive periodic signal may
interfere with the other timing input. Consider an Alternating Ramp mode with a level-sensitive 50% PWM as
the set_rising timing source and a level-sensitive
comparator as the set_falling timing source. If the comparator output reverses the ramp while the PWM signal
is still high, then the ramp will improperly reverse again
when the comparator signal goes low. That same
scenario with the set_rising timing input set for edge
sensitivity would properly change the ramp output to
rising only on the rising edge of the PWM signal.
30.2
Enable, Ready, Go
The EN bit of the PRGxCON0 register enables the
analog circuitry including the current sources. This permits preparing the PRG module for use and allowing it
to become stable before putting it into operation. When
the EN bit is set, then the timing inputs are enabled so
that initial ramp action can be determined before the
GO bit is set. The capacitor shorting switch is closed
when the EN bit is set and remains closed while the GO
bit is zero.
The RDY bit of the PRGxCON1 register indicates that
the analog circuits and current sources are stable.
The GO bit of the PRGxCON0 register enables the
switch control circuits, thereby putting the PRG into
operation. The GO transition, from cleared to set, triggers the one-shot, thereby extending the capacitor
shorting switch closure for the one-shot period.
To ensure predictable operation, set the EN bit first,
then wait for the RDY bit to go high before setting the
GO bit.
30.3
Independent Set_rising and
Set_falling Timing Inputs
The timing inputs determine when the ramp starts and
stops. In the Alternating Rising/Falling mode, the ramp
rises when the set_rising input goes true and falls when
the set_falling input goes true. In the Slope Compensation and Rising Ramp modes, the capacitor is discharged
when the set_falling timing input goes true and the ramp
starts when the set_rising timing input goes true. The
set_falling input dominates the set_rising input.
DS40001775B-page 360
Level-sensitive operation is useful when it is necessary
to detect a timing input true state after an overriding
condition ceases. For example, level sensitivity is useful for capacitor generated timing inputs that may be
suppressed by the overriding action of the one-shot.
With level sensitivity, a capacitor output that changes
during the one-shot period will be detected at the end
of the one-shot time. With edge sensitivity, the change
would be ignored.
set_rising and set_falling timing input edge sensitivity is
selected with the respective REDG and FEDG bits of
the PRGxCON1 register.
30.5
One-Shot Minimum Timing
The one-shot timer ensures a minimum capacitor discharge time in the Slope Compensation and Rising
Ramp modes, and a minimum rising or falling ramp
duration in the Alternating Ramp mode. Setting the OS
bit of the PRGxCON0 register enables the one-shot
timer.
30.6
DAC Voltage Sources
When using any of the DACs as the voltage source,
expect a voltage offset equal to the current setting
times the DAC equivalent resistance. This will be a
constant offset in the Slope Compensation and Ramp
modes, and a positive/negative step offset in the
Alternating mode. To avoid this limitation, feed the DAC
output to the PRG input through one of the op amps set
for unity gain.
30.7
Operation During Sleep
The PRG module is unaffected by Sleep.
30.8
Effects of a Reset
The PRG module resets to a disabled condition.
 2014-2015 Microchip Technology Inc.
 2014-2015 Microchip Technology Inc.
FIGURE 30-1:
SIMPLIFIED PRG MODULE BLOCK DIAGRAM
Rev. 10-000 220A
5/29/201 4
VDD
ISET<4:0>
RTSS<3:0>
RPOL
SW2
Set_rising Timing Sources
RAMPx_out
PRGxR
PPS
to
peripherals
GO
REDG
PRGxRPPS
EN
S
Q
Switch
Control
FTSS<3:0>
SW1
R
Set_falling Timing Sources
PRGxF
OS
MODE<1:0>
PPS
Voltage Sources
voltage_ref
PRGxIN
SW3
FPOL
INS<3:0>
PRGxFPPS
DS40001775B-page 361
ISET<4:0>
PIC16(L)F1764/5/8/9
FEDG
SLOPE COMPENSATION (FALLING RAMP) TIMING DIAGRAM (MODE<1:0> = 00)
Rev. 10-000 223A
5/2/201 4
Init
EN
RDY
GO
OS
set_rising
set_falling
one_shot
sw1_closed
sw2_closed
sw3_closed
voltage_ref
RAMPx_out
Running
Init
Running
PIC16(L)F1764/5/8/9
DS40001775B-page 362
FIGURE 30-2:
 2014-2015 Microchip Technology Inc.
 2014-2015 Microchip Technology Inc.
FIGURE 30-3:
ALTERNATING RISING/FALLING RAMP GENERATION TIMING DIAGRAM (OS = 0, MODE<1:0> = 01)
Rev. 10-000 222A
4/29/201 4
Init
Running
Init
Running
EN
RDY
GO
REDG
FEDG
set_rising
set_falling
one_shot
sw1_closed
sw2_closed
voltage_ref
RAMPx_out
DS40001775B-page 363
PIC16(L)F1764/5/8/9
sw3_closed
Rev. 10-000 226A
5/2/201 4
Init
EN
RDY
GO
REDG
FEDG
set_rising
set_falling
one_shot
sw1_closed
sw2_closed
sw3_closed
voltage_ref
RAMPx_out
Running
Init
Running
PIC16(L)F1764/5/8/9
DS40001775B-page 364
FIGURE 30-4:
Notes: ALTERNATING RISING/FALLING RAMP GENERATION TIMING DIAGRAM (OS = 1, MODE<1:0> = 01)
 2014-2015 Microchip Technology Inc.
 2014-2015 Microchip Technology Inc.
FIGURE 30-5:
RISING RAMP GENERATION TIMING DIAGRAM (MODE<1:0> = 10)
Rev. 10-000 224A
5/2/201 4
Init
Running
Init
Running
EN
RDY
GO
OS
set_rising
set_falling
one_shot
sw1_closed
sw2_closed
sw3_closed
voltage_ref
DS40001775B-page 365
PIC16(L)F1764/5/8/9
RAMPx_out
PIC16(L)F1764/5/8/9
30.9
For example, when the circuit is using a 1 current
sense resistor and the peak current is 1A, then the
peak current expressed as a voltage is 1V. Therefore,
for this example the op amp output should be designed
to operate at 1V. If the power supply PWM frequency is
1 MHz, then the period is 1 s. Therefore, the desired
slope is 0.5 V/s, which is computed as shown in
Equation 30-2.
Slope Compensation Application
An example slope compensation circuit is shown in
Figure 30-6. The PRG input voltage is PRGxIN which
shares an I/O pin with the op amp output. The op amp
output is designed to operate at the expected peak
current sense voltage, which we’ll call VREF. The PRG
output voltage starts at VREF and should fall at a rate
less than half the target circuit current sense voltage
rate of rise. Therefore, the compensator slope,
expressed as volts per µs, can be computed by
Equation 30-1.
EQUATION 30-1:
EQUATION 30-2:
1
V REF
--------------2
2
-------------------------------------------- = --------- = 0.5V   s
1s
PWM Period (  s 
COMPENSATOR SLOPE
V REF
------------V
2
------  ------------------------------------------- s PWM Period (  s 
FIGURE 30-6:
CALCULATION EXAMPLE
Note: The setting for 0.5V/s is ISET<4:0> = 6
EXAMPLE SLOPE COMPENSATION CIRCUIT
Rev. 10-000 221A
5/7/201 4
VIN
L1
D1
COGxOUTx
COG
C1
-
+
R2
CxINxR1
PRG
RGxIN
DAC
OPAxOUT
+
OPAxIN-
R4
R3
-
C2
R5
C3
DS40001775B-page 366
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
30.10 Register Definitions: Programmable Ramp Generator
Long bit name prefixes for the PRG peripherals are
shown in Table 30-1. Refer to Section 1.1 “Register
and Bit Naming Conventions” for more information.
TABLE 30-1:
BIT NAME PREFIXES
Peripheral
Bit Name Prefix
PRG1
RG1
PRG2(1)
RG2
Note 1:
PIC16(L)F1768/9 devices only.
REGISTER 30-1:
PRGxCON0: PROGRAMMABLE RAMP GENERATOR x CONTROL 0 REGISTER
R/W-0/0
U-0
R/W-0/0
R/W-0/0
EN
—
FEDG
REDG
R/W-0/0
R/W-0/0
MODE<1:0>
R/W-0/0
R/W-0/0
OS
GO
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
EN: Programmable Ramp Generator Enable bit
1 = PRG module is enabled
0 = PRG module is disabled
bit 6
Unimplemented: Read as ‘0’
bit 5
FEDG: set_falling Input Mode Select bit
1 = set_falling timing input is edge-sensitive
0 = set_falling timing input is level-sensitive
bit 4
REDG: set_rising Input Mode Select bit
1 = set_rising timing input is edge-sensitive
0 = set_rising timing input is level-sensitive
bit 3-2
MODE<1:0>: Programmable Ramp Generator Mode Selection bits
11 = Reserved
10 = Rising Ramp Generator
01 = Alternating Rising/Falling Ramp Generator
00 = Slope Compensation
bit 1
OS: One-Shot Enable bit
1 = One-shot is enabled; minimum capacitor discharge is internally timed by one-shot
0 = One-shot is disabled; capacitor is discharged when timing input is true
bit 0
GO: Ramp Generation Control Start bit
If EN = 0:
This bit is forced to ‘0’.
If EN = 1:
1 = Slope or ramp function is operating
0 = Slope or ramp function is not operating; all current source switches are open and capacitor
discharge switch is closed
 2014-2015 Microchip Technology Inc.
DS40001775B-page 367
PIC16(L)F1764/5/8/9
REGISTER 30-2:
PRGxCON1: PROGRAMMABLE RAMP GENERATOR x CONTROL 1 REGISTER
U-0
U-0
U-0
U-0
U-0
R-0
R/W-0/0
R/W-0/0
—
—
—
—
—
RDY
FPOL
RPOL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-3
Unimplemented: Read as ‘0’
bit 2
RDY: Slope Generator Ready Status bit
1 = PRG is ready
0 = PRG is not ready
bit 1
FPOL: Fall Event Polarity Select bit
1 = set_falling timing input is active-low
0 = set_falling timing input is active-high
bit 0
RPOL: Rise Event Polarity Select bit
1 = set_rising timing input is active-low
0 = set_rising timing input is active-high
REGISTER 30-3:
PRGxINS: PRGx VOLTAGE INPUT SELECT REGISTER
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
INS<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
INS<3:0>: Voltage Input Select bits
Selects source of voltage level at which the ramp starts. See Table 30-2.
DS40001775B-page 368
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
TABLE 30-2:
INS<2:0>
VOLTAGE INPUT SOURCES
PIC16(L)F1764/5 Voltage Source
PIC16(L)F1768/9 Voltage Source
1010-1111
Reserved
Reserved
Reserved
1001(1)
Reserved
Switched PRG1IN1/OPA2OUT
Switched PRG2IN1/OPA1OUT
1000(1)
Switched PRG1IN0/OPA1OUT
Switched PRG1IN0/OPA1OUT
Switched PRG2IN0/OPA2OUT
0111
Reserved
Reserved
Reserved
0110
Reserved
DAC4_output
DAC4_output
0101
DAC3_output
DAC3_output
DAC3_output
0100
Reserved
DAC2_output
DAC2_output
0011
DAC1_output
DAC1_output
DAC1_output
0010
FVR_buffer2
FVR_buffer2
FVR_buffer2
0001
Reserved
PRG1IN1/OPA2OUT
PRG2IN1/OPA1OUT
PRG1IN0/OPA1OUT
PRG1IN0/OPA1OUT
PRG2IN0/OPA2OUT
0000
Note 1:
Input source is switched off when op amp override is forcing tri-state. See Section 29.3 “Override Control”.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 369
PIC16(L)F1764/5/8/9
REGISTER 30-4:
PRGxCON2: PROGRAMMABLE RAMP GENERATOR x CONTROL 2 REGISTER
U-0
U-0
U-0
—
—
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ISET<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
ISET<4:0>: PRG Current Source/Sink Set bits
Current source/sink setting and slope rate. See Table 30-3.
TABLE 30-3:
ISET<4:0>
PROGRAMMABLE RAMP GENERATOR CURRENT SETTINGS
Current Setting
(A)
Slope Rate
(V/s)
ISET<4:0>
Current Setting
(A)
Slope Rate
(V/s)
0h
2
0.2
10h
10
1.0
1h
2.5
0.25
11h
11
1.1
2h
3
0.3
12h
12
1.2
3h
3.5
0.35
13h
13
1.3
4h
4
0.4
14h
14
1.4
5h
4.5
0.45
15h
15
1.5
6h
5
0.5
16h
16
1.6
7h
5.5
0.55
17h
17
1.7
8h
6
0.6
18h
18
1.8
9h
6.5
0.65
19h
19
1.9
Ah
7
0.7
1Ah
20
2.0
Bh
7.5
0.75
1Bh
21
2.1
Ch
8
0.8
1Ch
22
2.2
Dh
8.5
0.85
1Dh
23
2.3
Eh
9
0.9
1Eh
24
2.4
Fh
9.5
0.95
1Fh
25
2.5
DS40001775B-page 370
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
REGISTER 30-5:
PRGxRTSS: PRGx set_rising TIMING SOURCE SELECT REGISTER
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
RTSS<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
RTSS<3:0>: set_rising Timing Source Select bits
See Table 30-4.
REGISTER 30-6:
PRGxFTSS: PRGx set_falling TIMING SOURCE SELECT REGISTER
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
FTSS<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
FTSS<3:0>: set_falling Timing Source Select bits
See Table 30-4.
TABLE 30-4:
PROGRAMMABLE RAMP GENERATOR TIMING SOURCES
RTSS<3:0>/FTSS<3:0>
Timing Source
RTSS<3:0>/FTSS<3:0>
Timing Source
0000
sync_C1OUT
1000
PWM6_output(2)
0001
sync_C2OUT
1001
CCP1_out
0010
sync_C3OUT(2)
1010
CCP2_out(2)
0011
(2)
1011
Reserved
(1)
1100
Reserved
0101
PWM3_output
1101
Reserved
0110
PWM4_output(2)
1110
Reserved
0111
PWM5_output
1111
Reserved
0100
Note 1:
2:
sync_C4OUT
PRGxR/PRGxF Pin
Input pin is selected with the PRGxRPPS or PRGxFPPS register.
PIC16(L)F1768/9 only.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 371
PIC16(L)F1764/5/8/9
TABLE 30-5:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH THE PRG MODULE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Register
on Page
PRG1CON0
EN
—
FEDG
REDG
PRG1CON1
—
—
—
—
PRG1CON2
—
—
—
PRG1INS
—
—
—
PRG1RPPS
—
—
—
PRG1RPPS<4:0>
PRG1FPPS
—
—
—
PRG1FPPS<4:0>
PRG1RTSS
—
—
—
—
RTSS<3:0>
159, 161
PRG1FTSS
—
—
—
—
FTSS<3:0>
159, 161
PRG2CON0(1)
EN
—
FEDG
REDG
PRG2CON1(1)
—
—
—
—
PRG2CON2(1)
—
—
—
PRG2INS(1)
—
—
—
PRG2RPPS(1)
—
—
—
PRG2RPPS<4:0>
PRG2FPPS(1)
—
—
—
PRG2FPPS<4:0>
PRG2RTSS(1)
—
—
—
—
RTSS<3:0>
159, 161
PRG2FTSS(1)
—
—
—
—
FTSS<3:0>
159, 161
PORTC
RC<7:6>
TRISC<7:6>(1)
ANSELC
ANSC<7:6>(1)
WPUC
WPUC<7:6>(1)
Legend:
Note 1:
—
RDY
OS
GO
367
FPOL
RPOL
368
ISET<4:0>
—
370
INS<3:0>
RDY
368
371
371
MODE<1:0>
—
OS
GO
367
FPOL
RPOL
368
ISET<4:0>
—
(1)
TRISC
MODE<1:0>
Bit 0
370
INS<3:0>
368
371
371
RC<5:0>
TRISC<5:4>
—
—
WPUC<5:4>
152
TRISC<3:2>
TRISC<1:0>
152
ANSC<3:2>
ANSC<1:0>
153
WPUC<3:2>
WPUC<1:0>
154
— = unimplemented, read as ‘0’. Shaded cells are unused by the PRG module.
PIC16(L)F1768/9 only.
DS40001775B-page 372
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
31.0
Using this method, the DSM can generate the following
types of key modulation schemes:
DATA SIGNAL MODULATOR
(DSM)
• Frequency-Shift Keying (FSK)
• Phase-Shift Keying (PSK)
• On-Off Keying (OOK)
The Data Signal Modulator (DSM) is a peripheral that
allows the user to mix a data stream, also known as a
modulator signal, with a carrier signal to produce a
modulated output.
Additionally, the following features are provided within
the DSM module:
Both the carrier and the modulator signals are supplied
to the DSM module either internally, from the output of
a peripheral, or externally through an input pin.
•
•
•
•
•
•
•
The modulated output signal is generated by performing
a logical “AND” operation of both the carrier and
modulator signals and then provided to the MDxOUT pin.
The carrier signal is comprised of two distinct and separate signals: a Carrier High (CARH) signal and a Carrier
Low (CARL) signal. During the time in which the Modulator (MOD) signal is in a logic high state, the DSM mixes
the Carrier High signal with the Modulator signal. When
the Modulator signal is in a logic low state, the DSM
mixes the Carrier Low signal with the Modulator signal.
FIGURE 31-1:
Carrier Synchronization
Carrier Source Polarity Select
Carrier Source Pin Disable
Programmable Modulator Data
Modulator Source Pin Disable
Modulated Output Polarity Select
Slew Rate Control
Figure 31-1 shows a simplified block diagram of the
Data Signal Modulator peripheral.
SIMPLIFIED BLOCK DIAGRAM OF THE DATA SIGNAL MODULATOR
CH<3:0>
MDxCHPPS
EN
PPS
Data Signal
Modulator
Carrier High Sources,
See Table 31-4
CARH
CHPOL
D
SYNC
MS<3:0>
MDxMODPPS
Q
1
PPS
0
MDx_out
Modulation Sources,
See Table 31-3
MOD
CHSYNC
PPS
MDxOUT
OPOL
RxyPPS
D
CL<3:0>
SYNC
MDxCLPPS
Q
PPS
1
0
Carrier Low Sources,
See Table 31-5
CARL
CLSYNC
CLPOL
 2014-2015 Microchip Technology Inc.
DS40001775B-page 373
PIC16(L)F1764/5/8/9
31.1
DSM Operation
31.3
Carrier Signal Sources
The DSM module is enabled by setting the EN bit in the
MDxCON register. Clearing the EN bit in the MDxCON
register, disables the DSM module by automatically
switching the Carrier High and Carrier Low signals to
the VSS signal source. The Modulator signal source is
also switched to the BIT bit in the MDxCON0 register.
This not only assures that the DSM module is inactive,
but that it is also consuming the least amount of
current.
The Carrier High signal is selected by configuring the
CH<3:0> bits of the MDxCARH register. Selections are
shown in Table 31-4.
The values used to select the Carrier High, Carrier Low
and Modulator sources held by the Modulation Source,
Modulation High Carrier and Modulation Low Carrier
registers are not affected when the EN bit is cleared,
and the DSM module is disabled. The values inside
these registers remain unchanged while the DSM is
inactive. The sources for the Carrier High, Carrier Low
and Modulator signals will once again be selected
when the EN bit is set and the DSM module is enabled
and active.
During the time when the DSM switches between Carrier High and Carrier Low signal sources, the carrier
data in the modulated output signal can become
truncated. To prevent this, the carrier signal can be
synchronized to the Modulator signal. When synchronization is enabled, the carrier pulse that is being mixed
at the time of the transition is allowed to transition low
before the DSM switches over to the next carrier
source.
The modulated output signal can be output on any
device I/O pin by selecting the desired DSM module in
the pin’s PPS Control register (see Register 12-2). If
the output is not directed to any I/O pin, then the DSM
module will remain active and continue to mix signals,
but the output value will not be sent to any pin.
31.2
The Carrier Low signal is selected by configuring the
CL<3:0> bits of the MDxCARL register. Selections are
shown in Table 31-5.
31.4
Carrier Synchronization
Synchronization is enabled separately for the Carrier
High and Carrier Low signal sources. Synchronization
for the Carrier High signal is enabled by setting the
CHSYNC bit of the MDxCON1 register. Synchronization for the Carrier Low signal is enabled by setting the
CLSYNC bit of the MDxCON1 register.
Figure 31-1 through Figure 31-6 show timing diagrams
of using various synchronization methods.
Modulator Signal Sources
The Modulator signal is selected by configuring the
MS<4:0> bits of the MDxSRC register. Selections are
shown in Table 31-3.
DS40001775B-page 374
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
FIGURE 31-2:
ON-OFF KEYING (OOK) SYNCHRONIZATION
Carrier Low (CARL)
Carrier High (CARH)
Modulator (MOD)
1 x MDx_out
0 x MDx_out
MDCLSYNC
MDCHSYNC
FIGURE 31-3:
NO SYNCHRONIZATION (MDCHSYNC = 0, MDCLSYNC = 0)
Carrier High (CARH)
Carrier Low (CARL)
Modulator (MOD)
MDx_out
Active Carrier
State
FIGURE 31-4:
CARH
CARL
CARH
CARL
CARRIER HIGH SYNCHRONIZATION (MDCHSYNC = 1, MDCLSYNC = 0)
Carrier High (CARH)
Carrier Low (CARL)
Modulator (MOD)
MDx_out
Active Carrier
State
CARH
 2014-2015 Microchip Technology Inc.
both
CARL
CARH
both
CARL
DS40001775B-page 375
PIC16(L)F1764/5/8/9
FIGURE 31-5:
CARRIER LOW SYNCHRONIZATION (MDCHSYNC = 0, MDCLSYNC = 1)
Carrier High (CARH)
Carrier Low (CARL)
Modulator (MOD)
MDx_out
Active Carrier
State
FIGURE 31-6:
CARH
CARL
CARH
CARL
FULL SYNCHRONIZATION (MDCHSYNC = 1, MDCLSYNC = 1)
Carrier High (CARH)
Carrier Low (CARL)
Modulator (MOD)
Falling Edges
Used to Sync
MDx_out
Active Carrier
State
DS40001775B-page 376
CARH
CARL
CARH
CARL
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
31.5
Input and Output Through Pins
31.7
Programmable Modulator Data
The modulation and carrier sources may be selected to
come from any device pin with the PPS control logic.
Selecting a pin requires two settings: the source selection determines that the PPS will be used and the PPS
control selects the desired pin. Source and PPS registers
are identified in Table 31-1. PPS register pin selections
are shown in Register 12-1 and Register 12-2.
The BIT bit of the MDxCON0 register can be selected
as the source for the Modulator signal. When the BIT
source is selected, then software generates the Modulation signal by setting and clearing the BIT bit at the
respective desired modulation high and low times.
TABLE 31-1:
The modulated output signal provided on the MDxOUT
pin can also be inverted. Inverting the modulated output signal is enabled by setting the OPOL bit of the
MDxCON0 register.
PIN SELECTIONS
Source
Register
PPS Register
Modulation
MDxSRC
MDxMODPPS
Carrier High
MDxCARH
MDxCHPPS
Carrier Low
MDxCARL
MDxCLPPS
Source
31.8
31.9
Modulated Output Polarity
Operation in Sleep Mode
Any device pin can be selected as the modulation
output with the individual pin PPS controls. See
Register 12-2 for the pin output selections.
The DSM module is not affected by Sleep mode. The
DSM will operate during Sleep provided that the carrier
and modulator input sources are also active during
Sleep.
31.6
31.10 Effects of a Reset
Carrier Source Polarity Select
The signal provided from any selected input source for
the Carrier High and Carrier Low signals can be
inverted. Inverting the signal for the Carrier High source
is enabled by setting the CHPOL bit of the MDxCON1
register. Inverting the signal for the Carrier Low source
is enabled by setting the CLPOL bit of the MDxCON1
register.
 2014-2015 Microchip Technology Inc.
Upon any device Reset, the Data Signal Modulator
module is disabled. The user’s firmware is responsible
for initializing the module before enabling the output.
The registers are reset to their default values.
DS40001775B-page 377
PIC16(L)F1764/5/8/9
31.11 Register Definitions: Data Signal Modulator
Long bit name prefixes for the DSM peripherals are
shown in Table 31-2. Refer to Section 1.1.2.2 “Long
Bit Names” for more information.
TABLE 31-2:
BIT NAME PREFIXES
Peripheral
Bit Name Prefix
DSM1
MD1
DSM2
Note 1:
(1)
MD2
PIC16(L)F1768/9 devices only.
REGISTER 31-1:
MDxCON0: MODULATION x CONTROL REGISTER 0
R/W-0/0
U-0
R-0/0
R/W-0/0
U-0
U-0
U-0
R/W-0/0
EN
—
OUT
OPOL
—
—
—
BIT(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
EN: Modulator Module Enable bit
1 = Modulator module is enabled and mixing input signals
0 = Modulator module is disabled and has no output
bit 6
Unimplemented: Read as ‘0’
bit 5
OUT: Modulator Output bit
Displays the current output value of the modulator module.(1)
bit 4
OPOL: Modulator Output Polarity Select bit
1 = Modulator output signal is inverted; Idle high output
0 = Modulator output signal is not inverted; Idle low output
bit 3-1
Unimplemented: Read as ‘0’
bit 0
BIT: Direct Software Control of the Modulation Source Input to Module bit(2)
1 = Modulator uses Carrier High source
0 = Modulator uses Carrier Low source
Note 1:
2:
The modulated output frequency can be greater and asynchronous from the clock that updates this
register bit; the bit value may not be valid for higher speed modulator or carrier signals.
BIT must be selected as the modulation source in the MDxSRC register for this operation.
DS40001775B-page 378
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
REGISTER 31-2:
MDxCON1: MODULATION x CONTROL REGISTER 1
U-0
U-0
R/W-0/0
R/W-0/0
U-0
U-0
R/W-0/0
R/W-0/0
—
—
CHPOL
CHSYNC
—
—
CLPOL
CLSYNC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
Unimplemented: Read as ‘0’
bit 5
CHPOL: Modulation High Carrier Polarity Select bit
1 = Selected high carrier source is inverted
0 = Selected high carrier source is not inverted
bit 4
CHSYNC: Modulation High Carrier Synchronization Enable bit
1 = Modulator waits for a low edge on the high carrier before allowing a switch to the low carrier
0 = Modulator output is not synchronized to the high carrier(1)
bit 3-2
Unimplemented: Read as ‘0’
bit 1
CLPOL: Modulation Low Carrier Polarity Select bit
1 = Selected low carrier source is inverted
0 = Selected low carrier source is not inverted
bit 0
CLSYNC: Modulation Low Carrier Synchronization Enable bit
1 = Modulator waits for a low edge on the low carrier before allowing a switch to the high carrier
0 = Modulator output is not synchronized to the low carrier(1)
Note 1:
Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 379
PIC16(L)F1764/5/8/9
REGISTER 31-3:
MDxSRC: MODULATION x SOURCE CONTROL REGISTER
U-0
U-0
U-0
—
—
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
MS<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
MS<4:0> Modulation Source Selection bits
See Table 31-3.
TABLE 31-3:
MODULATION SOURCE
MS<4:0>
Modulation Source
PIC16(L)F1764/5
Modulation Source
PIC16(L)F1768/9
11111-10100
Fixed Low
Fixed Low
10011
Fixed Low
sync_C4OUT
10010
Fixed Low
sync_C3OUT
10001
sync_C2OUT
sync_C2OUT
10000
sync_C1OUT
sync_C1OUT
01111
LC3_out
LC3_out
01110
LC2_out
LC2_out
01101
LC1_out
LC1_out
01100
Fixed Low
PWM6_out
01011
PWM5_out
PWM5_out
01010
Fixed Low
PWM4_out
01001
PWM3_out
PWM3_out
01000
Fixed low
CCP2_out
00111
CCP1_out
CCP1_out
00110
SDO_out
SDO_out
00101
Fixed Low
COG2A
00100
DT
DT
00011
TX_out
TX_out
00010
COG1A
COG1A
00001
MDxBIT
MDxBIT
00000
MDxMODPPS Pin Selection
MDxMODPPS Pin Selection
DS40001775B-page 380
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
REGISTER 31-4:
MDxCARH: MODULATION x CARRIER HIGH CONTROL REGISTER
U-0
U-0
U-0
U-0
—
—
—
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
CH<3:0>(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
CH<3:0> Modulator Data High Carrier Selection bits(1)
See Table 31-4.
Note 1:
Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
TABLE 31-4:
HIGH CARRIER SOURCES
CH<3:0>
High Carrier Source
PIC16(L)F1764/5
High Carrier Source
PIC16(L)F1768/9
1111
LC3_out
LC3_out
1110
LC2_out
LC2_out
1101
LC1_out
LC1_out
1100
Fixed Low
PWM6_out
1011
PWM5_out
PWM5_out
1010
Fixed Low
PWM4_out
1001
PWM3_out
PWM3_out
1000
Fixed Low
CCP2_out
0111
CCP1_out
CCP1_out
0110
Fixed Low
Fixed Low
0101
Fixed Low
Fixed Low
0100
Fixed Low
Fixed Low
0011
Fixed Low
Fixed Low
0010
HFINTOSC
HFINTOSC
0001
FOSC
FOSC
0000
MDxCHPPS Pin Selection
MDxCHPPS Pin Selection
 2014-2015 Microchip Technology Inc.
DS40001775B-page 381
PIC16(L)F1764/5/8/9
REGISTER 31-5:
MDxCARL: MODULATION x CARRIER LOW CONTROL REGISTER
U-0
U-0
U-0
U-0
—
—
—
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
CL<3:0>(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
CL<3:0> Modulator Data Low Carrier Selection bits(1)
See Table 31-5.
Note 1:
Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
TABLE 31-5:
LOW CARRIER SOURCES
CL<3:0>
Low Carrier Source
PIC16(L)F1764/5
Low Carrier Source
PIC16(L)F1768/9
1111
LC3_out
LC3_out
1110
LC2_out
LC2_out
1101
LC1_out
LC1_out
1100
Fixed Low
PWM6_out
1011
PWM5_out
PWM5_out
1010
Fixed Low
PWM4_out
1001
PWM3_out
PWM3_out
TABLE 31-6:
1000
Fixed Low
CCP2_out
0111
CCP1_out
CCP1_out
0110
Fixed Low
Fixed Low
0101
Fixed Low
Fixed Low
0100
Fixed Low
Fixed Low
0011
Fixed Low
Fixed Low
0010
HFINTOSC
HFINTOSC
0001
FOSC
FOSC
0000
MDxCLPPS Pin Selection
MDxCLPPS Pin Selection
SUMMARY OF REGISTERS ASSOCIATED WITH DATA SIGNAL MODULATOR MODE
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
MDxCARH
—
—
—
—
CH<3:0>
381
MDxCARL
—
—
—
—
CL<3:0>
382
MDxSRC
—
—
—
MDxCON0
EN
—
OUT
OPOL
—
—
—
BIT
378
MDxCON1
—
—
CHPOL
CHSYNC
—
—
CLPOL
CLSYNC
378
MS<4:0>
379
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Data Signal Modulator.
DS40001775B-page 382
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
32.0
32.1
The SPI interface supports the following modes and
features:
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
•
•
•
•
•
MSSP Module Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
Master mode
Slave mode
Clock Parity
Slave Select Synchronization (Slave mode only)
Daisy-Chain Connection of Slave Devices
Figure 32-1 is a block diagram of the SPI interface
module.
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
FIGURE 32-1:
MSSP BLOCK DIAGRAM (SPI MODE)
Data Bus
Read
Write
SSPxBUF Reg
SSPDATPPS
SDI
PPS
SSPSR Reg
Shift
Clock
bit 0
SDO
PPS
RxyPPS
SS Control
Enable
SS
PPS
SSPSSPPS
Edge
Select
SSPCLKPPS(2)
SCK
Note 1:
2:
SSPM<3:0>
4
PPS
PPS
TRISx bit
2 (CKP, CKE)
Clock Select
RxyPPS(1)
Edge
Select
(
T2_match
2
)
Prescaler TOSC
4, 16, 64
Baud Rate
Generator
(SSPxADD)
Output selection for Master mode.
Input selection for Slave and Master modes.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 383
PIC16(L)F1764/5/8/9
The I2C interface supports the following modes and
features:
Master mode
Slave mode
Byte NACKing (Slave mode)
Limited multi-master support
7-Bit and 10-Bit Addressing
Start and Stop interrupts
Interrupt masking
Clock stretching
Bus collision detection
General call address matching
Address masking
Address Hold and Data Hold modes
Selectable SDA hold times
MSSP BLOCK DIAGRAM (I2C MASTER MODE)
FIGURE 32-2:
Internal
Data Bus
SSPDATPPS(1)
SDA
SDA In
PPS
[SSPM<3:0>]
Write
Read
SSPxBUF
Baud Rate
Generator
(SSPxADD)
Shift
Clock
RxyPPS(1)
SSPCLKPPS(2)
SCL
PPS
Receive Enable (RCEN)
MSb
LSb
Start bit, Stop bit,
Acknowledge
Generate (SSPxCON2)
Clock Cntl
SSPSR
PPS
Clock Arbitrate/BCOL Detect
(hold off clock source)
•
•
•
•
•
•
•
•
•
•
•
•
•
Figure 32-2 is a block diagram of the I2C interface
module in Master mode. Figure 32-3 is a diagram of the
I2C interface module in Slave mode.
PPS
RxyPPS(2)
SCL In
Bus Collision
Note 1:
2:
Start bit Detect,
Stop bit Detect,
Write Collision Detect,
Clock Arbitration,
State Counter for
End of XMIT/RCV,
Address Match Detect
Set/Reset: S, P, SSPxSTAT, WCOL, SSPOV;
Reset SEN, PEN (SSPxCON2);
Set SSP1IF, BCL1IF
SDA pin selections must be the same for input and output.
SCL pin selections must be the same for input and output.
DS40001775B-page 384
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
FIGURE 32-3:
MSSP BLOCK DIAGRAM (I2C SLAVE MODE)
Internal
Data Bus
Read
Write
SSPxBUF Reg
SSPCLKPPS(2)
SCL
PPS
PPS
Clock
Stretching
RxyPPS(2)
Shift
Clock
SSPSR Reg
MSb
LSb
SSPxMSK Reg
SSPDATPPS(1)
SDA
Match Detect
Addr Match
PPS
SSPxADD Reg
PPS
RxyPPS(1)
Note 1:
2:
Start and
Stop bit Detect
Set, Reset
S, P bits
(SSPxSTAT Reg)
SDA pin selections must be the same for input and output.
SCL pin selections must be the same for input and output.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 385
PIC16(L)F1764/5/8/9
32.2
SPI Mode Overview
The Serial Peripheral Interface (SPI) bus is a
synchronous serial data communication bus that
operates in Full-Duplex mode. Devices communicate
in a master/slave environment where the master device
initiates the communication. A slave device is
controlled through a chip select known as Slave Select.
The SPI bus specifies four signal connections:
•
•
•
•
Serial Clock (SCK)
Serial Data Out (SDO)
Serial Data In (SDI)
Slave Select (SS)
Figure 32-1 shows the block diagram of the MSSP
module when operating in SPI mode.
The SPI bus operates with a single master device and
one or more slave devices. When multiple slave
devices are used, an independent Slave Select
connection is required from the master device to each
slave device.
Figure 32-4 shows a typical connection between a
master device and multiple slave devices.
The master selects only one slave at a time. Most slave
devices have tri-state outputs so their output signal
appears disconnected from the bus when they are not
selected.
Transmissions involve two shift registers, eight bits in
size, one in the master and one in the slave. With either
the master or the slave device, data is always shifted
out one bit at a time, with the Most Significant bit (MSb)
shifted out first. At the same time, a new Least
Significant bit (LSb) is shifted into the same register.
Figure 32-5 shows a typical connection between two
processors configured as master and slave devices.
Data is shifted out of both shift registers on the
programmed clock edge and latched on the opposite
edge of the clock.
To begin communication, the master device first sends
out the clock signal. Both the master and the slave
devices should be configured for the same clock polarity.
The master device starts a transmission by sending out
the MSb from its shift register. The slave device reads
this bit from that same line and saves it into the LSb
position of its shift register.
During each SPI clock cycle, a full-duplex data
transmission occurs. This means that while the master
device is sending out the MSb from its shift register (on
its SDO pin), and the slave device is reading this bit and
saving it as the LSb of its shift register, that the slave
device is also sending out the MSb from its shift register
(on its SDO pin) and the master device is reading this
bit and saving it as the LSb of its shift register.
After eight bits have been shifted out, the master and
slave have exchanged register values.
If there is more data to exchange, the shift registers are
loaded with new data and the process repeats itself.
Whether the data is meaningful or not (dummy data),
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends useful data and slave sends dummy
data.
• Master sends useful data and slave sends useful
data.
• Master sends dummy data and slave sends useful
data.
Transmissions may involve any number of clock
cycles. When there is no more data to be transmitted,
the master stops sending the clock signal and it
deselects the slave.
Every slave device connected to the bus that has not
been selected through its Slave Select line must
disregard the clock and transmission signals and must
not transmit out any data of its own.
The master device transmits information out on its SDO
output pin, which is connected to, and received by, the
slave’s SDI input pin. The slave device transmits information out on its SDO output pin, which is connected
to, and received by, the master’s SDI input pin.
DS40001775B-page 386
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
FIGURE 32-4:
SPI MASTER AND MULTIPLE SLAVE CONNECTION
SPI Master
SCK
SCK
SDO
SDI
SDO
SDI
General I/O
General I/O
General I/O
SPI Slave
#1
SS
SCK
SDI
SDO
SPI Slave
#2
SS
SCK
SDI
SDO
SPI Slave
#3
SS
32.2.1
32.2.2
SPI MODE REGISTERS
The MSSP module has five registers for SPI mode
operation. These are:
•
•
•
•
•
•
MSSP Status Register (SSPxSTAT)
MSSP Control Register 1 (SSPxCON1)
MSSP Control Register 3 (SSPxCON3)
MSSP Data Buffer Register (SSPxBUF)
MSSP Address Register (SSPxADD)
MSSP Shift Register (SSPSR)
(Not directly accessible)
SSPxCON1 and SSPxSTAT are the control
STATUS registers in SPI mode operation.
SSPxCON1 register is readable and writable.
lower six bits of the SSPxSTAT are read-only.
upper two bits of the SSPxSTAT are read/write.
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
These control bits allow the following to be specified:
•
•
•
•
and
The
The
The
In one SPI Master mode, SSPxADD can be loaded
with a value used in the Baud Rate Generator. More
information on the Baud Rate Generator is available in
Section 32.7 “Baud Rate Generator”.
SSPSR is the shift register used for shifting data in and
out. SSPxBUF provides indirect access to the SSPSR
register. SSPxBUF is the buffer register to which data
bytes are written, and from which data bytes are read.
In receive operations, SSPSR and SSPxBUF together
create a buffered receiver. When SSPSR receives a
complete byte, it is transferred to SSPxBUF and the
SSPxIF interrupt is set.
During transmission, the SSPxBUF is not buffered. A
write to SSPxBUF will write to both SSPxBUF and
SSPSR.
 2014-2015 Microchip Technology Inc.
SPI MODE OPERATION
Master mode (SCK is the clock output)
Slave mode (SCK is the clock input)
Clock Polarity (Idle state of SCK)
Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
To enable the serial port, SSP Enable bit, SSPEN of the
SSPxCON1 register, must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, re-initialize the
SSPxCONx registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial port
pins. For the pins to behave as the serial port function,
some must have their data direction bits (in the TRISx
register) appropriately programmed as follows:
• SDI must have corresponding TRISx bit set
• SDO must have corresponding TRISx bit cleared
• SCK (Master mode) must have corresponding
TRISx bit cleared
• SCK (Slave mode) must have corresponding
TRISx bit set
• SS must have corresponding TRISx bit set
Any serial port function that is not desired may be
overridden by programming the corresponding Data
Direction (TRISx) register to the opposite value.
DS40001775B-page 387
PIC16(L)F1764/5/8/9
The MSSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPxBUF). The
SSPSR shifts the data in and out of the device, MSb
first. The SSPxBUF holds the data that was written to
the SSPSR until the received data is ready. Once the
eight bits of data have been received, that byte is
moved to the SSPxBUF register. Then, the Buffer Full
Detect bit, BF of the SSPxSTAT register, and the interrupt flag bit, SSPxIF, are set. This double-buffering of
the received data (SSPxBUF) allows the next byte to
start reception before reading the data that was just
received. Any write to the SSPxBUF register during
transmission/reception of data will be ignored and the
Write Collision Detect bit, WCOL of the SSPxCON1
register, will be set. User software must clear the
WCOL bit to allow the following write(s) to the
SSPxBUF register to complete successfully.
FIGURE 32-5:
When the application software is expecting to receive
valid data, the SSPxBUF should be read before the
next byte of data to transfer is written to the SSPxBUF.
The Buffer Full bit, BF of the SSPxSTAT register,
indicates when SSPxBUF has been loaded with the
received data (transmission is complete). When the
SSPxBUF is read, the BF bit is cleared. This data may
be irrelevant if the SPI is only a transmitter. Generally,
the MSSP interrupt is used to determine when the
transmission/reception has completed. If the interrupt
method is not going to be used, then software polling
can be done to ensure that a write collision does not
occur.
The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPxBUF register.
Additionally, the SSPxSTAT register indicates the
various Status conditions.
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM<3:0> = 00xx
= 1010
SPI Slave SSPM<3:0> = 010x
SDO
SDI
Serial Input Buffer
(SSPxBUF)
Serial Input Buffer
(BUF)
SDI
Shift Register
(SSPSR)
MSb
LSb
SCK
General I/O
Processor 1
DS40001775B-page 388
SDO
Serial Clock
Slave Select
(optional)
Shift Register
(SSPSR)
MSb
LSb
SCK
SS
Processor 2
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
32.2.3
SPI MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK line. The master
determines when the slave (Processor 2, Figure 32-5)
is to broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPxBUF register is written to. If the SPI
is only going to receive, the SDO output could be
disabled (programmed as an input). The SSPSR
register will continue to shift in the signal present on the
SDI pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPxBUF register as
if a normal received byte (interrupts and status bits
appropriately set).
The clock polarity is selected by appropriately
programming the CKP bit of the SSPxCON1 register
and the CKE bit of the SSPxSTAT register. This then,
would give waveforms for SPI communication as
shown in Figure 32-6, Figure 32-8, Figure 32-9 and
Figure 32-10, where the MSB is transmitted first. In
Master mode, the SPI clock rate (bit rate) is user
programmable to be one of the following:
•
•
•
•
•
FOSC/4 (or TCY)
FOSC/16 (or 4 * TCY)
FOSC/64 (or 16 * TCY)
Timer2 output/2
FOSC/(4 * (SSPxADD + 1))
Figure 32-6 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPxBUF is loaded with the received
data is shown.
Note:
 2014-2015 Microchip Technology Inc.
In Master mode, the clock signal output to
the SCK pin is also the clock signal input
to the peripheral. The pin selected for output with the RxyPPS register must also be
selected as the peripheral input with the
SSPCLKPPS register.
DS40001775B-page 389
PIC16(L)F1764/5/8/9
FIGURE 32-6:
SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPxBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
(CKE = 0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDO
(CKE = 1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit 0
bit 7
Input
Sample
(SMP = 1)
SSPxIF
SSPSR to
SSPxBUF
32.2.4
SPI SLAVE MODE
In Slave mode, the data is transmitted and received as
external clock pulses appear on SCK. When the last
bit is latched, the SSPxIF interrupt flag bit is set.
Before enabling the module in SPI Slave mode, the clock
line must match the proper Idle state. The clock line can
be observed by reading the SCK pin. The Idle state is
determined by the CKP bit of the SSPxCON1 register.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. The shift register is clocked from the SCK pin
input and when a byte is received, the device will
generate an interrupt. If enabled, the device will
wake-up from Sleep.
DS40001775B-page 390
32.2.4.1
Daisy-Chain Configuration
The SPI bus can sometimes be connected in a
daisy-chain configuration. The first slave output is
connected to the second slave input, the second slave
output is connected to the third slave input, and so on.
The final slave output is connected to the master input.
Each slave sends out, during a second group of clock
pulses, an exact copy of what was received during
the first group of clock pulses. The whole chain acts
as one large communication shift register. The
daisy-chain feature only requires a single Slave Select
line from the master device.
Figure 32-7 shows the block diagram of a typical
daisy-chain connection when operating in SPI mode.
In a daisy-chain configuration, only the most recent
byte on the bus is required by the slave. Setting the
BOEN bit of the SSPxCON3 register will enable writes
to the SSPxBUF register, even if the previous byte has
not been read. This allows the software to ignore data
that may not apply to it.
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
32.2.5
SLAVE SELECT
SYNCHRONIZATION
When the SS pin is low, transmission and reception are
enabled and the SDO pin is driven.
The Slave Select can also be used to synchronize
communication. The Slave Select line is held high until
the master device is ready to communicate. When the
Slave Select line is pulled low, the slave knows that a
new transmission is starting.
If the slave fails to receive the communication properly,
it will be reset at the end of the transmission, when the
Slave Select line returns to a high state. The slave is
then ready to receive a new transmission when the
Slave Select line is pulled low again. If the Slave Select
line is not used, there is a risk that the slave will
eventually become out of sync with the master. If the
slave misses a bit, it will always be one bit off in future
transmissions. Use of the Slave Select line allows the
slave and master to align themselves at the beginning
of each transmission.
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control enabled
(SSPxCON1<3:0> = 0100).
FIGURE 32-7:
When the SS pin goes high, the SDO pin is no longer
driven, even if in the middle of a transmitted byte and
becomes a floating output. External pull-up/pull-down
resistors may be desirable depending on the application.
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPxCON1<3:0> = 0100),
the SPI module will reset if the SS pin is set
to VDD.
2: When the SPI is used in Slave mode with
CKE set; the user must enable SS pin
control.
3: While operating in SPI Slave mode, the
SMP bit of the SSPxSTAT register must
remain clear.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
SPI DAISY-CHAIN CONNECTION
SPI Master
SCK
SCK
SDO
SDI
SDI
General I/O
SDO
SPI Slave
#1
SS
SCK
SDI
SDO
SPI Slave
#2
SS
SCK
SDI
SDO
SPI Slave
#3
SS
 2014-2015 Microchip Technology Inc.
DS40001775B-page 391
PIC16(L)F1764/5/8/9
FIGURE 32-8:
SLAVE SELECT SYNCHRONOUS WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPxBUF
Shift Register, SSPSR,
and Bit Count are Reset
SSPxBUF to
SSPSR
SDO
bit 7
bit 6
bit 7
SDI
bit 6
bit 0
bit 0
bit 7
bit 7
Input
Sample
SSPxIF
Interrupt
Flag
SSPSR to
SSPxBUF
DS40001775B-page 392
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
FIGURE 32-9:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPxBUF Valid
SDO
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
bit 0
bit 7
Input
Sample
SSPxIF
Interrupt
Flag
SSPSR to
SSPxBUF
Write Collision
Detection Active
FIGURE 32-10:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPxBUF Valid
SDO
bit 6
bit 7
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
bit 7
bit 0
Input
Sample
SSPxIF
Interrupt
Flag
SSPSR to
SSPxBUF
Write Collision
Detection Active
 2014-2015 Microchip Technology Inc.
DS40001775B-page 393
PIC16(L)F1764/5/8/9
32.2.6
SPI OPERATION IN SLEEP MODE
In SPI Master mode, module clocks may be operating
at a different speed than when in Full-Power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the MSSP
clock is much faster than the system clock.
In Slave mode, when MSSP interrupts are enabled,
after the master completes sending data, an MSSP
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSP
interrupts should be disabled.
TABLE 32-1:
Name
ANSELA
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all eight bits have been received, the
MSSP interrupt flag bit will be set and if enabled, will
wake the device.
SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
—
—
—
ANSA4
—
—
—
ANSC<7:6>(2)
ANSELC
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmission/reception will remain in that state until the device
wakes. After the device returns to Run mode, the
module will resume transmitting and receiving data.
Bit 2
Bit 1
Bit 0
ANSA<2:0>
Register
on Page
142
ANSC<3:0>
153
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
104
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
105
PIR1
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
108
INTCON
TMR1GIF
ADIF
RCIF
RxyPPS
—
—
—
RxyPPS<4:0>
159
SSPCLKPPS
—
—
—
SSPCLKPPS<4:0>
159, 161
SSPDATPPS
—
—
—
SSPDATPPS<4:0>
159, 161
—
—
—
SSPSSPPS<4:0>
159, 161
SSPSSPPS
SSP1BUF
Synchronous Serial Port Receive Buffer/Transmit Register
SSP1CON1
WCOL
SSPOV
SSPEN
CKP
SSP1CON3
ACKTIM
PCIE
SCIE
BOEN
SSP1STAT
SMP
CKE
D/A
P
—
—
TRISA
TRISB(2)
TRISA<5:4>
TRISB<7:4>
TRISC<7:6>(2)
TRISC
Legend:
*
Note 1:
2:
387*
SSPM<3:0>
SDAHT
SBCDE
S
R/W
—(1)
—
433
AHEN
DHEN
431
UA
BF
431
—
147
TRISA<2:0>
—
—
TRISC<5:0>
141
152
— = unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
Page provides register information.
Unimplemented, read as ‘1’.
PIC16(L)F1768/9 only.
DS40001775B-page 394
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
32.3
I2C MODE OVERVIEW
FIGURE 32-11:
The Inter-Integrated Circuit (I2C) bus is a multi-master
serial data communication bus. Devices communicate
in a master/slave environment where the master
devices initiate the communication. A slave device is
controlled through addressing.
VDD
SCL
The I2C bus specifies two signal connections:
• Serial Clock (SCL)
• Serial Data (SDA)
Figure 32-11 shows the block diagram of the MSSP
module when operating in I2C mode.
Both the SCL and SDA connections are bidirectional
open-drain lines, each requiring pull-up resistors for the
supply voltage. Pulling the line to ground is considered
a logical zero and letting the line float is considered a
logical one.
Figure 32-11 shows a typical connection between two
processors configured as master and slave devices.
The I2C bus can operate with one or more master
devices and one or more slave devices.
There are four potential modes of operation for a given
device:
• Master Transmit mode
(master is transmitting data to a slave)
• Master Receive mode
(master is receiving data from a slave)
• Slave Transmit mode
(slave is transmitting data to a master)
• Slave Receive mode
(slave is receiving data from the master)
To begin communication, a master device starts out in
Master Transmit mode. The master device sends out a
Start bit, followed by the address byte of the slave it
intends to communicate with. This is followed by a
single read/write bit, which determines whether the
master intends to transmit to or receive data from the
slave device.
If the requested slave exists on the bus, it will respond
with an Acknowledge bit, otherwise known as an ACK.
The master then continues in either Transmit mode or
Receive mode and the slave continues in the complement, either in Receive mode or Transmit mode,
respectively.
A Start bit is indicated by a high-to-low transition of the
SDA line while the SCL line is held high. Address and
data bytes are sent out, Most Significant bit (MSb) first.
The read/write bit is sent out as a logical one when the
master intends to read data from the slave and is sent
out as a logical zero when it intends to write data to the
slave.
 2014-2015 Microchip Technology Inc.
I2C MASTER/
SLAVE CONNECTION
SCL
VDD
Master
Slave
SDA
SDA
The Acknowledge bit (ACK) is an active-low signal,
which holds the SDA line low to indicate to the transmitter that the slave device has received the transmitted
data and is ready to receive more.
The transition of a data bit is always performed while
the SCL line is held low. Transitions that occur while the
SCL line is held high are used to indicate Start and Stop
bits.
If the master intends to write to the slave, then it repeatedly sends out a byte of data, with the slave responding
after each byte with an ACK bit. In this example, the
master device is in Master Transmit mode and the
slave is in Slave Receive mode.
If the master intends to read from the slave, then it
repeatedly receives a byte of data from the slave and
responds after each byte with an ACK bit. In this
example, the master device is in Master Receive mode
and the slave is Slave Transmit mode.
On the last byte of data communicated, the master
device may end the transmission by sending a Stop bit.
If the master device is in Receive mode, it sends the
Stop bit in place of the last ACK bit. A Stop bit is
indicated by a low-to-high transition of the SDA line
while the SCL line is held high.
In some cases, the master may want to maintain
control of the bus and re-initiate another transmission.
If so, the master device may send another Start bit in
place of the Stop bit or last ACK bit when it is in receive
mode.
The I2C bus specifies three message protocols;
• Single message where a master writes data to a
slave.
• Single message where a master reads data from
a slave.
• Combined message where a master initiates a
minimum of two writes, or two reads, or a
combination of writes and reads, to one or more
slaves.
DS40001775B-page 395
PIC16(L)F1764/5/8/9
When one device is transmitting a logical one, or letting
the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can
detect that the line is not a logical one. This detection,
when used on the SCL line, is called clock stretching.
Clock stretching gives slave devices a mechanism to
control the flow of data. When this detection is used on
the SDA line, it is called arbitration. Arbitration ensures
that there is only one master device communicating at
any single time.
32.3.1
CLOCK STRETCHING
When a slave device has not completed processing
data, it can delay the transfer of more data through the
process of clock stretching. An addressed slave device
may hold the SCL clock line low after receiving or sending a bit, indicating that it is not yet ready to continue.
The master that is communicating with the slave will
attempt to raise the SCL line in order to transfer the
next bit, but will detect that the clock line has not yet
been released. Because the SCL connection is
open-drain, the slave has the ability to hold that line low
until it is ready to continue communicating.
Clock stretching allows receivers that cannot keep up
with a transmitter to control the flow of incoming data.
32.3.2
ARBITRATION
Each master device must monitor the bus for Start and
Stop bits. If the device detects that the bus is busy, it
cannot begin a new message until the bus returns to an
Idle state.
For example, if one transmitter holds the SDA line to a
logical one (lets it float) and a second transmitter holds
it to a logical zero (pulls it low), the result is that the
SDA line will be low. The first transmitter then observes
that the level of the line is different than expected and
concludes that another transmitter is communicating.
The first transmitter to notice this difference is the one
that loses arbitration and must stop driving the SDA
line. If this transmitter is also a master device, it also
must stop driving the SCL line. It then can monitor the
lines for a Stop condition before trying to re-issue its
transmission. In the meantime, the other device that
has not noticed any difference between the expected
and actual levels on the SDA line continues with its
original transmission. It can do so without any complications, because so far, the transmission appears
exactly as expected with no other transmitter disturbing
the message.
Slave Transmit mode can also be arbitrated, when a
master addresses multiple slaves, but this is less
common.
If two master devices are sending a message to two
different slave devices at the address stage, the master
sending the lower slave address always wins arbitration. When two master devices send messages to the
same slave address, and addresses can sometimes
refer to multiple slaves, the arbitration process must
continue into the data stage.
Arbitration usually occurs very rarely, but it is a
necessary process for proper multi-master support.
However, two master devices may try to initiate a transmission on or about the same time. When this occurs,
the process of arbitration begins. Each transmitter
checks the level of the SDA data line and compares it
to the level that it expects to find. The first transmitter to
observe that the two levels do not match, loses
arbitration and must stop transmitting on the SDA line.
DS40001775B-page 396
 2014-2015 Microchip Technology Inc.
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32.4
I2C MODE OPERATION
All MSSP I2C communication is byte-oriented and
shifted out, MSb first. Six SFR registers and two
interrupt flags interface the module with the PIC®
microcontroller and user software. Two pins, SDA and
SCL, are exercised by the module to communicate
with other external I2C devices.
32.4.1
The clock signal, SCL, is provided by the master. Data
is valid to change while the SCL signal is low, and
sampled on the rising edge of the clock. Changes on
the SDA line while the SCL line is high define special
conditions on the bus, explained below.
DEFINITION OF I2C TERMINOLOGY
There is language and terminology in the description
of I2C communication that have definitions specific to
I2C. That word usage is defined below and may be
used in the rest of this document without explanation.
This table was adapted from the Philips® I2C
specification.
32.4.3
SDA AND SCL PINS
Selection of any I2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain. These
pins should be set by the user to inputs by setting the
appropriate TRISx bits.
Note 1: Data is tied to output zero when an I2C
mode is enabled.
2: Any device pin can be selected for SDA
and SCL functions with the PPS peripheral.
These functions are bidirectional. The SDA
input is selected with the SSPDATPPS
registers. The SCL input is selected with
the SSPCLKPPS registers. Outputs are
selected with the RxyPPS registers. It is the
user’s responsibility to make the selections
so that both the input and the output for
each function is on the same pin.
32.4.4
TERM
I2C BUS TERMS
Description
Transmitter
The device which shifts data out
onto the bus.
Receiver
The device which shifts data in
from the bus.
Master
The device that initiates a transfer,
generates clock signals and
terminates a transfer.
Slave
The device addressed by the
master.
Multi-master
A bus with more than one device
that can initiate data transfers.
Arbitration
Procedure to ensure that only one
master at a time controls the bus.
Winning arbitration ensures that
the message is not corrupted.
BYTE FORMAT
All communication in I2C is done in 9-bit segments. A
byte is sent from a master to a slave or vice-versa,
followed by an Acknowledge bit sent back. After the
eighth falling edge of the SCL line, the device outputting data on the SDA changes that pin to an input and
reads in an Acknowledge value on the next clock
pulse.
32.4.2
TABLE 32-2:
Synchronization Procedure to synchronize the
clocks of two or more devices on
the bus.
Idle
No master is controlling the bus,
and both SDA and SCL lines are
high.
Active
Any time one or more master
devices is controlling the bus.
Addressed
Slave
Slave device that has received a
matching address and is actively
being clocked by a master.
Matching
Address
Address byte that is clocked into a
slave that matches the value
stored in SSPxADD.
Write Request
Slave receives a matching
address with R/W bit clear and is
ready to clock in data.
Read Request
Master sends an address byte with
the R/W bit set, indicating that it
wishes to clock data out of the
slave. This data is the next and all
following bytes until a Restart or
Stop.
Clock Stretching When a device on the bus hold
SCL low to stall communication.
Bus Collision
Any time the SDA line is sampled
low by the module while it is
outputting and expected high
state.
SDA HOLD TIME
The hold time of the SDA pin is selected by the SDAHT
bit of the SSPxCON3 register. Hold time is the time
SDA is held valid after the falling edge of SCL. Setting
the SDAHT bit selects a longer 300 ns minimum hold
time and may help on buses with large capacitance.
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DS40001775B-page 397
PIC16(L)F1764/5/8/9
32.4.5
START CONDITION
32.4.7
2
The I C specification defines a Start condition as a
transition of SDA from a high to a low state while the
SCL line is high. A Start condition is always generated
by the master and signifies the transition of the bus
from an Idle to an active state. Figure 32-12 shows
wave forms for Start and Stop conditions.
A Restart is valid any time that a Stop would be valid.
A master can issue a Restart if it wishes to hold the
bus after terminating the current transfer. A Restart
has the same effect on the slave that a Start would,
resetting all slave logic and preparing it to clock in an
address. The master may want to address the same or
another slave. Figure 32-13 shows the wave form for a
Restart condition.
A bus collision can occur on a Start condition if the
module samples the SDA line low before asserting it
low. This does not conform to the I2C specification that
states no bus collision can occur on a Start.
32.4.6
RESTART CONDITION
In 10-Bit Addressing Slave mode, a Restart is required
for the master to clock data out of the addressed
slave. Once a slave has been fully addressed, matching both high and low address bytes, the master can
issue a Restart and the high address byte with the
R/W bit set. The slave logic will then hold the clock
and prepare to clock out data.
STOP CONDITION
A Stop condition is a transition of the SDA line from
low-to-high state while the SCL line is high.
Note: At least one SCL low time must appear
before a Stop is valid, therefore, if the SDA
line goes low, then high again while the SCL
line stays high, only the Start condition is
detected.
After a full match with R/W clear in 10-bit mode, a prior
match flag is set and maintained until a Stop condition, a
high address with R/W clear or high address match fails.
32.4.8
START/STOP CONDITION
INTERRUPT MASKING
The SCIE and PCIE bits of the SSPxCON3 register
can enable the generation of an interrupt in Slave
modes that do not typically support this function. In
Slave modes where interrupt on Start and Stop detect
is already enabled, these bits will have no effect.
I2C START AND STOP CONDITIONS
FIGURE 32-12:
SDA
SCL
S
Start
Condition
FIGURE 32-13:
P
Change of
Data Allowed
Change of
Data Allowed
Stop
Condition
I2C RESTART CONDITION
Sr
Change of
Data Allowed
DS40001775B-page 398
Restart
Condition
Change of
Data Allowed
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
32.4.9
ACKNOWLEDGE SEQUENCE
32.5.1
2
The 9th SCL pulse for any transferred byte in I C is
dedicated as an Acknowledge. It allows receiving
devices to respond back to the transmitter by pulling
the SDA line low. The transmitter must release control
of the line during this time to shift in the response. The
Acknowledge (ACK) is an active-low signal, pulling the
SDA line low indicates to the transmitter that the
device has received the transmitted data and is ready
to receive more.
The result of an ACK is placed in the ACKSTAT bit of
the SSPxCON2 register.
Slave software, when the AHEN and DHEN bits are
set, allows the user to set the ACK value sent back to
the transmitter. The ACKDT bit of the SSPxCON2
register is set/cleared to determine the response.
Slave hardware will generate an ACK response if the
AHEN and DHEN bits of the SSPxCON3 register are
clear.
There are certain conditions where an ACK will not be
sent by the slave. If the BF bit of the SSPxSTAT register or the SSPOV bit of the SSPxCON1 register are
set when a byte is received.
When the module is addressed, after the eighth falling
edge of SCL on the bus, the ACKTIM bit of the
SSPxCON3 register is set. The ACKTIM bit indicates
the Acknowledge time of the active bus. The ACKTIM
status bit is only active when the AHEN bit or DHEN bit
is enabled.
32.5
I2C Slave Mode Operation
The MSSP Slave mode operates in one of four modes
selected by the SSPM<3:0> bits of SSPxCON1 register. The modes can be divided into 7-Bit and 10-Bit
Addressing modes. 10-Bit Addressing mode operates
the same as 7-bit with some additional overhead for
handling the larger addresses.
Modes with Start and Stop bit interrupts operate the
same as the other modes, with SSPxIF additionally
getting set upon detection of a Start, Restart or Stop
condition.
 2014-2015 Microchip Technology Inc.
SLAVE MODE ADDRESSES
The SSPxADD register (Register 32-6) contains the
Slave mode address. The first byte received after a
Start or Restart condition is compared against the
value stored in this register. If the byte matches, the
value is loaded into the SSPxBUF register and an
interrupt is generated. If the value does not match, the
module goes Idle and no indication is given to the
software that anything happened.
The SSP Mask register (Register 32-5) affects the
address matching process. See Section 32.5.8 “SSP
Mask Register” for more information.
32.5.1.1
I2C Slave 7-Bit Addressing Mode
In 7-Bit Addressing mode, the LSb of the received data
byte is ignored when determining if there is an address
match.
32.5.1.2
I2C Slave 10-Bit Addressing Mode
In 10-Bit Addressing mode, the first received byte is
compared to the binary value of ‘1 1 1 1 0 A9 A8 0’.
A9 and A8 are the two MSbs of the 10-bit address and
stored in bits 2 and 1 of the SSPxADD register.
After the Acknowledge of the high byte, the UA bit is
set and SCL is held low until the user updates
SSPxADD with the low address. The low address byte
is clocked in and all eight bits are compared to the low
address value in SSPxADD. Even if there is not an
address match, SSPxIF and UA are set, and SCL is
held low until SSPxADD is updated to receive a high
byte again. When SSPxADD is updated, the UA bit is
cleared. This ensures the module is ready to receive
the high address byte on the next communication.
A high and low address match as a write request is
required at the start of all 10-Bit Addressing communication. A transmission can be initiated by issuing a
Restart once the slave is addressed, and clocking in
the high address with the R/W bit set. The slave
hardware will then Acknowledge the read request and
prepare to clock out data. This is only valid for a slave
after it has received a complete high and low address
byte match.
DS40001775B-page 399
PIC16(L)F1764/5/8/9
32.5.2
SLAVE RECEPTION
When the R/W bit of a matching received address byte
is clear, the R/W bit of the SSPxSTAT register is
cleared. The received address is loaded into the
SSPxBUF register and Acknowledged.
When the overflow condition exists for a received
address, then not Acknowledge is given. An overflow
condition is defined as either bit, BF of the SSPxSTAT
register, is set or bit, SSPOV of the SSPxCON1 register, is set. The BOEN bit of the SSPxCON3 register
modifies this operation. For more information see
Register 32-4.
An MSSP interrupt is generated for each transferred
data byte. Flag bit, SSPxIF, must be cleared by
software.
When the SEN bit of the SSPxCON2 register is set,
SCL will be held low (clock stretch) following each
received byte. The clock must be released by setting
the CKP bit of the SSPxCON1 register, except
sometimes in 10-bit mode. See Section 32.5.6.2
“10-Bit Addressing Mode” for more detail.
32.5.2.1
7-Bit Addressing Reception
This section describes a standard sequence of events
for the MSSP module configured as an I2C slave in
7-Bit
Addressing
mode.
Figure 32-14
and
Figure 32-15 is used as a visual reference for this
description.
This is a step by step process of what typically must
be done to accomplish I2C communication.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Start bit is detected.
S bit of SSPxSTAT is set; SSPxIF is set if
interrupt on Start detect is enabled.
Matching address with R/W bit clear is received.
The slave pulls SDA low, sending an ACK to the
master and sets the SSPxIF bit.
Software clears the SSPxIF bit.
Software reads the received address from
SSPxBUF, clearing the BF flag.
If SEN = 1, slave software sets the CKP bit to
release the SCL line.
The master clocks out a data byte.
Slave drives SDA low, sending an ACK to the
master and sets the SSPxIF bit.
Software clears SSPxIF.
Software reads the received byte from
SSPxBUF, clearing BF.
Steps 8-12 are repeated for all received bytes
from the master.
Master sends Stop condition, setting P bit of
SSPxSTAT and the bus goes Idle.
DS40001775B-page 400
32.5.2.2
7-Bit Reception with AHEN and DHEN
Slave device reception with AHEN and DHEN set
operates the same as without these options with extra
interrupts and clock stretching added after the eighth
falling edge of SCL. These additional interrupts allow
the slave software to decide whether it wants to ACK
the receive address or data byte, rather than the hardware. This functionality adds support for PMBus™ that
was not present on previous versions of this module.
This list describes the steps that need to be taken by
slave software to use these options for I2C communication. Figure 32-16 displays a module using both
address and data holding. Figure 32-17 includes the
operation with the SEN bit of the SSPxCON2 register
set.
1.
S bit of SSPxSTAT is set; SSPxIF is set if
interrupt on Start detect is enabled.
2. Matching address with R/W bit clear is clocked
in. SSPxIF is set and CKP cleared after the
eighth falling edge of SCL.
3. Slave clears SSPxIF.
4. Slave can look at the ACKTIM bit of the
SSPxCON3 register to determine if SSPxIF was
after or before the ACK.
5. Slave reads the address value from SSPxBUF,
clearing the BF flag.
6. Slave sets ACK value clocked out to the master
by setting ACKDT.
7. Slave releases the clock by setting CKP.
8. SSPxIF is set after an ACK, not after a NACK.
9. If SEN = 1, the slave hardware will stretch the
clock after the ACK.
10. Slave clears SSPxIF.
Note: SSPxIF is still set after the 9th falling edge
of SCL even if there is no clock stretching
and BF has been cleared. Only if NACK is
sent to master is SSPxIF not set
11. SSPxIF is set and CKP cleared after eighth
falling edge of SCL for a received data byte.
12. Slave looks at ACKTIM bit of SSPxCON3 to
determine the source of the interrupt.
13. Slave reads the received data from SSPxBUF,
clearing BF.
14. Steps 7-14 are the same for each received data
byte.
15. Communication is ended by either the slave
sending an ACK = 1 or the master sending a
Stop condition. If a Stop is sent and interrupt on
Stop detect is disabled, the slave will only know
by polling the P bit of the SSPxSTAT register.
 2014-2015 Microchip Technology Inc.
 2014-2015 Microchip Technology Inc.
SSPOV
BF
SSPxIF
S
1
A7
2
A6
3
A5
4
A4
5
A3
Receiving Address
6
A2
7
A1
8
9
ACK
1
D7
2
D6
4
5
D3
6
D2
7
D1
SSPxBUF is read
Cleared by software
3
D4
Receiving Data
D5
8
9
2
D6
First byte
of data is
available
in SSPxBUF
1
D0 ACK D7
4
5
D3
6
D2
7
D1
SSPOV set because
SSPxBUF is still full.
ACK is not sent.
Cleared by software
3
D4
Receiving Data
D5
8
D0
9
P
SSPxIF set on 9th
falling edge of
SCL
ACK = 1
FIGURE 32-14:
SCL
SDA
From Slave to Master
Bus Master sends
Stop condition
PIC16(L)F1764/5/8/9
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)
DS40001775B-page 401
DS40001775B-page 402
1
SCL S
CKP
SSPOV
BF
SSPxIF
A7
2
A6
3
A5
4
A4
5
A3
6
A2
7
A1
8
9
R/W = 0
ACK
SEN
2
D6
3
D5
4
D4
5
D3
6
D2
7
D1
8
D0
CKP is written to ‘1’ in software,
releasing SCL
SSPxBUF is read
Cleared by software
Clock is held low until CKP is set to ‘1’
1
D7
Receive Data
9
ACK
SEN
3
D5
4
D4
5
D3
First byte
of data is
available
in SSPxBUF
6
D2
7
D1
SSPOV set because
SSPxBUF is still full.
ACK is not sent.
Cleared by software
2
D6
CKP is written to ‘1’ in software,
releasing SCL
1
D7
Receive Data
8
D0
9
ACK
SCL is not held
low because
ACK= 1
SSPxIF set on 9th
falling edge of SCL
P
FIGURE 32-15:
SDA
Receive Address
Bus Master sends
Stop condition
PIC16(L)F1764/5/8/9
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)
 2014-2015 Microchip Technology Inc.
 2014-2015 Microchip Technology Inc.
P
S
ACKTIM
CKP
ACKDT
BF
SSPxIF
S
Receiving Address
1
3
5
6
7
8
ACK the received
byte
Slave software
clears ACKDT to
Address is
read from
SSBUF
If AHEN = 1:
SSPxIF is set
4
ACKTIM set by hardware
on 8th falling edge of SCL
When AHEN=1:
CKP is cleared by hardware
and SCL is stretched
2
A7 A6 A5 A4 A3 A2 A1
Receiving Data
9
2
3
4
5
6
7
ACKTIM cleared by
hardware in 9th
rising edge of SCL
When DHEN=1:
CKP is cleared by
hardware on 8th falling
edge of SCL
SSPxIF is set on
9th falling edge of
SCL, after ACK
1
8
ACK D7 D6 D5 D4 D3 D2 D1 D0
Received Data
1
2
4
5
6
ACKTIM set by hardware
on 8th falling edge of SCL
CKP set by software,
SCL is released
8
Slave software
sets ACKDT to
not ACK
7
Cleared by software
3
D7 D6 D5 D4 D3 D2 D1 D0
Data is read from SSPxBUF
9
ACK
9
P
No interrupt
after not ACK
from Slave
ACK=1
Master sends
Stop condition
FIGURE 32-16:
SCL
SDA
Master Releases SDA
to slave for ACK sequence
PIC16(L)F1764/5/8/9
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)
DS40001775B-page 403
DS40001775B-page 404
P
S
ACKTIM
CKP
ACKDT
BF
SSPxIF
S
Receiving Address
4
5
6 7
8
When AHEN = 1;
on the 8th falling edge
of SCL of an address
byte, CKP is cleared
Slave software clears
ACKDT to ACK
the received byte
Received
address is loaded into
SSPxBUF
2 3
ACKTIM is set by hardware
on 8th falling edge of SCL
1
A7 A6 A5 A4 A3 A2 A1
9
ACK
Receive Data
2 3
4
5
6 7
8
ACKTIM is cleared by hardware
on 9th rising edge of SCL
When DHEN = 1;
on the 8th falling edge
of SCL of a received
data byte, CKP is cleared
Received data is
available on SSPxBUF
Cleared by software
1
D7 D6 D5 D4 D3 D2 D1 D0
9
ACK
Receive Data
1
3 4
5
6 7
8
Set by software,
release SCL
Slave sends
not ACK
SSPxBUF can be
read any time before
next byte is loaded
2
D7 D6 D5 D4 D3 D2 D1 D0
9
ACK
CKP is not cleared
if not ACK
No interrupt after
if not ACK
from Slave
P
Master sends
Stop condition
FIGURE 32-17:
SCL
SDA
R/W = 0
Master releases
SDA to slave for ACK sequence
PIC16(L)F1764/5/8/9
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1)
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
32.5.3
SLAVE TRANSMISSION
32.5.3.2
7-Bit Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPxSTAT register is set. The received address is
loaded into the SSPxBUF register, and an ACK pulse is
sent by the slave on the ninth bit.
A master device can transmit a read request to a slave
and then clock data out of the slave. The list below
outlines what software for a slave will need to do to
accomplish a standard transmission. Figure 32-18 can
be used as a reference to this list.
Following the ACK, slave hardware clears the CKP bit
and the SCL pin is held low (see Section 32.5.6
“Clock Stretching” for more detail). By stretching the
clock, the master will be unable to assert another clock
pulse until the slave is done preparing the transmit
data.
1.
The transmit data must be loaded into the SSPxBUF
register which also loads the SSPSR register. Then,
the SCL pin should be released by setting the CKP bit
of the SSPxCON1 register. The eight data bits are
shifted out on the falling edge of the SCL input. This
ensures that the SDA signal is valid during the SCL
high time.
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. This ACK
value is copied to the ACKSTAT bit of the SSPxCON2
register. If ACKSTAT is set (not ACK), then the data
transfer is complete. In this case, when the not ACK is
latched by the slave, the slave goes Idle and waits for
another occurrence of the Start bit. If the SDA line was
low (ACK), the next transmit data must be loaded into
the SSPxBUF register. Again, the SCL pin must be
released by setting bit CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPxIF bit must be cleared by software and
the SSPxSTAT register is used to determine the status
of the byte. The SSPxIF bit is set on the falling edge of
the ninth clock pulse.
32.5.3.1
Slave Mode Bus Collision
A slave receives a read request and begins shifting
data out on the SDA line. If a bus collision is detected
and the SBCDE bit of the SSPxCON3 register is set,
the BCLIF bit of the PIR register is set. Once a bus collision is detected, the slave goes Idle and waits to be
addressed again. User software can use the BCLIF bit
to handle a slave bus collision.
 2014-2015 Microchip Technology Inc.
Master sends a Start condition on SDA and
SCL.
2. S bit of SSPxSTAT is set; SSPxIF is set if
interrupt on Start detect is enabled.
3. Matching address with R/W bit set is received by
the slave, setting SSPxIF bit.
4. Slave hardware generates an ACK and sets
SSPxIF.
5. SSPxIF bit is cleared by user.
6. Software reads the received address from
SSPxBUF, clearing BF.
7. R/W is set so CKP was automatically cleared
after the ACK.
8. The slave software loads the transmit data into
SSPxBUF.
9. CKP bit is set, releasing SCL, allowing the
master to clock the data out of the slave.
10. SSPxIF is set after the ACK response from the
master is loaded into the ACKSTAT register.
11. SSPxIF bit is cleared.
12. The slave software checks the ACKSTAT bit to
see if the master wants to clock out more data.
Note 1: If the master ACKs, the clock will be
stretched.
2: ACKSTAT is the only bit updated on the
rising edge of SCL (9th), rather than the
falling.
13. Steps 9-13 are repeated for each transmitted
byte.
14. If the master sends a not ACK, the clock is not
held, but SSPxIF is still set.
15. The master sends a Restart condition or a Stop.
16. The slave is no longer addressed.
DS40001775B-page 405
DS40001775B-page 406
P
S
D/A
R/W
ACKSTAT
CKP
BF
SSPxIF
S
1
2
5
6
7
8
Received address
is read from SSPxBUF
4
Indicates an address
has been received
R/W is copied from the
matching address byte
When R/W is set
SCL is always
held low after 9th SCL
falling edge
3
9
R/W = 1 Automatic
A7 A6 A5 A4 A3 A2 A1
ACK
Receiving Address
Automatic
2
3
4
5
Set by software
Data to transmit is
loaded into SSPxBUF
Cleared by software
1
6
7
8
9
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Transmitting Data
2
3
4
5
7
8
CKP is not
held for not
ACK
6
Masters not ACK
is copied to
ACKSTAT
BF is automatically
cleared after 8th falling
edge of SCL
1
D7 D6 D5 D4 D3 D2 D1 D0
Transmitting Data
9
ACK
P
FIGURE 32-18:
SCL
SDA
Master sends
Stop condition
PIC16(L)F1764/5/8/9
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0)
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
32.5.3.3
7-Bit Transmission with Address
Hold Enabled
Setting the AHEN bit of the SSPxCON3 register
enables additional clock stretching and interrupt
generation after the eighth falling edge of a received
matching address. Once a matching address has
been clocked in, CKP is cleared and the SSPxIF
interrupt is set.
Figure 32-19 displays a standard waveform of a 7-bit
address slave transmission with AHEN enabled.
1.
2.
3.
4.
5.
6.
7.
Bus starts Idle.
Master sends Start condition; the S bit of
SSPxSTAT is set; SSPxIF is set if interrupt on
Start detect is enabled.
Master sends matching address with R/W bit
set. After the eighth falling edge of the SCL line,
the CKP bit is cleared and the SSPxIF interrupt
is generated.
Slave software clears SSPxIF.
Slave software reads the ACKTIM bit of
SSPxCON3, and R/W and D/A of the
SSPxSTAT register to determine the source of
the interrupt.
Slave reads the address value from the
SSPxBUF register, clearing the BF bit.
Slave software decides from this information if it
wishes to ACK or not ACK and sets the ACKDT
bit of the SSPxCON2 register accordingly.
 2014-2015 Microchip Technology Inc.
8. Slave sets the CKP bit, releasing SCL.
9. Master clocks in the ACK value from the slave.
10. Slave hardware automatically clears the CKP bit
and sets SSPxIF after the ACK if the R/W bit is
set.
11. Slave software clears SSPxIF.
12. Slave loads value to transmit to the master into
SSPxBUF, setting the BF bit.
Note: SSPxBUF cannot be loaded until after the
ACK.
13. Slave sets the CKP bit, releasing the clock.
14. Master clocks out the data from the slave and
sends an ACK value on the 9th SCL pulse.
15. Slave hardware copies the ACK value into the
ACKSTAT bit of the SSPxCON2 register.
16. Steps 10-15 are repeated for each byte
transmitted to the master from the slave.
17. If the master sends a not ACK, the slave
releases the bus allowing the master to send a
Stop and end the communication.
Note: Master must send a not ACK on the last
byte to ensure that the slave releases the
SCL line to receive a Stop.
DS40001775B-page 407
DS40001775B-page 408
D/A
R/W
ACKTIM
CKP
ACKSTAT
ACKDT
BF
SSPxIF
4
5
6
7
8
ACKTIM is set on 8th falling
edge of SCL
When AHEN = 1;
CKP is cleared by hardware
after receiving matching
address.
Slave clears
ACKDT to ACK
address
Received address
is read from SSPxBUF
3
9
ACK
When R/W = 1;
CKP is always
cleared after ACK
R/W = 1
3
4
5
6
Cleared by software
2
Set by software,
releases SCL
Data to transmit is
loaded into SSPxBUF
1
7
8
9
Transmitting Data
Automatic
D7 D6 D5 D4 D3 D2 D1 D0 ACK
ACKTIM is cleared
on 9th rising edge of SCL
Automatic
Transmitting Data
1
3
4
5
6
7
after not ACK
CKP not cleared
Master’s ACK
response is copied
to SSPxSTAT
BF is automatically
cleared after 8th falling
edge of SCL
2
8
D7 D6 D5 D4 D3 D2 D1 D0
9
ACK
P
Master sends
Stop condition
FIGURE 32-19:
2
1
S
SCL
Receiving Address
A7 A6 A5 A4 A3 A2 A1
SDA
Master releases SDA
to slave for ACK sequence
PIC16(L)F1764/5/8/9
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
32.5.4
SLAVE MODE 10-BIT ADDRESS
RECEPTION
This section describes a standard sequence of events
for the MSSP module configured as an I2C slave in
10-Bit Addressing mode.
Figure 32-20 is used as a visual reference for this
description.
This is a step by step process of what must be done by
slave software to accomplish I2C communication.
1.
2.
3.
4.
5.
6.
7.
8.
Bus starts Idle.
Master sends Start condition. S bit of SSPxSTAT
is set; SSPxIF is set if interrupt on Start detect is
enabled.
Master sends matching high address with R/W
bit clear; UA bit of the SSPxSTAT register is set.
Slave sends ACK and SSPxIF is set.
Software clears the SSPxIF bit.
Software reads received address from
SSPxBUF, clearing the BF flag.
Slave loads low address into SSPxADD,
releasing SCL.
Master sends matching low address byte to the
slave; UA bit is set.
32.5.5
10-BIT ADDRESSING WITH
ADDRESS OR DATA HOLD
Reception using 10-Bit Addressing with AHEN or
DHEN set is the same as with 7-bit modes. The only
difference is the need to update the SSPxADD register
using the UA bit. All functionality, specifically when the
CKP bit is cleared and the SCL line is held low, are the
same. Figure 32-21 can be used as a reference of a
slave in 10-Bit Addressing with AHEN set.
Figure 32-22 shows a standard waveform for a slave
transmitter in 10-Bit Addressing mode.
Note: Updates to the SSPxADD register are not
allowed until after the ACK sequence.
9.
Slave sends ACK and SSPxIF is set.
Note: If the low address does not match, SSPxIF
and UA are still set so that the slave software can set SSPxADD back to the high
address. BF is not set because there is no
match. CKP is unaffected.
10. Slave clears SSPxIF.
11. Slave reads the received matching address
from SSPxBUF, clearing BF.
12. Slave loads high address into SSPxADD.
13. Master clocks a data byte to the slave and
clocks out the slave’s ACK on the 9th SCL
pulse; SSPxIF is set.
14. If SEN bit of SSPxCON2 is set, CKP is cleared
by hardware and the clock is stretched.
15. Slave clears SSPxIF.
16. Slave reads the received byte from SSPxBUF,
clearing BF.
17. If SEN is set, the slave sets CKP to release the
SCL.
18. Steps 13-17 repeat for each received byte.
19. Master sends Stop to end the transmission.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 409
DS40001775B-page 410
CKP
UA
BF
SSPxIF
S
1
1
2
1
5
6
7
0 A9 A8
8
Set by hardware
on 9th falling edge
4
1
When UA = 1;
SCL is held low
If address matches
SSPxADD it is loaded into
SSPxBUF
3
1
9
ACK
1
3
4
5
6
7
8
Software updates SSPxADD
and releases SCL
2
9
A7 A6 A5 A4 A3 A2 A1 A0 ACK
Receive Second Address Byte
1
3
4
5
6
7
8
9
1
3
4
5
6
7
Data is read
from SSPxBUF
SCL is held low
while CKP = 0
2
8
9
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Receive Data
Set by software,
When SEN = 1;
releasing SCL
CKP is cleared after
9th falling edge of received byte
Receive address is
read from SSPxBUF
Cleared by software
2
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Receive Data
P
FIGURE 32-20:
SCL
SDA
Receive First Address Byte
Master sends
Stop condition
PIC16(L)F1764/5/8/9
I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)
 2014-2015 Microchip Technology Inc.
 2014-2015 Microchip Technology Inc.
ACKTIM
CKP
UA
ACKDT
BF
SSPxIF
S
1
1
2
1
5
0
6
A9
7
A8
Set by hardware
on 9th falling edge
4
1
8
R/W = 0
ACKTIM is set by hardware
on 8th falling edge of SCL
If when AHEN = 1;
on the 8th falling edge
of SCL of an address
byte, CKP is cleared
Slave software clears
ACKDT to ACK
the received byte
3
1
Receive First Address Byte
9
ACK
UA
2
3
A5
4
A4
6
A2
7
A1
Update to SSPxADD is
not allowed until 9th
falling edge of SCL
SSPxBUF can be
read anytime before
the next received byte
5
A3
Receive Second Address Byte
A6
Cleared by software
1
A7
8
A0
9
ACK
UA
2
D6
3
D5
4
D4
6
D2
Set CKP with software
releases SCL
7
D1
Update of SSPxADD,
clears UA and releases
SCL
5
D3
Receive Data
Cleared by software
1
D7
8
9
2
Received data
is read from
SSPxBUF
1
D6 D5
Receive Data
D0 ACK D7
FIGURE 32-21:
SCL
SDA
PIC16(L)F1764/5/8/9
I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)
DS40001775B-page 411
DS40001775B-page 412
D/A
R/W
ACKSTAT
CKP
UA
BF
SSPxIF
S
2
4
5
6
7
Set by hardware
3
Indicates an address
has been received
UA indicates SSPxADD
must be updated
SSPxBUF loaded
with received address
1
8
9
Receiving Address R/W = 0
1 1 1 1 0 A9 A8
ACK
1
3
4
5
6
7 8
After SSPxADD is
updated, UA is cleared
and SCL is released
Cleared by software
2
9
A7 A6 A5 A4 A3 A2 A1 A0 ACK
Receiving Second Address Byte
1
4
5
6
7 8
Set by hardware
2 3
R/W is copied from the
matching address byte
When R/W = 1;
CKP is cleared on
9th falling edge of SCL
High address is loaded
back into SSPxADD
Received address is
read from SSPxBUF
Sr
1 1 1 1 0 A9 A8
Receive First Address Byte
9
ACK
2
3
4
5
6
7
8
Masters not ACK
is copied
Set by software
releases SCL
Data to transmit is
loaded into SSPxBUF
1
D7 D6 D5 D4 D3 D2 D1 D0
Transmitting Data Byte
9
P
Master sends
Stop condition
ACK = 1
Master sends
not ACK
FIGURE 32-22:
SCL
SDA
Master sends
Restart event
PIC16(L)F1764/5/8/9
I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
32.5.6
CLOCK STRETCHING
32.5.6.2
Clock stretching occurs when a device on the bus
holds the SCL line low, effectively pausing communication. The slave may stretch the clock to allow more
time to handle data or prepare a response for the
master device. A master device is not concerned with
stretching, as anytime it is active on the bus and not
transferring data, it is stretching. Any stretching done
by a slave is invisible to the master software and
handled by the hardware that generates SCL.
The CKP bit of the SSPxCON1 register is used to
control stretching in software. Any time the CKP bit is
cleared, the module will wait for the SCL line to go low
and then hold it. Setting CKP will release SCL and
allow more communication.
32.5.6.1
Normal Clock Stretching
Following an ACK, if the R/W bit of SSPxSTAT is set
and there is a read request, the slave hardware will
clear CKP. This allows the slave time to update
SSPxBUF with data to transfer to the master. If the
SEN bit of SSPxCON2 is set, the slave hardware will
always stretch the clock after the ACK sequence.
Once the slave is ready, CKP is set by software and
communication resumes.
Note 1: The BF bit has no effect on if the clock will
be stretched or not. This is different than
previous versions of the module that
would not stretch the clock, and cleared
CKP if SSPxBUF was read before the 9th
falling edge of SCL.
2: Previous versions of the module did not
stretch the clock for a transmission if
SSPxBUF was loaded before the 9th
falling edge of SCL; it is now always
cleared for read requests.
FIGURE 32-23:
10-Bit Addressing Mode
In 10-Bit Addressing mode when the UA bit is set, the
clock is always stretched. This is the only time the SCL
is stretched without CKP being cleared. SCL is
released immediately after a write to SSPxADD.
Note: Previous versions of the module did not
stretch the clock if the second address byte
did not match.
32.5.6.3
Byte NACKing
When the AHEN bit of SSPxCON3 is set, CKP is
cleared by hardware after the eighth falling edge of
SCL for a received matching address byte. When the
DHEN bit of SSPxCON3 is set, CKP is cleared after
the eighth falling edge of SCL for received data.
Stretching after the eighth falling edge of SCL allows
the slave to look at the received address or data and
decide if it wants to ACK the received data.
32.5.6.4
Clock Synchronization and
the CKP Bit
Any time the CKP bit is cleared, the module will wait
for the SCL line to go low and then hold it. However,
clearing the CKP bit will not assert the SCL output low
until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an
external I2C master device has already asserted the
SCL line. The SCL output will remain low until the CKP
bit is set and all other devices on the I2C bus have
released SCL. This ensures that a write to the CKP bit
will not violate the minimum high time requirement for
SCL (see Figure 32-23).
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
DX – 1
DX
SCL
CKP
Master Device
Asserts Clock
Master Device
Releases Clock
WR
SSPxCON1
 2014-2015 Microchip Technology Inc.
DS40001775B-page 413
PIC16(L)F1764/5/8/9
32.5.7
GENERAL CALL ADDRESS
SUPPORT
R/W bit clear, an interrupt is generated and slave software can read SSPxBUF and respond. Figure 32-24
shows a general call reception sequence.
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually determines which device will be the slave addressed by the
master device. The exception is the general call
address which can address all devices. When this
address is used, all devices should, in theory, respond
with an Acknowledge.
In 10-Bit Address mode, the UA bit will not be set on
the reception of the general call address. The slave
will prepare to receive the second byte as data, just as
it would in 7-bit mode.
If the AHEN bit of the SSPxCON3 register is set, just
as with any other address reception, the slave hardware will stretch the clock after the eighth falling edge
of SCL. The slave must then set its ACKDT value and
release the clock with communication progressing as it
would normally.
The general call address is a reserved address in the
I2C protocol, defined as address: 0x00. When the
GCEN bit of the SSPxCON2 register is set, the slave
module will automatically ACK the reception of this
address, regardless of the value stored in SSPxADD.
After the slave clocks in an address of all zeros, with the
FIGURE 32-24:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
Address is Compared to General Call Address
after ACK, Set Interrupt
R/W = 0
ACK D7
General Call Address
SDA
SCL
S
1
2
3
4
5
6
7
8
9
1
Receiving Data
ACK
D6
D5
D4
D3
D2
D1
D0
2
3
4
5
6
7
8
9
SSPxIF
BF (SSPxSTAT<0>)
Cleared by Software
GCEN (SSPxCON2<7>)
SSPxBUF is Read
‘1’
32.5.8
SSP MASK REGISTER
An MSSP Mask (SSPxMSK) register (Register 32-5) is
available in I2C Slave mode as a mask for the value
held in the SSPSR register during an address
comparison operation. A zero (‘0’) bit in the SSPxMSK
register has the effect of making the corresponding bit
of the received address a “don’t care”.
DS40001775B-page 414
This register is reset to all ‘1’s upon any Reset
condition, and therefore, has no effect on standard
SSP operation until written with a mask value.
The MSSP Mask register is active during:
• 7-Bit Address mode: Address compare of A<7:1>.
• 10-Bit Address mode: Address compare of
A<7:0> only. The MSSP mask has no effect
during the reception of the first (high) byte of the
address.
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
32.6
I2C Master Mode
32.6.1
I2C MASTER MODE OPERATION
Master mode is enabled by setting and clearing the
appropriate SSPM<3:0> bits in the SSPxCON1 register
and by setting the SSPEN bit. In Master mode, the SDA
and SCK pins must be configured as inputs. The MSSP
peripheral hardware will override the output driver TRIS
controls when necessary to drive the pins low.
The master device generates all of the serial clock
pulses, and the Start and Stop conditions. A transfer
is ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset or when the MSSP module is disabled.
Control of the I 2C bus may be taken when the P bit is
set or the bus is Idle.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted, eight bits at a time. After each byte is
transmitted, an Acknowledge bit is received. Start and
Stop conditions are output to indicate the beginning
and the end of a serial transfer.
In Firmware Controlled Master mode, user code
conducts all I 2C bus operations based on Start and
Stop bit condition detection. Start and Stop condition
detection is the only active circuitry in this mode. All
other communication is done by the user software
directly manipulating the SDA and SCL lines.
The following events will cause the SSP Interrupt Flag
bit, SSPxIF, to be set (SSP interrupt, if enabled):
•
•
•
•
•
Start condition detected
Stop condition detected
Data transfer byte transmitted/received
Acknowledge transmitted/received
Repeated Start generated
Note 1: The MSSP module, when configured in
I2C Master mode, does not allow queuing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPxBUF register
to initiate transmission before the Start
condition is complete. In this case, the
SSPxBUF will not be written to and the
WCOL bit will be set, indicating that a
write to the SSPxBUF did not occur
In Master Receive mode, the first byte transmitted
contains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDA, while SCL outputs the
serial clock. Serial data is received eight bits at a time.
After each byte is received, an Acknowledge bit is
transmitted. Start and Stop conditions indicate the
beginning and end of transmission.
A Baud Rate Generator is used to set the clock
frequency output on SCL. See Section 32.7 “Baud
Rate Generator” for more detail.
2: When in Master mode, Start/Stop
detection is masked, and an interrupt is
generated when the SEN/PEN bit is
cleared and the generation is complete.
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DS40001775B-page 415
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32.6.2
CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
releases the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the Baud Rate
Generator (BRG) is suspended from counting until the
FIGURE 32-25:
SDA
SCL pin is actually sampled high. When the SCL pin is
sampled high, the Baud Rate Generator is reloaded
with the contents of SSPxADD<7:0> and begins counting. This ensures that the SCL high time will always be
at least one BRG rollover count in the event that the
clock is held low by an external device (Figure 32-25).
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
DX – 1
DX
SCL Allowed to Transition High
SCL Deasserted but Slave Holds
SCL Low (clock arbitration)
SCL
BRG Decrements on
Q2 and Q4 Cycles
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCL is Sampled High, Reload Takes
Place and BRG Starts its Count
BRG
Reload
32.6.3
WCOL STATUS FLAG
If the user writes the SSPxBUF when a Start, Restart,
Stop, receive or transmit sequence is in progress, the
WCOL is set and the contents of the buffer are
unchanged (the write does not occur). Any time the
WCOL bit is set, it indicates that an action on SSPxBUF
was attempted while the module was not Idle.
DS40001775B-page 416
Note:
Because queuing of events is not allowed,
writing to the lower five bits of SSPxCON2
is disabled until the Start condition is
complete.
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PIC16(L)F1764/5/8/9
32.6.4
I2C MASTER MODE START
CONDITION TIMING
To initiate a Start condition (Figure 32-26), the user
sets the Start Enable bit, SEN, of the SSPxCON2 register. If the SDA and SCL pins are sampled high, the
Baud Rate Generator is reloaded with the contents of
SSPxADD<7:0> and starts its count. If SCL and SDA
are both sampled high when the Baud Rate Generator
times out (TBRG), the SDA pin is driven low. The action
of the SDA being driven low while SCL is high is the
Start condition and causes the S bit of the SSPxSTAT
register to be set. Following this, the Baud Rate
Generator is reloaded with the contents of
SSPxADD<7:0> and resumes its count. When the
Baud Rate Generator times out (TBRG), the SEN bit of
the SSPxCON2 register will be automatically cleared
FIGURE 32-26:
by hardware; the Baud Rate Generator is suspended,
leaving the SDA line held low and the Start condition is
complete.
Note 1: If, at the beginning of the Start condition,
the SDA and SCL pins are already
sampled low, or if during the Start condition, the SCL line is sampled low before
the SDA line is driven low, a bus collision
occurs. The Bus Collision Interrupt Flag,
BCLIF, is set, the Start condition is
aborted and the I2C module is reset into
its Idle state.
2: The Philips I2C specification states that a
bus collision cannot occur on a Start.
FIRST START BIT TIMING
Write to SEN bit Occurs Here
Set S bit (SSPxSTAT<3>)
At Completion of Start bit,
Hardware Clears SEN bit
and Sets SSPxIF bit
SDA = 1,
SCL = 1
TBRG
TBRG
Write to SSPxBUF Occurs Here
SDA
1st bit
2nd bit
TBRG
SCL
S
 2014-2015 Microchip Technology Inc.
TBRG
DS40001775B-page 417
PIC16(L)F1764/5/8/9
32.6.5
I2C MASTER MODE REPEATED
START CONDITION TIMING
cally cleared and the Baud Rate Generator will not be
reloaded, leaving the SDA pin held low. As soon as a
Start condition is detected on the SDA and SCL pins,
the S bit of the SSPxSTAT register will be set. The
SSPxIF bit will not be set until the Baud Rate Generator
has timed out.
A Repeated Start condition (Figure 32-27) occurs when
the RSEN bit of the SSPxCON2 register is
programmed high and the master state machine is no
longer active. When the RSEN bit is set, the SCL pin is
asserted low. When the SCL pin is sampled low, the
Baud Rate Generator is loaded and begins counting.
The SDA pin is released (brought high) for one Baud
Rate Generator count (TBRG). When the Baud Rate
Generator times out, if SDA is sampled high, the SCL
pin will be deasserted (brought high). When SCL is
sampled high, the Baud Rate Generator is reloaded
and begins counting. SDA and SCL must be sampled
high for one TBRG. This action is then followed by
assertion of the SDA pin (SDA = 0) for one TBRG while
SCL is high. SCL is asserted low. Following this, the
RSEN bit of the SSPxCON2 register will be automati-
FIGURE 32-27:
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL
goes from low-to-high.
• SCL goes low before SDA is
asserted low. This may indicate
that another master is attempting
to transmit a data ‘1’.
REPEATED START CONDITION WAVEFORM
S bit Set by Hardware
Write to SSPxCON2
Occurs Here
SDA = 1,
SCL (no change)
At Completion of Start bit,
Hardware Clears RSEN bit
and Sets SSPxIF
SDA = 1,
SCL = 1
TBRG
TBRG
TBRG
1st bit
SDA
Write to SSPxBUF Occurs Here
TBRG
SCL
Sr
TBRG
Repeated Start
DS40001775B-page 418
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PIC16(L)F1764/5/8/9
32.6.6
I2C MASTER MODE
TRANSMISSION
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPxBUF register. This action will
set the Buffer Full flag bit, BF, and allow the Baud Rate
Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted. SCL is held low for one Baud Rate Generator
rollover count (TBRG). Data should be valid before SCL
is released high. When the SCL pin is released high, it
is held that way for TBRG. The data on the SDA pin
must remain stable for that duration and some hold
time after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA.
This allows the slave device being addressed to
respond with an ACK bit during the ninth bit time if an
address match occurred or if data was received properly. The status of ACK is written into the ACKSTAT bit
on the rising edge of the ninth clock. If the master
receives an Acknowledge, the Acknowledge status bit,
ACKSTAT, is cleared. If not, the bit is set. After the ninth
clock, the SSPxIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPxBUF, leaving SCL low and SDA
unchanged (Figure 32-28).
After the write to the SSPxBUF, each bit of the address
will be shifted out on the falling edge of SCL until all
seven address bits and the R/W bit are completed. On
the falling edge of the eighth clock, the master will
release the SDA pin, allowing the slave to respond with
an Acknowledge. On the falling edge of the ninth clock,
the master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT status bit of the SSPxCON2
register. Following the falling edge of the ninth clock
transmission of the address, the SSPxIF is set, the BF
flag is cleared and the Baud Rate Generator is turned
off until another write to the SSPxBUF takes place,
holding SCL low and allowing SDA to float.
32.6.6.1
BF Status Flag
32.6.6.3
ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit of the SSPxCON2
register is cleared when the slave has sent an
Acknowledge (ACK = 0) and is set when the slave does
not Acknowledge (ACK = 1). A slave sends an
Acknowledge when it has recognized its address
(including a general call) or when the slave has
properly received its data.
32.6.6.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Typical Transmit Sequence:
The user generates a Start condition by setting
the SEN bit of the SSPxCON2 register.
SSPxIF is set by hardware on completion of the
Start.
SSPxIF is cleared by software.
The MSSP module will wait the required start
time before any other operation takes place.
The user loads the SSPxBUF with the slave
address to transmit.
Address is shifted out the SDA pin until all eight
bits are transmitted. Transmission begins as
soon as SSPxBUF is written to.
The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPxCON2 register.
The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the
SSPxIF bit.
The user loads the SSPxBUF with eight bits of
data.
Data is shifted out the SDA pin until all eight bits
are transmitted.
The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPxCON2 register.
Steps 8-11 are repeated for all transmitted data
bytes.
The user generates a Stop or Restart condition
by setting the PEN or RSEN bits of the
SSPxCON2 register. Interrupt is generated once
the Stop/Restart condition is complete.
In Transmit mode, the BF bit of the SSPxSTAT register
is set when the CPU writes to SSPxBUF and is cleared
when all eight bits are shifted out.
32.6.6.2
WCOL Status Flag
If the user writes the SSPxBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write does not occur).
WCOL must be cleared by software before the next
transmission.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 419
DS40001775B-page 420
S
R/W
PEN
SEN
BF (SSPxSTAT<0>)
SSPxIF
SCL
SDA
A6
A5
A4
A3
A2
A1
3
4
5
Cleared by software
2
6
7
8
9
After Start condition, SEN cleared by hardware
SSPxBUF written
1
D7
1
SCL held low
while CPU
responds to SSPxIF
ACK = 0
R/W = 0
SSPxBUF written with 7-bit address and R/W
start transmit
A7
Transmit Address to Slave
3
D5
4
D4
5
D3
6
D2
7
D1
8
D0
SSPxBUF is written by software
Cleared by software service routine
from SSP interrupt
2
D6
Transmitting Data or Second Half
of 10-bit Address
P
Cleared by software
9
ACK
From slave, clear ACKSTAT bit SSPxCON2<6>
ACKSTAT in
SSPxCON2 = 1
FIGURE 32-28:
SEN = 0
Write SSPxCON2<0> SEN = 1
Start condition begins
PIC16(L)F1764/5/8/9
I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
32.6.7
I2C MASTER MODE RECEPTION
Master mode reception (Figure 32-29) is enabled by
programming the Receive Enable bit, RCEN bit of the
SSPxCON2 register.
Note:
The MSSP module must be in an Idle
state before the RCEN bit is set or the
RCEN bit will be disregarded.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes
(high-to-low/low-to-high), and data is shifted into the
SSPSR. After the falling edge of the eighth clock, the
receive enable flag is automatically cleared, the
contents of the SSPSR are loaded into the SSPxBUF,
the BF flag bit is set, the SSPxIF flag bit is set and the
Baud Rate Generator is suspended from counting,
holding SCL low. The MSSP is now in Idle state
awaiting the next command. When the buffer is read by
the CPU, the BF flag bit is automatically cleared. The
user can then send an Acknowledge bit at the end of
reception by setting the Acknowledge Sequence
Enable bit, ACKEN, of the SSPxCON2 register.
32.6.7.1
BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPxBUF from SSPSR. It is
cleared when the SSPxBUF register is read.
32.6.7.2
SSPOV Status Flag
32.6.7.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
In receive operation, the SSPOV bit is set when eight
bits are received into the SSPSR and the BF flag bit is
already set from a previous reception.
13.
14.
32.6.7.3
15.
WCOL Status Flag
If the user writes the SSPxBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write does not occur).
 2014-2015 Microchip Technology Inc.
Typical Receive Sequence:
The user generates a Start condition by setting
the SEN bit of the SSPxCON2 register.
SSPxIF is set by hardware on completion of the
Start.
SSPxIF is cleared by software.
User writes SSPxBUF with the slave address to
transmit and the R/W bit set.
Address is shifted out the SDA pin until all eight
bits are transmitted. Transmission begins as
soon as SSPxBUF is written to.
The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPxCON2 register.
The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the
SSPxIF bit.
User sets the RCEN bit of the SSPxCON2 register and the master clocks in a byte from the slave.
After the eighth falling edge of SCL, SSPxIF and
BF are set.
Master clears SSPxIF and reads the received
byte from SSPxBUF, clears BF.
Master sets ACK value sent to slave in ACKDT
bit of the SSPxCON2 register and initiates the
ACK by setting the ACKEN bit.
Master’s ACK is clocked out to the slave and
SSPxIF is set.
User clears SSPxIF.
Steps 8-13 are repeated for each received byte
from the slave.
Master sends a not ACK or Stop to end
communication.
DS40001775B-page 421
DS40001775B-page 422
RCEN
ACKEN
SSPOV
BF
(SSPxSTAT<0>)
SDA = 0, SCL = 1
while CPU
responds to SSPxIF
SSPxIF
1
SCL
S
A7
2
4
5
6
Cleared by software
3
A6 A5 A4 A3 A2
Transmit Address to Slave
7
8
9
ACK
Receiving Data from Slave
2
3
5
6
7
8
D0
9
ACK
Receiving Data from Slave
2
3
4
RCEN cleared
automatically
5
6
7
Cleared by software
Set SSPxIF interrupt
at end of Acknowledge
sequence
Data shifted in on falling edge of CLK
1
ACK from Master
SDA = ACKDT = 0
Cleared in
software
Set SSPxIF at end
of receive
9
ACK is not sent
ACK
RCEN cleared
automatically
P
Set SSPxIF interrupt
at end of Acknowledge sequence
Bus master
terminates
transfer
Set P bit
(SSPxSTAT<4>)
and SSPxIF
PEN bit = 1
written here
SSPOV is set because
SSPxBUF is still full
8
D0
RCEN cleared
automatically
Set ACKEN, start Acknowledge sequence
SDA = ACKDT = 1
D7 D6 D5 D4 D3 D2 D1
Last bit is shifted into SSPSR and
contents are unloaded into SSPxBUF
Cleared by software
Set SSPxIF interrupt
at end of receive
4
Cleared by software
1
D7 D6 D5 D4 D3 D2 D1
Master configured as a receiver
by programming SSPxCON2<3> (RCEN = 1)
A1 R/W
RCEN = 1, start
next receive
ACK from Master
SDA = ACKDT = 0
FIGURE 32-29:
SDA
Master configured as a receiver
by programming SSPxCON2<3> (RCEN = 1)
SEN = 0
Write to SSPxBUF occurs here,
RCEN cleared
ACK from Slave
automatically
start XMIT
Write to SSPxCON2<0>(SEN = 1),
begin Start condition
Write to SSPxCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPxCON2<5>) = 0
PIC16(L)F1764/5/8/9
I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
32.6.8
ACKNOWLEDGE SEQUENCE
TIMING
32.6.9
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN, of the SSPxCON2 register. At the end of a
receive/transmit, the SCL line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDA line low. When the SDA
line is sampled low, the Baud Rate Generator is
reloaded and counts down to ‘0’. When the Baud Rate
Generator times out, the SCL pin will be brought high
and one TBRG (Baud Rate Generator rollover count)
later, the SDA pin will be deasserted. When the SDA
pin is sampled high while SCL is high, the P bit of the
SSPxSTAT register is set. A TBRG later, the PEN bit is
cleared and the SSPxIF bit is set (Figure 32-31).
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN, of the
SSPxCON2 register. When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to
generate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate Generator then counts for one rollover period (TBRG) and the
SCL pin is deasserted (pulled high). When the SCL pin is
sampled high (clock arbitration), the Baud Rate Generator
counts for TBRG. The SCL pin is then pulled low. Following
this, the ACKEN bit is automatically cleared, the Baud
Rate Generator is turned off and the MSSP module then
goes into Idle mode (Figure 32-30).
32.6.8.1
32.6.9.1
WCOL Status Flag
If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write does
not occur).
WCOL Status Flag
If the user writes the SSPxBUF when an Acknowledge
sequence is in progress, then the WCOL bit is set and
the contents of the buffer are unchanged (the write
does not occur).
FIGURE 32-30:
STOP CONDITION TIMING
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge Sequence Starts Here,
Write to SSPxCON2,
ACKEN = 1, ACKDT = 0
ACKEN Automatically Cleared
TBRG
TBRG
SDA
D0
SCL
8
ACK
9
SSPxIF
SSPxIF Set at
the End of Receive
Cleared in
Software
Cleared in
Software
SSPxIF Set at the End
of Acknowledge Sequence
Note: TBRG = one Baud Rate Generator period.
FIGURE 32-31:
STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL = 1 for TBRG, Followed by SDA = 1 for TBRG
after SDA Sampled High, P bit (SSPxSTAT<4>) is Set
Write to SSPxCON2,
Set PEN
Falling Edge of
9th Clock
TBRG
SCL
SDA
PEN bit (SSPxCON2<2>) is Cleared by
Hardware and the SSPxIF bit is Set
ACK
P
TBRG
TBRG
TBRG
SCL brought High after TBRG
SDA Asserted Low before Rising Edge of Clock
to Setup Stop Condition
Note: TBRG = one Baud Rate Generator period.
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32.6.10
SLEEP OPERATION
32.6.13
2
While in Sleep mode, the I C slave module can receive
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
32.6.11
EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
32.6.12
MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I 2C bus may
be taken when the P bit of the SSPxSTAT register is
set, or the bus is Idle, with both the S and P bits clear.
When the bus is busy, enabling the SSP interrupt will
generate the interrupt when the Stop condition occurs.
In multi-master operation, the SDA line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed by
hardware with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
•
•
•
•
•
Address Transfer
Data Transfer
A Start Condition
A Repeated Start Condition
An Acknowledge Condition
MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA, by letting SDA float high and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF, and reset the
I2C port to its Idle state (Figure 32-32).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPxBUF can be written to. When the user services
the bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the
condition is aborted, the SDA and SCL lines are deasserted and the respective control bits in the SSPxCON2
register are cleared. When the user services the bus
collision Interrupt Service Routine and if the I2C bus is
free, the user can resume communication by asserting a
Start condition.
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPxIF bit will be set.
A write to the SSPxBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can
be taken when the P bit is set in the SSPxSTAT register,
or the bus is Idle and the S and P bits are cleared.
FIGURE 32-32:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Data Changes
while SCL = 0
SDA Line Pulled Low
by Another Source
SDA Released
by Master
Sample SDA, while SCL is High,
Data does not Match what is Driven
by the Master;
Bus Collision has Occurred
SDA
SCL
Set Bus Collision
Interrupt (BCLIF)
BCLIF
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32.6.13.1
Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a)
b)
SDA or SCL is sampled low at the beginning of
the Start condition (Figure 32-33).
SCL is sampled low before SDA is asserted low
(Figure 32-34).
During a Start condition, both the SDA and the SCL
pins are monitored.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 32-35). If, however, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to zero; if the SCL pin is sampled as ‘0’
during this time, a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
Note:
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• The Start condition is aborted,
• The BCLIF flag is set and
• The MSSP module is reset to its Idle state
(Figure 32-33).
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded and counts down. If the
SCL pin is sampled low while SDA is high, a bus
collision occurs because it is assumed that another
master is attempting to drive a data ‘1’ during the Start
condition.
FIGURE 32-33:
The reason that bus collision is not a
factor during a Start condition is that no
two bus masters can assert a Start condition at the exact same time. Therefore,
one master will always assert SDA before
the other. This condition does not cause a
bus collision because the two masters
must be allowed to arbitrate the first
address following the Start condition. If the
address is the same, arbitration must be
allowed to continue into the data portion,
Repeated Start or Stop conditions.
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes Low before the SEN bit is Set,
Set BCLIF;
S bit and SSPxIF Set because
SDA = 0, SCL = 1
SDA
SCL
Set SEN, Enable Start
Condition if SDA = 1, SCL = 1
SEN Cleared Automatically because of Bus Collision
MSSP module Reset into Idle State
SEN
BCLIF
SDA Sampled Low Before
Start Condition, Set BCLIF;
S bit and SSPxIF Set because
SDA = 0, SCL = 1
SSPxIF and BCLIF are
Cleared by Software
S
SSPxIF
SSPxIF and BCLIF are
Cleared by Software
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FIGURE 32-34:
BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
SCL
Set SEN, Enable Start
Sequence if SDA = 1, SCL = 1
SCL = 0 before SDA = 0,
Bus Collision Occurs; Set BCLIF
SEN
SCL = 0 before BRG Time-out,
Bus Collision Occurs; Set BCLIF
BCLIF
Interrupt Cleared
by Software
S
‘0’
‘0’
SSPxIF ‘0’
‘0’
FIGURE 32-35:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Less than TBRG
SDA
Set SSPxIF
TBRG
SDA Pulled Low by Other Master,
Reset BRG and Assert SDA
SCL
S
SCL Pulled Low after BRG
Time-out
SEN
Set SEN, Enable Start
Sequence if SDA = 1, SCL = 1
‘0’
BCLIF
S
SSPxIF
SDA = 0, SCL = 1,
Set SSPxIF
DS40001775B-page 426
Interrupts Cleared
by Software
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
32.6.13.2
Bus Collision During a Repeated
Start Condition
During a Repeated Start condition, a bus collision
occurs if:
a)
b)
A low level is sampled on SDA when SCL goes
from low level to high level (Case 1).
SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’ (Case 2).
When the user releases SDA and the pin is allowed to
float high, the BRG is loaded with SSPxADD and
counts down to zero. The SCL pin is then deasserted
and when sampled high, the SDA pin is sampled.
FIGURE 32-36:
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, Figure 32-36).
If SDA is sampled high, the BRG is reloaded and begins
counting. If SDA goes from high-to-low before the BRG
times out, no bus collision occurs because no two
masters can assert SDA at exactly the same time.
If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated Start condition,
see Figure 32-37.
If, at the end of the BRG time-out, both SCL and SDA are
still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is complete.
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes High;
if SDA = 0, Set BCLIF and Release SDA and SCL
RSEN
BCLIF
Cleared by Software
S
‘0’
SSPxIF
‘0’
FIGURE 32-37:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
BCLIF
SCL goes Low before SDA,
Set BCLIF; Release SDA and SCL
Interrupt Cleared
by Software
RSEN
S
‘0’
SSPxIF
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32.6.13.3
Bus Collision During a Stop
Condition
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPxADD and
counts down to zero. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 32-38). If the SCL pin is sampled
low before SDA is allowed to float high, a bus collision
occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 32-39).
Bus collision occurs during a Stop condition if:
a)
b)
After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out (Case 1).
After the SCL pin is deasserted, SCL is sampled
low before SDA goes high (Case 2).
FIGURE 32-38:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
TBRG
TBRG
SDA Sampled
Low after TBRG,
Set BCLIF
TBRG
SDA
SDA Asserted Low
SCL
PEN
BCLIF
P
‘0’
SSPxIF
‘0’
FIGURE 32-39:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
Assert SDA
SCL goes Low before SDA goes High,
Set BCLIF
SCL
PEN
BCLIF
P
‘0’
SSPxIF
‘0’
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TABLE 32-3:
Name
ANSELA
SUMMARY OF REGISTERS ASSOCIATED WITH I2C OPERATION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
—
—
—
ANSA4
—
ANSELB(1)
ANSB<7:4>
ANSC<7:6>(1)
ANSELC
INTCON
Bit 2
Bit 1
Bit 0
Reset
Values on
Page:
—
148
IOCIF
104
ANSA<2:0>
—
—
—
—
—
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
142
ANSC<3:0>
153
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
105
PIE2
OSFIE
C2IE
C1IE
—
BCL1IE
C4IE(1)
C3IE(1)
CCP2IE(1)
106
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
108
PIR2
OSFIF
C2IF
C1IF
—
BCL1IF
C4IF(1)
C3IF(1)
CCP2IF(1)
109
RxyPPS
—
—
—
RxyPPS<4:0>
159
SSPCLKPPS
—
—
—
SSPCLKPPS<4:0>
159, 161
SSPDATPPS
—
—
—
SSPDATPPS<4:0>
159, 161
SSPSSPPS
—
—
—
SSPSSPPS<4:0>
159, 161
SSP1ADD
SSP1BUF
ADD<7:0>
437
Synchronous Serial Port Receive Buffer/Transmit Register
387*
SSP1CON1
WCOL
SSPOV
SSPEN
CKP
SSP1CON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
435
SSP1CON3
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
436
SSP1MSK
SSP1STAT
TRISA
SMP
CKE
—
—
D/A
TRISB<7:4>
TRISC<7:6>(1)
Legend:
*
Note 1:
2:
433
MSK<7:0>
TRISB(1)
TRISC
SSPM<3:0>
P
TRISA<5:4>
437
S
R/W
—(2)
—
UA
BF
TRISA<2:0>
—
—
431
141
—
TRISC<5:0>
147
152
— = unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module in I2C mode.
Page provides register information.
PIC16(L)F1768/9 only.
Unimplemented, read as ‘1’.
 2014-2015 Microchip Technology Inc.
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32.7
BAUD RATE GENERATOR
The MSSP module has a Baud Rate Generator available for clock generation in both I2C and SPI Master
modes. The Baud Rate Generator (BRG) reload value
is placed in the SSPxADD register (Register 32-6).
When a write occurs to SSPxBUF, the Baud Rate
Generator will automatically begin counting down.
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will
remain in its last state.
module clock line. The logic dictating when the reload
signal is asserted depends on the mode the MSSP is
being operated in.
Table 32-4 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPxADD.
EQUATION 32-1:
FOSC
FCLOCK = ------------------------------------------------ SSPxADD + 1   4 
An internal signal “Reload” in Figure 32-40 triggers the
value from SSPxADD to be loaded into the BRG
counter. This occurs twice for each oscillation of the
FIGURE 32-40:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM<3:0>
SSPM<3:0>
SCL
Reload
Control
SSPCLK
SSPxADD<7:0>
Reload
BRG Down Counter
FOSC/2
Note: Values of 0x00, 0x01 and 0x02 are not valid for SSPxADD when used as a Baud Rate Generator for I2C; this
is an implementation limitation.
TABLE 32-4:
Note:
MSSP CLOCK RATE w/BRG
FOSC
FCY
BRG Value
FCLOCK
(2 Rollovers of BRG)
32 MHz
8 MHz
13h
400 kHz
32 MHz
8 MHz
19h
308 kHz
32 MHz
8 MHz
4Fh
100 kHz
16 MHz
4 MHz
09h
400 kHz
16 MHz
4 MHz
0Ch
308 kHz
16 MHz
4 MHz
27h
100 kHz
4 MHz
1 MHz
09h
100 kHz
Refer to the I/O port electrical specifications in Table 36-4 to ensure the system is designed to support IOL
requirements.
DS40001775B-page 430
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32.8
Register Definitions: MSSP Control
REGISTER 32-1:
SSP1STAT: MSSP STATUS REGISTER
R/W-0/0
R/W-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
SMP
CKE
D/A
P
S
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
SMP: SPI Data Input Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
In I2 C Master or Slave mode:
1 = Slew rate control is disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control is enabled for High-Speed mode (400 kHz)
bit 6
CKE: SPI Clock Edge Select bit (SPI mode only)
In SPI Master or Slave mode:
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
In I2 C mode only:
1 = Enables input logic so that thresholds are compliant with SMBus specification
0 = Disables SMBus specific inputs
bit 5
D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4
P: Stop bit (I2C mode only; this bit is cleared when the MSSP module is disabled, SSPEN is cleared)
1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)
0 = Stop bit was not detected last
bit 3
S: Start bit (I2C mode only; this bit is cleared when the MSSP module is disabled, SSPEN is cleared)
1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0 = Start bit was not detected last
bit 2
R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next Start bit, Stop bit or not ACK bit.
In I2 C Slave mode:
1 = Read
0 = Write
In I2 C Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode.
bit 1
UA: Update Address bit (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPxADD register
0 = Address does not need to be updated
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REGISTER 32-1:
bit 0
SSP1STAT: MSSP STATUS REGISTER (CONTINUED)
BF: Buffer Full Status bit
Receive (SPI and I2 C modes):
1 = Receive is complete, SSPxBUF is full
0 = Receive is not complete, SSPxBUF is empty
Transmit (I2 C mode only):
1 = Data transmit is in progress (does not include the ACK and Stop bits), SSPxBUF is full
0 = Data transmit is complete (does not include the ACK and Stop bits), SSPxBUF is empty
DS40001775B-page 432
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REGISTER 32-2:
SSP1CON1: MSSP CONTROL REGISTER 1
R/C/HS-0/0
R/C/HS-0/0
R/W-0/0
R/W-0/0
WCOL
SSPOV(1)
SSPEN
CKP
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
SSPM<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
HS = Hardware Settable bit
C = Clearable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
WCOL: Write Collision Detect bit
Master mode:
1 = A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a
transmission to be started
0 = No collision
Slave mode:
1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0 = No collision
bit 6
SSPOV: Receive Overflow Indicator bit(1)
In SPI mode:
1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must
read the SSPxBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF
register (must be cleared in software).
0 = No overflow
In I2 C mode:
1 = A byte is received while the SSPxBUF register is still holding the previous byte. SSPOV is a “don’t
care” in Transmit mode (must be cleared in software).
0 = No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output.
In SPI mode:
1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2)
0 = Disables serial port and configures these pins as I/O port pins
In I2 C mode:
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3)
0 = Disables serial port and configures these pins as I/O port pins
Note 1:
2:
3:
4:
5:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPxBUF register.
When enabled, these pins must be properly configured as input or output. Use SSPSSPPS, SSPCLKPPS,
SSPDATPPS and RxyPPS to select the pins.
When enabled, the SDA and SCL pins must be configured as inputs. Use SSPCLKPPS, SSPDATPPS
and RxyPPS to select the pins.
SSPxADD values of 0, 1 or 2 are not supported for I2C mode.
SSPxADD value of 0 is not supported; use SSPM<3:0> = 0000 instead.
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REGISTER 32-2:
SSP1CON1: MSSP CONTROL REGISTER 1 (CONTINUED)
bit 4
CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I2 C Slave mode:
SCL release control.
1 = Enables clock
0 = Holds clock low (clock stretch), used to ensure data setup time
In I2 C Master mode:
Unused in this mode.
bit 3-0
SSPM<3:0>: Synchronous Serial Port Mode Select bits
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1101 = Reserved
1100 = Reserved
1011 = I2C Firmware Controlled Master mode (slave Idle)
1010 = SPI Master mode, clock = FOSC/(4 * (SSP1ADD + 1))(5)
1001 = Reserved
1000 = I2C Master mode, clock = FOSC/(4 * (SSP1ADD + 1))(4)
0111 = I2C Slave mode, 10-bit address
0110 = I2C Slave mode, 7-bit address
0101 = SPI Slave mode, clock = SCK pin, SS pin control is disabled, SS can be used as I/O pin
0100 = SPI Slave mode, clock = SCK pin, SS pin control is enabled
0011 = SPI Master mode, clock = T2_match/2
0010 = SPI Master mode, clock = FOSC/64
0001 = SPI Master mode, clock = FOSC/16
0000 = SPI Master mode, clock = FOSC/4
Note 1:
2:
3:
4:
5:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPxBUF register.
When enabled, these pins must be properly configured as input or output. Use SSPSSPPS, SSPCLKPPS,
SSPDATPPS and RxyPPS to select the pins.
When enabled, the SDA and SCL pins must be configured as inputs. Use SSPCLKPPS, SSPDATPPS
and RxyPPS to select the pins.
SSPxADD values of 0, 1 or 2 are not supported for I2C mode.
SSPxADD value of 0 is not supported; use SSPM<3:0> = 0000 instead.
DS40001775B-page 434
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SSP1CON2: MSSP CONTROL REGISTER 2(1)
REGISTER 32-3:
R/W-0/0
R-0/0
R/W-0/0
R/S/HS-0/0
R/S/HS-0/0
R/S/HS-0/0
R/S/HS-0/0
R/W/HS-0/0
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
HS = Hardware Settable bit
S = Settable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
GCEN: General Call Enable bit (in I2C Slave mode only)
1 = Enables interrupt when a general call address (0x00 or 00h) is received in the SSPSR
0 = General call address disabled
bit 6
ACKSTAT: Acknowledge Status bit (in I2C mode only)
1 = Acknowledge was not received
0 = Acknowledge was received
bit 5
ACKDT: Acknowledge Data bit (in I2C mode only)
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive.
1 = Not Acknowledge
0 = Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit;
automatically cleared by hardware
0 = Acknowledge sequence is Idle
bit 3
RCEN: Receive Enable bit (in I2C Master mode only)
1 = Enables Receive mode for I2C
0 = Receive is Idle
bit 2
PEN: Stop Condition Enable bit (in I2C Master mode only)
SCKMSSP Release Control:
1 = Initiates Stop condition on SDA and SCL pins; automatically cleared by hardware
0 = Stop condition is Idle
bit 1
RSEN: Repeated Start Condition Enable bit (in I2C Master mode only)
1 = Initiates Repeated Start condition on SDA and SCL pins; automatically cleared by hardware
0 = Repeated Start condition is Idle
bit 0
SEN: Start Condition Enable/Stretch Enable bit
In Master mode:
1 = Initiates Start condition on SDA and SCL pins; automatically cleared by hardware
0 = Start condition is Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in Idle mode, this bit may not be set
(no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).
 2014-2015 Microchip Technology Inc.
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REGISTER 32-4:
SSP1CON3: MSSP CONTROL REGISTER 3
R-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ACKTIM(3)
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
ACKTIM: Acknowledge Time Status bit (I2C mode only)(3)
1 = Indicates the I2C bus is in an Acknowledge sequence, set on eighth falling edge of SCL clock
0 = Not an Acknowledge sequence, cleared on 9th rising edge of SCL clock
bit 6
PCIE: Stop Condition Interrupt Enable bit (I2C mode only)
1 = Enables interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled(2)
bit 5
SCIE: Start Condition Interrupt Enable bit (I2C mode only)
1 = Enables interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled(2)
bit 4
BOEN: Buffer Overwrite Enable bit
In SPI Slave mode:(1)
1 = SSPxBUF updates every time that a new data byte is shifted in, ignoring the BF bit
0 = If new byte is received with BF bit of the SSPxSTAT register already set, the SSPOV bit of the
SSPxCON1 register is set and the buffer is not updated
2
In I C Master mode and SPI Master mode:
This bit is ignored.
In I2 C Slave mode:
1 = SSPxBUF is updated and ACK is generated for a received address/data byte, ignoring the state
of the SSPOV bit only if the BF bit = 0
0 = SSPxBUF is only updated when SSPOV is clear
bit 3
SDAHT: SDA Hold Time Selection bit (I2C mode only)
1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL
0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL
bit 2
SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
If, on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the
BCL1IF bit of the PIR2 register is set and the bus goes Idle
1 = Enables slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
bit 1
AHEN: Address Hold Enable bit (I2C Slave mode only)
1 = Following the eighth falling edge of SCL for a matching received address byte; CKP bit of the
SSPxCON1 register will be cleared and the SCL will be held low
0 = Address holding is disabled
bit 0
DHEN: Data Hold Enable bit (I2C Slave mode only)
1 = Following the eighth falling edge of SCL for a received data byte; slave hardware clears the CKP
bit of the SSPxCON1 register and SCL is held low
0 = Data holding is disabled
Note 1:
2:
3:
For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSP1BUF.
This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
The ACKTIM status bit is only active when the AHEN bit or DHEN bit is set.
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REGISTER 32-5:
R/W-1/1
SSP1MSK: MSSP MASK REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
MSK<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-1
MSK<7:1>: Mask bits
1 = The received address bit n is compared to SSPxADD<n> to detect I2C address match
0 = The received address bit n is not used to detect I2C address match
bit 0
MSK0: Mask for I2C Slave mode bit (10-Bit Address)
10-Bit Address, SSPM<3:0> = 0111 or 1111:
1 = The received address bit 0 is compared to SSPxADD<0> to detect I2C address match
0 = The received address bit 0 is not used to detect I2C address match
I2C Slave mode, 7-Bit Address, the bit is ignored.
REGISTER 32-6:
R/W-0/0
SSP1ADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE)
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ADD<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
bit 7-3
Master mode:
ADD<7:0>: Baud Rate Clock Divider bits
SCL pin clock period = ((ADD<7:0> + 1) * 4)/FOSC.
10-Bit Slave mode – Most Significant Address Byte:
ADD<7:3>: MSSP Address bits
Not Used: Unused for Most Significant Address Byte. Bit state of this register is a “don’t care”. Bit
pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits
are compared by hardware and are not affected by the value in this register.
bit 2-1
ADD<2:1>: Two Most Significant 10-Bit Address bits
bit 0
ADD0: MSSP Address bit
Not Used: Unused in this mode. Bit state is a “don’t care”.
bit 7-0
10-Bit Slave mode – Least Significant Address Byte:
ADD<7:0>: Eight Least Significant 10-Bit Address bits
bit 7-1
7-Bit Slave mode:
ADD<7:1>: MSSP 7-Bit Address bits
bit 0
ADD0: MSSP Address bit
Not Used: Unused in this mode. Bit state is a “don’t care”.
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NOTES:
DS40001775B-page 438
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33.0
The EUSART module includes the following capabilities:
ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
•
•
•
•
•
•
•
•
•
•
•
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock
generators, shift registers and data buffers necessary
to perform an input or output serial data transfer
independent of device program execution. The
EUSART, also known as a Serial Communications
Interface (SCI), can be configured as a full-duplex
asynchronous system or half-duplex synchronous system. Full-Duplex mode is useful for communications
with peripheral systems, such as CRT terminals and
personal computers. Half-Duplex Synchronous mode
is intended for communications with peripheral
devices, such as A/D or D/A integrated circuits, serial
EEPROMs or other microcontrollers. These devices
typically do not have internal clocks for baud rate generation and require the external clock signal provided
by a master synchronous device.
Full-duplex asynchronous transmit and receive
Two-character input buffer
One-character output buffer
Programmable 8-bit or 9-bit character length
Address detection in 9-bit mode
Input buffer overrun error detection
Received character framing error detection
Half-duplex synchronous master
Half-duplex synchronous slave
Programmable clock polarity in Synchronous modes
Sleep operation
The EUSART module implements the following
additional features, making it ideally suited for use in
Local Interconnect Network (LIN) bus systems:
• Automatic detection and calibration of the baud rate
• Wake-up on Break reception
• 13-bit Break character transmit
Block diagrams of the EUSART transmitter and
receiver are shown in Figure 33-1 and Figure 33-2.
The EUSART transmit output (TX_out) is available to
the TX/CK pin and internally to the following peripherals:
• Configurable Logic Cell (CLC)
• Data Signal Modulator (DSM)
FIGURE 33-1:
EUSART TRANSMIT BLOCK DIAGRAM
Data Bus
SYNC
CSRC
MSb
1
• • •
0
Pin Buffer
and Control
PPS
RX/DT
Pin
Transmit Shift Register (TSR)
CKPPS
SYNC
TRMT
FOSC
Multiplier
TX_out
÷n
TX9
n
BRG16
SPxBRGH SPxBRGL
RxyPPS(1)
LSb
(8)
0
+1
TXIF
8
TXEN
Baud Rate Generator
Interrupt
TXxREG Register
CK Pin
PPS
TXIE
x4
x16 x64
SYNC
1 x 0 0
0
BRGH
x 1 1 0
0
BRG16
x 1 0 1
0
TX9D
0
PPS
1
RxyPPS
TX/CK
Pin
SYNC
CSRC
Note 1:
In Synchronous mode, the DT output and RX input PPS selections should enable the same pin.
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FIGURE 33-2:
EUSART RECEIVE BLOCK DIAGRAM
SPEN
CREN
RXPPS(1)
MSb
RX/DT Pin
Data
Recovery
Pin Buffer
and Control
PPS
Baud Rate Generator
FOSC
BRG16
+1
SPxBRGH SPxBRGL
OERR
Multiplier
x4
x16 x64
SYNC
1 x 0 0
0
BRGH
x 1 1 0
0
BRG16
x 1 0 1
0
Stop
RCIDL
RSR Register
(8)
7
•••
1
LSb
0
RX9
÷n
n
FERR
RX9D
RCxREG Register
8
FIFO
Data Bus
RCIF
RCIE
Note 1:
Start
Interrupt
In Synchronous mode, the DT output and RX input PPS selections should enable the same pin.
The operation of the EUSART module is controlled
through three registers:
• Transmit Status and Control (TXxSTA)
• Receive Status and Control (RCxSTA)
• Baud Rate Control (BAUDxCON)
These registers are detailed in Register 33-1,
Register 33-2 and Register 33-3, respectively.
DS40001775B-page 440
The RX and CK input pins are selected with the RXPPS
and CKPPS registers, respectively. TX, CK and DT
output pins are selected with each pin’s RxyPPS register.
Since the RX input is coupled with the DT output in
Synchronous mode, it is the user’s responsibility to select
the same pin for both of these functions when operating
in Synchronous mode. The EUSART control logic will
control the data direction drivers automatically.
 2014-2015 Microchip Technology Inc.
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33.1
EUSART Asynchronous Mode
The EUSART transmits and receives data using the
standard Non-Return-to-Zero (NRZ) format. NRZ is
implemented with two levels: a VOH Mark state which
represents a ‘1’ data bit, and a VOL Space state which
represents a ‘0’ data bit. NRZ refers to the fact that
consecutively transmitted data bits of the same value
stay at the output level of that bit without returning to a
neutral level between each bit transmission. An NRZ
transmission port Idles in the Mark state. Each character
transmission consists of one Start bit, followed by eight
or nine data bits and is always terminated by one or
more Stop bits. The Start bit is always a space and the
Stop bits are always marks. The most common data
format is eight bits. Each transmitted bit persists for a
period of 1/(Baud Rate). An on-chip dedicated
8-bit/16-bit Baud Rate Generator is used to derive
standard baud rate frequencies from the system
oscillator. See Table 33-5 for examples of baud rate
configurations.
33.1.1.2
Transmitting Data
A transmission is initiated by writing a character to the
TXxREG register. If this is the first character, or the
previous character has been completely flushed from
the TSR, the data in the TXxREG is immediately
transferred to the TSR register. If the TSR still contains
all or part of a previous character, the new character
data is held in the TXxREG until the Stop bit of the
previous character has been transmitted. The pending
character in the TXxREG is then transferred to the TSR
in one TCY immediately following the Stop bit
transmission. The transmission of the Start bit, data bits
and Stop bit sequence commences immediately
following the transfer of the data to the TSR from the
TXxREG.
33.1.1.3
Transmit Data Polarity
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent, but share the same data format and baud
rate. Parity is not supported by the hardware, but can
be implemented in software and stored as the ninth
data bit.
The polarity of the transmit data can be controlled with
the SCKP bit of the BAUDxCON register. The default
state of this bit is ‘0’ which selects high true transmit Idle
and data bits. Setting the SCKP bit to ‘1’ will invert the
transmit data resulting in low true Idle and data bits. The
SCKP bit controls transmit data polarity in
Asynchronous mode only. In Synchronous mode, the
SCKP bit has a different function. See Section 33.5.1.2
“Clock Polarity”.
33.1.1
33.1.1.4
EUSART ASYNCHRONOUS
TRANSMITTER
The EUSART transmitter block diagram is shown in
Figure 33-1. The heart of the transmitter is the serial
Transmit Shift Register (TSR), which is not directly
accessible by software. The TSR obtains its data from
the transmit buffer, which is the TXxREG register.
33.1.1.1
Enabling the Transmitter
The EUSART transmitter is enabled for asynchronous
operations by configuring the following three control
bits:
• TXEN = 1
• SYNC = 0
• SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the TXEN bit of the TXxSTA register enables the
transmitter circuitry of the EUSART. Clearing the SYNC
bit of the TXxSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCxSTA register enables the EUSART and
automatically configures the TX/CK I/O pin as an output.
If the TX/CK pin is shared with an analog peripheral, the
analog I/O function must be disabled by clearing the
corresponding ANSELx bit.
Note:
Transmit Interrupt Flag
The TXIF interrupt flag bit of the PIR1 register is set
whenever the EUSART transmitter is enabled and no
character is being held for transmission in the TXxREG.
In other words, the TXIF bit is only clear when the TSR
is busy with a character and a new character has been
queued for transmission in the TXxREG. The TXIF flag
bit is not cleared immediately upon writing TXxREG.
TXIF becomes valid in the second instruction cycle
following the write execution. Polling TXIF immediately
following the TXxREG write will return invalid results.
The TXIF bit is read-only, it cannot be set or cleared by
software.
The TXIF interrupt can be enabled by setting the TXIE
interrupt enable bit of the PIE1 register. However, the
TXIF flag bit will be set whenever the TXxREG is
empty, regardless of the state of TXIE enable bit.
To use interrupts when transmitting data, set the TXIE
bit only when there is more data to send. Clear the
TXIE interrupt enable bit upon writing the last character
of the transmission to the TXxREG.
The TXIF transmitter interrupt flag is set
when the TXEN enable bit is set.
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33.1.1.5
TSR Status
33.1.1.7
The TRMT bit of the TXxSTA register indicates the
status of the TSR register. This is a read-only bit. The
TRMT bit is set when the TSR register is empty and is
cleared when a character is transferred to the TSR
register from the TXxREG. The TRMT bit remains clear
until all bits have been shifted out of the TSR register.
No interrupt logic is tied to this bit, so the user has to
poll this bit to determine the TSR status.
1.
2.
3.
The TSR register is not mapped in data
memory, so it is not available to the user.
Note:
33.1.1.6
Transmitting 9-Bit Characters
4.
5.
The EUSART supports 9-bit character transmissions.
When the TX9 bit of the TXxSTA register is set, the
EUSART will shift nine bits out for each character transmitted. The TX9D bit of the TXxSTA register is the
ninth, and Most Significant data bit. When transmitting
9-bit data, the TX9D data bit must be written before
writing the eight Least Significant bits into the TXxREG.
All nine bits of data will be transferred to the TSR shift
register immediately after the TXxREG is written.
6.
7.
8.
A special 9-Bit Address mode is available for use with
multiple receivers. See Section 33.1.2.7 “Address
Detection” for more information on the Address mode.
FIGURE 33-3:
Asynchronous Transmission Setup
Initialize the SPxBRGH, SPxBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 33.4 “EUSART
Baud Rate Generator (BRG)”).
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
If 9-bit transmission is desired, set the TX9
control bit. A set ninth data bit will indicate that
the eight Least Significant data bits are an
address when the receiver is set for address
detection.
Set SCKP bit if inverted transmit is desired.
Enable the transmission by setting the TXEN
control bit. This will cause the TXIF interrupt bit
to be set.
If interrupts are desired, set the TXIE interrupt
enable bit of the PIE1 register. An interrupt will
occur immediately provided that the GIE and
PEIE bits of the INTCON register are also set.
If 9-bit transmission is selected, the ninth bit
should be loaded into the TX9D data bit.
Load 8-bit data into the TXxREG register. This
will start the transmission.
ASYNCHRONOUS TRANSMISSION
Write to TXxREG
BRG Output
(Shift Clock)
TX/CK Pin
Word 1
Start bit
bit 0
bit 1
bit 7/8
Stop bit
Word 1
1 TCY
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
Word 1
Transmit Shift Reg.
TRMT bit
(Transmit Shift
Reg. Empty Flag)
DS40001775B-page 442
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FIGURE 33-4:
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXxREG
Word 2
Word 1
BRG Output
(Shift Clock)
Start bit
TX/CK Pin
bit 0
bit 1
Word 1
1 TCY
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
bit 7/8
Stop bit
Start bit
Word 2
bit 0
1 TCY
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
TRMT bit
(Transmit Shift
Reg. Empty Flag)
This timing diagram shows two consecutive transmissions.
Note:
TABLE 33-1:
Name
ANSELA
SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
—
—
—
ANSA4
—
—
—
RCIDL
—
SCKP
(1)
ANSELB
ANSB<7:4>
—
ANSC<7:6>(1)
ANSELC
BAUD1CON
ABDOVF
Bit 2
Bit 1
Bit 0
ANSA<2:0>
—
—
142
—
148
ABDEN
450
ANSC<3:0>
BRG16
—
WUE
Register on
Page
153
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
104
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
105
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
108
RC1STA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
449
RxyPPS
—
—
—
INTCON
RxyPPS<4:0>
SP1BRGL
BRG<7:0>
SP1BRGH
BRG<15:8>
—
TRISA
(1)
TRISB
—
TRISA<5:4>
TRISB<7:4>
TX1REG
TX1STA
*
Note 1:
2:
451*
—(2)
TRISA<2:0>
—
—
141
—
TRISC<5:0>
TX9
TXEN
147
152
EUSART Transmit Data Register
CSRC
Legend:
451*
—
TRISC<7:6>(1)
TRISC
159, 161
441*
SYNC
SENDB
BRGH
TRMT
TX9D
448
— = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous transmission.
Page provides register information.
PIC16(L)F1768/9 only.
Unimplemented, read as ‘1’.
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33.1.2
EUSART ASYNCHRONOUS
RECEIVER
The Asynchronous mode is typically used in RS-232
systems. The receiver block diagram is shown in
Figure 33-2. The data is received on the RX/DT pin and
drives the data recovery block. The data recovery block
is actually a high-speed shifter operating at 16 times
the baud rate, whereas the serial Receive Shift
Register (RSR) operates at the bit rate. When all eight
or nine bits of the character have been shifted in, they
are immediately transferred to a two-character
First-In-First-Out (FIFO) memory. The FIFO buffering
allows reception of two complete characters and the
start of a third character before software must start
servicing the EUSART receiver. The FIFO and RSR
registers are not directly accessible by software.
Access to the received data is via the RCxREG
register.
33.1.2.1
Enabling the Receiver
The EUSART receiver is enabled for asynchronous
operation by configuring the following three control bits:
• CREN = 1
• SYNC = 0
• SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the CREN bit of the RCxSTA register enables
the receiver circuitry of the EUSART. Clearing the SYNC
bit of the TXxSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCxSTA register enables the EUSART. The programmer
must set the corresponding TRIS bit to configure the
RX/DT I/O pin as an input.
Note:
If the RX/DT function is on an analog pin,
the corresponding ANSELx bit must be
cleared for the receiver to function.
33.1.2.2
Receiving Data
The receiver data recovery circuit initiates character
reception on the falling edge of the first bit. The first bit,
also known as the Start bit, is always a zero. The data
recovery circuit counts one-half bit time to the center of
the Start bit and verifies that the bit is still a zero. If it is
not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes
looking for the falling edge of the Start bit. If the Start bit
zero verification succeeds, then the data recovery
circuit counts a full bit time to the center of the next bit.
The bit is then sampled by a majority detect circuit and
the resulting ‘0’ or ‘1’ is shifted into the RSR. This
repeats until all data bits have been sampled and
shifted into the RSR. One final bit time is measured and
the level sampled. This is the Stop bit, which is always
a ‘1’. If the data recovery circuit samples a ‘0’ in the
Stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this
character. See Section 33.1.2.4 “Receive Framing
Error” for more information on framing errors.
Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
to the EUSART receive FIFO and the RCIF interrupt
flag bit of the PIR1 register is set. The top character in
the FIFO is transferred out of the FIFO by reading the
RCxREG register.
Note:
33.1.2.3
If the receive FIFO is overrun, no additional
characters will be received until the overrun
condition is cleared. See Section 33.1.2.5
“Receive Overrun Error” for more
information on overrun errors.
Receive Interrupts
The RCIF interrupt flag bit of the PIR1 register is set
whenever the EUSART receiver is enabled and there is
an unread character in the receive FIFO. The RCIF
interrupt flag bit is read-only; it cannot be set or cleared
by software.
RCIF interrupts are enabled by setting all of the
following bits:
• RCIE, Interrupt Enable bit of the PIE1 register
• PEIE, Peripheral Interrupt Enable bit of the
INTCON register
• GIE, Global Interrupt Enable bit of the INTCON
register
The RCIF interrupt flag bit will be set when there is an
unread character in the FIFO, regardless of the state of
interrupt enable bits.
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33.1.2.4
Receive Framing Error
Each character in the receive FIFO buffer has a
corresponding framing error status bit. A framing error
indicates that a Stop bit was not seen at the expected
time. The framing error status is accessed via the
FERR bit of the RCxSTA register. The FERR bit
represents the status of the top unread character in the
receive FIFO. Therefore, the FERR bit must be read
before reading the RCxREG.
The FERR bit is read-only and only applies to the top
unread character in the receive FIFO. A framing error
(FERR = 1) does not preclude reception of additional
characters. It is not necessary to clear the FERR bit.
Reading the next character from the FIFO buffer will
advance the FIFO to the next character and the next
corresponding framing error.
The FERR bit can be forced clear by clearing the SPEN
bit of the RCxSTA register which resets the EUSART.
Clearing the CREN bit of the RCxSTA register does not
affect the FERR bit. A framing error by itself does not
generate an interrupt.
Note:
33.1.2.5
If all receive characters in the receive
FIFO have framing errors, repeated reads
of the RCxREG will not clear the FERR bit.
Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before the FIFO is accessed. When
this happens, the OERR bit of the RCxSTA register is
set. The characters already in the FIFO buffer can be
read, but no additional characters will be received until
the error is cleared. The error must be cleared by either
clearing the CREN bit of the RCxSTA register or by
resetting the EUSART by clearing the SPEN bit of the
RCxSTA register.
 2014-2015 Microchip Technology Inc.
33.1.2.6
Receiving 9-Bit Characters
The EUSART supports 9-bit character reception. When
the RX9 bit of the RCxSTA register is set, the EUSART
will shift nine bits into the RSR for each character
received. The RX9D bit of the RCxSTA register is the
ninth and Most Significant data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the eight Least Significant bits
from the RCxREG.
33.1.2.7
Address Detection
A special Address Detection mode is available for use
when multiple receivers share the same transmission
line, such as in RS-485 systems. Address detection is
enabled by setting the ADDEN bit of the RCxSTA
register.
Address detection requires 9-bit character reception.
When address detection is enabled, only characters
with the ninth data bit set will be transferred to the
receive FIFO buffer, thereby setting the RCIF interrupt
bit. All other characters will be ignored.
Upon receiving an address character, user software
determines if the address matches its own. Upon
address match, user software must disable address
detection by clearing the ADDEN bit before the next
Stop bit occurs. When user software detects the end of
the message, determined by the message protocol
used, software places the receiver back into the
Address Detection mode by setting the ADDEN bit.
DS40001775B-page 445
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33.1.2.8
Asynchronous Reception Setup
33.1.2.9
1.
Initialize the SPxBRGH, SPxBRGL register pair,
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 33.4 “EUSART
Baud Rate Generator (BRG)”).
2. Clear the ANSELx bit for the RX pin (if
applicable).
3. Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
4. If interrupts are desired, set the RCIE bit of the
PIE1 register, and the GIE and PEIE bits of the
INTCON register.
5. If 9-bit reception is desired, set the RX9 bit.
6. Enable reception by setting the CREN bit.
7. The RCIF interrupt flag bit will be set when a
character is transferred from the RSR to the
receive buffer. An interrupt will be generated if
the RCIE interrupt enable bit was also set.
8. Read the RCxSTA register to get the error flags
and, if 9-bit data reception is enabled, the ninth
data bit.
9. Get the received eight Least Significant data bits
from the receive buffer by reading the RCxREG
register.
10. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
FIGURE 33-5:
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1.
Initialize the SPxBRGH, SPxBRGL register pair,
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 33.4 “EUSART
Baud Rate Generator (BRG)”).
2. Clear the ANSELx bit for the RX pin (if applicable).
3. Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
4. If interrupts are desired, set the RCIE bit of the
PIE1 register, and the GIE and PEIE bits of the
INTCON register.
5. Enable 9-bit reception by setting the RX9 bit.
6. Enable address detection by setting the ADDEN
bit.
7. Enable reception by setting the CREN bit.
8. The RCIF interrupt flag bit will be set when a
character with the ninth bit set is transferred
from the RSR to the receive buffer. An interrupt
will be generated if the RCIE interrupt enable bit
was also set.
9. Read the RCxSTA register to get the error flags.
The ninth data bit will always be set.
10. Get the received eight Least Significant data bits
from the receive buffer by reading the RCxREG
register. Software determines if this is the
device’s address.
11. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
12. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
ASYNCHRONOUS RECEPTION
Start
bit bit 0
RX/DT Pin
9-bit Address Detection Mode Setup
Rcv Shift Reg.
Rcv Buffer Reg.
bit 1
bit 7/8 Stop
bit
Start
bit
bit 0
Word 1
RCxREG
bit 7/8 Stop
bit
Start
bit
bit 7/8
Stop
bit
Word 2
RCxREG
RCIDL
Read Rcv
Buffer Reg.
RCxREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCxREG (receive buffer) is read after the third word,
causing the OERR (Overrun) bit to be set.
DS40001775B-page 446
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
TABLE 33-2:
Name
ANSELA
SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
—
—
—
ANSA4
—
ANSELB(1)
ANSB<7:4>
ANSC<7:6>(1)
ANSELC
BAUD1CON
ABDOVF
—
—
RCIDL
—
SCKP
Bit 2
Bit 0
Register
on Page
—
148
ABDEN
450
Bit 1
ANSA<2:0>
—
—
BRG16
—
142
—
ANSC<3:0>
WUE
153
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
104
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
105
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
INTCON
RC1REG
EUSART Receive Data Register
RC1STA
SPEN
RX9
SREN
RxyPPS
—
—
—
CREN
ADDEN
BRG<7:0>
SP1BRGH
BRG<15:8>
—
TRISA
—
TRISB(1)
CSRC
*
2:
RX9D
159
451
(2)
—
TRISA<2:0>
—
141
—
—
147
TRMT
TX9D
448
TRISC<5:0>
TXEN
SYNC
449
SENDB
BRGH
152
— = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous reception.
Legend:
Note 1:
TX9
OERR
451
—
TRISC<7:6>(1)
TX1STA
33.2
TRISA<5:4>
TRISB<7:4>
TRISC
FERR
RxyPPS<4:0>
SP1BRGL
108
444*
Page provides register information.
PIC16(L)F1768/9 only.
Unimplemented, read as ‘1’.
Clock Accuracy with
Asynchronous Operation
The factory calibrates the Internal Oscillator Block
(INTOSC) output. However, the INTOSC frequency
may drift as VDD or temperature changes and this
directly affects the asynchronous baud rate. Two
methods may be used to adjust the baud rate clock, but
both require a reference clock source of some kind.
The other method adjusts the value in the Baud Rate
Generator. This can be done automatically with the
Auto-Baud Detect feature (see Section 33.4.1
“Auto-Baud Detect”). There may not be fine enough
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.
The first (preferred) method uses the OSCTUNE
register to adjust the INTOSC output. Adjusting the
value in the OSCTUNE register allows for fine resolution
changes to the system clock source. See
Section 5.2.2.3 “Internal Oscillator Frequency
Adjustment” for more information.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 447
PIC16(L)F1764/5/8/9
33.3
Register Definitions: EUSART Control
REGISTER 33-1:
TX1STA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R-1/1
R/W-0/0
CSRC
TX9
TXEN(1)
SYNC
SENDB
BRGH
TRMT
TX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6
TX9: 9-Bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5
TXEN: Transmit Enable bit(1)
1 = Transmit is enabled
0 = Transmit is disabled
bit 4
SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3
SENDB: Send Break Character bit
Asynchronous mode:
1 = Sends Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission has completed
Synchronous mode:
Don’t care.
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode.
bit 1
TRMT: Transmit Shift Register Status bit
1 = TSR is empty
0 = TSR is full
bit 0
TX9D: Ninth bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1:
SREN/CREN overrides TXEN in Sync mode.
DS40001775B-page 448
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
REGISTER 33-2:
RC1STA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R-0/0
R-0/0
R-0/0
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
SPEN: Serial Port Enable bit
1 = Serial port is enabled
0 = Serial port is disabled (held in Reset)
bit 6
RX9: 9-Bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode, 9-bit (RX9 = 1):
1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode, 8-bit (RX9 = 0):
Don’t care.
bit 2
FERR: Framing Error bit
1 = Framing error (can be updated by reading RCxREG register and receiving next valid byte)
0 = No framing error
bit 1
OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit, CREN)
0 = No overrun error
bit 0
RX9D: Ninth bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 449
PIC16(L)F1764/5/8/9
REGISTER 33-3:
BAUD1CON: BAUD RATE CONTROL REGISTER
R-0/0
R-1/1
U-0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
ABDOVF
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
ABDOVF: Auto-Baud Detect Overflow bit
Asynchronous mode:
1 = Auto-baud timer overflowed
0 = Auto-baud timer did not overflow
Synchronous mode:
Don’t care.
bit 6
RCIDL: Receive Idle Flag bit
Asynchronous mode:
1 = Receiver is Idle
0 = Start bit has been received and the receiver is receiving
Synchronous mode:
Don’t care.
bit 5
Unimplemented: Read as ‘0’
bit 4
SCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
1 = Transmit inverted data to the TX/CK pin
0 = Transmit non-inverted data to the TX/CK pin
Synchronous mode:
1 = Data is clocked on rising edge of the clock
0 = Data is clocked on falling edge of the clock
bit 3
BRG16: 16-bit Baud Rate Generator bit
1 = 16-bit Baud Rate Generator is used
0 = 8-bit Baud Rate Generator is used
bit 2
Unimplemented: Read as ‘0’
bit 1
WUE: Wake-up Enable bit
Asynchronous mode:
1 = Receiver is waiting for a falling edge, no character will be received, byte RCIF will be set; WUE
will automatically clear after RCIF is set
0 = Receiver is operating normally
Synchronous mode:
Don’t care.
bit 0
ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete)
0 = Auto-Baud Detect mode is disabled
Synchronous mode:
Don’t care.
DS40001775B-page 450
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
33.4
EUSART Baud Rate Generator
(BRG)
The Baud Rate Generator (BRG) is an 8-bit or 16-bit
timer that is dedicated to the support of both the
asynchronous and synchronous EUSART operation.
By default, the BRG operates in 8-bit mode. Setting the
BRG16 bit of the BAUDxCON register selects 16-bit
mode.
The SPxBRGH, SPxBRGL register pair determines the
period of the free-running baud rate timer. In
Asynchronous mode, the multiplier of the baud rate
period is determined by both the BRGH bit of the
TXxSTA register and the BRG16 bit of the BAUDxCON
register. In Synchronous mode, the BRGH bit is ignored.
Table 33-3 contains the formulas for determining the
baud rate. Example 33-1 provides a sample calculation
for determining the baud rate and baud rate error.
Typical baud rates and error values for various
Asynchronous modes have been computed for your
convenience and are shown in Table 33-5. It may be
advantageous to use the high baud rate (BRGH = 1) or
the 16-bit BRG (BRG16 = 1) to reduce the baud rate
error. The 16-Bit BRG mode is used to achieve slow
baud rates for fast oscillator frequencies.
EXAMPLE 33-1:
CALCULATING BAUD
RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate
of 9600, Asynchronous mode, 8-bit BRG:
F OS C
Desired Baud Rate = -----------------------------------------------------------------------64  [SPBRGH:SPBRGL] + 1 
Solving for SPxBRGH:SPxBRGL:
FOSC
--------------------------------------------Desired Baud Rate
X = --------------------------------------------- – 1
64
16000000
-----------------------9600
= ------------------------ – 1
64
=  25.042  = 25
16000000
Calculated Baud Rate = --------------------------64  25 + 1 
= 9615
Calc. Baud Rate – Desired Baud Rate
Error = -------------------------------------------------------------------------------------------Desired Baud Rate
 9615 – 9600 
= ---------------------------------- = 0.16%
9600
Writing a new value to the SPxBRGH, SPxBRGL register pair causes the BRG timer to be reset (or cleared).
This ensures that the BRG does not wait for a timer
overflow before outputting the new baud rate.
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
make sure that the receive operation is Idle before
changing the system clock.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 451
PIC16(L)F1764/5/8/9
TABLE 33-3:
BAUD RATE FORMULAS
Configuration Bits
SYNC
BRG16
BRGH
BRG/EUSART Mode
Baud Rate Formula
FOSC/[64 (n+1)]
0
0
0
8-bit/Asynchronous
0
0
1
8-bit/Asynchronous
0
1
0
16-bit/Asynchronous
0
1
1
16-bit/Asynchronous
1
0
x
8-bit/Synchronous
1
1
x
16-bit/Synchronous
FOSC/[16 (n+1)]
FOSC/[4 (n+1)]
Legend: x = Don’t care, n = value of SPxBRGH, SPxBRGL register pair.
TABLE 33-4:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Bit 7
BAUD1CON ABDOVF
RC1STA
SPEN
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN
450
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
449
SP1BRGL
BRG<7:0>
SP1BRGH
TX1STA
451
BRG<15:8>
CSRC
TX9
TXEN
SYNC
SENDB
451
BRGH
TRMT
TX9D
448
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the Baud Rate Generator.
* Page provides register information.
DS40001775B-page 452
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
TABLE 33-5:
BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
RATE
300
FOSC = 32.000 MHz
FOSC = 20.000 MHz
FOSC = 18.432 MHz
FOSC = 11.0592 MHz
Actual
Rate
%
Error
SPxBRG
value
(decimal)
Actual
Rate
%
Error
SPxBRG
value
(decimal)
Actual
Rate
%
Error
SPxBRG
value
(decimal)
Actual
Rate
%
Error
SPxBRG
value
(decimal)
—
—
—
—
—
—
—
—
—
—
—
—
1200
—
—
—
1221
1.73
255
1200
0.00
239
1200
0.00
143
2400
2404
0.16
207
2404
0.16
129
2400
0.00
119
2400
0.00
71
9600
9615
0.16
51
9470
-1.36
32
9600
0.00
29
9600
0.00
17
10417
10417
0.00
47
10417
0.00
29
10286
-1.26
27
10165
-2.42
16
8
19.2k
19.23k
0.16
25
19.53k
1.73
15
19.20k
0.00
14
19.20k
0.00
57.6k
55.55k
-3.55
3
—
—
—
57.60k
0.00
7
57.60k
0.00
2
115.2k
—
—
—
—
—
—
—
—
—
—
—
—
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
RATE
FOSC = 8.000 MHz
Actual
Rate
%
Error
SPxBRG
value
(decimal)
FOSC = 4.000 MHz
Actual
Rate
%
Error
SPxBRG
value
(decimal)
FOSC = 3.6864 MHz
Actual
Rate
%
Error
SPxBRG
value
(decimal)
FOSC = 1.000 MHz
Actual
Rate
%
Error
SPxBRG
value
(decimal)
300
—
—
—
300
0.16
207
300
0.00
191
300
0.16
51
1200
1202
0.16
103
1202
0.16
51
1200
0.00
47
1202
0.16
12
2400
2404
0.16
51
2404
0.16
25
2400
0.00
23
—
—
—
9600
9615
0.16
12
—
—
—
9600
0.00
5
—
—
—
10417
10417
0.00
11
10417
0.00
5
—
—
—
—
—
—
19.2k
—
—
—
—
—
—
19.20k
0.00
2
—
—
—
57.6k
—
—
—
—
—
—
57.60k
0.00
0
—
—
—
115.2k
—
—
—
—
—
—
—
—
—
—
—
—
SYNC = 0, BRGH = 1, BRG16 = 0
BAUD
RATE
FOSC = 32.000 MHz
Actual
Rate
%
Error
SPxBRG
value
(decimal)
FOSC = 20.000 MHz
Actual
Rate
%
Error
SPxBRG
value
(decimal)
FOSC = 18.432 MHz
Actual
Rate
%
Error
SPxBRG
value
(decimal)
FOSC = 11.0592 MHz
Actual
Rate
%
Error
SPxBRG
value
(decimal)
300
—
—
—
—
—
—
—
—
—
—
—
—
1200
—
—
—
—
—
—
—
—
—
—
—
—
2400
—
—
—
—
—
—
—
—
—
—
—
—
9600
9615
0.16
207
9615
0.16
129
9600
0.00
119
9600
0.00
71
10417
10417
0.00
191
10417
0.00
119
10378
-0.37
110
10473
0.53
65
19.2k
19.23k
0.16
103
19.23k
0.16
64
19.20k
0.00
59
19.20k
0.00
35
57.6k
57.14k
-0.79
34
56.82k
-1.36
21
57.60k
0.00
19
57.60k
0.00
11
115.2k
117.64k
2.12
16
113.64k
-1.36
10
115.2k
0.00
9
115.2k
0.00
5
 2014-2015 Microchip Technology Inc.
DS40001775B-page 453
PIC16(L)F1764/5/8/9
TABLE 33-5:
BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 0
BAUD
RATE
FOSC = 8.000 MHz
Actual
Rate
%
Error
SPxBRG
value
(decimal)
FOSC = 4.000 MHz
Actual
Rate
%
Error
SPxBRG
value
(decimal)
FOSC = 3.6864 MHz
Actual
Rate
%
Error
SPxBRG
value
(decimal)
FOSC = 1.000 MHz
Actual
Rate
%
Error
SPxBRG
value
(decimal)
207
300
—
—
—
—
—
—
—
—
—
300
0.16
1200
—
—
—
1202
0.16
207
1200
0.00
191
1202
0.16
51
2400
2404
0.16
207
2404
0.16
103
2400
0.00
95
2404
0.16
25
9600
9615
0.16
51
9615
0.16
25
9600
0.00
23
—
—
—
10417
10417
0.00
47
10417
0.00
23
10473
0.53
21
10417
0.00
5
19.2k
19231
0.16
25
19.23k
0.16
12
19.2k
0.00
11
—
—
—
57.6k
55556
-3.55
8
—
—
—
57.60k
0.00
3
—
—
—
115.2k
—
—
—
—
—
—
115.2k
0.00
1
—
—
—
SYNC = 0, BRGH = 0, BRG16 = 1
BAUD
RATE
FOSC = 32.000 MHz
Actual
Rate
FOSC = 20.000 MHz
FOSC = 18.432 MHz
FOSC = 11.0592 MHz
%
Error
SPxBRG
value
(decimal)
Actual
Rate
%
Error
SPxBRG
value
(decimal)
Actual
Rate
%
Error
SPxBRG
value
(decimal)
Actual
Rate
%
Error
SPxBRG
value
(decimal)
300
300.0
0.00
6666
300.0
-0.01
4166
300.0
0.00
3839
300.0
0.00
2303
1200
1200
-0.02
3332
1200
-0.03
1041
1200
0.00
959
1200
0.00
575
2400
2401
-0.04
832
2399
-0.03
520
2400
0.00
479
2400
0.00
287
9600
9615
0.16
207
9615
0.16
129
9600
0.00
119
9600
0.00
71
10417
10417
0.00
191
10417
0.00
119
10378
-0.37
110
10473
0.53
65
19.2k
19.23k
0.16
103
19.23k
0.16
64
19.20k
0.00
59
19.20k
0.00
35
57.6k
57.14k
-0.79
34
56.818
-1.36
21
57.60k
0.00
19
57.60k
0.00
11
115.2k
117.6k
2.12
16
113.636
-1.36
10
115.2k
0.00
9
115.2k
0.00
5
SYNC = 0, BRGH = 0, BRG16 = 1
BAUD
RATE
FOSC = 8.000 MHz
Actual
Rate
FOSC = 4.000 MHz
FOSC = 3.6864 MHz
FOSC = 1.000 MHz
%
Error
SPxBRG
value
(decimal)
Actual
Rate
%
Error
SPxBRG
value
(decimal)
Actual
Rate
%
Error
SPxBRG
value
(decimal)
Actual
Rate
%
Error
SPxBRG
value
(decimal)
300
299.9
-0.02
1666
300.1
0.04
832
300.0
0.00
767
300.5
0.16
207
1200
1199
-0.08
416
1202
0.16
207
1200
0.00
191
1202
0.16
51
2400
2404
0.16
207
2404
0.16
103
2400
0.00
95
2404
0.16
25
9600
9615
0.16
51
9615
0.16
25
9600
0.00
23
—
—
—
10417
10417
0.00
47
10417
0.00
23
10473
0.53
21
10417
0.00
5
19.2k
19.23k
0.16
25
19.23k
0.16
12
19.20k
0.00
11
—
—
—
57.6k
55556
-3.55
8
—
—
—
57.60k
0.00
3
—
—
—
115.2k
—
—
—
—
—
—
115.2k
0.00
1
—
—
—
DS40001775B-page 454
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
TABLE 33-5:
BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
BAUD
RATE
FOSC = 32.000 MHz
Actual
Rate
FOSC = 20.000 MHz
%
Error
SPxBRG
value
(decimal)
Actual
Rate
FOSC = 18.432 MHz
FOSC = 11.0592 MHz
%
Error
SPxBRG
value
(decimal)
Actual
Rate
%
Error
SPxBRG
value
(decimal)
Actual
Rate
%
Error
SPxBRG
value
(decimal)
300
300.0
0.00
26666
300.0
0.00
16665
300.0
0.00
15359
300.0
0.00
9215
1200
1200
0.00
6666
1200
-0.01
4166
1200
0.00
3839
1200
0.00
2303
2400
2400
0.01
3332
2400
0.02
2082
2400
0.00
1919
2400
0.00
1151
9600
9604
0.04
832
9597
-0.03
520
9600
0.00
479
9600
0.00
287
10417
10417
0.00
767
10417
0.00
479
10425
0.08
441
10433
0.16
264
19.2k
19.18k
-0.08
416
19.23k
0.16
259
19.20k
0.00
239
19.20k
0.00
143
57.6k
57.55k
-0.08
138
57.47k
-0.22
86
57.60k
0.00
79
57.60k
0.00
47
115.2k
115.9k
0.64
68
116.3k
0.94
42
115.2k
0.00
39
115.2k
0.00
23
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
BAUD
RATE
FOSC = 8.000 MHz
Actual
Rate
FOSC = 4.000 MHz
FOSC = 3.6864 MHz
FOSC = 1.000 MHz
%
Error
SPxBRG
value
(decimal)
Actual
Rate
%
Error
SPxBRG
value
(decimal)
Actual
Rate
%
Error
SPxBRG
value
(decimal)
Actual
Rate
%
Error
SPxBRG
value
(decimal)
300
300.0
0.00
6666
300.0
0.01
3332
300.0
0.00
3071
300.1
0.04
832
1200
1200
-0.02
1666
1200
0.04
832
1200
0.00
767
1202
0.16
207
2400
2401
0.04
832
2398
0.08
416
2400
0.00
383
2404
0.16
103
9600
9615
0.16
207
9615
0.16
103
9600
0.00
95
9615
0.16
25
10417
10417
0
191
10417
0.00
95
10473
0.53
87
10417
0.00
23
19.2k
19.23k
0.16
103
19.23k
0.16
51
19.20k
0.00
47
19.23k
0.16
12
57.6k
57.14k
-0.79
34
58.82k
2.12
16
57.60k
0.00
15
—
—
—
115.2k
117.6k
2.12
16
111.1k
-3.55
8
115.2k
0.00
7
—
—
—
 2014-2015 Microchip Technology Inc.
DS40001775B-page 455
PIC16(L)F1764/5/8/9
33.4.1
AUTO-BAUD DETECT
The EUSART module supports automatic detection
and calibration of the baud rate.
In the Auto-Baud Detect (ABD) mode, the clock to the
BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG.
The Baud Rate Generator is used to time the period of
a received 55h (ASCII “U”), which is the Sync character
for the LIN bus. The unique feature of this character is
that it has five rising edges including the Stop bit edge.
Setting the ABDEN bit of the BAUDxCON register
starts the auto-baud calibration sequence. While the
ABD sequence takes place, the EUSART state
machine is held in Idle. On the first rising edge of the
receive line, after the Start bit, the SPxBRG begins
counting up using the BRG counter clock, as shown in
Figure 33-6. The fifth rising edge will occur on the RX
pin at the end of the eighth bit period. At that time, an
accumulated value totaling the proper BRG period is
left in the SPxBRGH, SPxBRGL register pair, the
ABDEN bit is automatically cleared and the RCIF interrupt flag is set. The value in the RCxREG needs to be
read to clear the RCIF interrupt. RCxREG content
should be discarded. When calibrating for modes that
do not use the SPxBRGH register, the user can verify
that the SPxBRGL register did not overflow by checking
for 00h in the SPxBRGH register.
The BRG auto-baud clock is determined by the BRG16
and BRGH bits as shown in Table 33-6. During ABD,
both the SPxBRGH and SPxBRGL registers are used
as a 16-bit counter, independent of the BRG16 bit setting. While calibrating the baud rate period, the
SPxBRGH and SPxBRGL registers are clocked at
FIGURE 33-6:
BRG Value
1/8th the BRG base clock rate. The resulting byte
measurement is the average bit time when clocked at
full speed.
Note 1: If the WUE bit is set with the ABDEN bit,
Auto-Baud Detection will occur on the
byte following the Break character (see
Section 33.4.3 “Auto-Wake-up on
Break”).
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible.
3: During the auto-baud process, the
auto-baud counter starts counting at one.
Upon completion of the auto-baud
sequence, to achieve maximum accuracy,
subtract 1 from the SPxBRGH:SPxBRGL
register pair.
TABLE 33-6:
BRG COUNTER CLOCK RATES
BRG16
BRGH
BRG Base
Clock
BRG ABD
Clock
0
0
FOSC/64
FOSC/512
0
1
FOSC/16
FOSC/128
1
0
FOSC/16
FOSC/128
1
1
FOSC/4
FOSC/32
Note:
During the ABD sequence, the SPxBRGL
and SPxBRGH registers are both used as a
16-bit counter, independent of the BRG16
setting.
AUTOMATIC BAUD RATE CALIBRATION
XXXXh
0000h
001Ch
Start
RX Pin
Edge #1
bit 1
bit 0
Edge #2
bit 3
bit 2
Edge #3
bit 5
bit 4
Edge #4
bit 7
bit 6
Edge #5
Stop bit
BRG Clock
Auto Cleared
Set by User
ABDEN bit
RCIDL
RCIF bit
(Interrupt)
Read
RCxREG
SPxBRGL
XXh
1Ch
SPxBRGH
XXh
00h
Note 1:
The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
DS40001775B-page 456
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
33.4.2
AUTO-BAUD OVERFLOW
During the course of Automatic Baud Detection, the
ABDOVF bit of the BAUDxCON register will be set if
the baud rate counter overflows before the fifth rising
edge is detected on the RX pin. The ABDOVF bit
indicates that the counter has exceeded the maximum
count that can fit in the 16 bits of the
SPxBRGH:SPxBRGL register pair. The overflow condition will set the RCIF flag. The counter continues to
count until the fifth rising edge is detected on the RX
pin. The RCIDL bit will remain false (‘0’) until the fifth
rising edge, at which time, the RCIDL bit will be set. If
the RCREG is read after the overflow occurs, but
before the fifth rising edge, then the fifth rising edge will
set the RCIF again.
Terminating the auto-baud process early to clear an
overflow condition will prevent proper detection of the
Sync character’s fifth rising edge. If any falling edges of
the Sync character have not yet occurred when the
ABDEN bit is cleared, then those will be falsely
detected as Start bits. The following steps are
recommended to clear the overflow condition:
1.
2.
3.
Read RCREG to clear RCIF.
If RCIDL is zero, then wait for RCIF and repeat
Step 1.
Clear the ABDOVF bit.
33.4.3
AUTO-WAKE-UP ON BREAK
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper character reception cannot be
performed. The auto-wake-up feature allows the
controller to wake-up due to activity on the RX/DT line.
This feature is available only in Asynchronous mode.
The auto-wake-up feature is enabled by setting the WUE
bit of the BAUDxCON register. Once set, the normal
receive sequence on RX/DT is disabled, and the
EUSART remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on the
RX/DT line. (This coincides with the start of a Sync Break
or a wake-up signal character for the LIN protocol.)
33.4.3.1
Special Considerations
Break Character
To avoid character errors or character fragments during a
wake-up event, the wake-up character must be all zeros.
When the wake-up is enabled, the function works
independent of the low time on the data stream. If the
WUE bit is set and a valid non-zero character is
received, the low time from the Start bit to the first rising
edge will be interpreted as the wake-up event. The
remaining bits in the character will be received as a
fragmented character and subsequent characters can
result in framing or overrun errors.
Therefore, the initial character in the transmission must
be all ‘0’s. This must be ten or more bit times, 13 bit
times recommended for LIN bus, or any number of bit
times for standard RS-232 devices.
Oscillator Start-up Time
Oscillator start-up time must be considered, especially
in applications using oscillators with longer start-up
intervals (i.e., LP, XT or HS/PLL mode). The Sync
Break (or wake-up signal) character must be of
sufficient length, and be followed by a sufficient
interval, to allow enough time for the selected oscillator
to start and provide proper initialization of the EUSART.
WUE Bit
The wake-up event causes a receive interrupt by
setting the RCIF bit. The WUE bit is cleared in
hardware by a rising edge on RX/DT. The interrupt
condition is then cleared in software by reading the
RCxREG register and discarding its contents.
To ensure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process
before setting the WUE bit. If a receive operation is not
occurring, the WUE bit may then be set just prior to
entering the Sleep mode.
The EUSART module generates an RCIF interrupt
coincident with the wake-up event. The interrupt is
generated synchronously to the Q clocks in normal CPU
operating modes (Figure 33-7), and asynchronously if
the device is in Sleep mode (Figure 33-8). The interrupt
condition is cleared by reading the RCxREG register.
The WUE bit is automatically cleared by the low-to-high
transition on the RX line at the end of the Break. This
signals to the user that the Break event is over. At this
point, the EUSART module is in Idle mode waiting to
receive the next character.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 457
PIC16(L)F1764/5/8/9
FIGURE 33-7:
AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE bit
Bit set by user
Auto-Cleared
RX/DT
Line
RCIF
Note 1:
Cleared due to User Read of RCxREG
The EUSART remains in Idle while the WUE bit is set.
FIGURE 33-8:
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4
OSC1
WUE bit
Auto-Cleared
Bit Set by User
RX/DT
Line
Note 1
RCIF
SLEEP Command Executed
Note 1:
2:
Sleep Ends
Cleared due to User Read of RCxREG
If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal
is still active. This sequence should not depend on the presence of Q clocks.
The EUSART remains in Idle while the WUE bit is set.
DS40001775B-page 458
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
33.4.4
BREAK CHARACTER SEQUENCE
The EUSART module has the capability of sending the
special Break character sequences that are required by
the LIN bus standard. A Break character consists of a
Start bit, followed by 12 ‘0’ bits and a Stop bit.
To send a Break character, set the SENDB and TXEN
bits of the TXxSTA register. The Break character transmission is then initiated by a write to the TXxREG. The
value of data written to TXxREG will be ignored and all
‘0’s will be transmitted.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
The TRMT bit of the TXxSTA register indicates when the
transmit operation is active or Idle, just as it does during
normal transmission. See Figure 33-9 for the timing of
the Break character sequence.
33.4.4.1
Break and Sync Transmit Sequence
The following sequence will start a message frame
header made up of a Break, followed by an auto-baud
Sync byte. This sequence is typical of a LIN bus master.
1.
2.
3.
4.
5.
33.4.5
RECEIVING A BREAK CHARACTER
The Enhanced USART module can receive a Break
character in two ways.
The first method to detect a Break character uses the
FERR bit of the RCxSTA register and the received data
as indicated by RCxREG. The Baud Rate Generator is
assumed to have been initialized to the expected baud
rate.
A Break character has been received when;
• RCIF bit is set
• FERR bit is set
• RCxREG = 00h
The second method uses the auto-wake-up feature
described in Section 33.4.3 “Auto-Wake-up on
Break”. By enabling this feature, the EUSART will
sample the next two transitions on RX/DT, cause an
RCIF interrupt and receive the next data byte followed
by another interrupt.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Detect feature.
For both methods, the user can set the ABDEN bit of
the BAUDxCON register before placing the EUSART in
Sleep mode.
Configure the EUSART for the desired mode.
Set the TXEN and SENDB bits to enable the
Break sequence.
Load the TXxREG with a dummy character to
initiate transmission (the value is ignored).
Write ‘55h’ to TXxREG to load the Sync character
into the transmit FIFO buffer.
After the Break has been sent, the SENDB bit is
reset by hardware and the Sync character is
then transmitted.
When the TXxREG becomes empty, as indicated by
the TXIF, the next data byte can be written to TXxREG.
FIGURE 33-9:
Write to TXxREG
SEND BREAK CHARACTER SEQUENCE
Dummy Write
BRG Output
(Shift Clock)
TX (pin)
Start bit
bit 0
bit 1
bit 11
Stop bit
Break
TXIF bit
(Transmit
Interrupt Flag)
TRMT bit
(Transmit Shift
Empty Flag)
SENDB
(send Break
control bit)
 2014-2015 Microchip Technology Inc.
SENDB Sampled Here
Auto Cleared
DS40001775B-page 459
PIC16(L)F1764/5/8/9
33.5
EUSART Synchronous Mode
Synchronous serial communications are typically used
in systems with a single master and one or more
slaves. The master device contains the necessary
circuitry for baud rate generation and supplies the clock
for all devices in the system. Slave devices can take
advantage of the master clock by eliminating the
internal clock generation circuitry.
There are two signal lines in Synchronous mode: a
bidirectional data line and a clock line. Slaves use the
external clock supplied by the master to shift the serial
data into and out of their respective receive and transmit shift registers. Since the data line is bidirectional,
synchronous operation is half-duplex only. Half-duplex
refers to the fact that master and slave devices can
receive and transmit data, but not both simultaneously.
The EUSART can operate as either a master or slave
device.
Start and Stop bits are not used in synchronous
transmissions.
33.5.1
SYNCHRONOUS MASTER MODE
The following bits are used to configure the EUSART
for synchronous master operation:
•
•
•
•
•
SYNC = 1
CSRC = 1
SREN = 0 (for transmit); SREN = 1 (for receive)
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1
Setting the SYNC bit of the TXxSTA register configures
the device for synchronous operation. Setting the CSRC
bit of the TXxSTA register configures the device as a
master. Clearing the SREN and CREN bits of the
RCxSTA register ensures that the device is in the
Transmit mode, otherwise the device will be configured
to receive. Setting the SPEN bit of the RCxSTA register
enables the EUSART.
33.5.1.1
Master Clock
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device configured as a master transmits the clock on the TX/CK line.
The TX/CK pin output driver is automatically enabled
when the EUSART is configured for synchronous
transmit or receive operation. Serial data bits change
on the leading edge to ensure they are valid at the
trailing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are
generated as there are data bits.
DS40001775B-page 460
33.5.1.2
Clock Polarity
A clock polarity option is provided for Microwire
compatibility. Clock polarity is selected with the SCKP
bit of the BAUDxCON register. Setting the SCKP bit
sets the clock Idle state as high. When the SCKP bit is
set, the data changes on the falling edge of each clock.
Clearing the SCKP bit sets the Idle state as low. When
the SCKP bit is cleared, the data changes on the rising
edge of each clock.
33.5.1.3
Synchronous Master Transmission
Data is transferred out of the device on the RX/DT pin.
The RX/DT and TX/CK pin output drivers are automatically enabled when the EUSART is configured for
synchronous master transmit operation.
A transmission is initiated by writing a character to the
TXxREG register. If the TSR still contains all or part of
a previous character the new character data is held in
the TXxREG until the last bit of the previous character
has been transmitted. If this is the first character, or the
previous character has been completely flushed from
the TSR, the data in the TXxREG is immediately transferred to the TSR. The transmission of the character
commences immediately following the transfer of the
data to the TSR from the TXxREG.
Each data bit changes on the leading edge of the
master clock and remains valid until the subsequent
leading clock edge.
Note:
The TSR register is not mapped in data
memory, so it is not available to the user.
33.5.1.4
Synchronous Master Transmission
Setup
1.
2.
3.
4.
5.
6.
7.
8.
Initialize the SPxBRGH, SPxBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 33.4 “EUSART
Baud Rate Generator (BRG)”).
Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
Disable Receive mode by clearing bits, SREN
and CREN.
Enable Transmit mode by setting the TXEN bit.
If 9-bit transmission is desired, set the TX9 bit.
If interrupts are desired, set the TXIE bit of the
PIE1 register, and the GIE and PEIE bits of the
INTCON register.
If 9-bit transmission is selected, the ninth bit
should be loaded in the TX9D bit.
Start transmission by loading data to the
TXxREG register.
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
FIGURE 33-10:
SYNCHRONOUS TRANSMISSION
RX/DT
Pin
TX/CK Pin
(SCKP = 0)
bit 0
bit 1
Word 1
bit 7
bit 2
bit 0
bit 1
Word 2
bit 7
TX/CK Pin
(SCKP = 1)
Write to
TXxREG Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
TXEN bit
Note:
‘1’
‘1’
Sync Master mode, SPxBRGL = 0; continuous transmission of two 8-bit words.
FIGURE 33-11:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RX/DT Pin
bit 0
bit 1
bit 2
bit 6
bit 7
TX/CK Pin
Write to
TXxREG Reg
TXIF bit
TRMT bit
TXEN bit
 2014-2015 Microchip Technology Inc.
DS40001775B-page 461
PIC16(L)F1764/5/8/9
TABLE 33-7:
Name
ANSELA
SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
TRANSMISSION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
—
—
—
ANSA4
—
ANSELB(1)
ANSB<7:4>
ANSC<7:6>(1)
ANSELC
BAUD1CON
ABDOVF
—
—
RCIDL
—
SCKP
Bit 2
Bit 1
Bit 0
Register
on Page
—
148
ABDEN
450
ANSA<2:0>
—
—
BRG16
—
—
142
ANSC<3:0>
WUE
153
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
104
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
105
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
108
RC1STA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
449
RxyPPS
—
—
—
INTCON
RxyPPS<4:0>
SP1BRGL
SP1BRGH
TRISB(1)
—
TRISA<5:4>
TRISB<7:4>
*
Note 1:
2:
—
—
141
—
TX9
TXEN
SYNC
SENDB
147
152
EUSART Transmit Data Register
CSRC
Legend:
TRISA<2:0>
TRISC<5:0>
TX1REG
TX1STA
451
—(2)
—
TRISC<7:6>(1)
TRISC
451
BRG<15:8>
—
TRISA
159
BRG<7:0>
441*
BRGH
TRMT
TX9D
448
— = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Page provides register information.
PIC16(L)F1768/9 only.
Unimplemented, read as ‘1’.
DS40001775B-page 462
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
33.5.1.5
Synchronous Master Reception
Data is received at the RX/DT pin. The RX/DT pin
output driver is automatically disabled when the
EUSART is configured for synchronous master receive
operation.
In Synchronous mode, reception is enabled by setting
either the Single Receive Enable bit (SREN of the
RCxSTA register) or the Continuous Receive Enable
bit (CREN of the RCxSTA register).
When SREN is set and CREN is clear, only as many
clock cycles are generated as there are data bits in a
single character. The SREN bit is automatically cleared
at the completion of one character. When CREN is set,
clocks are continuously generated until CREN is
cleared. If CREN is cleared in the middle of a character,
the CK clock stops immediately and the partial character is discarded. If SREN and CREN are both set, then
SREN is cleared at the completion of the first character
and CREN takes precedence.
To initiate reception, set either SREN or CREN. Data is
sampled at the RX/DT pin on the trailing edge of the
TX/CK clock pin and is shifted into the Receive Shift
Register (RSR). When a complete character is
received into the RSR, the RCIF bit is set and the character is automatically transferred to the two-character
receive FIFO. The Least Significant eight bits of the top
character in the receive FIFO are available in RCxREG.
The RCIF bit remains set as long as there are unread
characters in the receive FIFO.
Note:
33.5.1.6
If the RX/DT function is on an analog pin,
the corresponding ANSELx bit must be
cleared for the receiver to function.
Slave Clock
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device configured
as a slave receives the clock on the TX/CK line. The
TX/CK pin output driver is automatically disabled when
the device is configured for synchronous slave transmit
or receive operation. Serial data bits change on the
leading edge to ensure they are valid at the trailing edge
of each clock. One data bit is transferred for each clock
cycle. Only as many clock cycles should be received as
there are data bits.
Note:
If the device is configured as a slave and
the TX/CK function is on an analog pin, the
corresponding ANSELx bit must be
cleared.
 2014-2015 Microchip Technology Inc.
33.5.1.7
Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before RCxREG is read to access
the FIFO. When this happens, the OERR bit of the
RCxSTA register is set. Previous data in the FIFO will
not be overwritten. The two characters in the FIFO
buffer can be read, however, no additional characters
will be received until the error is cleared. The OERR bit
can only be cleared by clearing the overrun condition.
If the overrun error occurred when the SREN bit is set
and CREN is clear, then the error is cleared by reading
RCxREG. If the overrun occurred when the CREN bit is
set, then the error condition is cleared by either clearing
the CREN bit of the RCxSTA register or by clearing the
SPEN bit which resets the EUSART.
33.5.1.8
Receiving 9-Bit Characters
The EUSART supports 9-bit character reception. When
the RX9 bit of the RCxSTA register is set the EUSART
will shift nine bits into the RSR for each character
received. The RX9D bit of the RCxSTA register is the
ninth, and Most Significant, data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the eight Least Significant bits
from the RCxREG.
33.5.1.9
Synchronous Master Reception
Setup
1.
Initialize the SPxBRGH, SPxBRGL register pair
for the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
2. Clear the ANSELx bit for the RX pin (if applicable).
3. Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
4. Ensure bits, CREN and SREN, are clear.
5. If interrupts are desired, set the RCIE bit of the
PIE1 register, and the GIE and PEIE bits of the
INTCON register.
6. If 9-bit reception is desired, set bit, RX9.
7. Start reception by setting the SREN bit, or for
continuous reception, set the CREN bit.
8. Interrupt flag bit, RCIF, will be set when reception of a character is complete. An interrupt will
be generated if the enable bit, RCIE, was set.
9. Read the RCxSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
10. Read the 8-bit received data by reading the
RCxREG register.
11. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCxSTA
register or by clearing the SPEN bit which resets
the EUSART.
DS40001775B-page 463
PIC16(L)F1764/5/8/9
FIGURE 33-12:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RX/DT
Pin
bit 1
bit 0
bit 2
bit 5
bit 4
bit 3
bit 7
bit 6
TX/CK Pin
(SCKP = 0)
TX/CK Pin
(SCKP = 1)
Write to
SREN bit
SREN bit
‘0’
CREN bit
‘0’
RCIF bit
(Interrupt)
Read
RCxREG
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
Note:
TABLE 33-8:
Name
ANSELA
SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
RECEPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
—
—
—
ANSA4
—
ANSELB(1)
ANSB<7:4>
BAUD1CON
CKPPS
—
—
SCKP
ABDOVF
RCIDL
—
—
—
—
Bit 1
Bit 0
Register
on Page
—
148
ANSA<2:0>
—
ANSC<7:6>(1)
ANSELC
Bit 2
—
—
142
ANSC<3:0>
BRG16
—
WUE
153
ABDEN
CKPPS<4:0>
450
159, 161
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
104
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
105
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
INTCON
RC1REG
EUSART Receive Data Register
RC1STA
SPEN
RX9
SREN
RXPPS
—
—
—
RxyPPS
—
—
—
CREN
(1)
TRISB
—
TRISA<5:4>
TRISB<7:4>
CSRC
*
Note 1:
2:
TX9
159
451*
451*
—(2)
—
TRISA<2:0>
—
141
—
—
147
TRMT
TX9D
448
TRISC<5:0>
TXEN
SYNC
449
159, 161
RxyPPS<4:0>
TRISC<7:6>(1)
Legend:
RX9D
BRG<15:8>
—
TX1STA
OERR
BRG<7:0>
SP1BRGH
TRISC
FERR
RXPPS<4:0>
SP1BRGL
TRISA
ADDEN
108
444*
SENDB
BRGH
152
— = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master reception.
Page provides register information.
PIC16(L)F1768/9 only.
Unimplemented, read as ‘1’.
DS40001775B-page 464
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
33.5.2
SYNCHRONOUS SLAVE MODE
The following bits are used to configure the EUSART
for synchronous slave operation:
•
•
•
•
•
SYNC = 1
CSRC = 0
SREN = 0 (for transmit); SREN = 1 (for receive)
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1
Setting the SYNC bit of the TXxSTA register configures
the device for synchronous operation. Clearing the
CSRC bit of the TXxSTA register configures the device as
a slave. Clearing the SREN and CREN bits of the
RCxSTA register ensures that the device is in the
Transmit mode, otherwise the device will be configured to
receive. Setting the SPEN bit of the RCxSTA register
enables the EUSART.
33.5.2.1
33.5.2.2
1.
2.
3.
4.
5.
6.
7.
8.
Synchronous Slave Transmission
Setup
Set the SYNC and SPEN bits, and clear the
CSRC bit.
Clear the ANSEL bit for the CK pin (if applicable).
Clear the CREN and SREN bits.
If interrupts are desired, set the TXIE bit of the
PIE1 register, and the GIE and PEIE bits of the
INTCON register.
If 9-bit transmission is desired, set the TX9 bit.
Enable transmission by setting the TXEN bit.
If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
Start transmission by writing the Least
Significant eight bits to the TXxREG register.
EUSART Synchronous Slave
Transmit
The operation of the Synchronous Master and Slave
modes
are
identical
(see
Section 33.5.1.3
“Synchronous Master Transmission”), except in the
case of Sleep mode.
If two words are written to the TXxREG and then the
SLEEP instruction is executed, the following will occur:
1.
2.
3.
4.
5.
The first character will immediately transfer to
the TSR register and transmit.
The second word will remain in the TXxREG
register.
The TXIF bit will not be set.
After the first character has been shifted out of
TSR, the TXxREG register will transfer the
second character to the TSR and the TXIF bit will
now be set.
If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 465
PIC16(L)F1764/5/8/9
TABLE 33-9:
Name
ANSELA
SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE
TRANSMISSION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
—
—
—
ANSA4
—
ANSELB(1)
ANSB<7:4>
ANSC<7:6>(1)
ANSELC
BAUD1CON
ABDOVF
RCIDL
Bit 2
—
—
—
—
SCKP
BRG16
Register
on Page
—
148
WUE
ABDEN
450
ANSA<2:0>
—
—
Bit 0
Bit 1
—
142
ANSC<3:0>
153
CKPPS
—
—
—
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
CKPPS<4:0>
TMR0IF
INTF
IOCIF
104
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
105
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
108
CREN
ADDEN
FERR
OERR
RX9D
RC1STA
SPEN
RX9
SREN
RXPPS
—
—
—
RxyPPS
—
—
—
TRISA
—
—
TRISB(1)
RXPPS<4:0>
TRISB<7:4>
—
*
Note 1:
2:
—
—
141
—
TX9
TXEN
SYNC
SENDB
147
152
EUSART Transmit Data Register
CSRC
Legend:
159
TRISA<2:0>
TRISC<5:0>
TX1REG
TX1STA
—(2)
449
159, 161
RxyPPS<4:0>
TRISA<5:4>
TRISC<7:6>(1)
TRISC
159, 161
441*
BRGH
TRMT
TX9D
448
— = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Page provides register information.
PIC16(L)F1768/9 only.
Unimplemented, read as ‘1’.
DS40001775B-page 466
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
33.5.2.3
EUSART Synchronous Slave
Reception
33.5.2.4
1.
The operation of the Synchronous Master and Slave
modes is identical (Section 33.5.1.5 “Synchronous
Master Reception”), with the following exceptions:
Set the SYNC and SPEN bits, and clear the
CSRC bit.
Clear the ANSELx bit for both the CK and DT
pins (if applicable).
If interrupts are desired, set the RCIE bit of the
PIE1 register, and the GIE and PEIE bits of the
INTCON register.
If 9-bit reception is desired, set the RX9 bit.
Set the CREN bit to enable reception.
The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCxSTA
register.
Retrieve the eight Least Significant bits from the
receive FIFO by reading the RCxREG register.
If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCxSTA
register or by clearing the SPEN bit which resets
the EUSART.
2.
3.
• Sleep
• CREN bit is always set, therefore the receiver is
never Idle
• SREN bit, which is a “don’t care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCxREG register. If the RCIE enable bit is set,
the interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
Synchronous Slave Reception Setup
4.
5.
6.
7.
8.
9.
TABLE 33-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE
RECEPTION
Name
ANSELA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
—
—
—
ANSA4
—
—
—
SCKP
(1)
ANSELB
ANSB<7:4>
BAUD1CON
CKPPS
ABDOVF
RCIDL
—
—
—
—
Bit 1
Bit 0
ANSA<2:0>
—
ANSC<7:6>(1)
ANSELC
Bit 2
—
—
142
—
148
ABDEN
450
ANSC<3:0>
BRG16
—
WUE
Register
on Page
153
CKPPS<4:0>
159, 161
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
104
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
105
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
INTCON
RC1REG
EUSART Receive Data Register
RC1STA
SPEN
RX9
SREN
RXPPS
—
—
—
TRISA
—
—
TRISB(1)
CREN
TRISA<5:4>
TRISB<7:4>
CSRC
TX1STA
Legend:
*
Note 1:
2:
TX9
FERR
OERR
RX9D
RXPPS<4:0>
—(2)
—
TRISC<7:6>(1)
TRISC
ADDEN
TRISA<2:0>
—
SYNC
SENDB
BRGH
449
159, 161
141
—
—
147
TRMT
TX9D
448
TRISC<5:0>
TXEN
108
444*
152
— = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Page provides register information.
PIC16(L)F1768/9 only.
Unimplemented, read as ‘1’.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 467
PIC16(L)F1764/5/8/9
33.6
EUSART Operation During Sleep
The EUSART will remain active during Sleep only in the
Synchronous Slave mode. All other modes require the
system clock and therefore, cannot generate the
necessary signals to run the Transmit or Receive Shift
registers during Sleep.
Synchronous Slave mode uses an externally generated
clock to run the Transmit and Receive Shift registers.
33.6.1
SYNCHRONOUS RECEIVE DURING
SLEEP
To receive during Sleep, all the following conditions
must be met before entering Sleep mode:
• RCxSTA and TXxSTA Control registers must be
configured for synchronous slave reception (see
Section 33.5.2.4 “Synchronous Slave
Reception Setup”).
• If interrupts are desired, set the RCIE bit of the
PIE1 register, and the GIE and PEIE bits of the
INTCON register.
• The RCIF interrupt flag must be cleared by reading RCxREG to unload any pending characters in
the receive buffer.
Upon entering Sleep mode, the device will be ready to
accept data and clocks on the RX/DT and TX/CK pins,
respectively. When the data word has been completely
clocked in by the external device, the RCIF interrupt
flag bit of the PIR1 register will be set; thereby, waking
the processor from Sleep.
33.6.2
SYNCHRONOUS TRANSMIT
DURING SLEEP
To transmit during Sleep, all the following conditions
must be met before entering Sleep mode:
• The RCxSTA and TXxSTA Control registers must
be configured for synchronous slave transmission
(see Section 33.5.2.2 “Synchronous Slave
Transmission Setup”).
• The TXIF interrupt flag must be cleared by writing
the output data to the TXxREG; thereby, filling the
TSR and transmit buffer.
• If interrupts are desired, set the TXIE bit of the
PIE1 register and the PEIE bit of the INTCON
register.
• Interrupt enable bits, TXIE of the PIE1 register
and PEIE of the INTCON register, must set.
Upon entering Sleep mode, the device will be ready to
accept clocks on the TX/CK pin and transmit data on
the RX/DT pin. When the data word in the TSR has
been completely clocked out by the external device, the
pending byte in the TXxREG will transfer to the TSR
and the TXIF flag will be set; thereby, waking the
processor from Sleep. At this point, the TXxREG is
available to accept another character for transmission,
which will clear the TXIF flag.
Upon waking from Sleep, the instruction following the
SLEEP instruction will be executed. If the Global
Interrupt Enable (GIE) bit is also set, then the Interrupt
Service Routine at address, 0004h, will be called.
Upon waking from Sleep, the instruction following the
SLEEP instruction will be executed. If the Global
Interrupt Enable (GIE) bit of the INTCON register is
also set, then the Interrupt Service Routine at address,
004h, will be called.
DS40001775B-page 468
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
34.0
IN-CIRCUIT SERIAL
PROGRAMMING™ (ICSP™)
ICSP™ programming allows customers to manufacture
circuit boards with unprogrammed devices. Programming
can be done after the assembly process, allowing the
device to be programmed with the most recent firmware
or a custom firmware. Five pins are needed for ICSP™
programming:
• ICSPCLK
• ICSPDAT
• MCLR/VPP
• VDD
• VSS
In Program/Verify mode, the program memory, User
IDs and the Configuration Words are programmed
through serial communications. The ICSPDAT pin is a
bidirectional I/O used for transferring the serial data
and the ICSPCLK pin is the clock input. For more
information on ICSP™ refer to the “PIC16(L)F170X
Memory Programming Specification” (DS40001683).
34.1
High-Voltage Programming Entry
Mode
The device is placed into High-Voltage Programming
Entry mode by holding the ICSPCLK and ICSPDAT
pins low, then raising the voltage on MCLR/VPP to VIHH.
34.2
Low-Voltage Programming Entry
Mode
The Low-Voltage Programming Entry mode allows the
PIC® Flash MCUs to be programmed using VDD only,
without high voltage. When the LVP bit of Configuration
Words is set to ‘1’, the low-voltage ICSP programming
entry is enabled. To disable the Low-Voltage ICSP
mode, the LVP bit must be programmed to ‘0’.
Entry into the Low-Voltage Programming Entry mode
requires the following steps:
1.
2.
MCLR is brought to VIL.
A 32-bit key sequence is presented on
ICSPDAT, while clocking ICSPCLK.
34.3
Common Programming Interfaces
Connection to a target device is typically done through
an ICSP header. A commonly found connector on
development tools is the RJ-11 in the 6P6C (6-pin,
6-connector) configuration. See Figure 34-1.
FIGURE 34-1:
VDD
ICD RJ-11 STYLE
CONNECTOR INTERFACE
ICSPDAT
NC
2 4 6
ICSPCLK
1 3 5
Target
VPP/MCLR
VSS
PC Board
Bottom Side
Pin Description*
1 = VPP/MCLR
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
Another connector often found in use with the PICkit™
programmers is a standard 6-pin header with 0.1 inch
spacing. Refer to Figure 34-2.
For additional interface recommendations, refer to your
specific device programmer manual prior to PCB
design.
It is recommended that isolation devices be used to
separate the programming pins from other circuitry.
The type of isolation is highly dependent on the specific
application and may include devices, such as resistors,
diodes or even jumpers. See Figure 34-3 for more
information.
Once the key sequence is complete, MCLR must be
held at VIL for as long as Program/Verify mode is to be
maintained.
If Low-Voltage Programming mode is enabled
(LVP = 1), the MCLR Reset function is automatically
enabled and cannot be disabled. See Section 6.5
“MCLR” for more information.
The LVP bit can only be reprogrammed to ‘0’ by using
the High-Voltage Programming mode.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 469
PIC16(L)F1764/5/8/9
FIGURE 34-2:
PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE
Pin 1 Indicator
Pin Description*
1 = VPP/MCLR
1
2
3
4
5
6
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
*
FIGURE 34-3:
The 6-pin header (0.100" spacing) accepts 0.025" square pins.
TYPICAL CONNECTION FOR ICSP™ PROGRAMMING
External
Programming
Signals
Device to be
Programmed
VDD
VDD
VDD
VPP
MCLR/VPP
VSS
VSS
Data
ICSPDAT
Clock
ICSPCLK
*
*
*
To Normal Connections
* Isolation devices (as required).
DS40001775B-page 470
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
35.0
INSTRUCTION SET SUMMARY
35.1
Read-Modify-Write Operations
• Byte Oriented
• Bit Oriented
• Literal and Control
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified and
the result is stored according to either the instruction or
the destination designator, ‘d’. A read operation is
performed on a register even if the instruction writes to
that register.
The literal and control category contains the most
varied instruction word format.
TABLE 35-1:
Each instruction is a 14-bit word containing the operation code (opcode) and all required operands. The
opcodes are broken into three broad categories.
Table 35-3 lists the instructions recognized by the
MPASMTM assembler.
All instructions are executed within a single instruction
cycle, with the following exceptions, which may take
two or three cycles:
• Subroutine takes two cycles (CALL, CALLW)
• Returns from interrupts or subroutines take two
cycles (RETURN, RETLW, RETFIE)
• Program branching takes two cycles (GOTO, BRA,
BRW, BTFSS, BTFSC, DECFSZ, INCSFZ)
• One additional instruction cycle will be used when
any instruction references an indirect file register
and the file select register is pointing to program
memory.
One instruction cycle consists of four oscillator cycles;
for an oscillator frequency of 4 MHz, this gives a
nominal instruction execution rate of 1 MHz.
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
OPCODE FIELD
DESCRIPTIONS
Field
f
Description
Register file address (0x00 to 0x7F).
W
Working register (accumulator).
b
Bit address within an 8-bit file register.
k
Literal field, constant data or label
x
Don’t care location (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
n
FSR or INDF number (0-1).
mm
Pre/Post-Increment/Decrement mode
selection.
TABLE 35-2:
ABBREVIATION
DESCRIPTIONS
Field
PC
TO
C
DC
Z
PD
 2014-2015 Microchip Technology Inc.
Description
Program Counter
Time-out bit
Carry bit
Digit Carry bit
Zero bit
Power-Down bit
DS40001775B-page 471
PIC16(L)F1764/5/8/9
FIGURE 35-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8 7 6
OPCODE
d
f (FILE #)
0
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
0
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
13
OPCODE
8
7
0
k (literal)
k = 8-bit immediate value
CALL and GOTO instructions only
13
11 10
OPCODE
0
k (literal)
k = 11-bit immediate value
MOVLP instruction only
13
OPCODE
7
6
0
k (literal)
k = 7-bit immediate value
MOVLB instruction only
13
OPCODE
5 4
0
k (literal)
k = 5-bit immediate value
BRA instruction only
13
OPCODE
9
8
0
k (literal)
k = 9-bit immediate value
FSR Offset instructions
13
OPCODE
7
6
n
5
0
k (literal)
n = appropriate FSR
k = 6-bit immediate value
FSR Increment instructions
13
OPCODE
3
2 1
0
n m (mode)
n = appropriate FSR
m = 2-bit mode value
OPCODE only
13
0
OPCODE
DS40001775B-page 472
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
TABLE 35-3:
PIC16(L)F1764/5/8/9 INSTRUCTION SET
14-Bit Opcode
Mnemonic,
Operands
Description
Cycles
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
ADDWF
ADDWFC
ANDWF
ASRF
LSLF
LSRF
CLRF
CLRW
COMF
DECF
INCF
IORWF
MOVF
MOVWF
RLF
RRF
SUBWF
SUBWFB
SWAPF
XORWF
f, d
f, d
f, d
f, d
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
Add W and f
Add with Carry W and f
AND W with f
Arithmetic Right Shift
Logical Left Shift
Logical Right Shift
Clear f
Clear W
Complement f
Decrement f
Increment f
Inclusive OR W with f
Move f
Move W to f
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Subtract with Borrow W from f
Swap nibbles in f
Exclusive OR W with f
DECFSZ
INCFSZ
f, d
f, d
Decrement f, Skip if 0
Increment f, Skip if 0
BCF
BSF
f, b
f, b
Bit Clear f
Bit Set f
BTFSC
BTFSS
f, b
f, b
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
ADDLW
ANDLW
IORLW
MOVLB
MOVLP
MOVLW
SUBLW
XORLW
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Inclusive OR literal with W
Move literal to BSR
Move literal to PCLATH
Move literal to W
Subtract W from literal
Exclusive OR literal with W
Note 1:
If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
If this instruction addresses an INDFn register and the MSb of the corresponding FSRn is set, this instruction will require
one additional instruction cycle.
See Table 35-3 for the MOVIW and MOVWI instruction descriptions.
00
11
00
11
11
11
00
00
00
00
00
00
00
00
00
00
00
11
00
00
0111
1101
0101
0111
0101
0110
0001
0001
1001
0011
1010
0100
1000
0000
1101
1100
0010
1011
1110
0110
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0000
dfff
dfff
dfff
dfff
dfff
1fff
dfff
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
00xx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
C, DC, Z
C, DC, Z
Z
C, Z
C, Z
C, Z
Z
Z
Z
Z
Z
Z
Z
C
C
C, DC, Z
C, DC, Z
Z
2
2
2
2
2
2
2
2
2
2
2
2
BYTE ORIENTED SKIP OPERATIONS
1(2)
1(2)
00
00
1, 2
1, 2
1011 dfff ffff
1111 dfff ffff
BIT-ORIENTED FILE REGISTER OPERATIONS
1
1
00bb bfff ffff
01bb bfff ffff
2
2
01
01
10bb bfff ffff
11bb bfff ffff
1, 2
1, 2
11
11
11
00
11
11
11
11
1110
1001
1000
0000
0001
0000
1100
1010
01
01
BIT-ORIENTED SKIP OPERATIONS
1 (2)
1 (2)
LITERAL OPERATIONS
2:
3:
 2014-2015 Microchip Technology Inc.
1
1
1
1
1
1
1
1
kkkk
kkkk
kkkk
001k
1kkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
C, DC, Z
Z
Z
C, DC, Z
Z
DS40001775B-page 473
PIC16(L)F1764/5/8/9
TABLE 35-3:
PIC16(L)F1764/5/8/9 INSTRUCTION SET (CONTINUED)
14-Bit Opcode
Mnemonic,
Operands
Description
Cycles
MSb
LSb
Status
Affected
Notes
CONTROL OPERATIONS
BRA
BRW
CALL
CALLW
GOTO
RETFIE
RETLW
RETURN
k
–
k
–
k
k
k
–
Relative Branch
Relative Branch with W
Call Subroutine
Call Subroutine with W
Go to address
Return from interrupt
Return with literal in W
Return from Subroutine
2
2
2
2
2
2
2
2
11
00
10
00
10
00
11
00
001k
0000
0kkk
0000
1kkk
0000
0100
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
1011
kkkk
1010
kkkk
1001
kkkk
1000
00
00
00
00
00
00
0000
0000
0000
0000
0000
0000
0110
0000
0110
0000
0110
0110
0100 TO, PD
0000
0010
0001
0011 TO, PD
0fff
INHERENT OPERATIONS
CLRWDT
NOP
OPTION
RESET
SLEEP
TRIS
–
–
–
–
–
f
Clear Watchdog Timer
No Operation
Load OPTION_REG register with W
Software device Reset
Go into Standby mode
Load TRIS register with W
1
1
1
1
1
1
C-COMPILER OPTIMIZED
ADDFSR
MOVIW
n, k
n mm
MOVWI
k[n]
n mm
k[n]
Note 1:
2:
3:
Add Literal k to FSRn
Move Indirect FSRn to W with pre/post inc/dec
modifier, mm
Move INDFn to W, Indexed Indirect.
Move W to Indirect FSRn with pre/post inc/dec
modifier, mm
Move W to INDFn, Indexed Indirect.
1
1
11
00
0001 0nkk kkkk
0000 0001 0nmm Z
2, 3
1
1
11
00
1111 0nkk kkkk Z
0000 0001 1nmm
2
2, 3
1
11
1111 1nkk kkkk
2
If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
If this instruction addresses an INDFn register and the MSb of the corresponding FSRn is set, this instruction will require
one additional instruction cycle.
See Table 35-3 for the MOVIW and MOVWI instruction descriptions.
DS40001775B-page 474
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
35.2
Instruction Descriptions
ADDFSR
Add Literal to FSRn
ANDLW
AND literal with W
Syntax:
[ label ] ADDFSR FSRn, k
Syntax:
[ label ] ANDLW
Operands:
-32  k  31
n  [ 0, 1]
Operands:
0  k  255
Operation:
FSR(n) + k  FSR(n)
Status Affected:
None
Description:
The signed 6-bit literal ‘k’ is added to
the contents of the FSRnH:FSRnL
register pair.
k
Operation:
(W) .AND. (k)  (W)
Status Affected:
Z
Description:
The contents of W register are
AND’ed with the 8-bit literal ‘k’. The
result is placed in the W register.
ANDWF
AND W with f
FSRn is limited to the range
0000h-FFFFh. Moving beyond these
bounds will cause the FSRn to
wrap around.
ADDLW
Add literal and W
Syntax:
[ label ] ADDLW
Operands:
0  k  255
Operation:
(W) + k  (W)
Status Affected:
Description:
k
Syntax:
[ label ] ANDWF
Operands:
0  f  127
d 0,1
C, DC, Z
Operation:
(W) .AND. (f)  (destination)
The contents of the W register are
added to the 8-bit literal ‘k’ and the
result is placed in the W register.
Status Affected:
Z
Description:
AND the W register with register ‘f’. If
‘d’ is ‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
ADDWF
Add W and f
ASRF
Arithmetic Right Shift
Syntax:
[ label ] ADDWF
Syntax:
[ label ] ASRF
Operands:
0  f  127
d 0,1
Operands:
0  f  127
d [0,1]
Operation:
(f<7>) dest<7>
(f<7:1>)  dest<6:0>,
(f<0>)  C,
Status Affected:
C, Z
Description:
The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. The MSb remains unchanged. If
‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in
register ‘f’.
f,d
Operation:
(W) + (f)  (destination)
Status Affected:
C, DC, Z
Description:
Add the contents of the W register
with register ‘f’. If ‘d’ is ‘0’, the result is
stored in the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
ADDWFC
ADD W and CARRY bit to f
Syntax:
[ label ] ADDWFC
Operands:
0  f  127
d [0,1]
Operation:
(W) + (f) + (C)  dest
f {,d}
register f
C
f {,d}
Status Affected:
C, DC, Z
Description:
Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
 2014-2015 Microchip Technology Inc.
f,d
DS40001775B-page 475
PIC16(L)F1764/5/8/9
BTFSC
Bit Test f, Skip if Clear
Syntax:
[ label ] BTFSC f,b
0  f  127
0b7
Operands:
0  f  127
0b7
0  (f<b>)
Operation:
skip if (f<b>) = 0
Status Affected:
None
Status Affected:
None
Description:
Bit ‘b’ in register ‘f’ is cleared.
Description:
If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the next
instruction is discarded, and a NOP is
executed instead, making this a
2-cycle instruction.
BRA
Relative Branch
BTFSS
Bit Test f, Skip if Set
Syntax:
[ label ] BRA label
[ label ] BRA $+k
Syntax:
[ label ] BTFSS f,b
Operands:
Operands:
-256  label - PC + 1  255
-256  k  255
0  f  127
0b<7
Operation:
skip if (f<b>) = 1
Operation:
(PC) + 1 + k  PC
Status Affected:
None
Status Affected:
None
Description:
Description:
Add the signed 9-bit literal ‘k’ to the
PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 1 + k. This instruction is a
2-cycle instruction. This branch has a
limited range.
If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is executed.
If bit ‘b’ is ‘1’, then the next instruction
is discarded and a NOP is executed
instead, making this a 2-cycle
instruction.
BRW
Relative Branch with W
Syntax:
[ label ] BRW
BCF
Bit Clear f
Syntax:
[ label ] BCF
Operands:
Operation:
f,b
Operands:
None
Operation:
(PC) + (W)  PC
Status Affected:
None
Description:
Add the contents of W (unsigned) to
the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 1 + (W). This instruction is a
2-cycle instruction.
BSF
Bit Set f
Syntax:
[ label ] BSF
Operands:
0  f  127
0b7
Operation:
1  (f<b>)
Status Affected:
None
Description:
Bit ‘b’ in register ‘f’ is set.
DS40001775B-page 476
f,b
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
CALL
Call Subroutine
CLRWDT
Clear Watchdog Timer
[ label ] CLRWDT
Syntax:
[ label ] CALL k
Syntax:
Operands:
0  k  2047
Operands:
None
Operation:
(PC)+ 1 TOS,
k  PC<10:0>,
(PCLATH<6:3>)  PC<14:11>
Operation:
Status Affected:
None
00h  WDT
0  WDT prescaler,
1  TO
1  PD
Description:
Call Subroutine. First, return address
(PC + 1) is pushed onto the stack.
The 11-bit immediate address is
loaded into PC bits<10:0>. The upper
bits of the PC are loaded from
PCLATH. CALL is a 2-cycle
instruction.
Status Affected:
TO, PD
Description:
CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler
of the WDT. Status bits TO and PD
are set.
CALLW
Subroutine Call With W
COMF
Complement f
Syntax:
[ label ] CALLW
Syntax:
[ label ] COMF
Operands:
None
Operands:
Operation:
(PC) +1  TOS,
(W)  PC<7:0>,
(PCLATH<6:0>) PC<14:8>
0  f  127
d  [0,1]
Operation:
(f)  (destination)
Status Affected:
Z
Status Affected:
None
Description:
Description:
Subroutine call with W. First, the
return address (PC + 1) is pushed
onto the return stack. Then, the
contents of W are loaded into
PC<7:0>, and the contents of
PCLATH into PC<14:8>. CALLW is a
2-cycle instruction.
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
CLRF
Clear f
DECF
Decrement f
f
f,d
Syntax:
[ label ] CLRF
Syntax:
[ label ] DECF f,d
Operands:
0  f  127
Operands:
Operation:
00h  (f)
1Z
0  f  127
d  [0,1]
Operation:
(f) - 1  (destination)
Status Affected:
Z
Status Affected:
Z
Description:
The contents of register ‘f’ are cleared
and the Z bit is set.
Description:
Decrement register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If ‘d’
is ‘1’, the result is stored back in
register ‘f’.
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
None
Operation:
00h  (W)
1Z
Status Affected:
Z
Description:
W register is cleared. Zero bit (Z) is
set.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 477
PIC16(L)F1764/5/8/9
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Syntax:
[ label ]
Operands:
0  f  127
d  [0,1]
Operands:
0  f  127
d  [0,1]
Operation:
(f) - 1  (destination);
skip if result = 0
Operation:
(f) + 1  (destination),
skip if result = 0
Status Affected:
None
Status Affected:
None
Description:
The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, then a
NOP is executed instead, making it a
2-cycle instruction.
Description:
The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, a NOP is
executed instead, making it a 2-cycle
instruction.
GOTO
Unconditional Branch
IORLW
Inclusive OR literal with W
Syntax:
[ label ]
Syntax:
[ label ]
GOTO k
INCFSZ f,d
IORLW k
Operands:
0  k  2047
Operands:
0  k  255
Operation:
k  PC<10:0>
PCLATH<6:3>  PC<14:11>
Operation:
(W) .OR. k  (W)
Status Affected:
Z
Status Affected:
None
Description:
Description:
GOTO is an unconditional branch. The
11-bit immediate value is loaded into
PC bits <10:0>. The upper bits of PC
are loaded from PCLATH<4:3>. GOTO
is a 2-cycle instruction.
The contents of the W register are
OR’ed with the 8-bit literal ‘k’. The
result is placed in the W register.
INCF
Increment f
IORWF
Inclusive OR W with f
Syntax:
[ label ]
Operands:
0  f  127
d  [0,1]
Syntax:
[ label ]
Operands:
0  f  127
d  [0,1]
Operation:
(f) + 1  (destination)
Operation:
(W) .OR. (f)  (destination)
Status Affected:
Z
Status Affected:
Z
Description:
The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
Description:
Inclusive OR the W register with register ‘f’. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
DS40001775B-page 478
INCF f,d
IORWF
f,d
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
LSLF
Logical Left Shift
MOVF
f {,d}
Move f
Syntax:
[ label ] LSLF
Syntax:
[ label ]
Operands:
0  f  127
d [0,1]
Operands:
0  f  127
d  [0,1]
Operation:
(f<7>)  C
(f<6:0>)  dest<7:1>
0  dest<0>
Operation:
(f)  (dest)
Status Affected:
C, Z
Description:
The contents of register ‘f’ are shifted
one bit to the left through the Carry flag.
A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’,
the result is placed in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
C
register f
0
Status Affected:
Z
Description:
The contents of register f are moved
to a destination dependent upon the
status of d. If d = 0, destination is W
register. If d = 1, the destination is file
register f itself. d = 1 is useful to test a
file register since status flag Z is
affected.
Words:
1
Cycles:
1
Example:
Logical Right Shift
Syntax:
[ label ] LSRF
Operands:
0  f  127
d [0,1]
Operation:
0  dest<7>
(f<7:1>)  dest<6:0>,
(f<0>)  C,
Status Affected:
C, Z
Description:
The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. A ‘0’ is shifted into the MSb. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is stored back in register ‘f’.
f {,d}
register f
 2014-2015 Microchip Technology Inc.
MOVF
FSR, 0
After Instruction
W = value in FSRn register
Z = 1
LSRF
0
MOVF f,d
C
DS40001775B-page 479
PIC16(L)F1764/5/8/9
MOVIW
Move INDFn to W
Syntax:
[ label ] MOVIW ++FSRn
[ label ] MOVIW --FSRn
[ label ] MOVIW FSRn++
[ label ] MOVIW FSRn-[ label ] MOVIW k[FSRn]
Operands:
n  [0,1]
mm  [00,01, 10, 11]
-32  k  31
Operation:
INDFn  W
Effective address is determined by
• FSRn + 1 (preincrement)
• FSRn – 1 (predecrement)
• FSRn + k (relative offset)
After the Move, the FSRn value will be
either:
• FSRn + 1 (all increments)
• FSRn – 1 (all decrements)
• Unchanged
Status Affected:
MOVLP
Syntax:
[ label ] MOVLP k
Operands:
0  k  127
Operation:
k  PCLATH
Status Affected:
None
Description:
The 7-bit literal ‘k’ is loaded into the
PCLATH register.
MOVLW
Move literal to W
Syntax:
[ label ]
Operands:
0  k  255
k  (W)
Status Affected:
None
Description:
The 8-bit literal ‘k’ is loaded into W register. The “don’t cares” will assemble as
‘0’s.
Words:
1
1
Mode
Syntax
mm
Cycles:
Preincrement
++FSRn
00
Example:
--FSRn
01
Postincrement
FSRn++
10
Postdecrement
FSRn--
11
Description:
This instruction is used to move data
between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
Note: The INDFn registers are not
physical registers. Any instruction that
accesses an INDFn register actually
accesses the register at the address
specified by the FSRn.
FSRn is limited to the range
0000h-FFFFh.
Incrementing/decrementing it beyond
these bounds will cause it to
wrap around.
MOVLB
MOVLW k
Operation:
Z
Predecrement
Move literal to PCLATH
MOVLW
0x5A
After Instruction
W =
MOVWF
Move W to f
Syntax:
[ label ]
MOVWF
Operands:
0  f  127
Operation:
(W)  (f)
0x5A
f
Status Affected:
None
Description:
Move data from W register to register
‘f’.
Words:
1
Cycles:
1
Example:
MOVWF
OPTION_REG
Before Instruction
OPTION_REG = 0xFF
W = 0x4F
After Instruction
OPTION_REG = 0x4F
W = 0x4F
Move literal to BSR
Syntax:
[ label ] MOVLB k
Operands:
0  k  31
Operation:
k  BSR
Status Affected:
None
Description:
The 5-bit literal ‘k’ is loaded into the
Bank Select Register (BSR).
DS40001775B-page 480
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
MOVWI
Move W to INDFn
NOP
No Operation
Syntax:
[ label ] MOVWI ++FSRn
[ label ] MOVWI --FSRn
[ label ] MOVWI FSRn++
[ label ] MOVWI FSRn-[ label ] MOVWI k[FSRn]
Syntax:
[ label ]
NOP
Operands:
None
Operation:
No operation
Status Affected:
None
n  [0,1]
mm  [00,01, 10, 11]
-32  k  31
Description:
No operation.
Words:
1
W  INDFn
Effective address is determined by
• FSRn + 1 (preincrement)
• FSRn – 1 (predecrement)
• FSRn + k (relative offset)
After the Move, the FSRn value will be
either:
• FSRn + 1 (all increments)
• FSRn – 1 (all decrements)
Unchanged
Cycles:
1
Status Affected:
None
Mode
Syntax
Operands:
Operation:
mm
Example:
NOP
OPTION
Load OPTION_REG Register
with W
Syntax:
[ label ] OPTION
Operands:
None
Operation:
(W)  OPTION_REG
Status Affected:
None
Description:
Move data from W register to
OPTION_REG register.
1
Preincrement
++FSRn
00
Predecrement
--FSRn
01
Postincrement
FSRn++
10
Words:
Postdecrement
FSRn--
11
Cycles:
1
Example:
OPTION
Description:
This instruction is used to move data
between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
Note: The INDFn registers are not
physical registers. Any instruction that
accesses an INDFn register actually
accesses the register at the address
specified by the FSRn.
FSRn is limited to the range
0000h-FFFFh.
Incrementing/decrementing it beyond
these bounds will cause it to
wrap-around.
The increment/decrement operation on
FSRn WILL NOT affect any Status bits.
 2014-2015 Microchip Technology Inc.
Before Instruction
OPTION_REG = 0xFF
W = 0x4F
After Instruction
OPTION_REG = 0x4F
W = 0x4F
RESET
Software Reset
Syntax:
[ label ] RESET
Operands:
None
Operation:
Execute a device Reset. Resets the
RI flag of the PCON register.
Status Affected:
None
Description:
This instruction provides a way to
execute a hardware Reset by
software.
DS40001775B-page 481
PIC16(L)F1764/5/8/9
RETFIE
Return from Interrupt
RETFIE k
RETURN
Return from Subroutine
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
None
Operation:
TOS  PC,
1  GIE
Operation:
TOS  PC
Status Affected:
None
Description:
Return from subroutine. The stack is
POPed and the top of the stack (TOS)
is loaded into the Program Counter.
This is a 2-cycle instruction.
Status Affected:
None
Description:
Return from Interrupt. Stack is POPed
and Top-of-Stack (TOS) is loaded in
the PC. Interrupts are enabled by
setting Global Interrupt Enable bit,
GIE (INTCON<7>). This is a 2-cycle
instruction.
Words:
1
Cycles:
2
Example:
RETFIE
After Interrupt
PC =
GIE =
RETLW
RETURN
TOS
1
Return with literal in W
RLF
Rotate Left f through Carry
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0  k  255
Operands:
Operation:
k  (W);
TOS  PC
0  f  127
d  [0,1]
Operation:
See description below
Status Affected:
None
Status Affected:
C
Description:
The W register is loaded with the 8-bit
literal ‘k’. The Program Counter is
loaded from the top of the stack (the
return address). This is a 2-cycle
instruction.
Description:
The contents of register ‘f’ are rotated
one bit to the left through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Words:
1
Cycles:
2
Example:
TABLE
RETLW k
RLF
C
CALL TABLE;W contains table
;offset value
•
;W now has table value
•
•
ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
•
•
•
RETLW kn ; End of table
Before Instruction
W =
After Instruction
W =
DS40001775B-page 482
Words:
1
Cycles:
1
Example:
RLF
f,d
Register f
REG1,0
Before Instruction
REG1
C
After Instruction
REG1
W
C
=
=
1110 0110
0
=
=
=
1110 0110
1100 1100
1
0x07
value of k8
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
RRF
Rotate Right f through Carry
RRF f,d
SUBLW
Subtract W from literal
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0  f  127
d  [0,1]
Operands:
0 k 255
Operation:
k - (W) W)
Operation:
See description below
Status Affected:
C, DC, Z
Status Affected:
C
Description:
Description:
The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
The W register is subtracted (2’s
complement method) from the 8-bit
literal ‘k’. The result is placed in the W
register.
C
Register f
SUBLW k
C=0
Wk
C=1
Wk
DC = 0
W<3:0>  k<3:0>
DC = 1
W<3:0>  k<3:0>
SLEEP
Enter Sleep mode
SUBWF
Subtract W from f
Syntax:
[ label ]
Operands:
0 f 127
d  [0,1]
Syntax:
[ label ]
Operands:
None
SLEEP
Operation:
00h  WDT,
0  WDT prescaler,
1  TO,
0  PD
Status Affected:
TO, PD
Description:
The Power-Down Status bit, PD, is
cleared. Time-out Status bit, TO, is
set. Watchdog Timer and its
prescaler are cleared.
The processor is put into Sleep mode
with the oscillator stopped.
 2014-2015 Microchip Technology Inc.
SUBWF f,d
Operation:
(f) - (W) destination)
Status Affected:
C, DC, Z
Description:
Subtract (2’s complement method) W
register from register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If ‘d’ is
‘1’, the result is stored back in register
‘f.
C=0
Wf
C=1
Wf
DC = 0
W<3:0>  f<3:0>
DC = 1
W<3:0>  f<3:0>
SUBWFB
Subtract W from f with Borrow
Syntax:
SUBWFB
Operands:
0  f  127
d  [0,1]
Operation:
(f) – (W) – (B) dest
f {,d}
Status Affected:
C, DC, Z
Description:
Subtract W and the Borrow flag (Carry)
from register ‘f’ (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’.
DS40001775B-page 483
PIC16(L)F1764/5/8/9
SWAPF
Swap Nibbles in f
XORLW
Exclusive OR literal with W
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0  f  127
d  [0,1]
Operands:
0 k 255
(f<3:0>)  (destination<7:4>),
(f<7:4>)  (destination<3:0>)
Operation:
(W) .XOR. k W)
Status Affected:
Z
Description:
The contents of the W register are
XOR’ed with the 8-bit literal ‘k’. The
result is placed in the W register.
Operation:
SWAPF f,d
Status Affected:
None
Description:
The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is ‘0’,
the result is placed in the W register. If
‘d’ is ‘1’, the result is placed in register
‘f’.
TRIS
Load TRIS Register with W
XORWF
XORLW k
Exclusive OR W with f
Syntax:
[ label ] TRIS f
Syntax:
[ label ]
Operands:
5f7
Operands:
Operation:
(W)  TRIS register ‘f’
0  f  127
d  [0,1]
Status Affected:
None
Operation:
(W) .XOR. (f) destination)
Description:
Move data from W register to TRIS
register.
When ‘f’ = 5, TRISA is loaded.
When ‘f’ = 6, TRISB is loaded.
When ‘f’ = 7, TRISC is loaded.
DS40001775B-page 484
XORWF
f,d
Status Affected:
Z
Description:
Exclusive OR the contents of the W
register with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If ‘d’
is ‘1’, the result is stored back in
register ‘f’.
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
36.0
ELECTRICAL SPECIFICATIONS
36.1
Absolute Maximum Ratings(†)
Ambient temperature under bias............................................................................................................ -40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on pins with respect to VSS
on VDD pin
PIC16F1764/5/8/9 ........................................................................................................... -0.3V to +6.5V
PIC16LF1764/5/8/9 ......................................................................................................... -0.3V to +4.0V
on MCLR pin ................................................................................................................................. -0.3V to +9.0V
on all other pins .................................................................................................................. -0.3V to (VDD + 0.3V)
Maximum current
on VSS pin(1)
-40°C  TA  +85°C .................................................................................................................... 250 mA
+85°C  TA  +125°C ................................................................................................................... 85 mA
on VDD pin(1)
-40°C  TA  +85°C .................................................................................................................... 250 mA
+85°C  TA  +125°C ................................................................................................................... 85 mA
Sunk by any standard I/O pin ..................................................................................................................... 50 mA
Sourced by any standard I/O pin ................................................................................................................ 50 mA
Sunk by any high-current I/O pin .............................................................................................................. 100 mA
Sourced by any high-current I/O pin ......................................................................................................... 100 mA
Sourced by any op amp output pin ........................................................................................................... 100 mA
Clamp current, IK (VPIN < 0 or VPIN > VDD) ......................................................................................................... 20 mA
Total power dissipation(2) .....................................................................................................................................800 mW
Note 1:
2:
Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be
limited by the device package power dissipation characterizations, see Table 36-6: Thermal
Characteristics to calculate device specifications.
Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOl x IOL).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 485
PIC16(L)F1764/5/8/9
36.2
Standard Operating Conditions
The standard operating conditions for any device are defined as:
Operating Voltage:
Operating Temperature:
VDDMIN VDD VDDMAX
TA_MIN TA TA_MAX
VDD – Operating Supply Voltage(1)
PIC16LF1764/5/8/9
VDDMIN (FOSC  16 MHz) ............................................................................................................... +1.8V
VDDMIN (FOSC  16 MHz) ............................................................................................................... +2.5V
VDDMAX .......................................................................................................................................... +3.6V
PIC16F1764/5/8/9
VDDMIN (FOSC  16 MHz) ............................................................................................................... +2.3V
VDDMIN (FOSC 16 MHz) ............................................................................................................... +2.5V
VDDMAX .......................................................................................................................................... +5.5V
TA – Operating Ambient Temperature Range
Industrial Temperature
TA_MIN ............................................................................................................................................ -40°C
TA_MAX .......................................................................................................................................... +85°C
Extended Temperature
TA_MIN ............................................................................................................................................ -40°C
TA_MAX ........................................................................................................................................ +125°C
Note 1:
See Parameter D001, DS Characteristics: Supply Voltage.
DS40001775B-page 486
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C, PIC16F1764/5/8/9 ONLY
FIGURE 36-1:
VDD (V)
5.5
2.5
2.3
0
4
10
16
32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 36-7 for each Oscillator mode’s supported frequencies.
VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C, PIC16LF1764/5/8/9 ONLY
FIGURE 36-2:
VDD (V)
3.6
2.5
1.8
0
4
10
16
32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 36-7 for each Oscillator mode’s supported frequencies.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 487
PIC16(L)F1764/5/8/9
36.3
DC Characteristics
TABLE 36-1:
SUPPLY VOLTAGE
PIC16LF1764/5/8/9
Standard Operating Conditions (unless otherwise stated)
PIC16F1764/5/8/9
Param.
No.
D001
Sym.
VDD
Characteristic
PIC16F1764/5/8/9
VDR
Max.
Units
Conditions
VDDMIN
1.8
2.5
—
—
VDDMAX
3.6
3.6
V
V
FOSC  16 MHz
FOSC  32 MHz (Note 2)
2.3
2.5
—
—
5.5
5.5
V
V
FOSC  16 MHz:
FOSC  32 MHz (Note 2)
1.5
—
—
V
Device in Sleep mode
1.7
—
—
V
Device in Sleep mode
—
1.6
—
V
—
1.6
—
V
—
0.8
—
V
—
1.5
—
V
-4
-4
-5
—
—
—
+4
+4
+5
%
%
%
0.05
—
—
V/ms
RAM Data Retention Voltage(1)
D002*
D002A* VPOR
Typ†
Supply Voltage
D001
D002*
Min.
Power-on Reset Release Voltage(3)
D002A*
D002B* VPORR* Power-on Reset Rearm
Voltage(3)
D002B*
D003
VFVR
Fixed Voltage Reference Voltage(4)
D004*
SVDD
VDD Rise Rate(2)
1x gain, 1.024, VDD 2.5V, -40°C to +85°C
2x gain, 2.048, VDD 2.5V, -40°C to +85°C
4x gain, 4.096, VDD 4.5V, -40°C to +85°C
Ensures that the Power-on Reset
signal is released properly
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2: PLL required for 32 MHz operation.
3: See Figure 36-3: POR and POR Rearm with Slow Rising VDD.
4: Industrial temperature range only.
DS40001775B-page 488
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
FIGURE 36-3:
POR AND POR REARM WITH SLOW RISING VDD
VDD
VPOR
VPORR
SVDD
VSS
NPOR(1)
POR REARM
VSS
TVLOW(2)
Note 1:
2:
3:
TPOR(3)
When NPOR is low, the device is held in Reset.
TPOR 1 s typical.
TVLOW 2.7 s typical.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 489
PIC16(L)F1764/5/8/9
TABLE 36-2:
SUPPLY CURRENT (IDD)(1,2)
Standard Operating Conditions
(unless otherwise stated)
PIC16LF1764/5/8/9
PIC16F1764/5/8/9
Param
No.
D009
Device
Characteristics
Conditions
Min.
LDO Regulator
D010
D010
D012
D012
D014
D014
D015
D015
†
Typ†
Max.
Units
VDD
Note
—
75
—
A
—
High-Power mode, normal operation
—
15
—
A
—
Sleep, VREGCON<1> = 0
—
0.3
—
A
—
Sleep, VREGCON<1> = 1
—
8
—
A
1.8
—
12
—
A
3.0
FOSC = 32 kHz,
LP Oscillator mode,
-40°C  TA  +85°C
—
21
—
A
2.3
—
25
—
A
3.0
—
26
—
A
5.0
—
210
—
A
1.8
—
390
—
A
3.0
—
320
—
A
2.3
—
430
—
A
3.0
—
530
—
A
5.0
—
170
—
A
1.8
—
320
—
A
3.0
—
250
—
A
2.3
—
360
—
A
3.0
—
430
—
A
5.0
—
2.5
—
mA
3.0
—
3.1
—
mA
3.6
—
2.5
—
mA
3.0
—
2.7
—
mA
5.0
FOSC = 32 kHz,
LP Oscillator mode (Note 4),
-40°C  TA  +85°C
FOSC = 4 MHz,
XT Oscillator mode
FOSC = 4 MHz,
XT Oscillator mode
FOSC = 4 MHz,
External Clock (ECM),
Medium Power mode
FOSC = 4 MHz,
External Clock (ECM),
Medium Power mode
FOSC = 32 MHz,
External Clock (ECH),
High-Power mode
FOSC = 32 MHz,
External Clock (ECH),
High-Power mode
Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and
switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For EXTRC oscillator configurations, current through REXT is not included. The current through the resistor can be
extended by the formula: IR = VDD/2REXT (mA) with REXT in k
4: FVR and BOR are disabled.
5: 8 MHz crystal/oscillator with 4x PLL enabled.
DS40001775B-page 490
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
TABLE 36-2:
SUPPLY CURRENT (IDD)(1,2) (CONTINUED)
PIC16LF1764/5/8/9
(unless otherwise stated)
Standard Operating Conditions
PIC16F1764/5/8/9
Param
No.
Device
Characteristics
Conditions
Min.
D017
D017
D019
D019
D020
D020
D022
D022
†
Typ†
Max.
Units
Note
VDD
—
115
—
A
1.8
—
145
—
A
3.0
—
160
—
A
2.3
—
180
—
A
3.0
—
230
—
A
5.0
—
0.9
—
mA
1.8
—
1.5
—
mA
3.0
—
1.2
—
mA
2.3
—
1.5
—
mA
3.0
—
1.7
—
mA
5.0
—
2.9
—
mA
3.0
—
3.5
—
mA
3.6
—
2.9
—
mA
3.0
—
3.0
—
mA
5.0
—
2.8
—
mA
3.0
—
3.4
—
mA
3.6
—
2.9
—
mA
3.0
—
3.1
—
mA
5.0
FOSC = 500 kHz,
MFINTOSC mode
FOSC = 500 kHz,
MFINTOSC mode
FOSC = 16 MHz,
HFINTOSC mode
FOSC = 16 MHz,
HFINTOSC mode
FOSC = 32 MHz,
HFINTOSC mode
FOSC = 32 MHz,
HFINTOSC mode
FOSC = 32 MHz,
HS Oscillator mode (Note 5)
FOSC = 32 MHz
HS Oscillator mode (Note 5)
Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and
switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For EXTRC oscillator configurations, current through REXT is not included. The current through the resistor can be
extended by the formula: IR = VDD/2REXT (mA) with REXT in k
4: FVR and BOR are disabled.
5: 8 MHz crystal/oscillator with 4x PLL enabled.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 491
PIC16(L)F1764/5/8/9
TABLE 36-3:
POWER-DOWN CURRENTS (IPD)(1,2)
PIC16LF1764/5/8/9
Operating Conditions: (unless otherwise stated)
Low-Power Sleep Mode
PIC16F1764/5/8/9
Low-Power Sleep Mode, VREGPM = 1
Param
No.
D023
Device Characteristics
Base IPD
D023
Base IPD
D023A
Base IPD
D024
D024
D025
D025
Min.
Typ†
Max.
+85°C
Conditions
Max.
+125°C
Units
VDD
Note
—
0.05
1.0
8.0
A
1.8
—
0.08
2.0
9.0
A
3.0
—
0.3
3
11
A
2.3
—
0.4
4
12
A
3.0
—
0.5
6
15
A
5.0
—
9.8
16
18
A
2.3
—
10.3
18
20
A
3.0
—
11.5
21
26
A
5.0
WDT, BOR, FVR and SOSC
disabled, all peripherals inactive,
Normal Power Sleep mode,
VREGPM = 0
—
0.5
6
14
A
1.8
WDT current
—
0.8
7
17
A
3.0
—
0.8
6
15
A
2.3
—
0.9
7
20
A
3.0
—
1.0
8
22
A
5.0
—
15
28
30
A
1.8
—
24
35
38
A
3.0
—
18
33
35
A
2.3
—
24
35
37
A
3.0
WDT, BOR, FVR and SOSC
disabled, all peripherals inactive
WDT, BOR, FVR and SOSC
disabled, all peripherals inactive,
Low-Power Sleep mode
WDT current
FVR current
FVR current
—
26
37
39
A
5.0
D026
—
7.5
25
28
A
3.0
BOR current
D026
—
10
25
28
A
3.0
BOR current
—
12
28
31
A
5.0
D027
—
0.5
4
10
A
3.0
LPBOR current
D027
—
0.8
6
14
A
3.0
LPBOR current
—
1
8
17
A
5.0
—
0.5
5
9
A
1.8
—
0.8
8.5
12
A
3.0
—
1.1
6
10
A
2.3
—
1.3
8.5
20
A
3.0
—
1.4
10
25
A
5.0
—
0.05
2
9
A
1.8
—
0.08
3
10
A
3.0
—
0.3
4
12
A
2.3
—
0.4
5
13
A
3.0
—
0.5
7
16
A
5.0
D028
D028
D029
D029
SOSC current
SOSC current
ADC current, no conversion in
progress (Note 3)
ADC current, no conversion in
progress (Note 3)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The peripheral current is the sum of the base IPD and the additional current consumed when this peripheral is enabled.
The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max values should
be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the
part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS.
3: ADC clock source is FRC.
DS40001775B-page 492
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
TABLE 36-3:
POWER-DOWN CURRENTS (IPD)(1,2) (CONTINUED)
PIC16LF1764/5/8/9
Operating Conditions: (unless otherwise stated)
Low-Power Sleep Mode
PIC16F1764/5/8/9
Low-Power Sleep Mode, VREGPM = 1
Param
No.
Device Characteristics
D030
D030
Min.
Typ†
Conditions
Max.
+85°C
Max.
+125°C
Units
VDD
—
250
—
—
A
1.8
—
250
—
—
A
3.0
—
280
—
—
A
2.3
—
280
—
—
A
3.0
Note
ADC current, conversion in
progress (Note 3)
ADC current, conversion in
progress (Note 3)
—
380
—
—
A
5.0
D031
—
250
650
—
A
3.0
Op Amp (high power)
D031
—
250
650
—
A
3.0
Op Amp (high power)
—
350
850
—
A
5.0
—
250
600
—
A
1.8
—
300
650
—
A
3.0
—
280
600
—
A
2.3
—
300
650
—
A
3.0
—
310
650
—
A
5.0
D032
D032
Comparator
Comparator,
VREGPM = 0
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The peripheral current is the sum of the base IPD and the additional current consumed when this peripheral is enabled.
The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max values should
be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the
part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS.
3: ADC clock source is FRC.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 493
PIC16(L)F1764/5/8/9
TABLE 36-4:
I/O PORTS
Standard Operating Conditions (unless otherwise stated)
Param
No.
Sym.
VIL
Characteristic
Min.
Typ†
Max.
Units
—
—
with Schmitt Trigger Buffer
with I2C Levels
Conditions
—
0.8
V
4.5V  VDD  5.5V
—
0.15 VDD
V
1.8V  VDD  4.5V
—
—
0.2 VDD
V
2.0V  VDD  5.5V
—
—
0.3 VDD
V
Input Low Voltage
I/O Ports:
D034
with TTL Buffer
D034A
D035
—
—
0.8
V
2.7V  VDD  5.5V
MCLR, OSC1 (EXTRC mode)
—
—
0.2 VDD
V
(Note 1)
OSC1 (HS mode)
—
—
0.3 VDD
V
2.0
—
—
V
4.5V  VDD 5.5V
with SMBus Levels
D036
D036A
VIH
Input High Voltage
I/O Ports:
D040
with TTL Buffer
0.25 VDD + 0.8
—
—
V
1.8V  VDD  4.5V
with Schmitt Trigger Buffer
0.8 VDD
—
—
V
2.0V  VDD  5.5V
with I2C Levels
0.7 VDD
—
—
V
2.1
—
—
V
D040A
D041
with SMBus Levels
2.7V  VDD  5.5V
D042
MCLR
0.8 VDD
—
—
V
D043A
OSC1 (HS mode)
0.7 VDD
—
—
V
D043B
OSC1 (EXTRC oscillator)
0.9 VDD
—
—
V
VDD  2.0V(Note 1)
—
±5
± 125
nA
VSS  VPIN  VDD,
Pin at high-impedance, +85°C
—
±5
± 1000
nA
VSS  VPIN  VDD,
Pin at high-impedance, +125°C
—
± 50
± 200
nA
VSS  VPIN  VDD,
Pin at high-impedance, +85°C
25
100
200
A
VDD = 3.3V, VPIN = VSS
25
140
300
A
VDD = 5.0V, VPIN = VSS
IIL
D060
Input Leakage Current(2)
I/O Ports
MCLR(3)
D061
IPUR
Weak Pull-up Current
D070*
VOL
Output Low
Voltage(4)
D080
Standard I/O ports
—
—
0.6
V
IOL = 8mA, VDD = 5V
IOL = 6mA, VDD = 3.3V
IOL = 1.8mA, VDD = 1.8V
D080A
High Drive I/O ports
—
—
—
—
0.6
0.6
0.6
—
—
V
V
V
IOH = 10mA, VDD = 2.3V, HIDCx = 1
IOH = 32mA, VDD = 3.0V, HIDCx = 1
IOH = 51mA, VDD = 5.0V, HIDCx = 1
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in EXTRC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: Including OSC2 in CLKOUT mode.
DS40001775B-page 494
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
TABLE 36-4:
I/O PORTS (CONTINUED)
Standard Operating Conditions (unless otherwise stated)
Param
No.
Sym.
VOH
Characteristic
Min.
Typ†
Max.
Units
Conditions
Output High Voltage(4)
D090
Standard I/O Ports
VDD – 0.7
—
—
V
IOH = 3.5mA, VDD = 5V
IOH = 3mA, VDD = 3.3V
IOH = 1mA, VDD = 1.8V
D090A
High Drive I/O Ports
VDD – 0.7
—
—
—
VDD - 0.7
VDD - 0.7
—
—
—
V
V
V
IOH = 10mA, VDD = 2.3V, HIDCX = 1
IOH = 37mA, VDD = 3.0V, HIDCX = 1
IOH = 54mA, VDD = 5.0V, HIDCX = 1
—
—
15
pF
In XT, HS and LP modes when
external clock is used to drive
OSC1
—
—
50
pF
Capacitive Loading Specs on Output Pins
D101*
COSC2 OSC2 Pin
D101A* CIO
All I/O Pins
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in EXTRC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: Including OSC2 in CLKOUT mode.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 495
PIC16(L)F1764/5/8/9
TABLE 36-5:
MEMORY PROGRAMMING SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Param
No.
Sym.
Characteristic
Min.
Typ†
Max.
Units
Conditions
Program Memory
Programming Specifications
D110
VIHH
Voltage on MCLR/VPP Pin
8.0
—
9.0
V
D111
IDDP
Supply Current during
Programming
—
—
10
mA
D112
VBE
VDD for Bulk Erase
D113
VPEW
VDD for Write or Row Erase
D114
D115
2.7
—
VDDMAX
V
VDDMIN
—
VDDMAX
V
IPPPGM Current on MCLR/VPP during
Erase/Write
—
1.0
—
mA
IDDPGM Current on VDD during
Erase/Write
—
5.0
—
mA
10K
—
—
E/W
VDDMIN
—
VDDMAX
V
(Note 2)
Program Flash Memory
-40C  TA  +85C
(Note 1)
D121
EP
Cell Endurance
D122
VPRW
VDD for Read/Write
D123
TIW
Self-Timed Write Cycle Time
—
2
2.5
D124
TRETD
Characteristic Retention
—
40
—
Year Provided no other
specifications are violated
D125
EHEFC
High-Endurance Flash Cell
100K
—
—
E/W
ms
-0C  TA  +60°C, Lower
byte last 128 addresses
† Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Self-write and block erase.
2: Required only if single-supply programming is disabled.
DS40001775B-page 496
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
TABLE 36-6:
THERMAL CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Param
No.
TH01
TH02
TH03
Sym.
JA
JC
Characteristic
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Case
Typ.
Units
Conditions
70.0
C/W
14-pin PDIP package
95.3
C/W
14-pin SOIC package
100.0
C/W
14-pin TSSOP package
51.5
C/W
16-pin QFN 4x4 mm package
62.2
C/W
20-pin PDIP package
87.3
C/W
20-pin SSOP
77.7
C/W
20-pin SOIC package
43.0
C/W
20-pin QFN 4x4 mm package
32.75
C/W
14-pin PDIP package
31.0
C/W
14-pin SOIC package
24.4
C/W
14-pin TSSOP package
5.4
C/W
16-pin QFN 4x4 mm package
27.5
C/W
20-pin PDIP package
31.1
C/W
20-pin SSOP
23.1
C/W
20-pin SOIC package
20-pin QFN 4x4 mm package
5.3
C/W
150
C
—
W
PD = PINTERNAL + PI/O
—
W
PINTERNAL = IDD x VDD(1)
I/O Power Dissipation
—
W
PI/O =  (IOL * VOL) +  (IOH * (VDD – VOH))
Derated Power
—
W
PDER = PDMAX (TJ – TA)/JA(2)
TJMAX
Maximum Junction Temperature
TH04
PD
Power Dissipation
TH05
PINTERNAL Internal Power Dissipation
TH06
PI/O
TH07
PDER
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature, TJ = Junction Temperature.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 497
PIC16(L)F1764/5/8/9
36.4
AC Characteristics
Timing Parameter Symbology has been created with one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O PORT
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (High-impedance)
L
Low
FIGURE 36-4:
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
High-impedance
LOAD CONDITIONS
Rev. 10-000133A
8/1/2013
Load Condition
Pin
CL
VSS
Legend: CL=50 pF for all pins
DS40001775B-page 498
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
FIGURE 36-5:
CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
CLKIN
OS12
OS02
OS11
OS03
CLKOUT
(CLKOUT Mode)
Note 1:
See Table 36-10.
TABLE 36-7:
CLOCK OSCILLATOR TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param
No.
OS01
Sym.
FOSC
Characteristic
Min.
External CLKIN Frequency(1)
Oscillator Frequency(1)
OS02
TOSC
External CLKIN
Period(1)
(1)
Oscillator Period
OS03
TCY
Instruction Cycle Time(1)
OS04*
TosH,
TosL
External CLKIN High,
External CLKIN Low
OS05*
TosR,
TosF
External CLKIN Rise,
External CLKIN Fall
Typ†
Max.
Units
Conditions
DC
—
0.5
MHz
External Clock (ECL)
DC
—
4
MHz
External Clock (ECM)
DC
—
20
MHz
External Clock (ECH)
—
32.768
—
kHz
LP Oscillator
0.1
—
4
MHz
XT Oscillator
1
—
4
MHz
HS Oscillator
1
—
20
MHz
HS Oscillator, VDD > 2.7V
DC
—
4
MHz
EXTRC, VDD > 2.0V
27
—

s
LP Oscillator
250
—

ns
XT Oscillator
50
—

ns
HS Oscillator
50
—

ns
External Clock (EC)
—
30.5
—
s
LP Oscillator
250
—
10,000
ns
XT Oscillator
50
—
1,000
ns
HS Oscillator
250
—
—
ns
EXTRC
125
TCY
DC
ns
TCY = 4/FOSC
2
—
—
s
LP Oscillator
100
—
—
ns
XT Oscillator
20
—
—
ns
HS Oscillator
0
—

ns
LP Oscillator
0
—

ns
XT Oscillator
0
—

ns
HS Oscillator
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min” values with an external
clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no
clock) for all devices.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 499
PIC16(L)F1764/5/8/9
TABLE 36-8:
OSCILLATOR PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Param
No.
Sym.
Freq.
Min. Typ† Max. Units
Tolerance
Characteristic
Conditions
HFOSC
Internal Calibrated HFINTOSC
Frequency(1)
±2%
—
16.0
—
MHz VDD = 3.0V, TA = 25°C
(Note 2)
OS08A MFOSC
Internal Calibrated MFINTOSC
Frequency(1)
±2%
—
500
—
kHz VDD = 3.0V, TA = 25°C
(Note 3)
OS09
LFOSC
Internal LFINTOSC Frequency
—
—
31
—
kHz -40°C  TA  +125°C
OS10*
TWARM
HFINTOSC
Wake-up from Sleep Start-up Time
MFINTOSC
Wake-up from Sleep Start-up Time
—
—
3.2
8
s
—
—
24
35
s
—
—
0.5
—
ms
OS08
LFINTOSC
Wake-up from Sleep Start-up Time
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the
device as possible. 0.1 F and 0.01 F values in parallel are recommended.
2: See Figure 37-22: Sleep Mode, Wake Period with HFINTOSC Source, PIC16LF1764/5/8/9 Only and
Figure 36-6: HFINTOSC Frequency Accuracy Over Device VDD and Temperature.
3: See Figure 37-20: LFINTOSC Frequency Over VDD and Temperature, PIC16LF1764/5/8/9 Only and
Figure 37-21: LFINTOSC Frequency Over VDD and Temperature, PIC16F1764/5/8/9 Only.
FIGURE 36-6:
HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE
125
± 5%
85
Temperature (°C)
± 3%
60
± 2%
25
0
-20
-40
1.8
± 5%
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS40001775B-page 500
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
TABLE 36-9:
PLL CLOCK TIMING SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Param
No.
Sym.
F10
F11
FOSC Oscillator Frequency Range
FSYS On-Chip VCO System Frequency
F12
TRC
PLL Start-up Time (Lock Time)
F13*
CLK
CLKOUT Stability (Jitter)
Characteristic
Min.
Typ†
Max.
Units
4
16
—
—
8
32
MHz
MHz
—
—
2
ms
-0.25%
—
+0.25%
%
Conditions
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, +25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 501
PIC16(L)F1764/5/8/9
FIGURE 36-7:
CLKOUT AND I/O TIMING
Cycle
Write
Fetch
Q1
Q4
Read
Execute
Q2
Q3
FOSC
OS12
OS11
OS20
OS21
CLKOUT
OS19
OS18
OS16
OS13
OS17
I/O Pin
(Input)
OS14
OS15
I/O Pin
(Output)
New Value
Old Value
OS18, OS19
TABLE 36-10: CLKOUT AND I/O TIMING PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Param
No.
Sym.
Characteristic
Min.
Typ†
Max.
Units
Conditions
OS11
TosH2ckL
FOSC to CLKOUT(1)
—
—
70
ns
3.3V  VDD 5.0V
OS12
TosH2ckH
FOSC to CLKOUT(1)
—
—
72
ns
3.3V  VDD 5.0V
OS13
TckL2ioV
CLKOUT to Port Out Valid(1)
—
—
20
ns
OS14
TioV2ckH
Port Input Valid before CLKOUT(1)
TOSC + 200 ns
—
—
ns
OS15
TosH2ioV
FOSC (Q1 cycle) to Port Out Valid
—
50
70*
ns
3.3V  VDD 5.0V
OS16
TosH2ioI
FOSC (Q2 cycle) to Port Input Invalid
(I/O in hold time)
50
—
—
ns
3.3V  VDD 5.0V
OS17
TioV2osH
Port Input Valid to Fosc(Q2 cycle)
(I/O in setup time)
20
—
—
ns
OS18*
TioR
Port Output Rise Time
—
—
40
15
72
32
ns
VDD = 1.8V,
3.3V  VDD 5.0V
OS19*
TioF
Port Output Fall Time
—
—
28
15
55
30
ns
VDD = 1.8V,
3.3V  VDD 5.0V
OS20*
Tinp
INT Pin Input High or Low Time
25
—
—
ns
OS21*
Tioc
Interrupt-On-Change New Input Level Time
25
—
—
ns
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, +25C unless otherwise stated.
Note 1: Measurements are taken in EXTRC mode where CLKOUT output is 4 x TOSC.
DS40001775B-page 502
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
FIGURE 36-8:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
PWRT
Time-out
33
32
OSC
Start-up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
34
31
34
I/O Pins
Note 1: Asserted low.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 503
PIC16(L)F1764/5/8/9
TABLE 36-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Param
No.
Sym.
Characteristic
Min.
Typ†
Max.
Units
2
—
—
s
10
16
27
ms
Conditions
30
TMCL
31
TWDTLP Low-Power Watchdog Timer
Time-out Period
32
TOST
Oscillator Start-up Timer Period(1)
—
1024
—
Tosc
33*
TPWRT
Power-up Timer Period, PWRTE = 0
40
65
140
ms
34*
TIOZ
I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
—
—
2.0
s
35
VBOR
Brown-out Reset Voltage(2)
2.55
2.30
1.80
2.70
2.45
1.90
2.85
2.60
2.10
V
V
V
BORV = 0
BORV = 1 (PIC16F1764/5/8/9)
BORV = 1 (PIC16LF1764/5/8/9)
35A
VLPBOR Low-Power Brown-out
1.8
2.1
2.5
V
LPBOR = 1
36*
VHYST
0
25
75
mV
-40°C  TA  +85°C
1
3
35
s
VDD  VBOR
37*
MCLR Pulse Width (low)
Brown-out Reset Hysteresis
TBORDC Brown-out Reset DC Response Time
*
†
Note 1:
2:
VDD = 3.3V-5V,
1:512 prescaler used
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency.
To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
DS40001775B-page 504
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FIGURE 36-9:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40
41
42
T1CKI
45
46
47
49
TMR0 or
TMR1
FIGURE 36-10:
BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
VBOR and VHYST
VBOR
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
37
Reset
(due to BOR)
33(1)
Note 1: The delay (TPWRT) releasing Reset only occurs when the Power-up Timer is enabled (PWRTE = 0).
 2014-2015 Microchip Technology Inc.
DS40001775B-page 505
PIC16(L)F1764/5/8/9
TABLE 36-12: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym.
Characteristic
40*
TT0H
T0CKI High Pulse Width
No Prescaler
41*
TT0L
T0CKI Low Pulse Width
No Prescaler
With Prescaler
With Prescaler
Min.
Typ†
Max.
Units
0.5 TCY + 20
—
—
ns
ns
10
—
—
0.5 TCY + 20
—
—
ns
10
—
—
ns
Greater of:
20 or TCY + 40
N
—
—
ns
42*
TT0P
T0CKI Period
45*
TT1H
T1CKI High Synchronous, No Prescaler
Time
Synchronous, with Prescaler
0.5 TCY + 20
—
—
ns
15
—
—
ns
Asynchronous
30
—
—
ns
Synchronous, No Prescaler
0.5 TCY + 20
—
—
ns
Synchronous, with Prescaler
15
—
—
ns
Asynchronous
30
—
—
ns
Greater of:
30 or TCY + 40
N
—
—
ns
60
—
—
ns
32.4
32.768
33.1
kHz
2 TOSC
—
7 TOSC
—
TT1L
46*
TT1P
47*
T1CKI Low
Time
T1CKI Input Synchronous
Period
Asynchronous
48
FT1
Secondary Oscillator Input Frequency Range
(oscillator enabled by setting bit, T1OSCEN)
49*
TCKEZTMR1 Delay from External Clock Edge to Timer
Increment
Conditions
N = prescale value
N = prescale value
Timers in Sync
mode
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
DS40001775B-page 506
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FIGURE 36-11:
CAPTURE/COMPARE/PWM TIMINGS (CCP)
CCPx
(Capture mode)
CC01
CC02
CC03
Note:
Refer to Figure 36-4 for load conditions.
TABLE 36-13: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)
Standard Operating Conditions (unless otherwise stated)
Param
Sym.
No.
Characteristic
CC01* TccL
CCPx Input Low Time
No Prescaler
CC02* TccH
CCPx Input High Time
No Prescaler
With Prescaler
With Prescaler
CC03* TccP
*
†
CCPx Input Period
Min.
Typ†
Max.
Units
0.5TCY + 20
—
—
ns
ns
20
—
—
0.5TCY + 20
—
—
ns
20
—
—
ns
3 TCY + 40
N
—
—
ns
Conditions
N = prescale value
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 507
PIC16(L)F1764/5/8/9
FIGURE 36-12:
CLC PROPAGATION TIMING
CLCxINn
CLC
Input time
CLCxINn
CLC
Input time
LCx_in[n](1)
LCx_in[n](1)
CLC01
Note 1:
CLC
Module
LCx_out(1)
CLC
Output time
CLCx
CLC
Module
LCx_out(1)
CLC
Output time
CLCx
CLC02
CLC03
See Figure 28-1 to identify specific CLC signals.
TABLE 36-14: CONFIGURATION LOGIC CELL (CLC) CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C
Param.
No.
Sym.
Characteristic
Min.
CLC01* TCLCIN
CLC Input Time
CLC02* TCLC
CLC Module Input to Output Progagation Time
Rise Time
—
OS18
Fall Time
—
OS19
—
45
—
MHz
CLC03* TCLCOUT CLC Output Time
CLC04* FCLCMAX CLC Maximum Switching Frequency
Typ†
Max.
Units
Conditions
—
7
OS17
ns
(Note 1)
—
—
24
12
—
—
ns
ns
VDD = 1.8V
VDD > 3.6V
—
—
(Note 1)
—
—
(Note 1)
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: See Table 36-10 for OS17, OS18 and OS19 rise and fall times.
DS40001775B-page 508
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TABLE 36-15:
ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS(1,2,3,4)
Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = +25°C, Single-Ended, 2 s TAD, VREF+ = 3V, VREF- = VSS
Param
Sym.
No.
Characteristic
Min.
Typ†
Max.
Units
—
—
10
bit
AD01
NR
Resolution
AD02
EIL
Integral Error
—
—
±1.7
AD03
EDL
Differential Error
—
—
±1
AD04
EOFF Offset Error
AD05
EGN
AD06
VREF Reference Voltage
AD07
VAIN
Full-Scale Range
AD08
ZAIN
Recommended Impedance of
Analog Voltage Source
Gain Error
Conditions
LSb VREF = 3.0V
LSb No missing codes, VREF = 3.0V
—
—
±2.5
LSb VREF = 3.0V
—
—
±2.0
LSb VREF = 3.0V
1.8
—
VDD
V
VSS
—
VREF
V
—
—
10
k
VREF = (VREF+ – VREF-)
Can go higher if external 0.01 F capacitor is
present on input pin
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Total Absolute Error includes integral, differential, offset and gain errors.
2: The ADC conversion result never decreases with an increase in the input voltage and has no missing codes.
3: ADC VREF is from external VREF+ pin, VDD pin or FVR, whichever is selected as reference input.
4: See Section 37.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.
TABLE 36-16: ADC CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param
Sym.
No.
AD130* TAD
AD131 TCNV
Characteristic
Min.
Typ†
Max.
Units
ADC Clock Period (TADC)
1.0
ADC Internal FRC Oscillator Period
(TFRC)
1.0
Conversion Time (not including
Acquisition Time)(1)
—
Conditions
—
9.0
s
FOSC-based
2
6.0
s
ADCS<1:0> = 11 (ADC FRC mode)
13
—
TAD
Set GO/DONE bit to conversion
complete
s
AD132* TACQ Acquisition Time
—
5.0
—
AD133* THCD Holding Capacitor Disconnect Time
—
1/2 TAD
—
ADCS<2:0>  x11 (FOSC-based)
—
1/2 TAD + 1 TCY
—
ADCS<2:0> = x11 (FRC-based)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The ADRES register may be read on the following TCY cycle.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 509
PIC16(L)F1764/5/8/9
FIGURE 36-13:
ADC CONVERSION TIMING (ADC CLOCK FOSC-BASED)
BSF ADCON0, GO
1 TCY
AD133
AD131
Q4
AD130
ADC_clk
ADC Data
9
ADRES
8
7
6
3
2
1
0
OLD_DATA
NEW_DATA
ADIF
1 TCY
DONE
GO
Sample
Sampling Stopped
AD132
FIGURE 36-14:
ADC CONVERSION TIMING (ADC CLOCK FROM FRC)
BSF ADCON0, GO
AD133
1 TCY
AD131
Q4
AD130
ADC_clk
ADC Data
9
8
7
6
OLD_DATA
ADRES
3
2
1
0
NEW_DATA
ADIF
1 TCY
GO
DONE
Sample
AD132
Sampling Stopped
Note 1: If the ADC clock source is selected as FRC, a time of TCY is added before the ADC clock starts. This allows
the SLEEP instruction to be executed.
DS40001775B-page 510
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TABLE 36-17: OPERATIONAL AMPLIFIER (OPA)
Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = +25°C, OPAxSP = 1 (High GBWP mode)
Param
No.
Symbol
Parameters
Min.
Typ.
Max.
Units
OPA01* GBWP
Gain Bandwidth Product
—
2
—
MHz
OPA02* TON
Turn-on Time
—
10
—
s
OPA03* PM
Phase Margin
—
40
—
degrees
OPA04* SR
Slew Rate
—
3
—
V/s
OPA05
OFF
Offset
—
±3
±9
mV
OPA06
CMRR
Common-Mode Rejection Ratio
52
70
—
dB
OPA07* AOL
Open-Loop Gain
—
90
—
dB
OPA08
Input Common-Mode Voltage
0
—
VDD
V
OPA09* PSRR
Power Supply Rejection Ratio
—
80
—
dB
OPA10* HZ
High-Impedance On/Off Time
—
50
—
ns
VICM
*
Conditions
VDD > 2.5V
These parameters are characterized but not tested.
TABLE 36-18: PROGRAMMABLE RAMP GENERATOR (PRG) SPECIFICATIONS
Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = +25°C (unless otherwise stated)
Param
No.
Sym.
Characteristics
Min.
Typ.
Max.
Units
Comments
PRG01
RRR
Rising Ramp Rate
—
1
—
V/s
PRGxCON2 = 10h
PRG02
FRR
Falling Ramp Rate
—
1
—
V/s
PRGxCON2 = 10h
*
These parameters are characterized but not tested.
TABLE 36-19: COMPARATOR SPECIFICATIONS
Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = +25°C
See Section 37.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.
Param
No.
Sym.
Characteristics
Input Offset Voltage
Min.
Typ.
Max.
Units
—
±2.5
±5
mV
CM01
VIOFF
CM02
VICM
Input Common-Mode Voltage
0
—
VDD
V
CM03
CMRR
Common-Mode Rejection Ratio
40
50
—
dB
CM04A
TRESP(1)
Comments
VICM = VDD/2
Response Time Rising Edge
—
60
125
ns
Normal Power mode
CM04B
Response Time Falling Edge
—
60
110
ns
Normal Power mode
CM04C
Response Time Rising Edge
—
85
—
ns
Low-Power mode
CM04D
Response Time Falling Edge
—
85
—
ns
Low-Power mode
Comparator Mode Change to
Output Valid*
—
—
10
s
20
45
75
mV
CM05*
TMC2OV
CM06
CHYSTER Comparator Hysteresis
*
Note 1:
These parameters are characterized but not tested.
Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to
VDD.
 2014-2015 Microchip Technology Inc.
CxHYS = 1
DS40001775B-page 511
PIC16(L)F1764/5/8/9
TABLE 36-20: 10-BIT DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS
Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = +25°C
See Section 37.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.
Param
No.
DAC01*
Sym.
CLSB
Characteristics
Min.
Typ.
Max.
Units
—
VDD/1024
—
V
Step-Size
DAC02
CINL
Integral Error
—
—
1.5
LSb
DAC03
CDNL
Differential Error(2)
—
—
1
LSb
DAC04
COFF
Offset Error(2)
—
—
3
LSb
DAC05
CGN
Gain Error(2)
—
—
3
LSb
(2)
Comments
For codes: 0x004 to 0x3FB
DAC06*
CR
Unit Resistor Value (R)
—
300
—

DAC07*
CST
Settling Time(1)
—
—
10
s
*
Note 1:
2:
These parameters are characterized but not tested.
Settling time measured while DACR<9:0> transitions from 0x000 to 0x3FF.
Buffered by op amp in unity gain.
TABLE 36-21: 5-BIT DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS
Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = +25°C
See Section 37.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.
Param
No.
DAC10*
Sym.
CLSB
Characteristics
Min.
Typ.
Max.
Units
—
VDD/32
—
V
Step-Size
DAC11
CACC
Absolute
—
—
0.5
LSb
DAC12*
CR
Unit Resistor Value (R)
—
6000
—

DAC13*
CST
Time(1)
—
—
10
s
*
Note 1:
2:
These parameters are characterized but not tested.
Settling time measured while DACR<4:0> transitions from 0x00 to 0x1F.
Buffered by op amp in unity gain.
Settling
Accuracy(2)
Comments
TABLE 36-22: ZERO-CROSS PIN SPECIFICATIONS
Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = +25°C
Param.
No.
Sym.
Characteristics
Min.
Typ.
Max.
Units
ZC01
ZCPINV
Voltage on Zero-Cross Pin
—
0.75
—
V
ZC02
ZCSNK
Maximum Source or Sink Current
—
—
600
A
ZC04
ZCISW
Response Time Rising Edge
—
1
—
s
Response Time Falling Edge
—
1
—
s
ZC05
ZCOUT
*
Response Time Rising Edge
—
1
—
s
Response Time Falling Edge
—
1
—
s
Comments
These parameters are characterized but not tested.
DS40001775B-page 512
 2014-2015 Microchip Technology Inc.
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FIGURE 36-15:
EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
CK
US121
US121
DT
US122
US120
Note:
Refer to Figure 36-4 for load conditions.
TABLE 36-23: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
US120
US121
US122
Symbol
TCKH2DTV
TCKRF
TDTRF
FIGURE 36-16:
Characteristic
Min.
Max.
Units
Conditions
SYNC XMIT (Master and Slave)
Clock High to Data-out Valid
—
80
ns
3.0V  VDD  5.5V
—
100
ns
1.8V  VDD  5.5V
Clock Out Rise Time and Fall Time
(Master mode)
—
45
ns
3.0V  VDD  5.5V
—
50
ns
1.8V  VDD  5.5V
Data-out Rise Time and Fall Time
—
45
ns
3.0V  VDD  5.5V
—
50
ns
1.8V  VDD  5.5V
EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
CK
US125
DT
US126
Note: Refer to Figure 36-4 for load conditions.
TABLE 36-24: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Symbol
Characteristic
US125 TDTV2CKL SYNC RCV (Master and Slave)
Data-Setup before CK  (DT hold time)
US126 TCKL2DTL
Data-hold after CK  (DT hold time)
 2014-2015 Microchip Technology Inc.
Min.
Max.
Units
10
—
ns
15
—
ns
Conditions
DS40001775B-page 513
PIC16(L)F1764/5/8/9
FIGURE 36-17:
SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
SS
SP81
SCK
(CKP = 0)
SP71
SP72
SP78
SP79
SP79
SP78
SCK
(CKP = 1)
SP80
SDO
MSb
bit 6 - - - - - -1
LSb
SP75, SP76
SDI
MSb In
SP73
bit 6 - - - -1
LSb In
SP74
Note: Refer to Figure 36-4 for load conditions.
FIGURE 36-18:
SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SS
SP81
SCK
(CKP = 0)
SP71
SP72
SP79
SP73
SCK
(CKP = 1)
SP80
SDO
MSb
SP78
bit 6 - - - - - -1
LSb
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
Note: Refer to Figure 36-4 for load conditions.
DS40001775B-page 514
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FIGURE 36-19:
SPI SLAVE MODE TIMING (CKE = 0)
SS
SP70
SCK
(CKP = 0)
SP83
SP71
SP72
SP78
SP79
SP79
SP78
SCK
(CKP = 1)
SP80
SDO
MSb
bit 6 - - - - - -1
LSb
SP77
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
SP73
Note: Refer to Figure 36-4 for load conditions.
FIGURE 36-20:
SS
SPI SLAVE MODE TIMING (CKE = 1)
SP82
SP70
SP83
SCK
(CKP = 0)
SP71
SP72
SCK
(CKP = 1)
SP80
SDO
MSb
bit 6 - - - - - -1
LSb
SP77
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
Note: Refer to Figure 36-4 for load conditions.
 2014-2015 Microchip Technology Inc.
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PIC16(L)F1764/5/8/9
TABLE 36-25: SPI MODE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param
No.
Symbol
Characteristic
Min.
Typ†
Max. Units
TCY
—
—
ns
—
—
ns
Conditions
SP70*
TSSL2SCH,
TSSL2SCL
SS to SCK or SCK Input
SP71*
TSCH
SCK Input High Time (Slave mode)
TCY + 20
SP72*
TSCL
SCK Input Low Time (Slave mode)
TCY + 20
—
—
ns
SP73*
TDIV2SCH,
TDIV2SCL
Setup Time of SDI Data Input to
SCK Edge
100
—
—
ns
SP74*
TSCH2DIL,
TSCL2DIL
Hold Time of SDI Data Input to
SCK Edge
100
—
—
ns
SP75*
TDOR
SDO Data Output Rise Time
—
10
25
ns
3.0V  VDD  5.5V
—
25
50
ns
1.8V  VDD  5.5V
SP76*
TDOF
SDO Data Output Fall Time
—
10
25
ns
SP77*
TSSH2DOZ
SS to SDO Output
High-Impedance
10
—
50
ns
SP78*
TSCR
SCK Output Rise Time
(Master mode)
—
10
25
ns
3.0V  VDD  5.5V
—
25
50
ns
1.8V  VDD  5.5V
SP79*
TSCF
SCK Output Fall Time
(Master mode)
—
10
25
ns
SP80*
TSCH2DOV,
TSCL2DOV
SDO Data Output Valid after
SCK Edge
—
—
50
ns
3.0V  VDD  5.5V
1.8V  VDD  5.5V
SP81*
TDOV2SCH, SDO Data Output Setup to
TDOV2SCL SCK Edge
SP82*
TSSL2DOV
SDO Data Output Valid after
SS Edge
SP83*
TSCH2SSH,
TSCL2SSH
SS after SCK Edge
—
—
145
ns
1 TCY
—
—
ns
—
—
50
ns
1.5 TCY + 40
—
—
ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
DS40001775B-page 516
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
FIGURE 36-21:
I2C BUS START/STOP BITS TIMING
SCL
SP93
SP91
SP90
SP92
SDA
Stop
Condition
Start
Condition
Note: Refer to Figure 36-4 for load conditions.
TABLE 36-26: I2C BUS START/STOP BITS REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param
No.
Symbol
TSU:STA
SP90*
SP91*
THD:STA
TSU:STO
SP92*
SP93
Characteristic
Typ
Max. Units
Start Condition
100 kHz mode
4700
—
—
Setup Time
400 kHz mode
600
—
—
Start Condition
100 kHz mode
4000
—
—
Hold Time
400 kHz mode
600
—
—
Stop Condition
100 kHz mode
4700
—
—
Setup Time
400 kHz mode
600
—
—
100 kHz mode
4000
—
—
400 kHz mode
600
—
—
THD:STO Stop Condition
Hold Time
*
Min.
Conditions
ns
Only relevant for Repeated
Start condition
ns
After this period, the first
clock pulse is generated
ns
ns
These parameters are characterized but not tested.
FIGURE 36-22:
I2C BUS DATA TIMING
SP103
SP100
SP102
SP101
SCL
SP106
SP90
SP107
SP91
SDA
In
SP92
SP110
SP109
SP109
SDA
Out
Note: Refer to Figure 36-4 for load conditions.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 517
PIC16(L)F1764/5/8/9
TABLE 36-27: I2C BUS DATA REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
SP100*
Symbol
THIGH
Characteristic
Clock High Time
Min.
Max.
Units
100 kHz mode
4.0
—
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
—
s
Device must operate at a
minimum of 10 MHz
1.5 TCY
—
TCY
100 kHz mode
4.7
—
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
s
Device must operate at a
minimum of 10 MHz
1.5 TCY
—
TCY
SSP module
SP101*
TLOW
Clock Low Time
SSP module
SP102*
SP103*
TR
TF
SDA and SCL Rise 100 kHz mode
Time
400 kHz mode
—
1000
ns
20 + 0.1 CB
300
ns
SDA and SCL Fall
Time
100 kHz mode
—
250
ns
400 kHz mode
20 + 0.1 CB
250
ns
0
—
ns
SP106*
THD:DAT
Data Input Hold
Time
100 kHz mode
400 kHz mode
0
0.9
s
SP107*
TSU:DAT
Data Input Setup
Time
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
SP109*
TAA
Output Valid from
Clock
100 kHz mode
—
3500
ns
400 kHz mode
—
—
ns
SP110*
TBUF
Bus Free Time
100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
—
400
pF
CB is specified to be from
10-400 pF
CB is specified to be from
10-400 pF
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission
can start
SP111
CB
*
Note 1:
These parameters are characterized but not tested.
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the
requirement, TSU:DAT 250 ns, must then be met. This will automatically be the case if the device does not
stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it
must output the next data bit to the SDA line, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the
Standard mode I2C bus specification), before the SCL line is released.
2:
DS40001775B-page 518
Bus Capacitive Loading
Conditions
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
37.0
DC AND AC CHARACTERISTICS GRAPHS AND CHARTS
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
Unless otherwise noted, all graphs apply to both the L and LF devices.
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at +25C. “MAXIMUM”, “Max.”, “MINIMUM” or “Min.”
represents (mean + 3) or (mean - 3) respectively, where  is a standard deviation, over each
temperature range.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 519
PIC16(L)F1764/5/8/9
FIGURE 37-1:
VOH vs. IOH OVER TEMPERATURE, VDD = 5.5V, PIC16F1764/5/8/9 ONLY
6
Max: 125°C + 3ı
Typical: 25°C
Min: -40°C - 3ı
5
VOH (V)
4
Min. (-40°C)
3
Typical (25°C)
2
Max. (125°C)
1
0
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
IOH (mA)
FIGURE 37-2:
VOL vs. IOL OVER TEMPERATURE, VDD = 5.5V, PIC16F1764/5/8/9 ONLY
5
Max: 125°C + 3ı
Typical: 25°C
Min: -40°C - 3ı
4
Max. (125°C)
VOL (V)
Typical (25°C)
3
Min. (-40°C)
2
1
0
0
10
DS40001775B-page 520
20
30
40
50
IOL (mA)
60
70
80
90
100
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
FIGURE 37-3:
VOH vs. IOH OVER TEMPERATURE, VDD = 3.0V
3.5
Max: 125°C + 3ı
Typical: 25°C
Min: -40°C - 3ı
3.0
VOH (V)
2.5
2.0
1.5
1.0
Min. (-40°C)
Typical (25°C)
Max. (125°C)
0.5
0.0
-15
-13
-11
-9
-7
-5
-3
-1
IOH (mA)
FIGURE 37-4:
VOL vs. IOL OVER TEMPERATURE, VDD = 3.0V
5
Max: 125°C + 3ı
Typical: 25°C
Min: -40°C - 3ı
4
Max. (125°C)
VOL (V)
Typical (25°C)
3
Min. (-40°C)
2
1
0
0
10
20
 2014-2015 Microchip Technology Inc.
30
40
50
IOL (mA)
60
70
80
90
100
DS40001775B-page 521
PIC16(L)F1764/5/8/9
FIGURE 37-5:
VOH vs. IOH OVER TEMPERATURE, VDD = 1.8V, PIC16LF1764/5/8/9 ONLY
2.0
1.8
Max: 125°C + 3ı
Typical: 25°C
Min: -40°C - 3ı
1.6
VOH (V)
1.4
1.2
Min. (-40°C)
Max. (125°C)
Typical (25°C)
1.0
0.8
0.6
0.4
0.2
0.0
-4.5
-4.0
-3.5
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
IOH (mA)
FIGURE 37-6:
VOL vs. IOL OVER TEMPERATURE, VDD = 1.8V, PIC16LF1764/5/8/9 ONLY
1.8
Max: 125°C + 3ı
Typical: 25°C
Min: -40°C - 3ı
1.6
1.4
VOL (V)
1.2
1.0
0.8
Max. (125°C)
Min. (-40°C)
Typical (25°C)
0.6
0.4
0.2
0.0
0
1
2
3
4
5
6
7
8
9
10
IOL (mA)
DS40001775B-page 522
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
FIGURE 37-7:
POR RELEASE VOLTAGE
1.70
1.68
Max.
1.66
Voltage (V)
1.64
Typical
1.62
Min.
1.60
1.58
1.56
Max: Typical + 3ı
Typical: 25°C
Min: Typical - 3ı
1.54
1.52
1.50
-60
-40
-20
0
20
40
60
80
100
120
140
120
140
Temperature (°C)
FIGURE 37-8:
POR REARM VOLTAGE, PIC16F1764/5/8/9 ONLY
1.54
Max: Typical + 3ı
Typical: 25°C
Min: Typical - 3ı
1.52
1.50
Max.
Voltage (V)
1.48
1.46
1.44
Typical
1.42
1.40
Min.
1.38
1.36
1.34
-60
-40
-20
0
20
40
60
80
100
Temperature (°C)
 2014-2015 Microchip Technology Inc.
DS40001775B-page 523
PIC16(L)F1764/5/8/9
FIGURE 37-9:
BROWN-OUT RESET VOLTAGE, BORV = 1, PIC16LF1764/5/8/9 ONLY
2.00
Max.
Voltage (V)
1.95
Typical
1.90
1.85
Min.
Max: Typical + 3ı
Min: Typical - 3ı
1.80
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
FIGURE 37-10:
BROWN-OUT RESET HYSTERESIS, BORV = 1, PIC16LF1764/5/8/9 ONLY
60
50
Max.
Max: Typical + 3ı
Typical: 25°C
Min: Typical - 3ı
Voltage (mV)
40
Typical
30
20
Min.
10
0
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
DS40001775B-page 524
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
FIGURE 37-11:
BROWN-OUT RESET VOLTAGE, BORV = 1, PIC16F1764/5/8/9 ONLY
2.60
Max.
2.55
Voltage (V)
2.50
Typical
2.45
Min.
2.40
Max: Typical + 3ı
Min: Typical - 3ı
2.35
2.30
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
FIGURE 37-12:
BROWN-OUT RESET HYSTERESIS, BORV = 1, PIC16F1764/5/8/9 ONLY
70
Max.
60
Max: Typical + 3ı
Typical: 25°C
Min: Typical - 3ı
Voltage (mV)
50
40
Typical
30
20
Min.
10
0
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
 2014-2015 Microchip Technology Inc.
DS40001775B-page 525
PIC16(L)F1764/5/8/9
FIGURE 37-13:
BROWN-OUT RESET VOLTAGE, BORV = 0
2.80
2.75
Voltage (V)
Max.
2.70
Typical
2.65
Min.
Max: Typical + 3ı
Min: Typical - 3ı
2.60
2.55
-60
-40
-20
0
20
40
60
80
100
120
140
120
140
Temperature (°C)
FIGURE 37-14:
BROWN-OUT RESET HYSTERESIS, BORV = 0
90
80
Min.
70
Voltage (mV)
60
Typical
50
40
Max: Typical + 3ı
Typical: 25°C
Min: Typical - 3ı
30
20
Max.
10
0
-60
-40
-20
0
20
40
60
80
100
Temperature (°C)
DS40001775B-page 526
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
FIGURE 37-15:
LOW-POWER BROWN-OUT RESET VOLTAGE, LPBOR = 0
2.50
Max.
Max: Typical + 3ı
Min: Typical - 3ı
2.40
Voltage (V)
2.30
Typical
2.20
2.10
2.00
Min.
1.90
1.80
-60
-40
-20
0
20
40
60
80
100
120
140
120
140
Temperature (°C)
FIGURE 37-16:
LOW-POWER BROWN-OUT RESET HYSTERESIS, LPBOR = 0
45
Max: Typical + 3ı
Typical: 25°C
Min: Typical - 3ı
40
35
Max.
Typical
Voltage (mV)
30
25
Min.
20
15
10
5
0
-60
-40
-20
0
20
40
60
80
100
Temperature (°C)
 2014-2015 Microchip Technology Inc.
DS40001775B-page 527
PIC16(L)F1764/5/8/9
FIGURE 37-17:
WDT TIME-OUT PERIOD
24
22
Max.
Time (ms)
20
18
Typical
16
Min.
14
Max: Typical + 3ı (-40°C to +125°C)
Typical: statistical mean @ 25°C
Min: Typical - 3ı (-40°C to +125°C)
12
10
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 37-18:
PWRT PERIOD
100
Max: Typical + 3ı (-40°C to +125°C)
Typical: statistical mean @ 25°C
Min: Typical - 3ı (-40°C to +125°C)
90
Max.
Time (ms)
80
70
Typical
60
Min.
50
40
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001775B-page 528
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
FIGURE 37-19:
FVR STABILIZATION PERIOD
60
Max: Typical + 3ı
Typical: statistical mean @ 25°C
50
Max.
Time (us)
40
Typical
30
20
Note:
The FVR Stabilization Period applies when:
1) coming out of Reset or exiting Sleep mode for PIC12/16LFxxxx devices.
2) when exiting Sleep mode with VREGPM = 1 for PIC12/16Fxxxx devices
In all other cases, the FVR is stable when released from Reset.
10
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 37-20:
LFINTOSC FREQUENCY OVER VDD AND TEMPERATURE, PIC16LF1764/5/8/9
ONLY
36
34
Max.
Frequency (kHz)
32
30
Typical
28
Min.
26
24
Max: Typical + 3ı (-40°C to +125°C)
Typical: statistical mean @ 25°C
Min: Typical - 3ı (-40°C to +125°C)
22
20
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
 2014-2015 Microchip Technology Inc.
DS40001775B-page 529
PIC16(L)F1764/5/8/9
FIGURE 37-21:
LFINTOSC FREQUENCY OVER VDD AND TEMPERATURE, PIC16F1764/5/8/9
ONLY
36
34
Max.
Frequency (kHz)
32
30
Typical
28
26
Min.
24
Max: Typical + 3ı (-40°C to +125°C)
Typical: statistical mean @ 25°C
Min: Typical - 3ı (-40°C to +125°C)
22
20
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 37-22:
SLEEP MODE, WAKE PERIOD WITH HFINTOSC SOURCE, PIC16LF1764/5/8/9
ONLY
5.0
4.5
Max.
4.0
Time (us)
3.5
Typical
3.0
2.5
2.0
1.5
Max: 85°C + 3ı
Typical: 25°C
1.0
0.5
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
DS40001775B-page 530
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
FIGURE 37-23:
LOW-POWER SLEEP MODE, WAKE PERIOD WITH HFINTOSC SOURCE,
VREGPM = 1, PIC16F1764/5/8/9 ONLY
35
Max.
30
Typical
Time (us)
25
20
15
10
Max: 85°C + 3ı
Typical: 25°C
5
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 37-24:
SLEEP MODE, WAKE PERIOD WITH HFINTOSC SOURCE, VREGPM = 0,
PIC16F1764/5/8/9 ONLY
12
Max.
10
Time (us)
8
Typical
6
4
Max: 85°C + 3ı
Typical: 25°C
2
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
 2014-2015 Microchip Technology Inc.
DS40001775B-page 531
PIC16(L)F1764/5/8/9
NOTES:
DS40001775B-page 532
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
38.0
DEVELOPMENT SUPPORT
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range
of software and hardware development tools:
• Integrated Development Environment
- MPLAB® X IDE Software
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB X SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
- PICkit™ 3
• Device Programmers
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits and Starter Kits
• Third-party development tools
38.1
MPLAB X Integrated Development
Environment Software
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for highperformance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
With complete project management, visual call graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multiple projects with simultaneous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
Feature-Rich Editor:
• Color syntax highlighting
• Smart code completion makes suggestions and
provides hints as you type
• Automatic code formatting based on user-defined
rules
• Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
•
•
•
•
Multiple projects
Multiple tools
Multiple configurations
Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker
 2014-2015 Microchip Technology Inc.
DS40001775B-page 533
PIC16(L)F1764/5/8/9
38.2
MPLAB XC Compilers
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16, and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
For easy source level debugging, the compilers provide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
MPLAB XC Compilers include an assembler, linker and
utilities. The assembler generates relocatable object
files that can then be archived or linked with other relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler to
produce its object file. Notable features of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
38.3
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
The MPASM Assembler features include:
38.4
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
38.5
MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archived or linked with other relocatable object
files and archives to create an executable file. Notable
features of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process
DS40001775B-page 534
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
38.6
MPLAB X SIM Software Simulator
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory environment, making it an excellent, economical software
development tool.
38.7
MPLAB REAL ICE In-Circuit
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection
(CAT5).
The emulator is field upgradeable through future firmware downloads in MPLAB X IDE. MPLAB REAL ICE
offers significant advantages over competitive emulators
including full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, logic
probes, a ruggedized probe interface and long (up to
three meters) interconnection cables.
 2014-2015 Microchip Technology Inc.
38.8
MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the MPLAB
IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a highspeed USB 2.0 interface and is connected to the target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
38.9
PICkit 3 In-Circuit Debugger/
Programmer
The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineer’s PC using a fullspeed USB interface and can be connected to the target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming™ (ICSP™).
38.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
DS40001775B-page 535
PIC16(L)F1764/5/8/9
38.11 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide application firmware and source code for examination and
modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
38.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. These tools are carefully selected
to offer good value and unique functionality.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Software Tools from companies, such as Gimpel
and Trace Systems
• Protocol Analyzers from companies, such as
Saleae and Total Phase
• Demonstration Boards from companies, such as
MikroElektronika, Digilent® and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS40001775B-page 536
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
39.0
PACKAGING INFORMATION
39.1
Package Marking Information
14-Lead PDIP (300 mil)
Example
PIC16F1764
-P e3
1404017
28-Lead SOIC (7.50 mm)
14-Lead SOIC (3.90 mm)
Example
Example
PIC16F1764
-SO e3
1404017
14-Lead TSSOP (4.4 mm)
Example
XXXXXXXX
YYWW
NNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
16F1764
1404
017
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC® designator e( 3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 537
PIC16(L)F1764/5/8/9
Package Marking Information (Continued)
16-Lead QFN (4x4x0.9 mm)
PIN 1
Example
PIN 1
PIC16
F1765
-MV
140417
e3
20-Lead PDIP (300 mil)
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
20-Lead SSOP (5.30 mm)
Example
PIC16F1768
-ML e3
140417
Example
PIC16F1769
-PT e3
140417
20-Lead SOIC (7.50 mm)
Example
PIC16F1769
-PT e3
140417
DS40001775B-page 538
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
Package Marking Information (Continued)
20-Lead QFN (4x4x0.9 mm)
PIN 1
Example
PIN 1
PIC16
F1769
-MV
140417
e3
 2014-2015 Microchip Technology Inc.
DS40001775B-page 539
PIC16(L)F1764/5/8/9
39.2
Package Details
The following sections give the technical details of the packages.
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 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2014-2015 Microchip Technology Inc.
DS40001775B-page 541
PIC16(L)F1764/5/8/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001775B-page 542
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
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DS40001775B-page 543
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Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001775B-page 544
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2014-2015 Microchip Technology Inc.
DS40001775B-page 545
PIC16(L)F1764/5/8/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001775B-page 546
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
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 2014-2015 Microchip Technology Inc.
DS40001775B-page 547
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Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001775B-page 548
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
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 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2014-2015 Microchip Technology Inc.
DS40001775B-page 551
PIC16(L)F1764/5/8/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001775B-page 552
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2014-2015 Microchip Technology Inc.
DS40001775B-page 553
PIC16(L)F1764/5/8/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001775B-page 554
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
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DS40001775B-page 556
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
APPENDIX A:
DATA SHEET
REVISION HISTORY
Revision A (12/2014)
Initial release of this document.
Revision B (09/2015)
Added Section 5.3.5 “Clock Switch Before Sleep”.
Updated Cover page; Example 3-2; Figures 19-2, 31-2,
31-3, and 31-4; Registers 14-4, 16-3, 19-4, 24-2, 26-6,
27-4, 27-6, 27-8, 27-10, and 30-3; Sections 12.0, 12.2,
23.3.3, 23.6, 29.1 and 30.10; and Tables 1, 3, 4, 3-16,
5-1, 12-1, 16-1, 27-4, 28-1, 29-2, 30-2, 30-5, 36-2,
36-3, 36-8 and 36-11.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 557
PIC16(L)F1764/5/8/9
NOTES:
DS40001775B-page 558
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers
should
contact
their
distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
 2014-2015 Microchip Technology Inc.
DS40001775B-page 559
PIC16(L)F1764/5/8/9
NOTES:
DS40001775B-page 560
 2014-2015 Microchip Technology Inc.
PIC16(L)F1764/5/8/9
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office .
[X](1)
PART NO.
Device
-
X
Tape and Reel Temperature
Option
Range
/XX
XXX
Package
Pattern
Examples:
a)
b)
Device:
PIC16F1764, PIC16LF1764,
PIC16F1765, PIC16LF1765,
PIC16F1768, PIC16LF1768,
PIC16F1769, PIC16LF1769
Tape and Reel
Option:
Blank
T
= Standard packaging (tube or tray)
= Tape and Reel(1)
Temperature
Range:
I
E
= -40C to +85C
= -40C to +125C
Package:(2)
ML
P
SL
SO
SS
ST
=
=
=
=
=
=
Pattern:
(Industrial)
(Extended)
QFN
PDIP
SOIC
SOIC
SSOP
TSSOP
QTP, SQTP, Code or Special Requirements
(blank otherwise)
 2014-2015 Microchip Technology Inc.
Note
PIC16LF1764- I/P
Industrial temperature
PDIP package
PIC16F1769- E/SS
Extended temperature,
SSOP package
1:
2:
Tape and Reel identifier only appears in
the catalog part number description. This
identifier is used for ordering purposes and
is not printed on the device package.
Check with your Microchip Sales Office
for package availability with the Tape and
Reel option.
Small form-factor packaging options may
be available. Please check
www.microchip.com/packaging for
small-form factor package availability, or
contact your local Sales Office.
DS40001775B-page 561
PIC16(L)F1764/5/8/9
NOTES:
DS40001775B-page 562
 2014-2015 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O,
Total Endurance, TSHARC, USBCheck, VariSense,
ViewSpan, WiperLock, Wireless DNA, and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2014-2015, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63277-833-8
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
 2014-2015 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS40001775B-page 563
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Germany - Dusseldorf
Tel: 49-2129-3766400
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Austin, TX
Tel: 512-257-3370
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
China - Dongguan
Tel: 86-769-8702-9880
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
Germany - Karlsruhe
Tel: 49-721-625370
India - Pune
Tel: 91-20-3019-1500
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Italy - Venice
Tel: 39-049-7625286
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-213-7828
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Poland - Warsaw
Tel: 48-22-3325737
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
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