Data Sheet

74LVC2G241-Q100
Dual buffer/line driver; 3-state
Rev. 1 — 4 April 2013
Product data sheet
1. General description
The 74LVC2G241-Q100 is a dual non-inverting buffer/line driver with 3-state outputs. The
output enable inputs 1OE and 2OE control the 3-state outputs:
• A HIGH level at pin 1OE causes output 1Y to assume a high-impedance OFF-state.
• A LOW level at pin 2OE causes output 2Y to assume a high-impedance OFF-state.
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and
fall times. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the
use of the 74LVC2G241-Q100 as a translator in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +85 C and from 40 C to +125 C
 Wide supply voltage range from 1.65 V to 5.5 V
 5 V tolerant input/output for interfacing with 5 V logic
 High noise immunity
 Complies with JEDEC standard:
 JESD8-7 (1.65 V to 1.95 V)
 JESD8-5 (2.3 V to 2.7 V)
 JESD8-B/JESD36 (2.7 V to 3.6 V)
 ESD protection:
 MIL-STD-883, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
 24 mA output drive (VCC = 3.0 V)
 CMOS low power consumption
 Latch-up performance exceeds 250 mA
 Direct interface with TTL levels
 Inputs accept voltages up to 5 V
 Multiple package options
74LVC2G241-Q100
NXP Semiconductors
Dual buffer/line driver; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
40 C to +125 C
TSSOP8
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
74LVC2G241DC-Q100 40 C to +125 C
VSSOP8
plastic very thin shrink small outline package;
8 leads; body width 2.3 mm
SOT765-1
74LVC2G241DP-Q100
4. Marking
Table 2.
Marking codes
Type number
Marking code[1]
74LVC2G241DP-Q100
V241
74LVC2G241DC-Q100
V41
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1OE
1A
1Y
1
EN1
2OE
2A
2Y
2
EN2
001aah844
Fig 1.
001aah845
Logic symbol
Fig 2.
IEC logic symbol
6. Pinning information
6.1 Pinning
/9&*4
2(
9&&
$
2(
<
<
*1'
$
DDD
Fig 3.
Pin configuration SOT505-2 and SOT765-1
74LVC2G241_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 April 2013
© NXP B.V. 2013. All rights reserved.
2 of 15
74LVC2G241-Q100
NXP Semiconductors
Dual buffer/line driver; 3-state
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
1OE
1
output enable input (active LOW)
1A, 2A
2, 5
data input
GND
4
ground (0 V)
1Y, 2Y
6, 3
data output
2OE
7
output enable input (active HIGH)
VCC
8
supply voltage
7. Functional description
Table 4.
Function table[1]
Input
Output
1OE
1A
2OE
2A
1Y
2Y
L
L
H
L
L
L
L
H
H
H
H
H
H
X
L
X
Z
Z
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
Conditions
VI < 0 V
[1]
Min
Max
Unit
0.5
+6.5
V
50
-
mA
0.5
+6.5
V
VI
input voltage
IOK
output clamping current
VO > VCC or VO < 0 V
-
50
mA
VO
output voltage
enable mode
[1]
0.5
VCC + 0.5
V
disable mode
[1]
0.5
+6.5
V
[1][2]
0.5
+6.5
V
Power-down mode
IO
output current
-
50
mA
ICC
supply current
-
100
mA
IGND
ground current
100
-
mA
Tstg
storage temperature
65
+150
C
-
300
mW
total power dissipation
Ptot
VO = 0 V to VCC
Tamb = 40 C to +125 C
[3]
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3]
For TSSOP8 packages: above 55 C the value of Ptot derates linearly at 2.5 mW/K.
For VSSOP8 packages: above 110 C the value of Ptot derates linearly at 8.0 mW/K.
74LVC2G241_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 April 2013
© NXP B.V. 2013. All rights reserved.
3 of 15
74LVC2G241-Q100
NXP Semiconductors
Dual buffer/line driver; 3-state
9. Recommended operating conditions
Table 6.
Operating conditions
Symbol
Parameter
VCC
Conditions
Min
Max
Unit
supply voltage
1.65
5.5
V
VI
input voltage
0
5.5
V
VO
output voltage
VCC = 1.65 V to 5.5 V; enable mode
0
VCC
V
VCC = 1.65 V to 5.5 V; disable mode
0
5.5
V
VCC = 0 V; Power-down mode
0
5.5
V
40
+125
C
Tamb
ambient temperature
t/V
input transition rise and fall rate
VCC = 1.65 V to 2.7 V
-
20
ns/V
VCC = 2.7 V to 5.5 V
-
10
ns/V
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ[1] Max
VCC = 1.65 V to 1.95 V
0.65  VCC
-
-
V
VCC = 2.3 V to 2.7 V
1.7
-
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
V
VCC = 4.5 V to 5.5 V
0.7  VCC
-
-
V
VCC = 1.65 V to 1.95 V
-
-
0.35  VCC V
VCC = 2.3 V to 2.7 V
-
-
0.7
V
VCC = 2.7 V to 3.6 V
-
-
0.8
V
VCC = 4.5 V to 5.5 V
-
-
0.3  VCC
V
IO = 100 A; VCC = 1.65 V to 5.5 V
-
-
0.1
V
IO = 4 mA; VCC = 1.65 V
-
-
0.45
V
IO = 8 mA; VCC = 2.3 V
-
-
0.3
V
Unit
Tamb = 40 C to +85 C
VIH
VIL
VOL
VOH
II
HIGH-level input voltage
LOW-level input voltage
LOW-level output voltage
VI = VIH or VIL
IO = 12 mA; VCC = 2.7 V
-
-
0.4
V
IO = 24 mA; VCC = 3.0 V
-
-
0.55
V
IO = 32 mA; VCC = 4.5 V
-
-
0.55
V
HIGH-level output voltage VI = VIH or VIL
input leakage current
74LVC2G241_Q100
Product data sheet
IO = 100 A; VCC = 1.65 V to 5.5 V
VCC  0.1
-
-
V
IO = 4 mA; VCC = 1.65 V
1.2
-
-
V
IO = 8 mA; VCC = 2.3 V
1.9
-
-
V
IO = 12 mA; VCC = 2.7 V
2.2
-
-
V
IO = 24 mA; VCC = 3.0 V
2.3
-
-
V
IO = 32 mA; VCC = 4.5 V
3.8
-
-
V
-
0.1
5
A
VI = 5.5 V or GND; VCC = 0 V to 5.5 V
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 April 2013
© NXP B.V. 2013. All rights reserved.
4 of 15
74LVC2G241-Q100
NXP Semiconductors
Dual buffer/line driver; 3-state
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ[1] Max
Unit
IOZ
OFF-state output current
VI = VIH or VIL; VO = 5.5 V or GND;
VCC = 3.6 V
-
0.1
A
IOFF
power-off leakage current
VI or VO = 5.5 V; VCC = 0 V
-
0.1
10
A
ICC
supply current
VI = 5.5 V or GND; IO = 0 A;
VCC = 1.65 V to 5.5 V
-
0.1
10
A
ICC
additional supply current
per pin; VI = VCC  0.6 V; IO = 0 A;
VCC = 2.3 V to 5.5 V
-
5
500
A
CI
input capacitance
-
2
-
pF
VCC = 1.65 V to 1.95 V
0.65  VCC
-
-
V
VCC = 2.3 V to 2.7 V
1.7
-
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
V
VCC = 4.5 V to 5.5 V
0.7  VCC
-
-
V
VCC = 1.65 V to 1.95 V
-
-
0.35  VCC V
10
Tamb = 40 C to +125 C
HIGH-level input voltage
VIH
LOW-level input voltage
VIL
LOW-level output voltage
VOL
VOH
VCC = 2.3 V to 2.7 V
-
-
0.7
V
VCC = 2.7 V to 3.6 V
-
-
0.8
V
VCC = 4.5 V to 5.5 V
-
-
0.3  VCC
V
IO = 100 A; VCC = 1.65 V to 5.5 V
-
-
0.1
V
IO = 4 mA; VCC = 1.65 V
-
-
0.70
V
IO = 8 mA; VCC = 2.3 V
-
-
0.45
V
IO = 12 mA; VCC = 2.7 V
-
-
0.60
V
IO = 24 mA; VCC = 3.0 V
-
-
0.80
V
IO = 32 mA; VCC = 4.5 V
-
-
0.80
V
IO = 100 A; VCC = 1.65 V to 5.5 V
VCC  0.1
-
-
V
VI = VIH or VIL
HIGH-level output voltage VI = VIH or VIL
IO = 4 mA; VCC = 1.65 V
0.95
-
-
V
IO = 8 mA; VCC = 2.3 V
1.7
-
-
V
IO = 12 mA; VCC = 2.7 V
1.9
-
-
V
IO = 24 mA; VCC = 3.0 V
2.0
-
-
V
IO = 32 mA; VCC = 4.5 V
3.4
-
-
V
II
input leakage current
VI = 5.5 V or GND; VCC = 0 V to 5.5 V
-
-
20
A
IOZ
OFF-state output current
VI = VIH or VIL; VO = 5.5 V or GND;
VCC = 3.6 V
-
-
20
A
IOFF
power-off leakage current
VI or VO = 5.5 V; VCC = 0 V
-
-
20
A
ICC
supply current
VI = 5.5 V or GND; IO = 0 A;
VCC = 1.65 V to 5.5 V
-
-
40
A
ICC
additional supply current
per pin; VI = VCC  0.6 V; IO = 0 A;
VCC = 2.3 V to 5.5 V
-
-
5
mA
[1]
Typical values are measured at VCC = 3.3 V and Tamb = 25 C.
74LVC2G241_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 April 2013
© NXP B.V. 2013. All rights reserved.
5 of 15
74LVC2G241-Q100
NXP Semiconductors
Dual buffer/line driver; 3-state
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter
tpd
ten
40 C to +85 C
Conditions
Min
Max
Min
Max
VCC = 1.65 V to 1.95 V
1.0
4.5
8.8
1.0
11.0
ns
VCC = 2.3 V to 2.7 V
0.5
2.8
4.9
0.5
6.3
ns
VCC = 2.7 V
1.0
2.8
4.7
1.0
5.9
ns
VCC = 3.0 V to 3.6 V
0.5
2.6
4.3
0.5
5.4
ns
VCC = 4.5 V to 5.5 V
0.5
2.1
3.7
0.5
4.6
ns
VCC = 1.65 V to 1.95 V
1.5
5.2
9.9
1.5
12.4
ns
VCC = 2.3 V to 2.7 V
1.0
3.1
5.6
1.0
7.0
ns
VCC = 2.7 V
1.5
3.2
5.5
1.5
6.9
ns
VCC = 3.0 V to 3.6 V
0.5
2.7
4.7
0.5
5.9
ns
0.5
2.0
3.8
0.5
4.8
ns
VCC = 1.65 V to 1.95 V
1.0
4.3
8.8
1.0
11.0
ns
VCC = 2.3 V to 2.7 V
1.0
2.7
4.7
1.0
5.9
ns
VCC = 2.7 V
1.0
2.7
4.6
1.0
5.8
ns
VCC = 3.0 V to 3.6 V
1.0
2.5
4.1
1.0
5.1
ns
VCC = 4.5 V to 5.5 V
0.5
1.9
3.3
0.5
4.1
ns
VCC = 1.65 V to 1.95 V
1.0
3.2
11.6
1.0
14.1
ns
VCC = 2.3 V to 2.7 V
0.5
2.2
5.8
0.5
7.6
ns
VCC = 2.7 V
1.0
2.8
4.6
1.0
5.9
ns
VCC = 3.0 V to 3.6 V
1.0
2.6
4.4
1.0
5.7
ns
0.5
2.0
3.4
0.5
4.6
ns
VCC = 1.65 V to 1.95 V
1.0
3.6
12.5
1.0
15.2
ns
VCC = 2.3 V to 2.7 V
0.5
2.0
5.2
0.5
6.9
ns
VCC = 2.7 V
1.5
3.2
4.9
1.5
6.3
ns
VCC = 3.0 V to 3.6 V
1.0
2.8
4.2
1.0
5.4
ns
VCC = 4.5 V to 5.5 V
0.5
2.0
3.3
0.5
4.4
ns
propagation delay nA to nY; see Figure 4
enable time
1OE to 1Y; see Figure 5
[2]
[3]
VCC = 4.5 V to 5.5 V
2OE to 2Y; see Figure 6
tdis
disable time
1OE to 1Y; see Figure 5
[3]
[4]
VCC = 4.5 V to 5.5 V
2OE to 2Y; see Figure 6
74LVC2G241_Q100
Product data sheet
40 C to +125 C Unit
Typ[1]
[4]
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Rev. 1 — 4 April 2013
© NXP B.V. 2013. All rights reserved.
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74LVC2G241-Q100
NXP Semiconductors
Dual buffer/line driver; 3-state
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter
CPD
[1]
power dissipation
capacitance
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
output enabled
-
20
-
-
-
pF
output disabled
-
5
-
-
-
pF
[5]
per buffer; VI = GND to VCC
Typical values are measured at nominal VCC and at Tamb = 25 C.
[2]
tpd is the same as tPLH and tPHL.
[3]
ten is the same as tPZH and tPZL.
[4]
tdis is the same as tPLZ and tPHZ.
[5]
40 C to +85 C
Conditions
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL  VCC2  fo) = sum of outputs.
12. Waveforms
VI
VM
nA input
GND
tPHL
tPLH
VOH
VM
nY output
VOL
mna230
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 4.
The data input (nA) to output (nY) propagation delays
Table 9.
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
VX
VY
1.65 V to 1.95 V
0.5  VCC
0.5  VCC
VOL + 0.15 V
VOH  0.15 V
2.3 V to 2.7 V
0.5  VCC
0.5  VCC
VOL + 0.15 V
VOH  0.15 V
2.7 V
1.5 V
1.5 V
VOL + 0.3 V
VOH  0.3 V
3.0 V to 3.6 V
1.5 V
1.5 V
VOL + 0.3 V
VOH  0.3 V
4.5 V to 5.5 V
0.5  VCC
0.5  VCC
VOL + 0.3 V
VOH  0.3 V
74LVC2G241_Q100
Product data sheet
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Rev. 1 — 4 April 2013
© NXP B.V. 2013. All rights reserved.
7 of 15
74LVC2G241-Q100
NXP Semiconductors
Dual buffer/line driver; 3-state
VI
1OE input
VM
GND
t PLZ
t PZL
VCC
output
LOW-to-OFF
OFF-to-LOW
VM
VX
VOL
t PZH
t PHZ
VOH
VY
output
HIGH-to-OFF
OFF-to-HIGH
VM
GND
outputs
enabled
outputs
enabled
outputs
disabled
mna730
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5.
Enable and disable times for input 1OE
VI
2OE input
VM
GND
t PLZ
t PZL
VCC
output
LOW-to-OFF
OFF-to-LOW
VM
VX
VOL
t PZH
t PHZ
VOH
VY
output
HIGH-to-OFF
OFF-to-HIGH
VM
GND
outputs
enabled
outputs
disabled
outputs
enabled
mna731
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6.
Enable and disable times for input 2OE
74LVC2G241_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 April 2013
© NXP B.V. 2013. All rights reserved.
8 of 15
74LVC2G241-Q100
NXP Semiconductors
Dual buffer/line driver; 3-state
tW
VI
90 %
negative
pulse
VM
VM
10 %
0V
VI
tf
tr
tr
tf
90 %
positive
pulse
VM
VM
10 %
0V
tW
VEXT
VCC
PULSE
GENERATOR
VI
RL
VO
DUT
RT
CL
RL
001aae235
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
Fig 7.
Test circuit for measuring switching times
Table 10.
Test data
Supply voltage
Input
Load
VI
CL
RL
VEXT
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
1.65 V to 1.95 V
VCC
30 pF
1 k
open
GND
2  VCC
2.3 V to 2.7 V
VCC
30 pF
500 
open
GND
2  VCC
2.7 V
2.7 V
50 pF
500 
open
GND
6V
3.0 V to 3.6 V
2.7 V
50 pF
500 
open
GND
6V
4.5 V to 5.5 V
VCC
50 pF
500 
open
GND
2  VCC
74LVC2G241_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 April 2013
© NXP B.V. 2013. All rights reserved.
9 of 15
74LVC2G241-Q100
NXP Semiconductors
Dual buffer/line driver; 3-state
13. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
D
E
A
SOT505-2
X
c
HE
y
v M A
Z
5
8
A
A2
(A3)
A1
pin 1 index
θ
Lp
L
1
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(1)
e
HE
L
Lp
v
w
y
Z(1)
θ
mm
1.1
0.15
0.00
0.95
0.75
0.25
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
0.65
4.1
3.9
0.5
0.47
0.33
0.2
0.13
0.1
0.70
0.35
8°
0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT505-2
Fig 8.
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
02-01-16
---
Package outline SOT505-2 (TSSOP8)
74LVC2G241_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 April 2013
© NXP B.V. 2013. All rights reserved.
10 of 15
74LVC2G241-Q100
NXP Semiconductors
Dual buffer/line driver; 3-state
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
D
E
SOT765-1
A
X
c
y
HE
v M A
Z
5
8
Q
A
A2
A1
pin 1 index
(A3)
θ
Lp
1
4
e
L
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(2)
e
HE
L
Lp
Q
v
w
y
Z(1)
θ
mm
1
0.15
0.00
0.85
0.60
0.12
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
0.5
3.2
3.0
0.4
0.40
0.15
0.21
0.19
0.2
0.13
0.1
0.4
0.1
8°
0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT765-1
Fig 9.
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
02-06-07
MO-187
Package outline SOT765-1 (VSSOP8)
74LVC2G241_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 April 2013
© NXP B.V. 2013. All rights reserved.
11 of 15
74LVC2G241-Q100
NXP Semiconductors
Dual buffer/line driver; 3-state
14. Abbreviations
Table 11.
Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MIL
Military
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LVC2G241_Q100 v.1
20130404
Product data sheet
-
-
74LVC2G241_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 April 2013
© NXP B.V. 2013. All rights reserved.
12 of 15
74LVC2G241-Q100
NXP Semiconductors
Dual buffer/line driver; 3-state
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74LVC2G241_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 April 2013
© NXP B.V. 2013. All rights reserved.
13 of 15
74LVC2G241-Q100
NXP Semiconductors
Dual buffer/line driver; 3-state
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVC2G241_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 April 2013
© NXP B.V. 2013. All rights reserved.
14 of 15
NXP Semiconductors
74LVC2G241-Q100
Dual buffer/line driver; 3-state
18. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 4 April 2013
Document identifier: 74LVC2G241_Q100