CFL Ballast Design Using Passive PFC and Crest Factor Control

Application Note AN-1157
CFL Ballast Design
Using Passive PFC and Crest Factor Control
By Masashi Sekine and Tom Ribarich
Table of Contents
Page
Introduction ...................................................................................................1
Functional Description ................................................................................. 2
Conclusion …................................................................................................ 5
Introduction
Compact fluorescent lamps (CFLs) are now replacing incandescent bulbs
because of longer life time and energy saving.
Most CFLs seen in the market are electronic ballast integrated CFLs. Due to the
cost, these electronic ballasts don’t include PFC circuit witch typically requires
additional control IC, inductor and switch, resulting in low power factor and high
THD.
This application note describes a CFL ballast using valley fill passive PFC circuit
and IR2520D ballast control IC. This ballast design achieves high power factor
(>0.9), low THD (<30%) and regulated lamp current crest factor without typical
active PFC circuit.
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Functional Description
Valley Fill Passive PFC Circuit
Figure 1 shows the valley fill circuitry to achieve high power factor and low THD
in simple and low cost.
Fig.1: 50% Valley Fill Passive PFC Circuit
Fig. 2: Valley Fill Circuit Waveforms
Upper: DC BUS (in Yellow), Middle Front: Iinput (Red)
Middle Back: ILamp (in Green), Lower: VLamp (in Blue)
The capacitors CVF1 and CVF2 are charged to ½ of the AC peak voltage in
series via the diode DVF2 and resistor RVF on each half cycle of the rectified AC
input. RVF is for reducing the peaks in the current waveform as the capacitors
charge. They supply output current after the BUS voltage follows the sinusoidal
waveform down to Vpeak/2. At this time the caps are essentially in parallel an
supply load current until the rectified AC input again exceeds Vpeak/2 on the next
half cycle. This valley fill passive PFC circuit presents good power factor (>0.9)
and low THD (<30%), the major drawback is the 50% DC BUS ripple witch result
in a very high lamp current crest factor. (Fig.2)
The capacitor CX is for filtering the half-bridge inverter switching spikes witch
appears at DC BUS. Especially at the light load condition or at the peak of AC
input, a big spike occurs at every switching cycle when switching frequency
decreases towards resonance causing load voltage and current to increase as
seen in Figure 3. Table 1 shows bigger CX cap value gives better filtering, but
also decreases PF value.
Fig.3: Half-Bridge Inverter Switching Waveforms
Upper: with CX (in Red), Lower: without CX (in Yellow)
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Table 1: PF Value vs. CX Value
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Lamp Current Crest Factor Control Circuit
If the ballast operating frequency is fixed, 50% DC BUS ripple caused by valley
fill circuit generates very high lamp current crest factor because higher DC BUS
voltage gives higher lamp current in the resonant output stage. Since high lamp
current crest factor shortens lamp life, a compensation circuit is required to
decrease lamp current crest factor. Figure 4 shows the crest factor control circuit
by modulating half-bridge inverter switching frequency when IR2520D is used for
controlling the ballast.
VCO
(IR2520D
Pin 2)
FMIN
(IR2520D
Pin 3)
to DC BUS
(+)
RFMIN2
RBUS1
CVCO
QFMIN
RFMIN1
RFMIN3
RBUS2
to DC BUS
(-)
Fig.4: Lamp Current Crest Factor Control Circuit
Since IR2520D has VCO with externally programmable minimum frequency,
half-bridge inverter switching frequency is determined by the voltage on VCO pin
and the value of resistor connected to FMIN pin. (Please refer to the IR2520D
datasheet for detail.) When DC BUS reaches a certain voltage, the voltage on
the base of QFMIN connected to the voltage divider, which consists of RBUS1
and RBUS2, exceeds the QFMIN conduction threshold and then QFMIN turns
on. At this case, the resistance between FMIN pin and ground becomes parallel
RFMIN1 and series RFMIN2 and RFMIN3, which is lower than RFMIN1. Since
lower resistance on FMIN pin gives higher switching frequency, the inverter
switching frequency at near peak of the DC BUS is higher than at near valley of
the DC BUS. As a result, crest factor value witch is given by ILAMP(pk) / ILAMP(avg)
will be decreased.
Fig.5: Waveforms without crest factor control circuit
Fig. 6: Waveforms without crest factor control circuit
CF =1.95, half-Bridge (Upper), ILMAP (Mid), VLMAP (Lower)
CF =1.71, Half-Bridge (Upper), ILMAP (Mid), VLMAP (Lower)
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Fig. 8: Waveforms at Near DC BUS Peak
fSWITCH =61.6KHz, MLS Drain (Yellow), ILMAP (Green),
Fig.7: Waveforms at Near DC BUS Valley
fSWITCH =53.0KHz, MLS Drain (Yellow), ILMAP (Green),
DC BUS (Red), VLMAP (Blue)
DC BUS (Red), VLMAP (Blue)
The purpose of RFMIN3 is emitter degeneration for improving linearity. Without
RFMIN3, QFMIN turns on quickly when the voltage on base of QFMIN reaches
threshold. This causes lamp current shape distortion because of rapid operating
frequency increase.
Fig. 10: Waveforms with RFMIN3
Fig.9: Waveforms with RFMIN3 short
ILMAP (Upper), DC BUS (Mid), VLMAP (Lower)
ILMAP (Upper), DC BUS (Mid), VLMAP (Lower)
Electronic Ballast Design
Figure 11 shows the complete CFL ballast design. This ballast includes AC input
stage with EMI filter, valley fill PFC stage, ballast control stage using IR2520D
adaptive ballast control IC and lamp current crest factor control circuit, half-bridge
inverter and resonant output stage.
RSUPPLY
+
CVF1
PL
LF
F1
DB3
DVF2
IC1
RVF
1
LAMP
MHS
RBUS1
DVF3
DB1
RMHS
8
CF
2
DB2
+
DVF1
3
CVF2
CVCC
CX
4
IR2520D
DB4
PN
7
CBS
1
A1
6
LRES
A2 A3
A4
CDC
6
CRES
MLS
5
RMLS
CSNUB
RFMIN2
DCP2
QFMIN
RFMIN1
CVCO
RFMIN3
RBUS2
DCP1
Fig.11: Electronic CFL ballast Circuit using IR2520D
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Measurements
Table 2 shows measurement results. Following are the measurement conditions:
1. AC input: 200VAC to 260VAC
2. Lamp Type: 23W Spiral
3. Bill of Material
Parameter
Input
200VAC
220VAC
240VAC
260VAC
Pin (W)
Iin (mA)
PF
THD (%)
Lamp CF
19.7
20.1
21.4
21.5
97.3
88.1
85.4
83.5
0.965
0.961
0.959
0.957
25.8
27.5
28.5
28.9
1.62
1.71
1.78
1.84
Table 2: Major Electrical Parameters
Conclusion
This application note suggests a CFL ballast circuit that achieves good power
factor and low THD in cost effective way. The design includes low cost PFC
stage and control stage using IR2520D 8-pin ballast control IC. Because of the
simplicity of the ballast control method, total number of components used in this
ballast is minimized, however, the design satisfies all of the necessary ballast
features.
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