ATS128 Datasheet

ATS128LSE
Highly Programmable, Back-Biased, Hall-Effect Switch
with TPOS Functionality
Features and Benefits
Description
• Chopper stabilization for stable switchpoints throughout
operating temperature range
• User-programmable:
▫ Magnetic operate point through the VCC pin:
9 programming bits provide 4-gauss resolution
▫ Output polarity
▫ Output fall time for reduced EMI in
automotive applications
• On-board voltage regulator for 3 to 24 V operation
• On-chip protection against:
▫ Supply transients
▫ Output short-circuits
▫ Reverse battery condition
• True Zero-Speed Operation
• True Power-On State
The ATS128LSE programmable, true power-on state (TPOS),
sensor IC is an optimized combination of Hall-effect IC and
rare-earth pellet that switches in response to magnetic signals
created by ferromagnetic targets in gear-tooth sensing and
proximity sensing applications.
These devices offer a wide programming range for the magnetic
operate point, BOP . A fixed hysteresis then sets the magnetic
release point, BRP , based on the selected BOP .
The devices are externally programmable. A wide range of
programmability is available on the magnetic operate point,
BOP , while the hysteresis remains fixed. This advanced
feature allows optimization of the sensor IC switchpoint and
can drastically reduce the effects of mechanical placement
tolerances found in production environments.
A proprietary dynamic offset cancellation technique, with
an internal high-frequency clock, reduces the residual offset
voltage, which is normally caused by device overmolding,
temperature dependencies, and thermal stress. Having the Hall
element and amplifier in a single chip minimizes many problems
normally associated with low-level analog signals.
Package: 4-pin SIP (suffix SE)
This device is ideal for use in gathering speed or position
information using gear-tooth–based configurations, or for
proximity sensing with ferromagnetic targets.
The ATS128 is provided in a 4-pin SIP. It is lead (Pb) free,
with 100% matte tin leadframe plating.
Not to scale
Functional Block Diagram
VCC
To all subcircuits
Regulator
Trim Control
Dynamic Offset
Cancellation
TC Trim
Amp
Switchpoint
Signal Recovery
Output Fall Time
Program Control
Output Polarity
GND
ATS128LSE-DS
VOUT
Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
Selection Guide
Part Number
Packing*
ATS128LSETN-T
450 pieces per 13-in. reel
*Contact Allegro™ for additional packing options
Absolute Maximum Ratings
Rating
Unit
Forward Supply Voltage
Characteristic
VCC
28
V
Reverse Supply Voltage
VRCC
–18
V
Forward Output Voltage
VOUT
28
V
Reverse Output Voltage
VROUT
–0.7
V
20
mA
Output Current Sink
Symbol
IOUT(SINK)
Notes
Internal current limiting is intended to protect
the device from output short circuits, but is not
intended for continuous operation.
Operating Ambient Temperature
TA
–40 to 150
ºC
Maximum Junction Temperature
TJ(max)
165
ºC
Tstg
–65 to 170
ºC
Storage Temperature
L temperature range
Pin-out Diagram
Terminal List Table
1 2
3
4
Number
Name
1
VCC
2
VOUT
3
NC
4
GND
Function
Input power supply
Output signal
No connect
Ground
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
OPERATING CHARACTERISTICS Valid with TA = –40°C to 150°C, CBYPASS = 0.1 μF, VCC = 12 V, unless otherwise noted
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Electrical Characteristics
Supply Voltage
VCC
Supply Current
ICC
3
12
24
V
No load on VOUT
–
–
5.5
mA
Supply Zener Clamp Voltage
VZSUPPLY
TA = 25°C, ICC = ICC(max) + 3 mA
28
–
–
V
Supply Zener Current
IZSUPPLY
VCC = 28 V
–
–
8.5
mA
Output Zener Clamp Voltage
VZOUTPUT
IOUT = 3 mA
28
–
–
V
IRCC
VCC = –18 V
–5
–
–
mA
–
400
–
kHz
–
–
30
μs
Reverse Battery Current
Chopping Frequency
fC
Power-On Characteristics
Power-On Time1
tPO
Power-On State2
POS
TA = 25°C; CLOAD (PROBE) = 10 pF
POL = 0
B < BRP , t > ton
–
High
–
–
POL = 1
B < BRP , t > ton
–
Low
–
–
–
175
400
mV
Output Stage Characteristics
Output Saturation Voltage
Output Leakage Current
Output Current Limit
Output Rise
Time3
Output Fall Time4
Continued on the next page…
VOUT(sat)
Output = On, IOUT = 20 mA
IOFF
VOUT = 24 V; Output = Off
–
–
10
μA
Short-Circuit Protection, Output = On
30
–
90
mA
VCC = 12 V, RPU = 820 Ω, CLOAD = 10 pF,
see figure 1
–
–
2
μs
VCC = 12 V, RPU = 2 kΩ, CLOAD = 4.7 nF,
see figure 1
–
21
–
μs
IOUT(lim)
tr
FALL = 0
VCC = 12 V, RLOAD = 820 Ω,
CLOAD = 10 pF, see figure 1
–
–
2
μs
FALL = 1
VCC = 12 V, RLOAD = 2 kΩ,
CLOAD = 4.7 nF, see figure 1
5
–
10
μs
FALL = 3
VCC = 12 V, RLOAD = 2 kΩ,
CLOAD = 4.7 nF, see figure 1
8
–
13
μs
FALL = 4
VCC = 12 V, RLOAD = 2 kΩ,
CLOAD = 4.7 nF, see figure 1
10
–
16
μs
tf
V+
VOUT(High)
%
100
90
10
0
VOUT(Low)
tr
tf
Figure 1. Rise Time and Fall Time Definitions
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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3
Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
OPERATING CHARACTERISTICS (continued) Valid with TA = –40°C to 150°C, CBYPASS = 0.1 μF, VCC = 12 V,
unless otherwise noted
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
B > BOP , opposite tooth
–
Low
–
–
Output Stage Characteristics (continued)
POL = 0
Output Polarity2
POL
POL = 1
B < BRP , opposite valley
–
High
–
–
B > BOP , opposite tooth
–
High
–
–
B < BRP , opposite valley
–
Low
–
–
Magnetic Characteristics valid VCC = 3 to 24 V, TJ ≤ TJ(max), using Allegro 8X reference target, unless otherwise noted
Air Gap Setpoint Drift Over Temperature5
AGDrift
Device programmed with air gap of 2.5 mm
–
±0.2
–
mm
Programming Characteristics
Switchpoint Magnitude Selection Bits
BitBOPSEL
–
8
–
Bit
Switchpoint Polarity Bits
BitBOPPOL
–
1
–
Bit
Output Polarity Bits
BitPOL
–
1
–
Bit
Fall Time Bits
BitFALL
–
2
–
Bit
Device Lock Bits
BitLOCK
–
1
–
Bit
TA = 25°C, Minimum code (BOPPOL = 1,
BOPSEL = 255)
2.5
–
–
mm
TA = 25°C, Maximum code (BOPPOL = 0,
BOPSEL = 255)
–
–
1.5
mm
TA = 25°C, device programmed with air gap of
2.5 mm
–
0.05
–
mm
Programmable Air Gap
Range6,7
AGRange Programming Resolution
AGRange
ResAG
1Determined
by design and device characterization.
state when device configured as shown in figure 4.
3Output Rise Time is governed by external circuit tied to VOUT. Measured from 10% to 90% of steady state output.
4Measured from 90% to 10% of steady state output.
5Switchpoint varies with temperature, proportionally to the programmed air gap. This parameter is based on characterization data and is not a tested
parameter in production. The AGDrift value trends smaller as temperature increases.
6Switchpoint varies with temperature. A sufficient margin, obtained through customer testing, is recommended to ensure functionality across the
operating temperature range. Programming at larger air gaps leaves less margin for switchpoint drift.
7At the minimum code setpoint (BOPSEL = 255, BOPPOL = 1), the switchpoint can correspond to an air gap greater than 2.5 mm, and at maximum
code setpoint (BOPSEL = 255, BOPPOL = 0), the switchpoint can correspond to an air gap smaller than 1.5 mm.
2Output
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information
Characteristic
Symbol
Test Conditions*
RθJA
Package Thermal Resistance
Value Units
1-layer PCB with copper limited to solder pads
101
ºC/W
1-layer PCB with copper limited to solder pads and 3.57 in.2 (23.03 cm2)
of copper area each side
77
ºC/W
*Additional information is available on the Allegro Web site.
Power Derating Curve
30
VCC(max)
Maximum Allowable VCC (V)
25
20
1-Layer PCB
(RQJA = 77 ºC/W)
15
Pads Only PCB
(RQJA = 101 ºC/W)
10
5
VCC(min)
0
20
40
60
80
100
120
140
160
180
Temperature, TA (ºC)
Power Dissipation, PD (m W)
Power Dissipation versus Ambient Temperature
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
1
(R -lay
QJ
A
er
= PC
77 B
ºC
/W
Pa
(R dson
QJ
ly
A =
10 PC
1º B
C/
W
20
40
60
)
)
80
100
120
140
Temperature, TA (°C)
160
180
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
Characteristic Performance
Programmed Switchpoints versus Temperature
at Various Air Gaps (8X Reference Target)
4.0
Code: –32 (BRP)
Air Gap (mm)
3.5
Code: –32 (BOP)
3.0
Code: –16 (BRP)
2.5
Code: –16 (BOP)
2.0
Code: 32 (BRP)
Code: 32 (BOP)
Code: 64 (BRP)
Code: 64 (BOP)
1.5
Code: 128 (BRP)
1.0
Code: 128 (BOP)
0.5
0.0
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
Supply Current (On) versus Ambient Temperature
Supply Current, ICC (mA)
6
5
4
VCC (V)
3.3
3
5
24
2
1
0
-50
-25
0
25
50
75
100
125
150
175
Ambient Temperature, TA (°C)
Supply Current (Off) versus Ambient Temperature
Supply Current, ICC (mA)
6
5
4
VCC (V)
3.3
3
5
24
2
1
0
-50
-25
0
25
50
75
100
125
150
175
Ambient Temperature, TA (°C)
Saturation Voltage, VOUT(sat) (V)
Saturation Voltage versus Ambient Temperature
500
400
IOUT = 20 mA
300
VCC (V)
3.3
5
200
24
100
0
-50
-25
0
25
50
75
100
125
150
175
Ambient Temperature, TA (°C)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
Functional Description
V+
VOUT(off)
VOUT(off)
VOUT
Switch Off
V+
Switch On
Switch On
VOUT
In the alternative case, in which the Output Polarity bit is set
(POL = 1), the ATS128 output switches off when the magnetic
field at the Hall sensor IC exceeds the operate point threshold,
BOP . When the magnetic field is reduced to below the release
point threshold, BRP , the device output switches on.
Switch Off
When the Output Polarity bit is not set (POL = 0), the ATS128
output switches on after the magnetic field at the Hall sensor IC
exceeds the operate point threshold, BOP . When the magnetic field
is reduced to below the release point threshold, BRP , the device
output switches off. The difference between the magnetic operate
and release points is called the hysteresis of the device, BHYS.
VOUT(on)(sat)
(B) BOPPOL = 0
POL = 1
(A) BOPPOL = 0
POL = 0
VOUT(off)
VOUT
Switch Off
VOUT(off)
Switch On
Switch On
VOUT
V+
BHYS
(C) BOPPOL = 1
POL = 0
B–
BRP
0 BOPinit
VOUT(on)(sat)
BOP
BRP
BOP
VOUT(on)(sat)
B–
B+
BHYS
BHYS
V+
BOP
BOPinit 0
Switch Off
BRP
B+
BRP
BOP
BOPinit 0
VOUT(on)(sat)
0 BOPinit
BHYS
(D) BOPPOL = 1
POL = 1
Figure 2. Hysteresis Diagrams. These plots demonstrate the behavior of the ATS128 with the applied magnetic field
impinging on the branded face of the device case (refer to Package Outline Drawings section). On the horizontal axis,
the B+ direction indicates increasing south or decreasing north magnetic flux density, and the B– direction indicates
increasing north or decreasing south magnetic flux density.
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
ATS128LSE
Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
Air Gap Operating Range
The Programmable Air Gap Range, AGRange , can be programmed around the zero crossing point, within the range limits:
AGRange(min) and AGRange(max). The available programming
range for AGRange falls within the distributions of the initial,
minimum code setpoint (BOPSEL = 255, BOPPOL = 1), and the
maximum code setpoint (BOPSEL = 255, BOPPOL = 0). The
switchpoint can correspond to an air gap smaller than 1.5 mm or
larger than 2.5 mm, as shown in figure 3.
AGRange(max)
= 1.5 mm
Typical initial value
before customer
programming
Air Gap, AG
Programming range
(specified limits)
Distribution of values
resulting from maximum
programming code
AGRange(min)
= 2.5 mm
Distribution of values
resulting from minimum
programming code
Figure 3. On the horizontal axis, the operating air gap may exceed the
recommended range for switching. The maximum and minimum values
for the actual operating air gap range are described by distributions of the
maximum and minimum code setpoints.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
Application Information
V+
100 Ω
RLOAD
1.2 kΩ
1
A
VCC
ATS128
CBYPASS
0.1 μF
VOUT
A
A
GND
2
A
IC Output
3
CLOAD
120 pF
A
Tie to device pins using
traces as short as possible
Figure 4. Typical Application Circuit
Chopper Stabilization Technique
When using Hall-effect technology, a limiting factor for
switchpoint accuracy is the small signal voltage developed across
the Hall element. This voltage is disproportionally small relative
to the offset that can be produced at the output of the Hall sensor
IC. This makes it difficult to process the signal while maintaining an accurate, reliable output over the specified operating
temperature and voltage ranges. Chopper stabilization is a unique
approach used to minimize Hall offset on the chip. Allegro
employs a patented technique to remove key sources of the output drift induced by thermal and mechanical stresses. This offset
reduction technique is based on a signal modulation-demodulation process. The undesired offset signal is separated from the
magnetic field-induced signal in the frequency domain, through
modulation. The subsequent demodulation acts as a modulation
process for the offset, causing the magnetic field-induced signal
to recover its original spectrum at base band, while the DC offset
becomes a high-frequency signal. The magnetic-sourced signal
then can pass through a low-pass filter, while the modulated DC
offset is suppressed. In addition to the removal of the thermal and
stress related offset, this novel technique also reduces the amount
of thermal noise in the Hall sensor IC while completely removing
the modulated residue resulting from the chopper operation. The
chopper stabilization technique uses a high frequency sampling
clock. For demodulation process, a sample and hold technique is
used. This high-frequency operation allows a greater sampling
rate, which results in higher accuracy and faster signal-processing
capability. This approach desensitizes the chip to the effects
of thermal and mechanical stresses, and produces devices that
have extremely stable quiescent Hall output voltages and precise
recoverability after temperature cycling. This technique is made
possible through the use of a BiCMOS process, which allows the
use of low-offset, low-noise amplifiers in combination with highdensity logic integration and sample-and-hold circuits.
Regulator
Clock/Logic
Hall Element
Amp
Anit-aliasing
LP Filter
Tuned
Filter
Figure 5. Concept of Chopper Stabilization Technique
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
Reference Target Characteristics
REFERENCE TARGET 8X
Test Conditions
Typ.
Units
Do
Outside diameter of target
120
mm
Face Width
F
Breadth of tooth, with respect to
branded face
6
mm
Circular Tooth Length
t
Length of tooth, with respect to
branded face; measured at Do
23.6
mm
Circular Valley Length
tv
Length of valley, with respect to
branded face; measured at Do
23.6
mm
Tooth Whole Depth
ht
5
mm
–
–
Symbol Key
Branded Face
of Package
ØDO
ht
F
t
Outside Diameter
Symbol
tV
Characteristic
Material
CRS 1018
Air Gap
Target / Gear Parameters for Correct Operation
For correct operation, TPOS or continuous, the target must
generate a minimum difference between the applied flux density over a tooth and the applied flux density over a valley, at
the maximum installation air gap.
The following recommendations should be followed in the
design and specification of targets:
•
•
•
•
Face Width, F ≥ 5 mm
Circular Tooth Length, t ≥ 5 mm
Circular Valley Length, tv > 13 mm
Whole Tooth Depth, ht > 5 mm
Branded Face
of Package
Reference Target 8X
Target Flux Density versus Target Rotation
1400
1400
Air Gap
(mm)
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
3.25
3.50
3.75
4.00
4.25
4.50
4.75
5.00
5.25
5.50
5.75
6.00
1200
1000
800
600
400
200
0
0
*B
30
60
90
120 150 180 210 240 270 300 330 360
Rotation (º)
1200
Flux Density B (G)
Relative Magnetic Flux Density*, B (G)
Reference Gear Magnetic Gradient Amplitude versus Air Gap
Allegro Reference Target 8X
1000
800
600
Opposite tooth
400
200
Opposite valley
0
0
1
2
3
4
5
6
Air Gap (mm)
measured relative to the baseline magnetic field; field polarity referenced to the branded face.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
Programming Guidelines
Overview
Programming is accomplished by sending a series of input voltage pulses serially through the VCC (supply) pin of the device.
A unique combination of different voltage level pulses controls
the internal programming logic of the device to select a desired
programmable parameter and change its value. There are three
voltage levels that must be taken into account when programming. These levels are referred to as high (VPH), mid (VPM), and
low (VPL).
highly recommends using the Allegro Sensor IC Evaluation Kit,
available on the Allegro website On-line Store. The manual for
that kit is available for download free of charge, and provides
additional information on programming these devices. (Note: This
kit is not recommended for production purposes.)
The ATS128 features three programmable modes, Try mode,
Blow mode, and Read mode:
Bit Field The internal fuses unique to each register, represented
as a binary number. Changing the bit field settings of a particular
Definition of Terms
Register The section of the programming logic that controls the
choice of programmable modes and parameters.
• In Try mode, programmable parameter values are set and measured simultaneously. A parameter value is stored temporarily,
and reset after cycling the supply voltage.
tACTIVE
Supply Voltage, VCC
• In Blow mode, the value of a programmable parameter may
be permanently set by blowing solid-state fuses internal to the
device. Device locking is also accomplished in this mode.
• In Read mode, each bit may be verified as blown or not blown.
The programming sequence is designed to help prevent the device
from being programmed accidentally; for example, as a result of
noise on the supply line. Note that, for all programming modes, no
parameter programming registers are accessible after the devicelevel LOCK bit is set. The only function that remains accessible is
the overall Fuse Checking feature.
Although any programmable variable power supply can be used
to generate the pulse waveforms, for design evaluations, Allegro
tPr
VPH
tBLOW
tPf
VPM
VPL
(Supply
cycled)
tLOW
tLOW
GND
Programming
pulses
Blow
pulse
Figure 6. Programming pulse definitions (see table 1)
Table 1. Programming Pulse Requirements, Protocol at TA = 25°C
Characteristics
Symbol
Notes
Min.
VPL
Programming Voltage
VPM
Measured at the VCC pin
VPH
Programming Current
IPP
tLOW
Pulse Width
Pulse Rise Time
Pulse Fall Time
Blow Pulse Slew Rate
VCC = 5 → 26 V, CBLOW = 0.1 μF (min); minimum supply current required to
ensure proper fuse blowing.
Typ.
Max.
Unit
4.5
5
5.5
V
12.5
–
14
V
21
–
27
V
175
–
–
mA
Duration of VPL separating pulses at VPM or VPH
20
–
–
μs
tACTIVE
Duration of pulses at VPM or VPH for key/code selection
20
–
–
μs
tBLOW
Duration of pulse at VPH for fuse blowing
90
100
–
μs
tPr
VPL to VPM or VPL to VPH
5
–
100
μs
tPf
VPM to VPL or VPH to VPL
5
–
100
μs
0.375
–
–
V/μs
SRBLOW
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
Fuse Blowing Applying a high voltage pulse of sufficient
duration to permanently set an addressed bit by blowing a fuse
internal to the device. Once a bit (fuse) has been blown, it cannot
be reset.
Blow Pulse A high voltage pulse of sufficient duration to blow
the addressed fuse.
Cycling the Supply Powering-down, and then powering-up the
supply voltage. Cycling the supply is used to clear the programming settings in Try mode.
Programming Procedure
Programming involves selection of a register and mode, and then
setting values for parameters in the register for evaluation or fuse
blowing. Figure 10 provides an overview state diagram.
Register Selection
Each programmable parameter can be accessed through a specific
register. To select a register, from the Initial state, a sequence of
voltage pulses consisting of one VPH pulse, one VPM pulse, and
then a unique combination of VPH and VPM pulses, is applied
serially to the VCC pin (with no VCC supply interruptions). This
sequence of pulses is called the key, and uniquely identifies each
register. An example register selection key is shown in figure 7.
Mode Selection
The same physical registers are used for all programming modes.
To distinguish the Blow mode and Read mode, when selecting
the registers an additional pulse sequence consisting of eleven
VPM pulses followed by one VPH pulse is added to the key. The
combined register and mode keys are shown in table 3.
Try Mode
In Try mode, the bit field addressing is accomplished by applying a series of VPM pulses to the VCC pin of the device, as shown
in figure 7. Each pulse increases the total bit field value of the
selected parameter, increasing by one on the falling edge of each
additional VPM pulse. When addressing a bit field in Try mode,
the number of VPM pulses is represented by a decimal number
called a code. Addressing activates the corresponding fuse locations in the given bit field by increasing the binary value of an
internal DAC, up to the maximum possible code. As the value
of the bit field code increases, the value of the programmable
parameter changes. Measurements can be taken after each VPM
pulse to determine if the desired result for the programmable
parameter has been reached. Cycling the supply voltage resets
all the locations in the bit field that have un-blown fuses to their
initial states. This should also be done before selection of a different register in Try mode.
When addressing a parameter in Try mode, the bit field address
(code) defaults to the value 1, on the falling edge of the final register selection key VPH pulse (see figure 8). A complete example
is shown figure 12. Note that, in the four BOP selection virtual
registers, after the maximum code is entered, the next VPM pulse
wraps back to the beginning of the register, and selects code 0.
VPH
VPM
VPL
GND
Figure 7. Example of Try mode register selection pulses, for the BOP
Negative Trim, Up-Counting register.
VCC
VCC
VPH
VPM
Code 2n –1
Addressing Increasing the bit field code of a selected register
by serially applying a pulse train through the VCC pin of the
device. Each parameter can be measured during the addressing
process, but the internal fuses must be blown before the programming code (and parameter value) becomes permanent.
Code 2n –2
Code The number used to identify the combination of fuses
activated in a bit field, expressed as the decimal equivalent of the
binary value. The LSB of a bit field is denoted as code 1, or bit 0.
Code 3
Key A series of voltage pulses used to select a register or mode.
To simplify Try mode, the ATS128 provides a set of four virtual
registers, one for each combination of: BOP selection (BOPSEL),
BOP polarity (BOPPOL), and a facility for transiting BOP magnitude values in an increasing or decreasing sequence. These registers also allow wrapping back to the beginning of the register
after transiting the register.
Code 2
register causes its programmable parameter to change, based on
the internal programming logic.
Code 1
ATS128LSE
VPL
GND
Figure 8. Try mode bit field addressing pulses.
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Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
The four BOP selecting virtual registers allow the programmer
to adjust the BOP parameter for use with a wide magnetic field
range. In addition, values can be traversed from low to high, or
from high to low. Figure 12 shows the relationship between the
BOP parameter and the different Try mode registers. Note: See the
Output Polarity section for information about setting the POL bit
before using Try mode.
The FALL and POL fields are in the same register (FALL is
bits 1:0, and POL is bit 2). Therefore, in Try mode both can be
programmed simultaneously by adding the codes for the two
parameters, and send the sum as the code. For example, sending
code 7 (111) sets FALL to 3 (x11) and sets POL (1xx).
Blow Mode
After the required code is determined for a given parameter, its
value can be set permanently by blowing individual fuses in the
appropriate register bit field. Blowing is accomplished by selecting the register and mode selection key, followed by the appropriate bit field address, and ending the sequence with a Blow
pulse. The Blow mode selection key is a sequence of eleven VPM
pulses followed by one VPH pulse. The Blow pulse consists of a
VPH pulse of sufficient duration, tBLOW , to permanently set an
addressed bit by blowing a fuse internal to the device. The device
power must be cycled after each individual fuse is blown.
A 0.1 μF blowing capacitor, CBLOW , must be mounted between
the VCC pin and the GND pin during programming, to ensure
enough current is available to blow fuses. If programming in the
application, CBYPASS (see figure 4) can serve the same purpose.
Due to power requirements, the fuse for each bit in the bit field
must be blown individually. The ATS128 built-in circuitry allows
only one fuse at a time to be blown. During Blow mode, the bit
field can be considered a one-hot shift register. Table 2 illustrates
how to relate the number of VPM pulses to the binary and decimal
value for Blow mode bit field addressing. It should be noted that
the simple relationship between the number of VPM pulses and
the required code is:
2n = Code,
where n is the number of VPM pulses, and the bit field has an initial state of decimal code 1 (binary 00000001). To correctly blow
the required fuses, the code representing the required parameter
value must be translated to a binary number. For example, as
shown in figure 9, decimal code 5 is equivalent to the binary
number 101. Therefore bit 2 must be addressed and blown, the
device power supply cycled, and then bit 0 must be addressed
and blown. The order of blowing bits, however, is not important. Blowing bit 0 first, and then bit 2 is acceptable. A complete
example is shown in figure 13.
Note: After blowing, the programming is not reversible, even
after cycling the supply power. Although a register bit field fuse
cannot be reset after it is blown, additional bits within the same
register can be blown at any time until the device is locked. For
example, if bit 1 (binary 10) has been blown, it is still possible to
blow bit 0. The end result would be binary 11 (decimal code 3).
Locking the Device
After the required code for each parameter is programmed, the
device can be locked to prevent further programming of any
parameters. To do so, perform the following steps:
1. Ensure that the CBLOW capacitor is mounted.
2. Select the Output/Lock Bit register key.
3. Select Blow mode selection key.
4. Address bit 4 (10000) by sending four VPM pulses.
5. Send one Blow pulse, at IPP and SRBLOW, and sustain it for
tBLOW.
6. Delay for a tLOW interval, then power-down.
7. Optionally check all fuses.
Table 2. Blow Mode Bit Field Addressing
Quantity of
VPM Pulses
Binary
Register Bit Field
Decimal Equivalent
Code
0
00000001
1
1
00000010
2
2
00000100
4
3
00001000
8
4
00010000
16
5
00100000
32
6
01000000
64
7
10000000
128
Bit Field Selection
Address Code Format
(Decimal Equivalent)
Code 5
Code in Binary
(Binary)
1 0 1
Fuse Blowing
Target Bits
Bit 2
Fuse Blowing
Address Code Format
Bit 0
Code 4
Code 1
(Decimal Equivalents)
Figure 9. Example of code 5 broken into its binary components.
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Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
Table 3. Programming Logic Table
Bit Field Address (Code)
Register Name
[Selection Key]
Notes
Decimal
Binary
(MSB→LSB) Equivalent
Try Mode Register Selections1
00000000
0
11111111
255
00000000
0
11111111
255
BOP Positive, Trim Down-Counting
[ 2 × VPH → 4 × VPM → VPH ]
11111111
0
00000000
255
BOP Negative, Trim Down-Counting
[VPH → VPM → 2 × VPH
→ 4 × VPM → VPH ]
11111111
0
00000000
255
x01
1
Output Fall Time (FALL). Least significant bit.
x11
3
Output Fall Time (FALL). Most significant bit.
0xx
0
Output Polarity Bit (POL). Default, no fuse blowing required.
POL = 0, VOUT = Low opposite target tooth.
1xx
4
Output Polarity Bit (POL).
POL = 1, VOUT = High opposite target tooth. Code references a single bit only.
1000
8
Fuse Threshold Low Register. Checks un-blown fuses. Code references a
single bit only.
1001
9
Fuse Threshold High Register. Checks blown fuses.
00000000
0
BOP magnitude selection. Default, no fuse blowing required.
Minimum value, corresponding to AGRange(max).
11111111
255
0
0
South field polarity. Default, no fuse blowing required.
1
1
North field polarity.
00
0
Output Fall Time (FALL). Default, no fuse blowing required.
11
3
Output Fall Time (FALL) selection is at maximum value.
000
0
Output Polarity Bit (POL). Default, no fuse blowing required.
POL = 0, VOUT = Low opposite target tooth.
100
4
Output Polarity Bit (POL). Code refers to bit 2 only. POL = 1, VOUT = High
opposite target tooth.
10000
16
Lock bit (LOCK). Locks access to all registers with exception of Fuse
Threshold registers. Code refers to bit 5 only.
0 to 1111111
–
Read mode bit values. Sequentially selects each bit in selected Blow mode register
for reading bit status as blown or not blown. Monitor VOUT after each pulse.
BOP Positive, Trim Up-Counting
[ 2 × VPH ]
BOP Negative, Trim Up-Counting
[ VPH → VPM → 2 × VPH ]
Output / Fuse Checking
[ VPH → 3 × VPM → VPH ]
Blow or Read Mode Register
BOP Selection
(BOPSEL)
[ 2 × VPH
→ 11 × VPM → VPH ]
BOP Polarity
(BOPPOL)
[ VPH → VPM → VPH
→ 11 × VPM → VPH ]
Output / Lock Bit
[ VPH → 3 × VPM → VPH
→ 11 × VPM → VPH ]
Increase BOP (South field), wraps back to code 0.
BOP selection is at maximum value.
Increase BOP (North field), wraps back to code 0.
BOP selection is at maximum value.
Decrease BOP (South field), wraps back to code 0. Code is automatically
inverted (code 1 selects BOP selection maximum value minus 1.)
BOP selection is at minimum value.
Decrease BOP (North field), wraps back to code 0. Code is automatically
inverted (code 1 selects BOP selection maximum value minus 1.)
BOP selection is at minimum value.
Selections2
BOP magnitude selection. Maximum value, corresponding to AGRange(min).
1Code
1 is automatically selected after the falling edge of the final VPH in the register key. Each subsequent VPM in the bit field addresses the next
decimal code.
2Bit 0, or code 1, is automatically selected after the falling edge of the final V
PH in the register key. Each subsequent VPM in the bit field addresses the
next bit.
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Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
Power-up
VPM
Initial State
VPH
Register Selection
VPM
→VPH
VPM
→VPH
→11×VPM
→VPH
3 × VPM
→VPH
→11×VPM
→VPH
Output/
Lock Bit
VPH
→11×VPM
→VPH
(BOPPOL)
BOP
Polarity
→VPH
VPH
BOP
Positive
Trim Up
VPM
→2 × VPH
→4 × VPM
→ VPH
VPH
→4 × VPM
→ VPH
BOP
Negative
Trim Up
BOP
Positive
Trim Down
3 × VPM
→VPH
BOP
Negative
Trim Down
Output/
Fuse
Checking
(BOPSEL)
BOP
Selection
User power-down
required
Try Mode
VPM
Code 0
VPM
Yes
VPM
BOP Trim
register?
VPM
Code 2
Code 1
Code 2n–1
[Optional: test output or check fuse integrity]
Blow Mode
VPM
VPM
Bit 1
Bit 0
VPH
VPH
(Blow Pulse) (Blow Pulse)
Bit n-1
VPH
(Blow Pulse)
Blow Fuse
Read Mode
VPM
Bit 0
VPM
Bit 1
Bit n-1
Figure 10. Programming State Diagram
[Read fuse status on VOUT]
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Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
Fuse Checking
Incorporated in the ATS128 is circuitry to simultaneously check
the integrity of the fuse bits. The fuse checking feature is enabled
by using the Fuse Checking registers, and while in Try mode,
applying the codes shown in table 3. The register is only valid
in Try mode and is available before or after the programming
LOCK bit is set.
Additional Guidelines
The additional guidelines in this section should be followed to
ensure the proper behavior of these devices:
• The power supply used for programming must be capable of
delivering at least VPH and IPP .
Selecting the Fuse Threshold High register checks that all blown
fuses are properly blown. Selecting the Fuse Threshold Low
register checks all un-blown fuses are properly intact. The supply
current, ICC , increases by 250 μA if a marginal fuse is detected.
If all fuses are correctly blown or fully intact, there will be no
change in supply current.
• Set the LOCK bit (only after all other parameters have been
programmed and validated) to prevent any further programming
of the device.
• Be careful to observe the tLOW delay time before powering
down the device after blowing each bit.
Read Mode
The ATS128 features a Read mode that allows the status of each
programmable fuse to be read back individually. The status,
blown or not blown, of the addressed fuse is determined by monitoring the state of the VOUT pin. A complete example is shown
in figure 11.
Output Polarity
When selecting the BOP registers in Try mode, the output polarity
is determined by the value of the Output Polarity bit (POL). The
default value is POL = 0 (fuse un-blown). For applications that
require the output states defined by POL = 1 (see Operating Characteristics table), it is recommended to first permanently blow the
POL bit by selecting the Output / Lock bit register, and code 4.
The output is then defined by POL = 1 when selecting the BOP
Try mode registers. See table 3 for parameter details.
Read mode uses the same register selection keys as Blow mode
(see table 3), allowing direct addressing of the individual fuses in
the BOPPOL and BOPSEL registers (do not inadvertently send a
Blow pulse while in Read mode). After sending the register and
mode selection keys, that is, after the falling edge of the final VPH
pulse in the key, the first bit (the LSB) is selected. Each addi-
Register (and Mode) Selection Key
Bit Field (Fuse) Address Codes
VPM
1
2
3
4
5
6
8
9
10 11
1
2
3
4
5
6
7
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 3 Un-Blown
Bit 4 Un-Blown
Bit 5 Blown
Bit 6 Un-Blown
Bit 7 Blown
Don’t Care
Bit 2 Blown
VPM
Bit 1 Blown
VPH
Bit 0
VPL
GND
VOUT
7
Bit 0 Un-Blown
VCC
VPH
VPL
Fuse blown
Fuse intact
GND
Read-out on VOUT pin
Figure 11. Read mode example. Pulse sequence for accessing the BOP Selection register
(BOPSEL) and reading back the status of each of the eight bit fields. In this example, the code
(blown fuses) is 2 + 22 +25 + 27 = 166 (10100110). After each address pulse is sent, the voltage
on the VOUT pin will be at GND for un-blown fuses and at VCC (at VPL or VPM) for blown fuses.
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Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
(the status of the Output Polarity bit, POL, does not affect Read
mode output values, allowing POL to be tested also). If the output
state is low, the fuse can be considered un-blown. During Read
mode VOUT must be pulled high using a pull-up resistor (see
RLOAD in the Typical Application Circuit diagram).
tional VPM pulse addresses the next bit in the selected register, up
to the MSB. Read mode is available only before the LOCK bit
has been set.
After the final VPH key pulse, and after each VPM address pulse,
if VOUT is high, the corresponding fuse can be considered blown
Bit Field
Address Codes
Register (and Mode)
Selection Key
6
Code 7
7
8
9
10 11
VPL
GND
Code 12
5
Code 11
4
Code 10
3
Code 9
2
Code 8
1
Code 6
4
Code 5
3
Code 4
2
Code 3
1
Code 2
VPM
Code 1
VCC
VPH
Figure 12. Example of Try mode programming pulses applied to the VCC pin. In this example, BOP Positive Trim, DownCounting register is addressed to code 12 by the eleven VPM pulses (code 1 is selected automatically at the falling edge
of the register-mode selection key).
Bit Field (Fuse)
Address Codes
Register (and Mode) Selection Key
2
3
4
5
6
7
8
9
10 11
1
2
3
Code 8 Bit 3
1
Bit 2
VPM
Bit 1
Blow
Pulse
VPL
GND
tLOW
VCC
VPH
Figure 13. Example of Blow mode programming pulses applied to the VCC pin. In this example, the BOP Magnitude
Selection register (BOPSEL) is addressed to code 8 (bit 3, or 3 VPM pulses) and its value is permanently blown.
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Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
BOP Selection
The ATS128 allows accurate trimming of the magnetic operate
point, BOP , within the application. This programmable feature
reduces effects due to mechanical placement tolerances and
improves performance when used in proximity or gear tooth sensing applications.
BOP can be set to any value within the range allowed by the
BOPSEL registers. This includes switchpoints of south or north
polarity, and switchpoints at or near the zero crossing point for
B. However, switching is recommended only within the air gap
limits specified in the Operating Characteristics table.
Magnetic Field Intensity, B (G)
Trimming of BOP is typically done in two stages. In the first
stage, BOP is adjusted temporarily using the Try mode programming features, to find the fuse value that corresponds to the
optimum BOP . After a value is determined, then it can be permanently set using the Blow mode features.
B+ (south)
BOP(max)
BOP Setpoint
0
BOP(min)
B– (north)
0
As an aid to programming the ATS128 has several options available in Try Mode for adjusting the BOP parameter. As shown in
figure 14, these allow trimming of BOP for operation in north or
south polarity magnetic fields. In addition the BOP parameter can
either trim-up, start at the BOP minimum value and increase to
the maximum value, or trim-down, starting at the BOP maximum
value and decreasing to the minimum value.
The Trim Up-Counting and Trim Down-Counting features can
simplify switchpoint calibration by allowing the user to find
the codes for both the magnetic operation point, BOP , and the
magnetic release point, BRP . As an example, consider using the
ATS128 as a proximity sensor to detect rotational displacement
of a ferromagnetic target (see figure 15). When the ferromagnetic
target is centered opposite the device branded face, its location
is considered homed (0 mm displacement). If the target rotates
a certain distance, ± θ, in either direction, the sensor IC output
should change state.
Magnetic Field Intensity, B (G)
ATS128LSE
B+ (south)
BOP(max)
BOP Setpoint
0
BOP(min)
B– (north)
0
255
Try Mode, Bit Field Code
(A) BOP Positive, Trim Up-Counting Register
(B) BOP Positive, Trim Down-Counting Register
B+ (south)
Try Mode, Bit Field Code
255
BOP(min)
0
BOP Setpoint
BOP(max)
B– (north)
(C) BOP Negative, Trim Up-Counting Register
Magnetic Field Intensity, B (G)
Magnetic Field Intensity, B (G)
Try Mode, Bit Field Code
0
255
Try Mode, Bit Field Code
B+ (south)
0
255
BOP(min)
0
BOP Setpoint
BOP(max)
B– (north)
(D) BOP Negative, Trim Down-Counting Register
Figure 14. BOP profiles for each of the four BOP Selection virtual registers available in Try mode.
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Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
Figure 15 shows a plot of the example, indicating magnetic field
density versus displacement, at a fixed air gap. For the example,
the magnetic field is assumed to be positive (south). At the Home
position the device output will be in a state defined by B > BOP ,
low (assuming POL = 0) . In a position at a displacement greater
than ±θ, the output will be in the state defined by B < BRP , high.
To achieve the required result, BOP is programmed to a level such
that the sensor IC changes state from low to high at ±θ.
density, Bactual, and output is low. (See A in figure 16.)
As the code is increased, BOP is increased. When BOP is increased
to a level where BOP point is greater than Bactual, the output
changes state from low to high. The code value when the device
switched from low to high corresponds to the BRP point (record
this for later reference). (See B in figure 16.)
To find the code that corresponds to BOP , the device Positive
Trim, Down-Counting register is selected, and the output is monitored while the addressed code is increased. When the register
is entered, the default magnitude (code 1) BOP is higher than the
ambient field flux density, Bactual, (because the codes are inverted
for down-counting) and output is high. (See C in figure 17.)
First, the target is located at the corresponding switchpoint location, the –θ° or +θ° position. Next, the device Positive Trim, UpCounting register is selected and the output is monitored while
the addressed code is increased. When the register is entered, the
default magnitude (code 1) of BOP is lower than the magnetic flux
Displaced
Counterclockwise
Home
Position
Displaced
Clockwise
Magnetic Field Intensity, B (G)
B+
BOP
Target BRP
B–
–θ
0
θ
Target Displacement from Home Position, θ (°)
Figure 15. Example of magnetic flux density versus target displacement. In an
application, an increasing B value could indicate either an increasing intensity of a
south field or a decreasing intensity of a north field.
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Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
As the code is increased, BOP is decreased. When BOP is less
than Bactual the output changes state from high to low. (See D in
figure 17.) Record the BOP selection for later use. Because when
using the Down-Counting register the BOP selection is automatically inverted, therefore the recorded value is equal to the maximum value minus the addressed code.
BOP(max)
B
B(actual)
0
BOP Setpoint
BRP
A
BOP(min)
BOP Setpoint
BRP
B– (north)
0
Device Output, VOUT (V)
Magnetic Field Intensity, B (G)
B+ (south)
BOP Positive, Trim Down-Counting Register
B+ (south)
C
BOP(max)
High
Low
t
Figure 16. Positive Trim, Up-Counting to find BRP .
BOP Setpoint
BRP
D
B(actual)
BOP Setpoint
BRP
0
BOP(min)
B– (north)
0
255
Try Mode, Bit Field Code
255
Try Mode, Bit Field Code
Device Output, VOUT (V)
Magnetic Field Intensity, B (G)
BOP Positive, Trim Up-Counting Register
The air gap mechanical position is also a factor in determining
the magnetic switchpoints. As seen in figure 18, at smaller air
gaps the change in flux density versus change in displacement
is large, represented by a steeply sloped function, and there is
relatively little difference between the target displacements at BOP
and BRP . At larger air gaps, however, the change function is shal-
High
Low
t
Figure 17. Positive Trim, Down-Counting to find BOP .
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Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
lower, and therefore the difference between BOP and BRP must
be considered. If BRP is more appropriate as the actual device
switchpoint, the code determined using the Up-Counting register
in the example can be programmed and set. If BOP is more appropriate as the switchpoint, the code determined using the DownCounting register can be programmed and set.
It should be noted that in the proximity sensor example given
above, the magnetic field was defined as positive (south) and
the BOP Positive, Trim Up- and Trim Down-Counting registers
were used. If in the application the magnetic field is negative,
the BOP Negative, Trim Up- and Trim Down-Counting registers
should be used as shown in figures 14C and 14D. The procedure
for programming these registers is the same as discussed in the
proximity sensor example. Note the purpose of the example is to
show how to use some of the ATS128 BOP programming options
and is not based on any reference design.
Magnetic Field Intensity, B (G)
B+ (south)
BRP
BOP
Smaller Air Gap
(Steeper slope)
BRP
BOP
Larger Air Gap
(Shallower slope)
B– (north)
–θ
Target Displacement from Home Position, θ (°)
Figure 18. Example switchpoints versus mechanical location.
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ATS128LSE
Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
Power Derating
The device must be operated below the maximum junction
temperature of the device, TJ(max) . Under certain combinations of peak conditions, reliable operation may require derating
supplied power or improving the heat dissipation properties of
the application. This section presents a procedure for correlating
factors affecting operating TJ. (Thermal data is also available on
the Allegro MicroSystems website.)
The Package Thermal Resistance, RJA, is a figure of merit summarizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity,
K, of the printed circuit board, including adjacent devices and
traces. Radiation from the die through the device case, RJC, is
relatively small component of RJA. Ambient air temperature,
TA, and air motion are significant external factors, damped by
overmolding.
The effect of varying power levels (Power Dissipation, PD), can
be estimated. The following formulas represent the fundamental
relationships used to estimate TJ, at PD.


PD = VIN × IIN
(1)
T = PD × RJA
(2)
TJ = TA + ΔT
(3)
Example: Reliability for VCC at TA = 150°C, package SE, using a
single-layer PCB.
Observe the worst-case ratings for the device, specifically:
RJA = 101 °C/W, TJ(max) = 165°C, VCC(max) = 24 V, and
ICC(max) = 5.5 mA.
Calculate the maximum allowable power level, PD(max) . First,
invert equation 3:
Tmax = TJ(max) – TA = 165 °C – 150 °C = 15 °C
This provides the allowable increase to TJ resulting from internal
power dissipation. Then, invert equation 2:
PD(max) = Tmax ÷ RJA = 15°C ÷ 101 °C/W = 149 mW
Finally, invert equation 1 with respect to voltage:
VCC(est) = PD(max) ÷ ICC(max) = 149 mW ÷ 5.5 mA = 27 V
The result indicates that, at TA, the application and device can
dissipate adequate amounts of heat at voltages ≤VCC(est) .
Compare VCC(est) to VCC(max) . If VCC(est) ≤ VCC(max) , then
reliable operation between VCC(est) and VCC(max) requires
enhanced RJA. If VCC(est) ≥ VCC(max) , then operation
between VCC(est) and VCC(max) is reliable under these conditions.
For example, given common conditions such as: TA= 25°C,
VIN = 12 V, IIN = 4 mA, and RJA = 140 °C/W, then:
PD = VIN × IIN = 12 V × 4 mA = 48 mW

T = PD × RJA = 48 mW × 140 °C/W = 7°C
TJ = TA + T = 25°C + 7°C = 32°C
A worst-case estimate, PD(max) , represents the maximum allowable power level, without exceeding TJ(max) , at a selected RJA
and TA.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
23
Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
Package SE 4-Pin SIP
7.00±0.05
B
E
10.00±0.05
LLLLLLL
NNN
YYWW
3.3±0.1
F
Branded
Face
D
= Supplier emblem
L = Lot identifier
N = Last three numbers of device part number
and optional subtype codes
Y = Last two digits of year of manufacture
W = Week of manufacture
1.3±0.1
A
4.9±0.1
1
6.23±0.10
2
3
Standard Branding Reference View
4
0.9±0.1
+0.06
0.38 –0.04
24.65±0.10
0.60±0.10
For Reference Only, not for tooling use (reference DWG-9001)
Dimensions in millimeters
A Dambar removal protrusion (16X)
11.60±0.10
B Metallic protrusion, electrically connected to pin 4 and substrate (both sides)
1.0 REF
C Thermoplastic Molded Lead Bar for alignment during shipment
D Branding scale and appearance at supplier discretion
2.00±0.10
E Active Area Depth, 0.43 mm
F Hall element (not to scale)
1.0 REF
A
1.60±0.10
C
1.27±0.10
0.71±0.10
0.71±0.10
5.50±0.10
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
24
ATS128LSE
Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
Copyright ©2010-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
25
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