TI TMS28F210

TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
D
D
D
D
6 5
DQ12
DQ11
DQ10
DQ9
DQ8
VSS
NC
DQ7
DQ6
DQ5
DQ4
4
3
W
NC
A15
A14
2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
A13
A12
A11
A10
A9
VSS
NC
A8
A7
A6
A5
18 19 20 21 22 23 24 25 26 27 28
G
NC
A0
A1
A2
A3
A4
D
D
FN PACKAGE
( TOP VIEW )
DQ13
DQ14
DQ15
E
VPP
NC
VCC
D
D
D
Organization . . . 65 536 by 16-Bits
Pin Compatible With Existing 1-Megabit
EPROMs
All Inputs/Outputs TTL Compatible
VCC Tolerance ±10%
Maximum Access/Minimum Cycle Time
’28F210-10 100 ns
’28F210-12 120 ns
’28F210-15 150 ns
’28F210-17 170 ns
Industry-Standard Programming Algorithm
PEP4 Version Available With 168-Hour
Burn-In and Choice of Operating
Temperature Ranges
10 000 and 1 000 Program/Erase Cycles
Latchup Immunity of 250 mA on All Input
and Output Lines
Low Power Dissipation ( VCC = 5.5 V )
– Active Write . . . 55 mW
– Active Read . . . 165 mW
– Electrical Erase . . . 82.5 mW
– Standby . . . 0.55 mW
(CMOS-Input Levels)
Automotive Temperature Range
– 40°C to 125°C
DQ3
DQ2
DQ1
DQ0
D
D
description
The TMS28F210 is a 65 536 by 16-bit (1048 576-bit), programmable read-only memory that can be electrically
bulk-erased and reprogrammed. It is available in 10 000- and 1 000-program/erase-endurance-cycle versions.
The TMS28F210 flash memory is offered in a 44-lead plastic leaded chip carrier package using 1,25 mm
(50-mil) lead spacing (FN suffix), and a 40-lead thin small-outline package (DBW suffix).
The TMS28F210 is characterized for operation in temperature ranges of 0°C to 70°C, – 40°C to 85°C, and
– 40°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
DBW PACKAGE
( TOP VIEW )
A9
A10
A11
A12
A13
A14
A15
NC
W
VCC
VPP
E
D15
D14
D13
D12
D11
D10
D9
D8
1
40
2
39
3
38
4
37
5
36
6
35
7
34
8
33
9
32
10
31
11
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
PIN NOMENCLATURE
A0 – A15
E
G
VSS
NC
W
DQ0 – DQ15
VCC
VPP
Address Inputs
Chip Enable
Output Enable
Ground
No Connection
Program
Inputs (programming)/Outputs
5-V Supply
12-V Power Supply†
† Only in program mode
2
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VSS
A8
A7
A6
A5
A4
A3
A2
A1
A0
G
D0
D1
D2
D3
D4
D5
D6
D7
VSS
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
device symbol nomenclature
TMS28F210
-12
C4
FN
L
Temperature Range Designator
L =
0°C to 70°C
E = – 40°C to 85°C
Q = – 40°C to 125°C
Package Designator
DBW = Thin Small-Outline Package
FN = Plastic Leaded Chip Carrier
Package
Program/Erase Endurance
C4 = 10 000 Cycles
C3 = 1 000 Cycles
Speed Designator
-10 = 100 ns
-12 = 120 ns
-15 = 150 ns
-17 = 170 ns
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3
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
logic symbol†
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
E
G
W
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
24
25
26
27
28
29
30
31
32
35
36
37
38
39
40
41
3
22
43
21
0
FLASH
EEPROM
65 536 × 16
A
0
65 535
15
G1
[PWR DWN]
G2
1, 2 EN (READ)
1C3 (WRITE)
A, 3D
∇4
A, Z4
20
19
18
17
16
15
14
11
10
9
8
7
6
5
4
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the FN package.
4
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TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
logic symbol† (continued)
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
E
G
W
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
31
32
33
34
35
36
37
38
39
1
2
3
4
5
6
7
12
30
9
29
0
FLASH
EEPROM
65 536 × 16
A
0
65 535
15
G1
[PWR DWN]
G2
1, 2 EN (READ)
1C3 (WRITE)
A, 3D
∇4
A, Z4
28
27
26
25
24
23
22
20
19
18
17
16
15
14
13
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DBW package.
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5
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
functional block diagram
DQ0 – DQ15
16
VPP
W
Erase-Voltage Switch
Input / Output Buffers
State Control
To Array
Program/Erase
Stop Timer
Command Register
Program-Voltage
Switch
STB
Data Latch
Chip-Enable and
Output-Enable
Logic
E
G
STB
A0 – A15
A
d
d
r
e
s
s
16
L
a
t
c
h
6
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Column Decoder
Column Gating
Row Decoder
1 048 576-Bit
Array Matrix
• HOUSTON, TEXAS 77251–1443
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
operation
Modes of operation are defined in Table 1.
Table 1. Operation Modes†‡
FUNCTION
VPP§
11
E
G
A0
A9
W
DQ0 – DQ15
12
30
31
1
9
13 – 20, 22 – 29
2
3
22
24
35
43
4 – 11, 14 – 21
VPPL
VPPL
VIL
VIL
X
X
VIH
VIH
Data Out
X
Standby and Write Inhibit
VPPL
VIH
VIL
VIH
X
X
Output Disable
X
X
X
MODE
DBW
PACKAGE
FN PACKAGE
Read
Read
Read/
Write
Algorithm Selection Mode
Algorithm-Selection
VPPL
VIL
VIL
Read
VPPH
VPPH
VIL
VIL
VPPH
VPPH
VIH
VIL
VIL
VIH
X
Output Disable
Standby and Write Inhibit
Hi-Z
Hi-Z
VIL
VIH
VID
VIH
X
X
X
VIH
VIH
Data Out
X
X
X
X
Hi-Z
X
X
VIL
Data In
Write
VIH
† See the recommended operating conditions table.
‡ X can be VIL or VIH.
§ VPPL ≤ VCC + 2 V; VPPH is the programming voltage specified for the device.
Mfr. Equivalent Code 0097h
Device Equivalent Code 00E5h
Hi-Z
read/output disable
When the outputs of two or more TMS28F210s are connected in parallel on the same bus, the output of any
particular device in the circuit can be read with no interference from the competing outputs of other devices. To
read the output of the TMS28F210, a low-level signal is applied to the E and G pins. All other devices in the circuit
should have their outputs disabled by applying a high-level signal to one of these pins.
standby and write inhibit
Active ICC current can be reduced from 50 mA to 1 mA by applying a high TTL level on E or reduced to 100 µA
with a high CMOS level on E. In this mode, all outputs are in the high-impedance state. The TMS28F210 draws
active current when it is deselected during programming, erasure, or program/erase verification. It continues
to draw active current until the operation is terminated.
algorithm-selection mode
The algorithm-selection mode provides access to a binary code that identifies the correct programming and
erase algorithms. This mode is activated when A9 is forced to VID. Two identifier bytes are accessed by toggling
A0. All other addresses must be held low. A0 low selects the manufacturer-equivalent code 0097h, and A0 high
selects the device-equivalent code 00E5h, as shown in Table 2.
Table 2. Algorithm-Selection Modes¶
IDENTIFIER
Manufacturer-Equivalent Code
PINS#
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
HEX
VIL
VIH
1
0
0
1
0
1
1
1
0097
0
0
1
0
1
00E5
Device-Equivalent Code
1
1
1
¶ E = G = A1 – A8 = A10 – A15 = VIL, A9 = VID, VPP = VPPL
# D8 – D15 are not shown in the table because the upper eight data bits read 0.
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7
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
programming and erasure
In the erased state, all bits are at a logic 1. Before erasing the device, all memory bits must be programmed to
a logic 0. Afterwards, the entire chip is erased. At this point, the bits, now logic 1s, can be programmed
accordingly. Refer to the Fastwrite and Fasterase algorithms for further detail.
command register
The command register controls the program and erase functions of the TMS28F210. The algorithm-selection
mode can be activated using the command register in addition to the above method. When VPP is high, the
contents of the command register and the function being performed can be changed. The command register
is written to when E is low and W is pulsed low. The address is latched on the leading edge of the pulse, while
the data is latched on the trailing edge. Accidental programming or erasure is minimized because two
commands must be executed to invoke either operation. The command register is inhibited when VCC is below
the erase / write lockout voltage, VLKO .
power supply considerations
Each device should have a 0.1-µF ceramic capacitor connected between VCC and VSS to suppress circuit noise.
Changes in current drain on VPP requires it to have a bypass capacitor as well. Printed circuit traces for both
power supplies should be appropriate to handle the current demand.
command definitions
See Table 3 for command definitions.
Table 3. Command Definitions
COMMAND
Read
REQUIRED
BUS
CYCLES
OPERATION†
ADDRESS
DATA
OPERATION†
1
Write
X
0000h
Read
RA
RD
Read
0000
0001
0097h
00E5h
FIRST BUS CYCLE
X
SECOND BUS CYCLE
0090h
ADDRESS
DATA
Algorithm-Selection Mode
3
Write
Set-Up-Erase/Erase
2
Write
X
0020h
Write
X
20h
Erase Verify
2
Write
EA
00A0h
Read
X
EVD
Set-Up-Program/Program
2
Write
X
0040h
Write
PA
PD
Program Verify
2
Write
X
00C0h
Read
X
PVD
Write
X
00FFh
Reset
2
Write
X
00FFh
† Modes of operation are defined in Table 1.
Legend:
EA
Address of memory location to be read during erase verify
RA
Address of memory location to be read
PA
Address of memory location to be programmed. Address is latched on the falling edge of W.
RD
Data read from location RA during the read operation
EVD
Data read from location EA during erase verify
PD
Data to be programmed at location PA. Data is latched on the rising edge of W.
PVD
Data read from location PA during program verify
X
Don’t care.
read command
Memory contents can be accessed while VPP is high or low. When VPP is high, writing 0000h into the command
register invokes the read operation. When the device is powered up, the default contents of the command
register are 0000h and the read operation is enabled. The read operation remains enabled until a different valid
command is written to the command register.
8
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TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
algorithm-selection-mode command
The algorithm-selection mode is activated by writing 0090h into the command register. The manufacturer
equivalent code (0097h) is identified by the value read from address location 0000h, and the device equivalent
code (00E5h) is identified by the value read from address location 0001h.
set-up-program/program commands
The programming algorithm initiates with E = VIL, W = VIL, G = VIH, VPP = VPPH, and VCC = 5 V. To enter the
programming mode, write the set-up-program command, 0040h, into the command register. The programming
operation is invoked by the next write-enable pulse. Addresses are latched internally on the falling edge of W,
and data is latched internally on the rising edge of W. The programming operation begins on the rising edge
of W and ends on the rising edge of the next W pulse. The program operation requires 10 µs for completion
before the program-verify command, 00C0h, can be loaded.
Maximum program timing is controlled by the internal stop timer. When the stop timer terminates the program
operation, the device enters an inactive state and remains inactive until a command is received.
program-verify command
The TMS28F210 can be programmed sequentially or randomly because it is programmed one word at a time.
Each word must be verified after it is programmed. The program-verify operation prepares the device to verify
the most recently programmed word. To invoke the program-verify operation, 00C0h must be written into the
command register. The program-verify operation ends on the rising edge of W.
While verifying a word, the TMS28F210 applies an internal margin voltage to the designated word. If the true
data and programmed data match, programming continues to the next designated word location; otherwise, the
word must be reprogrammed. Figure 1 shows how commands and bus operations are combined for word
programming.
set-up-erase/erase commands
The erase algorithm initiates with E = VIL, W = VIL, G = VIH, VPP = VPPH, and VCC = 5 V. To enter the erase mode,
write the set-up-erase command, 0020h, into the command register. After the TMS28F210 is in the erase mode,
writing a second erase command, 0020h, into the command register invokes the erase operation. The erase
operation begins on the rising edge of W and ends on the rising edge of the next W. The erase operation requires
10 ms to complete before the erase-verify command, 00A0h, can be loaded.
Maximum erase timing is controlled by the internal stop timer. When the stop timer terminates the erase
operation, the device enters an inactive state and remains inactive until a command is received.
erase-verify command
All words must be verified following an erase operation. After the erase operation is complete, an erased word
can be verified by writing the erase-verify command, 00A0h, into the command register. This command causes
the device to exit the erase mode on the rising edge of W. The address of the word to be verified is latched on
the falling edge of W. The erase-verify operation remains enabled until a command is written to the command
register.
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9
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
Bus
Operation
Start
Address = 00h
Initialize
Address
VCC = 5 V ± 10%, VPP = 12 V ± 5%
Standby
Command
Comments
Wait for VPP to ramp to
VPPH (see Note A)
Setup
X=1
Initialize pulse count
Write Set-Up-Program
Command
Write
Set-Up-Pr
ogram
Data = 0040h
Write Data
Write
Write Data
Valid address / data
Increment
Address
Wait = 10 µs
X=X+1
Write Program-Verify Command
No
Write
Wait
Wait==6 6µs
µs
Read
Fail
and Verify
Word
Wait = 10 µs
Standby
ProgramVerify
Standby
Wait = 6 µs
Read
Read word to verify
programming; compare
output to expected output
X = 25?
Yes
Pass
Interactive
Mode
No
Data = 00C0h; ends
program operation
Last
Address
?
Yes
Write Read Command
Power
Down
Apply VPPL
Write
Read
Apply VPPL
Standby
Device Passed
Device Failed
NOTES: A. Refer to the recommended operating conditions for the value of VPPH
B. Refer to the recommended operating conditions for the value of VPPL
Figure 1. Programming Flowchart: Fastwrite Algorithm
10
Data = 0000h; resets
register for read operations
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Wait for VPP to ramp to
VPPL (see Note B)
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
erase-verify command (continued)
To determine whether or not all the words have been erased, the TMS28F210 applies a margin voltage to each
word. If FFFFh is read from the word, all bits in the designated word have been erased. The erase-verify
operation continues until all of the words have been verified. If FFFFh is not read from a word, an additional erase
operation needs to be executed. Figure 2 shows the combination of commands and bus operations for
electrically erasing the TMS28F210.
reset command
To reset the TMS28F210 after a set-up-erase operation or a set-up-program operation without changing the
contents in memory, write 00FFh into the command register two consecutive times. After executing the reset
command, the device defaults to the read mode.
Fastwrite algorithm
The TMS28F210 is programmed using the Texas Instruments fastwrite algorithm previously shown in Figure
1. This algorithm programs in a nominal time of two seconds.
Fasterase algorithm
The TMS28F210 is erased using the Texas Instruments fasterase algorithm shown in Figure 2. The memory
array needs to be programmed completely (using the fastwrite algorithm) before erasure begins. Erasure
typically occurs in one second.
parallel erasure
To reduce total erase time, several devices can be erased in parallel. Since each flash memory can erase at
a different rate, every device must be verified separately after each erase pulse. After a given device has been
erased successfully, the erase command should not be issued to this device again. All devices that complete
erasure should be masked until the parallel erasure process is finished shown in Figure 3.
Examples of how to mask a device during parallel erase include driving the E pin high, writing the read command
(0000h) to the device when the others receive a set-up-erase or erase command, or disconnecting it from all
electrical signals with relays or other types of switches.
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11
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
Bus
Operation
Start
Command
Entire memory must = 0000h
before erasure
Preprogram
All
Words =
0000h
?
Yes
No
Comments
Program All
Words to
0000h
Use Fastwrite
programming algorithm
Initialize addresses
Address = 00h
Standby
VCC = 5 V ± 10%, VPP = 12 V ± 5%
Wait for VPP to ramp to
VPPH (see Note A)
Setup
X=1
Write Set-Up-Erase Command
Initialize pulse count
Write
Set-UpErase
Data = 0020h
Write
Erase
Data = 0020h
Write Erase Command
Wait = 10 ms
X=X+1
Wait = 10 ms
Standby
Interactive
Mode
Write Erase-Verify Command
Write
Erase
Verify
Wait = 6 µs
No
Increment
Address
Read
and Verify
Word
Standby
Wait = 6 µs
Read
Read word to verify erasure;
compare output to FFFFh
Fail
Pass
No
Addr = Word to verify;
data = 00A0h; ends the erase
operation
X = 1000?
Yes
Last
Address?
Yes
Write Read Command
Write
Apply VPPL
Apply VPPL
Device Passed
Device Failed
Power
Down
Read
Standby
NOTES: A. Refer to the recommended operating conditions for the value of VPPH
B. Refer to the recommended operating conditions for the value of VPPL
Figure 2. Flash-Erase Flowchart: Fasterase Algorithm
12
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Data = 0000h; resets register
for read operations
Wait for VPP to ramp to
VPPL (see Note B)
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
Start
Program All Devices to 0000h
X=1
Give Erase Command To All
Devices
D=1
Yes
Mask Device #D
Is
Device #D
Erased
?
X=X+1
No
D=n
?
Give Erase
Command To
All Unmasked
Devices
No
D=D+1
Yes
No
Are
All Devices
Erased
?
No
X = 1000
?
Yes
Yes
Give Read
Command To
All Devices
Give Read
Command To
All Devices
All Devices Pass
Finished With Errors
NOTE: n = number of devices being erased
Figure 3. Parallel-Erase Flow Diagram
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13
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 7 V
Programming supply voltage range, VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 14 V
Input voltage range (see Note 2): All inputs except A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to VCC + 1 V
A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 13.5 V
Output voltage range (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to VCC + 1 V
Operating free-air temperature range during read/erase/program, TA
L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to VSS.
2. The voltage on any input can undershoot to –2 V for periods less than 20 ns.
3. The voltage on any output can overshoot to 7 V for periods less than 20 ns.
recommended operating conditions
VCC
Supply voltage
VPP
Programming supply voltage
VID
Voltage level on A9 for algorithm-selection mode
VIH
High level dc input voltage
High-level
VIL
Low level dc input voltage
Low-level
TA
14
During write/read/flash erase
During read only ( VPPL )
MAX
5
55
5.5
V
VCC + 2
12.6
V
12
13
V
11.4
11.5
TTL
CMOS
POST OFFICE BOX 1443
NOM
45
4.5
0
During write/read/flash erase ( VPPH )
Operating free-air temperature
MIN
2
TTL
VCC – 0.5
– 0.5
CMOS
GND – 0.2
VCC + 0.5
VCC + 0.5
0.8
GND + 0.2
L
0
E
– 40
85
Q
– 40
125
• HOUSTON, TEXAS 77251–1443
UNIT
V
V
V
70
°C
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
VOH
High level output voltage
High-level
VOL
Low level output voltage
Low-level
II
Input current (leakage)
IO
IID
Output current (leakage)
TEST CONDITIONS
TTL
IOH = – 2.5 mA
IOH = – 100 µA
CMOS
TTL
MIN
2.4
All except A9
A9
A9 algorithm-selection-mode current
UNIT
V
VCC – 0.4
IOL = 5.8 mA
IOL = 100 µA
CMOS
MAX
0.45
0.1
±1
V
VI = 0 V to 5.5 V
VI = 0 V to 13 V
± 200
VO = 0 V to VCC
A9 = VID max
±10
µA
± 200
µA
200
µA
±10
µA
IPP1
VPP supply current (read/standby)
VPP = VPPH,
VPP = VPPL
IPP2
VPP supply current (during program pulse)
(see Note 4)
VPP = VPPH
50
mA
IPP3
VPP supply current (during flash erase)
(see Note 4)
VPP = VPPH
50
mA
IPP4
VPP supply current (during program/erase verify)
(see Note 4)
VPP = VPPH
5
mA
ICCS
VCC supply current (standby)
1
mA
100
µA
50
mA
TTL-input level
CMOS-input level
VCC = 5.5 V,
VCC = 5.5 V,
Read mode
µA
E = VIH
E = VCC
E = VIL,
f = 6 MHz
ICC1
VCC supply current (active read)
VCC = 5.5 V,
IOUT = 0 mA,
ICC2
VCC average supply current (active write)
(see Note 4)
VCC = 5.5 V,
E = VIL,
Programming in progress
10
mA
ICC3
VCC average supply current (flash erase)
(see Note 4)
VCC = 5.5 V,
E = VIL,
Erasure in progress
15
mA
ICC4
VCC average supply current (program/erase verify)
(see Note 4)
VCC = 5.5 V,
E = VIL,
VPP = VPPH,
Program /erase verify in progress
15
mA
NOTE 4: Characterization data available
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz†
PARAMETER
Ci
TEST CONDITIONS
Input capacitance
Co
Output capacitance
† Capacitance measurements are made on sample basis only.
POST OFFICE BOX 1443
VI = 0 V,
VO = 0 V,
• HOUSTON, TEXAS 77251–1443
MIN
MAX
UNIT
f = 1 MHz
6
pF
f = 1 MHz
12
pF
15
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETERS
TEST
CONDITIONS
ALTERNATE
SYMBOL
’28F210-10
MIN
MAX
’28F210-12
MIN
MAX
’28F210-15
MIN
MAX
’28F210-17
MIN
MAX
UNIT
ta(A)
Access time
from address
tAVQV
100
120
150
170
ns
ta(E)
Access time
from E
tELQV
100
120
150
170
ns
ten(G)
Access time
from G
tGLQV
45
50
55
60
ns
tc(R)
Cycle time,
read
tAVAV
100
120
150
170
ns
td(E)
Delay time, chip
enable low to
low-Z output
tELQX
0
0
0
0
ns
tGLQX
0
0
0
0
ns
tEHQZ
0
55
0
55
0
55
0
55
ns
30
0
30
0
35
0
35
ns
CL = 100 pF,
1 Series 74
TTL load,
Input tr ≤ 20 ns,
Input tf ≤ 20 ns
td(G)
Delay time, G
low to low-Z
output
tdis(E)
Chip disable to
hi-Z output
tdis(G)
Disable time,
output enable to
hi-Z output
tGHQZ
0
th(D)
Hold time, data
valid from
address, E, or
G†
tAXQX
0
0
0
0
ns
trec(W)
Write recovery
time before
read
tWHGL
6
6
6
6
µs
† Whichever occurs first
16
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
timing requirements—write/erase/program operations
tc(W)
tc(W)PR
Cycle time, write using W
tc(W)ER
th(A)
Cycle time, erase operation
th(E)
th(WHD)
Hold time, E
tsu(A)
tsu(D)
Setup time, address
tsu(E)
tsu(EHVPP)
Setup time, E before W
tsu(VPPEL)
trec(W)
Setup time, VPP to E low
trec(R)
tw(W)
Recovery time, read before W
tw(WH)
tr(VPP)
Pulse duration, W high
tf(VPP)
’28F210 - 10
ALTERNATE
SYMBOL
MIN
tAVAV
100
tWHWH1
tWHWH2
9.5
Cycle time, programming operation
Hold time, address
tWLAX
tWHEH
tWHDX
Hold time, data valid after W high
tAVWL
tDVWH
tELWL
Setup time, data
NOM
’28F210 - 12
MAX
MIN
NOM
MAX
120
10
ns
µs
10
10
9.5
UNIT
10
ms
55
60
ns
0
0
ns
10
10
ns
0
0
ns
50
50
ns
ns
20
20
tEHVP
tVPEL
100
100
ns
1
1
µs
tWHGL
tGHWL
6
6
µs
0
0
µs
60
60
ns
20
20
ns
Rise time, VPP
tWLWH
tWHWL
tVPPR
1
1
µs
Fall time, VPP
tVPPF
1
1
µs
’28F210 - 15
’28F210 - 17
Setup time, E high to VPP ramp
Recovery time, W before read
Pulse duration, W
tc(W)
tc(W)PR
Cycle time, write using W
tc(W)ER
th(A)
Cycle time, erase operation
th(E)
th(WHD)
Hold time, E
tsu(A)
tsu(D)
Setup time, address
tsu(E)
tsu(EHVPP)
Setup time, E before W
tsu(VPPEL)
trec(W)
Setup time, VPP to E low
trec(R)
tw(W)
Recovery time, read before W
tw(WH)
tr(VPP)
Pulse duration, W high
tf(VPP)
Fall time, VPP
ALTERNATE
SYMBOL
MIN
tAVAV
150
tWHWH1
tWHWH2
9.5
Cycle time, programming operation
Hold time, address
Hold time, data valid after W high
Setup time, data
Setup time, E high to VPP ramp
Recovery time, W before read
Pulse duration, W
Rise time, VPP
POST OFFICE BOX 1443
NOM
60
tWHDX
tAVWL
tDVWH
tELWL
MIN
NOM
170
10
tWLAX
tWHEH
MAX
9.5
UNIT
ns
µs
10
10
MAX
10
ms
70
ns
0
0
ns
10
10
ns
0
0
ns
50
50
ns
20
20
ns
tEHVP
tVPEL
100
100
ns
1
1
µs
tWHGL
tGHWL
6
6
µs
0
0
µs
tWLWH
tWHWL
60
60
ns
20
20
ns
tVPPR
tVPPF
1
1
µs
1
1
µs
• HOUSTON, TEXAS 77251–1443
17
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
timing requirements—alternative E-controlled writes
’28F210 - 10
ALTERNATE
SYMBOL
MIN
’28F210 - 12
MAX
MIN
MAX
’28F210 - 15
MIN
MAX
’28F210 - 17
MIN
MAX
UNIT
tc(W)
Cycle time, write using E
tAVAV
100
120
150
170
ns
tc(E)PR
Cycle time, programming
operation
tEHEH
10
10
10
10
µs
tELAX
tEHDX
tEHWH
75
80
80
90
ns
10
10
10
10
ns
0
0
0
0
ns
tAVEL
tDVEH
0
0
0
0
ns
50
50
50
50
ns
th(EA)
th(ED)
Hold time, address
th(W)
tsu(A)
Hold time, W
tsu(D)
tsu(W)
Setup time, data
0
0
0
ns
Setup time, VPP to E low
tWLEL
tVPEL
0
tsu(VPPEL)
1
1
1
1
µs
trec(E)R
Recovery time, write using E
before read
tEHGL
6
6
6
6
µs
trec(E)W
Recovery time, read before
write using E
tGHEL
0
0
0
0
µs
tELEH
tEHEL
70
70
70
80
ns
20
20
20
20
ns
tw(E)
tw(EH)
Hold time, data
Setup time, address
Setup time, W before E
Pulse duration, write using E
Pulse duration, write, E high
PARAMETER MEASUREMENT INFORMATION
2.08 V
RL = 800 Ω
Output
Under Test
CL = 100 pF
(see Note A)
LOAD CIRCUIT
2.4 V
0.45 V
2V
0.8 V
2V
0.8 V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and fixture capacitance.
B. AC testing inputs are driven at 2.4 V for logic high
and 0.45 V for logic low. Timing measurements
are made at 2 V for logic high and
0.8 V for logic low on both inputs and outputs.
Each device should have a 0.1-µF ceramic
capacitor connected between VCC and VSS as
close as possible to the device pins.
Figure 4. Load Circuit and Voltage Waveforms
18
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
PARAMETER MEASUREMENT INFORMATION
tc(R)
Address Valid
A0 – A15
ta(A)
E
ta(E)
tdis(E)
G
trec(W)
ten(G)
W
td(E)
DQ0 – DQ15
tdis(G)
td(G)
Hi-Z
th(D)
Output Valid
Hi-Z
Figure 5. Read-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
19
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
PARAMETER MEASUREMENT INFORMATION
Program
Command
Latch
ProgramAddress
Verify
and Data Programming Command
Power Up Set-UpProgram
and
Standby Command
Program
Verification
Standby/
Power Down
A0 – A15
tc(W)
tc(W)
tc(W)
tsu(A)
tc(R)
th(A)
th(A)
tsu(A)
E
tsu(E)
tsu(E)
tdis(E)
tsu(E)
th(E)
th(E)
G
th(E)
tc(W)PR
trec(R)
tw(WH)
tdis(G)
trec(W)
W
th(D)
th(D)
tw(W)
tw(W)
tsu(D)
tsu(D)
DQ0 –
DQ15
th(D)
tsu(D)
Data In
Data In = 00C0h
Valid Data Out
tsu( VPPEL)
VPPH
VPPL
tf( VPP)
tr( VPP)
Figure 6. Write-Cycle Timing
20
td(E)
ta(E)
5V
0V
VPP
td(G)
tw(W)
Hi-Z
Data In = 0040h
VCC
th(D)
ten(G)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
PARAMETER MEASUREMENT INFORMATION
Program
Command
Latch
ProgramAddress
Verify
and Data Programming Command
Set-UpPower Up
Program
and
Standby Command
Program
Verification
Standby/
Power Down
A0 – A15
tc(W)
tc(W)
tc(W)
tsu(A)
tc(R)
th(A)
th(A)
tsu(A)
W
tsu(W)
th(W)
th(W)
th(W)
tdis(G)
tsu(W)
tsu(W)
G
tc(E)PR
trec(E)W
tdis(E)
trec(E)R
tw(EH)
E
tw(E)
tw(E)
tsu(D)
DQ0 –
DQ15
th(D)
th(D)
th(D)
th(D)
td(G)
tw(E)
tsu(D)
tsu(D)
Hi-Z
Data In
Data In = 0040h
VCC
ten(G)
Data In =00C0h
td(E)
ta(E)
Valid Data Out
5V
0V
VPPH
VPP
VPPL
tsu( VPPEL)
tf( VPP)
tr( VPP)
Figure 7. Write-Cycle (Alternative E-Controlled Writes) Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
21
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
PARAMETER MEASUREMENT INFORMATION
Set-Up
Power-Up
Erase
and
Standby Command
Erase
Command
Erasing
Erase
Verify
Command
Erase
Standby/
Verification Power-Down
A0 – A15
tc(W)
tc(W)
tc(W)
tc(R)
th(A)
tsu(A)
E
tsu(E)
tsu(E)
tsu(E)
th(E)
th(E)
G
tw(WH)
trec(R)
tc(W)ER
th(E)
tdis(E)
trec(W)
tdis(G)
W
th(D)
th(D)
th(D)
tw(W)
tw(W)
DQ0 –
DQ15
tsu(D)
tsu(D)
Hi-Z
Data In = 0020h
tw(W)
th(D)
ten(G)
td(G)
tsu(D)
Data In = 0020h
Data In = 00A0h
td(E)
ta(E)
Valid Data Out
5V
VCC
0V
tsu( VPPEL)
VPPH
VPP
VPPL
tf( VPP)
tr( VPP)
Figure 8. Flash-Erase-Cycle Timing
22
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
MECHANICAL DATA
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
D
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
E
18
D2 / E2
E1
D2 / E2
14
8
0.021 (0,53)
0.013 (0,33)
0.007 (0,18) M
0.050 (1,27)
9
13
0.008 (0,20) NOM
D/E
D2 / E2
D1 / E1
NO. OF
PINS
**
MIN
MAX
MIN
MAX
MIN
MAX
20
0.385 (9,78)
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.169 (4,29)
28
0.485 (12,32)
0.495 (12,57)
0.450 (11,43)
0.456 (11,58)
0.191 (4,85)
0.219 (5,56)
44
0.685 (17,40)
0.695 (17,65)
0.650 (16,51)
0.656 (16,66)
0.291 (7,39)
0.319 (8,10)
52
0.785 (19,94)
0.795 (20,19)
0.750 (19,05)
0.756 (19,20)
0.341 (8,66)
0.369 (9,37)
68
0.985 (25,02)
0.995 (25,27)
0.950 (24,13)
0.958 (24,33)
0.441 (11,20)
0.469 (11,91)
84
1.185 (30,10)
1.195 (30,35)
1.150 (29,21)
1.158 (29,41)
0.541 (13,74)
0.569 (14,45)
4040005 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
23
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
MECHANICAL DATA
DBW (R-PDSO-G40)
PLASTIC DUAL SMALL-OUTLINE PACKAGE
1
40
0.020 (0,50)
0.386 (9,80)
0.402 (10,20)
0.010 (0,25)
0.006 (0,15)
0.007 (0,18) M
21
20
0.484 (12,30)
0.492 (12,50)
0.024 (0,60)
0.016 (0,40)
0.047 (1,20) MAX
Seating Plane
0.004 (0,10)
0.006 (0,15)
NOM
0.005 (0,13) MIN
0.559 (14,20)
0.543 (13,80)
4073304/A 09/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
24
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
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