tw6872

DATASHEET
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Triple-Rate (SD/HD/3G) SDI Transmitter with VC-2
Encoder and Audio Decoder
TW6872
Features
The TW6872 is a triple-rate (SD/HD/3G) SDI transmitter. It
receives parallel BT.656/BT.1120/ASI video data from a
CMOS sensor/ISP chip. It also receives analog audio, or serial
digital audio. The TW6872 serializes the video and audio into
an SDI stream and transmits it to an SDI receiver via its
integrated cable driver.
• Triple-rate (SD/HD/3G) SDI transmitter for Standard
Definition (SD) and High Definition (HD), and 3G 10-bit
component video
• Encoding SDI standard of ITU-R BT.656/SMPTE 259M
Level C, ITU-R BT.1120/SMPTE ST 292, SMPTE 424M 10-bit
parallel component video inputs into 10-bit serial video
output
• BT.656/BT.1120 interface for CMOS sensor/ISP chip
In addition to the standard SDI format with uncompressed raw
video data, TW6872 can optionally compress video with a
visually lossless VC-2 compression algorithm to send the video
formats normally running at HD rate (1.5Gbps) on the cable at
SD rate (270Mbps), and therefore achieve longer cable reach.
• Asynchronous Serial Interface (ASI) for IEC 13818-1
compliant transport streams
• Integrated 75Ω cable driver with pre/de-emphasis
Together, the TW6872 and Intersil’s TW6874 SDI receiver
provide a complete end-to-end SDI link solution and can
operate with or without VC-2 compression. Integrated
audio/video test patterns and PRBS checker ease system
design and implementation.
• Integrated VC-2 encoder allows transmission of HD video
over SD transmission lengths
• Analog audio and I2S serial audio input interfaces over
ancillary field
• Digital audio with PCM encoding for embedding audio
samples into the audio ancillary field of SDI stream
The TW6872 is available in a 76 Ld QFN. It is specified for
operation over the -40°C to +85°C ambient temperature
range and operates on two power supplies: 1V and 3.3V. A
single 27MHz crystal is used for all supported audio/video
operating modes.
• Single 27MHz clock/crystal input
• Optional clock output for use as the ISP chip’s clock input to
enhance overall jitter
Applications
• PRBS7/23 and video/audio pattern generator
• I2C for external micro-controller interface
• SD/HD/3G-SDI Camera
• Low power consumption
• Small footprint LTZ-QFN76L (9mm x9mm) package
• Pb-free (RoHS compliant)
1.0V
3.3V
CLK
CMOS
SENSOR
3.3V
ISP
21
3
DATA
CLKO
SDO
VD
SDO
d
u
m
m
y
AIN0
4.7k
75
COAX
1µF
d
u
m
m
y
75
22pF
27MHz
XTO
AIN1
22pF
RSET
1.6k 
HOST
PROCESSOR
TW6874S
DI RX
XTI
2.2µF
4.7k 
0 
75 
open*
TW6872
1µF
open*
3.3V
I2S
2.2µF
0
75 
IRQ
I2C
AINN
*Final RLN values pending optimization.
Place holder for inductor recommended.
2.2µF
FIGURE 1. TW6872 TYPICAL APPLICATION
May 23, 2014
FN8616.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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TW6872
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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FN8616.0
May 23, 2014