5 4 3 2 1 REVISION HISTORY E2 E1 E3 E5 E4 R6 1.2K VCCS 1 VCC 1 2 DC590 JP2 ENABLE EN 2 3 3 R7 806 SLP_EN JP3 2 VTH2 3 VTH1 3 JP10 5V MOSI/SDA C MISO SCK/SCL CS EESDA EESCL EEVCC EEGND 7 2 5 3 4 4 6 5 9 6 VCCS 10 8 12 R18 4.99K 14 R19 4.99K 6 4 2 SPI JP1 VCC EN IBIAS MOSI VCMP 0 1 1 2 2 3 3 MASTER SLAVE JP5 R2 1K MISO GND SCK SLOW CS8 MSTR VCCS POL PHA 0.1uF IP U1 IM VCC 15 IP E7 14 13 R14 0 12 11 R9 60.1 10 9 T2 1 2 R10 294 1 DNI 2 C5 10nF C1 0.1uF R8 60.1 C49 4 3 4 10nF 3 R11 294 3 2 B 3 4 A0 VCC A1 WP A2 SCL VSS U2 SDA 24LC025-I/ST VCC 8 T5 CEEH96B SUMIDA 4 2 R12 0 1 R13 0 C isoSPI J1 RJ45 2 4 6 8 R15 DNS 1 3 5 7 R16 0 DLW43SH101XK2 7 B 6 5 VCCS VCC EXT 1 1 2 2 3 3 JP6 POL 1 1 0 JP8 PHA E8 1 0 2 3 A NOTES: UNLESS OTHERWISE SPECIFIED, E10 APPROVALS LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED APP ENG. CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. TECHNOLOGY AK isoIM isoSPI TWO WIRE SERIAL INTERFACE SIZE THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. 3 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 www.linear.com Fax: (408)434-0507 LTC Confidential-For Customer Use Only CUYLER L. TITLE: SCHEMATIC 1. ALL CAPACITORS AND RESISTORS ARE 0603. 4 IM JP7 CUSTOMER NOTICE 5 isoIP E9 T1 1 DATE D JP4 JP9 16 3 8 13 7 C2 GND GND GND AUX 1 11 APPROVED CUYLER L. 04-14-16 LTC6820 1 2 5 3 1 V+ R3 R4 2K 2K SLOW 1 VTH2 VTH1 2 R1 1K J2 MOLEX, 87831-1420 DESCRIPTION PRODUCTION VCC 1 VCC 1 E6 D EXT REV __ VICMP IBIAS GND ECO 11 12 GND 1 VCCS 1.5V - 5.5V VCC 2.7V - 5.5V N/A SCALE = NONE 2 DATE: IC NO. LTC6820 DEMO CIRCUIT 1941D REV. 1 Thursday, April 14, 2016 SHEET 1 1 OF 1 A