DC1033B - Schematic

5
4
3
2
1
REVISION HISTORY
J2
0 (OPT)
NOTE 4
V2(WALL)
2.7V - 28V E11
REV
__
1
DESCRIPTION
08-31-15
5
OUT
/SHDN
ADJ
2
R13
105k
1%
U4
D1
D1
E22
2P6V
CO
0.47uF
R2
100k
1%
NOTE 2
J1
0 (OPT)
C1
0.1uF
50V
GND
D
NOTE 5
R16
511k
1%
OPT
R1
365k
1%
R14
100k
1%
LT3010EMS8E
8
7
S1
G1
1
2
G1
2
S1
D1
1
7
D1
4
GND
CVS
0.47uF
50V
IN
1
GND
5
6
D2
GND
8
Si7923DN
8
E10
VM
E13
2P6V
E21
PFI
2
M2
18
M1
19
PB#
4
V1
2
1
LO
JP1
C2
1nF
16V
R10
100k
1%
V2MON
4
3
TIEM1
2
1
LO
R15
100k
1
1
1
R8
100
INT#
D2
ORN
D3
ORN
D1
ORN
D5
RED
C
2
RST#
2
PFO#
VM
2
1
R5
100
G1STAT
2
1
VM
VS
EN
G1STAT
V2
PFO#
PFI
RST#
M2
INT#
M1
KILL#
PB#
WDE
GND
M2CONFG
6
5
PB#
SW1
R6
100
E14
EN
17
G1STAT
6
PFO#
E2
5
RST#
E3
10
INT#
20
KILL#
3
WDE
JP2
3
3
2
2
OPEN
1
1
CONT
0.022uF
PFO#
RST#
INT#
E5
E6
KILL#
E7
WDE
INT# / KILL#
3
UNTIE
2
CAP
JP3
PB#
G1STAT
E4
1
ONT
EN
E1
11
TO MICROPROCESSOR
13
9
M1CONFG
3
D4
GRN
2
15
V2
2
E18
VS
G2
V1
U1
LTC2952
G1
1
M1
16
OFFT
E17
SUP_EN
R7
100
8
M2
G1
GND
R4
100k
1%
14
G2
CV1
OPT
50V
PFI
E15
12
R12
1k
R3
511k
ONT
R17
511k
1%
OPT
21
R9
845k
1%
7
NOTE 3
C
1%
1
R11
100
VS
HI
DATE
DILIAN R.
E12
R18
100k
U3
Si7923DN
B
APPROVED
REBUILD WITH CHANGE
9
U2
D2
3
S2
4
G2
4
G2
5
3
S2
D2
6
D2
E20
V1(BAT)
2.7V - 28V
ECO
VS
CV2
OPT
50V
GND
D
VS
COFFT
0.068uF
OFFT
B
TIE
JP5
CAP
OPEN
GND
JP4
E19
E9
GND
E8
NOTE: UNLESS OTHERWISE SPECIFIED
1. ALL RESISTORS AND CAPACITORS ARE 0603.
2. BYPASS V1 SECOND FET OPTION WITH 0 OHM RESISTOR.
3. BYPASS V2 SECOND FET OPTION WITH 0 OHM RESISTOR.
4. REMOVE R3 AND INCLUDE R17 TO MONITOR V2 AT PFI.
5. REMOVE R1 AND INCLUDE R16 FOR VM TO MONITOR VS
INSTEAD OF DC/DC OUTPUT VOLTAGE.
6. CV1, CV2 SHOULD BE SMALL IF NEEDED.
A
5
4
CUSTOMER NOTICE
APPROVALS
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
APP ENG.
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
TECHNOLOGY
KIM T.
DILIAN R.
TITLE: SCHEMATIC
PUSHBUTTON ON/OFF POWERPATH CONTROLLER
SIZE
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
3
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900 www.linear.com
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
N/A
SCALE = NONE
2
DATE:
IC NO.
REV.
LTC2952CUF
DEMO CIRCUIT 1033B
Monday, August 31, 2015
1
SHEET
1
1
OF
1
A
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