Data Sheet

HEF4050B-Q100
Hex non-inverting buffers
Rev. 2 — 15 June 2016
Product data sheet
1. General description
The HEF4050B-Q100 provides six non-inverting buffers with high current output capability
suitable for driving TTL or high capacitive loads. Voltages in excess of the buffer supply
voltage are permitted. This feature allows the buffers to be used to convert logic levels of
up to 15 V to standard TTL levels. Their guaranteed fan-out into common bipolar logic
elements is shown in Table 3.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 3) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 3)
 Specified from 40 C to +85 C
 Accepts input voltages in excess of the supply voltage
 Fully static operation
 5 V, 10 V, and 15 V parametric ratings
 Standardized symmetrical output characteristics
 ESD protection:
 MIL-STD-883, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
 Complies with JEDEC standard JESD 13-B
3. Applications
 LOCMOS (Local Oxidation CMOS) to DTL/TTL converter
 HIGH sink current for driving two TTL loads
 HIGH-to-LOW level logic conversion
HEF4050B-Q100
NXP Semiconductors
Hex non-inverting buffers
4. Ordering information
Table 1.
Ordering information
All types operate from 40 C to +85 C.
Type number
Package
Name
HEF4050BT-Q100 SO16
Description
Version
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
5. Functional diagram
$
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LQSXW
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DDH
Fig 1.
Logic symbol
966
DDH
DDH
Fig 2.
Logic diagram for one gate
Fig 3.
Input protection circuit
6. Pinning information
6.1 Pinning
+()%4
9''
QF
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QF
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966
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DDD
Fig 4.
Pin configuration
HEF4050B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
2 of 11
HEF4050B-Q100
NXP Semiconductors
Hex non-inverting buffers
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
VDD
1
supply voltage
1Y to 6Y
2, 4, 6, 10, 12, 15
output
1A to 6A
3, 5, 7, 9, 11, 14,
input
VSS
8
ground supply voltage
n.c.
13, 16
not connected
7. Functional description
Table 3.
Guaranteed fan-out
Driven element
Guaranteed fan-out
Standard TTL
2
74 LS
9
74 L
16
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
II/O
input/output current
IDD
supply current
Tstg
storage temperature
Tamb
ambient temperature
Conditions
VI < 0.5 V
VO < 0.5 V or VO > VDD + 0.5 V
Ptot
total power dissipation
Tamb 40 C to +85 C
P
power dissipation
per output
[1]
[1]
Min
Max
Unit
0.5
+18
V
10
-
0.5
+18
V
-
10
mA
-
10
mA
mA
-
50
mA
65
+150
C
40
+85
C
-
500
mW
-
100
mW
For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
HEF4050B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
3 of 11
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Hex non-inverting buffers
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
VDD
VI
Conditions
Min
Max
Unit
supply voltage
3
15
V
input voltage
0
15
V
Tamb
ambient temperature
in free air
40
+85
C
t/V
input transition rise and fall rate
VDD = 5 V
-
3.75
s/V
VDD = 10 V
-
0.5
s/V
VDD = 15 V
-
0.08
s/V
10. Static characteristics
Table 6.
Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol
VIH
VIL
VOH
VOL
IOH
IOL
Parameter
HIGH-level input voltage
LOW-level input voltage
Conditions
IO < 1 A
IO < 1 A
HIGH-level output voltage IO < 1 A
Tamb = 40 C
Tamb = 85 C
Max
Min
Max
Min
Max
5V
3.5
-
3.5
-
3.5
-
V
10 V
7.0
-
7.0
-
7.0
-
V
15 V
11.0
-
11.0
-
11.0
-
V
5V
-
1.5
-
1.5
-
1.5
V
10 V
-
3.0
-
3.0
-
3.0
V
15 V
-
4.0
-
4.0
-
4.0
V
Unit
5V
4.95
-
4.95
-
4.95
-
V
10 V
9.95
-
9.95
-
9.95
-
V
15 V
14.95
-
14.95
-
14.95
-
V
5V
-
0.05
-
0.05
-
0.05
V
10 V
-
0.05
-
0.05
-
0.05
V
15 V
-
0.05
-
0.05
-
0.05
V
HIGH-level output current VO = 2.5 V
5V
-
1.7
-
1.4
-
1.1
mA
VO = 4.6 V
5V
-
0.52
-
0.44
-
0.36 mA
VO = 9.5 V
10 V
-
1.3
-
1.1
-
0.9
mA
VO = 13.5 V
15 V
-
3.6
-
3.0
-
2.4
mA
VO = 0.4 V
4.75 V
3.5
-
2.9
-
2.3
-
mA
VO = 0.5 V
10 V
12.0
-
10.0
-
8.0
-
mA
LOW-level output voltage
LOW-level output current
IO < 1 A
VO = 1.5 V
II
input leakage current
IDD
supply current
CI
Tamb = 25 C
Min
VDD
IO = 0 A
15 V
24.0
-
20.0
-
16.0
-
mA
15 V
-
0.3
-
0.3
-
1.0
A
5V
-
4.0
-
4.0
-
30
A
10 V
-
8.0
-
8.0
-
60
A
15 V
-
16.0
-
16.0
-
120
A
-
-
-
7.5
-
-
pF
input capacitance
HEF4050B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
4 of 11
HEF4050B-Q100
NXP Semiconductors
Hex non-inverting buffers
11. Dynamic characteristics
Table 7.
Dynamic characteristics
VSS = 0 V; Tamb = 25 C; unless otherwise specified. for test circuit, see Figure 6.
Symbol
Parameter
HIGH to LOW
propagation delay
tPHL
LOW to HIGH
propagation delay
tPLH
Conditions
nA to nY;
see Figure 5
nA to nY;
see Figure 5
VDD
Extrapolation formula
Min
Typ
Max
26 ns + (0.18 ns/pF)CL
-
35
70
ns
10 V
16 ns + (0.08 ns/pF)CL
-
20
35
ns
15 V
12 ns + (0.05 ns/pF)CL
-
15
30
ns
28 ns + (0.55 ns/pF)CL
-
55
110
ns
14 ns + (0.23 ns/pF)CL
-
25
55
ns
12 ns + (0.16 ns/pF)CL
-
20
40
ns
7 ns + (0.35 ns/pF)CL
-
25
50
ns
3 ns + (0.14 ns/pF)CL
-
10
20
ns
2 ns + (0.09 ns/pF)CL
-
7
14
ns
5V
5V
[1]
[1]
10 V
15 V
HIGH to LOW
see Figure 5
output transition time
tTHL
5V
[1]
10 V
15 V
LOW to HIGH
see Figure 5
output transition time
tTLH
[1]
5V
[1]
Unit
10 ns + (1.00 ns/pF)CL
-
60
120
ns
10 V
9 ns + (0.42 ns/pF)CL
-
30
60
ns
15 V
6 ns + (0.28 ns/pF)CL
-
20
40
ns
The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
Table 8.
Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf  20 ns; Tamb = 25 C.
Symbol
PD
Parameter
dynamic power
dissipation
VDD
Typical formula for PD (W)
where:
5V
PD = 3800  fi + (fo  CL)  VDD
10 V
PD = 11600  fi + (fo  CL)  VDD2
fo = output frequency in MHz,
15 V
PD = 65900  fi + (fo  CL) 
CL = output load capacitance in pF,
2
VDD2
fi = input frequency in MHz,
VDD = supply voltage in V,
(fo  CL) = sum of the outputs.
HEF4050B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
5 of 11
HEF4050B-Q100
NXP Semiconductors
Hex non-inverting buffers
12. Waveforms
WU
9,
WI
LQSXW
90
9
W3/+
92+
W3+/
90
RXWSXW
92/
W7/+
W7+/
DDL
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5.
Input to output propagation delays
Table 9.
Measurement points
Input
Output
VM
VI
VM
0.5VDD
0 V to VDD
0.5VDD
9''
*
9,
92
'87
57
&/
DDJ
Test data is given in Table 10.
Definitions for test circuit:
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 6.
Test circuit for measuring switching times
Table 10.
Test data
Supply voltage
5 V to 15 V
HEF4050B_Q100
Product data sheet
Input
Load
VI
VM
tr, tf
CL
VDD
0.5VI
 20 ns
50 pF
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
6 of 11
HEF4050B-Q100
NXP Semiconductors
Hex non-inverting buffers
13. Package outline
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HEF4050B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
7 of 11
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NXP Semiconductors
Hex non-inverting buffers
14. Abbreviations
Table 11.
Abbreviations
Acronym
Description
DTL
Diode Transistor Logic
DUT
Device Under Test
LOCMOS
Local Oxidation CMOS
HBM
Human Body Model
ESD
ElectroStatic Discharge
MM
Machine Model
MIL
Military
TTL
Transistor-Transistor Logic
15. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
HEF4050B-Q100 v.2
20160615
Product data sheet
-
HEF4050B-Q100 v.1
Modifications:
HEF4050B_Q100 v.1
HEF4050B_Q100
Product data sheet
•
•
Table 4: condition for input clamping current changed (typo corrected).
Table 5: maximum value for input voltage changed (typo corrected).
20131111
Product data sheet
-
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 June 2016
-
© NXP Semiconductors N.V. 2016. All rights reserved.
8 of 11
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Hex non-inverting buffers
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
HEF4050B_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
9 of 11
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Hex non-inverting buffers
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
HEF4050B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
10 of 11
NXP Semiconductors
HEF4050B-Q100
Hex non-inverting buffers
18. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 8
Legal information. . . . . . . . . . . . . . . . . . . . . . . . 9
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 9
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Contact information. . . . . . . . . . . . . . . . . . . . . 10
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2016.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 June 2016
Document identifier: HEF4050B_Q100