isl71831seh

DATASHEET
Radiation Hardened 5V 32-Channel Analog Multiplexer
ISL71831SEH
Features
The ISL71831SEH is a radiation tolerant, 32-channel
multiplexer that is fabricated using Intersil’s proprietary P6-SOI
process technology to provide excellent latch-up performance.
It operates with a single supply range from 3V to 5.5V and has
a 5-bit address line plus an enable that can be driven with
adjustable logic thresholds to conveniently select one of 32
available channels. An inactive channel is separated from the
active channel by a high impedance, which inhibits any
interaction between them.
• DLA SMD# 5962-15248
The ISL71831SEH’s low rDS(ON) allows for improved signal
integrity and reduced power losses. The ISL71831SEH is also
designed for cold sparing making it excellent for redundancy in
high reliability applications. It is designed to provide a high
impedance to the analog source in a powered off condition,
making it easy to add additional backup devices without
incurring extra power dissipation. The ISL71831SEH also has
analog overvoltage protection on the input that disables the
switch during an overvoltage event to protect upstream and
downstream devices.
• Cold sparing capable . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 7V
The ISL71831SEH is available in a 48 Ld CQFP and operates
across the extended temperature range of -55°C to +125°C.
There is also a 16-channel version available offered in a 28 Ld
CDFP, please refer to the ISL71830SEH datasheet for more
information. For a list of differences please refer to Table 1 on
page 2.
Related Literature
• Fabricated using P6 SOI process technology
• Rail-to-rail operation
• No latch-up
• Low rDS(ON) . . . . . . . . . . . . . . . . . . . . . . . . . .<120Ω (maximum)
• Single supply operation. . . . . . . . . . . . . . . . . . . . . . . 3V to 5.5V
- Adjustable logic threshold control
• Analog overvoltage range . . . . . . . . . . . . . . . . . . . . -0.4V to 7V
• Switch input off leakage . . . . . . . . . . . . . . . . . . . . . . . . . 120nA
• Transition times (tAHL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70ns
• Internally grounded metal lid
• Break-before-make switching
• ESD protection ≥5kV (HBM)
• Operating temperature range. . . . . . . . . . . .-55°C to +125°C
• Radiation tolerance
- Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . . . .75krad(Si)
- SEL/SEB LETTH (V+ = 6.3V). . . . . . . . . . . . . 60MeV•cm2/mg
NOTE: All lots are assurance tested to 75krad (0.01rad(Si)/s)
wafer-by-wafer.
Applications
• Telemetry signal processing
• TR017, “Single Event Effects (SEE) Testing of the
ISL71831SEH”
• Harsh environments
• UG040, “ISL71831SEHEV1Z Evaluation Board User Guide”
• Down-hole drilling
• TR021, “Total Dose Testing of the ISL71831SEH 5V
32-Channel Analog Multiplexer”
90
ISL71831SEH
80
IN01
IN02
.
.
.
+25°C
60
OUT
ADC
rDS(ON) (Ω)
IN03
+125°C
70
50
40
30
IN32
-55°C
20
10
5
0
ADDRESS
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
COMMON-MODE VOLTAGE (V)
EN
FIGURE 1. TYPICAL APPLICATION
December 10, 2015
FN8759.1
0
1
FIGURE 2. rDS(ON) vs COMMON-MODE VOLTAGE (V+ = 5V)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL71831SEH
Ordering Information
ORDERING NUMBER
(Note 2)
PART NUMBER
(Note 1)
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
5962L1524801VXC
ISL71831SEHVF
-55 to +125
48 Ld CQFP
R48.A
ISL71831SEHF/PROTO
ISL71831SEHF/PROTO
-55 to +125
48 Ld CQFP
R48.A
5962L1524801V9A
ISL71831SEHVX
-55 to +125
DIE
ISL71831SEHX/SAMPLE
ISL71831SEHX/SAMPLE
-55 to +125
DIE
ISL71831SEHEV1Z
Evaluation Board
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the
“Ordering Information” table must be used when ordering.
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART NUMBER
NUMBER OF CHANNELS
OUTPUT LEAKAGE
PACKAGE
ISL71830SEH
16
60nA
28 Ld CDFP
ISL71831SEH
32
120nA
48 Ld CQFP
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ISL71831SEH
Pin Configuration
IN29
IN30
2
IN31
NC
3
IN32
IN16
4
NC
IN15
5
NC
IN14
6
OUT
IN13
ISL71831SEH
(48 LD CQFP)
TOP VIEW
IN25
IN8
11
38
IN24
IN7
12
37
IN23
IN6
13
36
IN22
IN5
14
35
IN21
IN4
15
34
IN20
IN3
16
33
IN19
IN2
17
32
IN18
IN1
31
18
19 20 21 22 23 24 25 26 27 28 29 30
IN17
NC
39
GND
10
EN
IN26
IN9
NC
40
NC
9
A4
IN27
IN10
A3
41
A2
8
A1
IN28
IN11
A0
1 48 47 46 45 44 43
42
V+
7
VREF
IN12
Pin Descriptions
PIN NAME
PIN NUMBER
OUT
1
Output for multiplexer
V+
19
Positive power supply
INx
DESCRIPTION
3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, Inputs for multiplexer
14, 15, 16, 17, 18, 31, 32, 33,
34, 35, 36, 37, 38, 39, 40, 41,
42, 43, 44, 45, 46
Ax
21, 22, 23, 24, 25
EN
28
Enable control for multiplexer (active low)
VREF
20
Reference voltage used to set logic thresholds
GND
29
Ground
LID
-
NC
2, 26, 27, 30, 47, 48
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3
Address lines for multiplexer
Package lid is internally connected to GND (pin 29)
Not electrically connected
FN8759.1
December 10, 2015
ISL71831SEH
Absolute Maximum Ratings
Thermal Information
(V+
Maximum Supply Voltage
to GND). . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Maximum Supply Voltage (V+ to GND) (Note 5) . . . . . . . . . . . . . . . . . . .6.3V
Analog Input Voltage Range (INX) . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 7V
Digital Input Voltage Range (EN, AX) . . . . . . . . . . . . . . . (GND - 0.4V) to VREF
VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V
ESD Tolerance
Human Body Model (Tested per MIL-STD-883 TM 3015) . . . . . . . . . 5kV
Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . 250V
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . . 250V
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
48 Ld CQFP (Notes 3, 4) . . . . . . . . . . . . . . .
59
5
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Recommended Operating Conditions
Ambient Operating Temperature Range . . . . . . . . . . . . . .-55°C to +125°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+150°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3V to 5.5V
VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3V to 5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
4. For JC, the “case temp” location is the center of the package underside.
5. Tested in a heavy ion environment at LET = 60MeV•cm2/mg at +125°C.
Electrical Specifications V+ = 5V, GND = 0V, VREF = 3.3V, VIH = 3.3V, VIL = 0V, TA= +25°C, unless otherwise noted. Boldface limits apply
across the operating temperature range, -55°C to +125°C.; over a total ionizing dose of 75krad(Si) with exposure at a low dose rate
of <10mrad(Si)/s.
PARAMETER
VIN
DESCRIPTION
TEST CONDITIONS
Analog Input Signal Range
MIN
(Note 6)
TYP
0
MAX
(Note 6)
UNIT
V+
V
rDS(ON)
Channel On-Resistance
V+ = 4.5V, VIN = 0V to V+
IOUT = 1mA
-
40
120
Ω
ΔrDS(ON)
rDS(ON) Match between Channels
V+ = 4.5V, VIN = 0V, 2.25V, 4.5V
IOUT = 1mA
-
-
5
Ω
rFLAT(ON)
On-Resistance Flatness
V+ = 4.5V, VIN = 0V to V+
-
-
40
Ω
Switch Input Off Leakage
V+
= 5.5V, VIN = 5V,
Unused inputs and VOUT = 0.5V
-30
-
30
nA
V+ = 5.5V, VIN = 0.5V,
Unused inputs and VOUT = 5V
-30
-
30
nA
Switch Input Off Overvoltage Leakage V+ = 5.5V, VIN = 7V,
Unused inputs and VOUT = 0V
TA = +25°C, -55°C
-30
-
30
nA
TA = +125°C
-30
-
120
nA
Post radiation, +25°C
-30
-
30
nA
VIN = 7V, VOUT = 0V
V+ = VEN = VREF = 0V
TA = +25°C, -55°C
-20
-
20
nA
TA = +125°C
-20
-
100
nA
Post radiation, +25°C
-20
-
20
nA
VIN = 7V, VOUT = 0V
V+ = VEN = VREF = Open,
TA = +25°C, -55°C
-20
-
20
nA
TA = +125°C
-20
-
100
nA
Post radiation, +25°C
-20
-
20
nA
2.75
-
5.5
µA
IIN(OFF)
IIN(OFF-OV)
IIN(POWER-OFF)
IIN(POWER-OFF)
IIN(ON-OV)
Switch Input Off Leakage
with Supply Voltage Grounded
Switch Input Off Leakage
with Supply Voltage Open
Switch On Input Leakage with
Overvoltage Applied to the Input
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V+
= 5.5V, VIN = 7V
VOUT = OPEN
FN8759.1
December 10, 2015
ISL71831SEH
Electrical Specifications V+ = 5V, GND = 0V, VREF = 3.3V, VIH = 3.3V, VIL = 0V, TA= +25°C, unless otherwise noted. Boldface limits apply
across the operating temperature range, -55°C to +125°C.; over a total ionizing dose of 75krad(Si) with exposure at a low dose rate
of <10mrad(Si)/s. (Continued)
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
-30
-
30
nA
0
-
200
nA
Post radiation, +25°C
-30
-
30
nA
V+
= 5.5V, VOUT = 0.5V
All Inputs = 5V,
TA = +25°C, -55°C
-30
-
30
nA
TA = +125°C
-60
-
0
nA
Post radiation, +25°C
-30
-
30
nA
V+ = 5.5V, VIN = VOUT = 5V
All unused inputs at 0.5V
TA = +25°C, -55°C
-30
-
30
nA
0
-
200
nA
Post radiation, +25°C
-30
-
30
nA
V+
= 5.5V, VIN = VOUT = 0.5V
All unused inputs at 5V
TA = +25°C, -55°C
-30
-
30
nA
TA = +125°C
-60
-
0
nA
Post radiation, +25°C
-30
-
30
nA
Logic Input Voltage High/Low
V+
= 5.5V
VREF = 3.3V
1.3
-
1.6
V
IAH, IENH
Input Current with VAH, VENH
V+ = 5.5V
VEN = VA = VREF
-0.1
-
0.1
µA
IAL, IENL
Input Current with VAL, VENL
V+ = 5.5V
VEN = VA = 0V
-0.1
-
0.1
µA
ISUPPLY
Quiescent Supply Current
V+ = VREF = VEN = 5.5V
VA = 0V, TA = +25°C, -55°C
-
-
100
nA
TA = +125°C
-
-
500
nA
Post radiation, +25°C
-
-
300
nA
V+
-
-
200
nA
PARAMETER
IOUT(OFF)
DESCRIPTION
Switch Output Off Leakage
TEST CONDITIONS
V+
= 5.5V, VOUT = 5V
All inputs = 0.5V,
TA = +25°C, -55°C
TA = +125°C
IOUT(ON)
Switch Output Leakage
with Switch Enabled
TA = +125°C
VIH/L
IREF
Reference Quiescent Supply Current
= VREF = VEN = 5.5V
VA = 0V
tAHL
Addressing Transition Time
V+ = 4.5V; Figure 3
10
-
70
ns
tBBM
Break-Before-Make Delay
V+ = 4.5V; Figure 5
5
18
40
ns
tEN(ON)
Enable Turn-On Time
V+
= 4.5V; Figure 4
-
-
40
ns
tEN(OFF)
Enable Turn-Off Time
V+ = 4.5V; Figure 4
-
-
50
ns
VCTE
Charge Injection
CL = 100pF, VIN = 0V, Figure 6
-
1.4
5.0
pC
VISO
Off Isolation
VEN = VREF, RL = open, f = 1kHz
60
-
-
dB
VCT
Crosstalk
VEN = 0V, f = 1kHz, VP-P = 1V
RL = open
73
-
-
dB
Input Capacitance
f = 1MHz
-
-
5
pF
Output Capacitance
f = 1MHz
-
-
25
pF
DYNAMIC
CIN(OFF)
COUT(OFF)
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FN8759.1
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ISL71831SEH
Electrical Specifications
V+ = 3.3V, VREF = 3.3V, VIH = 3.3V, VIL = 0V, TA= +25°C, unless otherwise noted. Boldface limits apply across
the operating temperature range, -55°C to +125°C.; over a total ionizing dose of 75krad(Si) with exposure at a low dose rate
of <10mrad(Si)/s.
PARAMETER
VIN
DESCRIPTION
CONDITIONS
Analog Input Signal Range
Channel On-Resistance
V+ = 3V, VIN = 0V to V+
IOUT = 1mA
ΔrDS(ON)
rDS(ON) Match Between Channels
rFLAT(ON)
IIN(OFF-OV)
TYP
0
rDS(ON)
IIN(OFF)
MIN
(Note 6)
MAX
(Note 6)
UNIT
V+
V
25
70
200
Ω
V+ = 3V, VIN = 0.5V, 2.5V
IOUT = 1mA
-
-
5
Ω
On-Resistance Flatness
V+ = 3V, VIN = 0V to V+
-
-
50
Ω
Switch Input Off Leakage
V+
= 3.6V, VIN = 3.1V,
Unused inputs and VOUT = 0.5V
-30
-
30
nA
V+ = 3.6V, VIN = 0.5V,
Unused inputs and VOUT = 3.1V
-30
-
30
nA
-30
-
30
nA
TA = +125°C
-30
-
100
nA
Post radiation, +25°C
-30
-
30
nA
Switch Input Off Overvoltage Leakage V+ = 3.6V, VIN = 7V,
Unused inputs and VOUT = 0V,
TA = +25°C, -55°C
IIN(ON-OV)
Switch On Input Leakage with
Overvoltage Applied to the Input
V+ = 3.6V, VIN = 7V
VOUT = OPEN
1.8
-
3.6
µA
IOUT(OFF)
Switch Output Off Leakage
V+ = 3.6V, VOUT = 3.1V,
All Inputs = 0.5V,
TA = +25°C, -55°C
-30
-
30
nA
0
-
120
nA
Post radiation, +25°C
-30
-
30
nA
V+
-30
-
30
nA
0
-
30
nA
Post radiation, +25°C
-30
-
30
nA
V+
-30
-
30
nA
TA = +125°C
= 3.6V, VOUT = 0.5V,
All inputs = 3.1V,
TA = +25°C, -55°C
TA = +125°C
IOUT(ON)
Switch Output Leakage with Switch
Enabled
= 3.6V, VIN = VOUT = 3.1V
All unused inputs at 0.5V,
TA = +25°C, -55°C
TA = +125°C
0
-
120
nA
Post radiation, +25°C
-30
-
30
nA
V+ = 3.6V, VIN = VOUT = 0.5V
All unused inputs at 3.1V,
TA = +25°C, -55°C
-30
-
30
nA
0
-
30
nA
TA = +125°C
Post radiation, +25°C
ISUPPLY
IREF
Quiescent Supply Current
Reference Quiescent Supply Current
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6
-30
-
30
nA
V+
= VREF = VEN = 3.6V
VA = 0V, TA = +25°C, -55°C
-
-
100
nA
TA = +125°C
-
-
300
nA
Post radiation, +25°C
-
-
300
nA
V+
-
-
200
nA
= VREF = VEN = 3.6V, VA = 0V
FN8759.1
December 10, 2015
ISL71831SEH
Electrical Specifications
V+ = 3.3V, VREF = 3.3V, VIH = 3.3V, VIL = 0V, TA= +25°C, unless otherwise noted. Boldface limits apply across
the operating temperature range, -55°C to +125°C.; over a total ionizing dose of 75krad(Si) with exposure at a low dose rate
of <10mrad(Si)/s. (Continued)
PARAMETER
DESCRIPTION
CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
DYNAMIC
tAHL
tBBM
tEN(ON)
tEN(OFF)
Addressing Transition Time
V+ = 3V; Figure 3
10
-
100
ns
Break-Before-Make Delay
V+
= 3V; Figure 5
5
15
50
ns
Enable Turn-On Time
V+ = 3V; Figure 4
-
-
60
ns
Enable Turn Off Time
V+
-
-
80
ns
= 3V; Figure 4
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
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ISL71831SEH
TABLE 2. TRUTH TABLE
A4
A3
A2
A1
A0
EN
“ON”-CHANNEL
X
X
X
X
X
1
None
0
0
0
0
0
0
1
0
0
0
0
1
0
2
0
0
0
1
0
0
3
0
0
0
1
1
0
4
0
0
1
0
0
0
5
0
0
1
0
1
0
6
0
0
1
1
0
0
7
0
0
1
1
1
0
8
0
1
0
0
0
0
9
0
1
0
0
1
0
10
0
1
0
1
0
0
11
0
1
0
1
1
0
12
0
1
1
0
0
0
13
0
1
1
0
1
0
14
0
1
1
1
0
0
15
0
1
1
1
1
0
16
1
0
0
0
0
0
17
1
0
0
0
1
0
18
1
0
0
1
0
0
19
1
0
0
1
1
0
20
1
0
1
0
0
0
21
1
0
1
0
1
0
22
1
0
1
1
0
0
23
1
0
1
1
1
0
24
1
1
0
0
0
0
25
1
1
0
0
1
0
26
1
1
0
1
0
0
27
1
1
0
1
1
0
28
1
1
1
0
0
0
29
1
1
1
0
1
0
30
1
1
1
1
0
0
31
1
1
1
1
1
0
32
Note: X = Don’t care, “1” = Logic High, “0” = Logic Low
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ISL71831SEH
Timing Diagrams
VREF
ISL71831SEH
VREF
A4
A3
A2
A1
A0
50Ω
0V
+
V , 0V
IN01
ADDRESS
IN02-IN31
0V, V
IN32
50%
“00000”
0V
+
tAHL
VOUT
OUT
EN
50%
+
V
0V
“11111”
50pF
10kΩ
tALH
90%
90%
OUTPUT
0V
FIGURE 4. ADDRESS TIME TO OUTPUT DIAGRAM
FIGURE 3. ADDRESS TIME TO OUTPUT TEST CIRCUIT
VREF
ISL71831SEH
A4
A3
A2
A1
A0
+
IN01
IN02-IN32
V
ENABLE
50%
50%
0V
EN
VREF
OUT
VOUT
1kΩ
50 Ω
0V
50pF
V+
t DISABLE
tENABLE
90%
OUTPUT
10%
0V
FIGURE 6. TIME TO ENABLE/DISABLE OUTPUT DIAGRAM
FIGURE 5. TIME TO ENABLE/DISABLE OUTPUT TEST CIRCUIT
VREF
ISL71831SEH
VREF
A4
A3
A2
A1
A0
50Ω
0V
IN01
V
+
ADDRESS
IN02-IN31
IN32
0V
+
0V
OUT
EN
VOUT
100Ω
50pF
V
50%
OUT
0V
FIGURE 8. BREAK-BEFORE-MAKE DIAGRAM
FIGURE 7. BREAK-BEFORE-MAKE TEST CIRCUIT
VREF
ISL71831SEH
VREF
0V
50Ω
0V
A4
A3
A2
A1
A0
IN01
IN02-IN31
IN32
EN
OUT
tBBM
0V
ADDRESS
0V
VOUT
100pF
Q = 100pF * ΔVOUT
OUT
ΔVOUT
0V
FIGURE 9. CHARGE INJECTION TEST CIRCUIT
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FIGURE 10. CHARGE INJECTION DIAGRAM
FN8759.1
December 10, 2015
ISL71831SEH
Typical Performance Curves
V+ = 5V, VREF = 3.3V, VIN = 0V, RL = Open, TA = +25°C, unless otherwise specified.
90
90
80
70
80
+125°C
+25°C
+25°C
60
rDS(ON) (Ω)
rDS(ON) (Ω)
60
50
40
-55°C
30
50
40
30
20
20
10
10
0
+125°C
70
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
4.5
-55°C
0
0.5
1.0
2.0
2.5
3.0
80
4.5
5.0
+125°C
120
+125°C
+25°C
60
100
rDS(ON) (Ω)
50
40
30
80
60
-55°C
+25°C
40
20
-55°C
20
10
0
0
1
2
3
4
0
5
0
0.5
COMMON-MODE VOLTAGE (V)
1.0
1.5
2.0
2.5
3.0
COMMON-MODE VOLTAGE (V)
FIGURE 13. rDS(ON) vs COMMON-MODE VOLTAGE (V+ = 5.5V)
FIGURE 14. rDS(ON) vs COMMON-MODE VOLTAGE (V+ = 3V)
120
120
+125°C
100
100
80
80
rDS(ON) (Ω)
rDS(ON) (Ω)
4.0
140
70
60
+25°C
-55°C
40
20
0
3.5
FIGURE 12. rDS(ON) vs COMMON-MODE VOLTAGE (V+ = 5V)
FIGURE 11. rDS(ON) vs COMMON-MODE VOLTAGE (V+ = 4.5V)
rDS(ON) (Ω)
1.5
COMMON-MODE VOLTAGE (V)
COMMON-MODE VOLTAGE (V)
+125°C
60
40
-55°C
+25°C
20
0
0.5
1.0
1.5
2.0
2.5
3.0
COMMON-MODE VOLTAGE (V)
FIGURE 15. rDS(ON) vs COMMON-MODE VOLTAGE (V+ = 3.3V)
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10
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
COMMON-MODE VOLTAGE (V)
FIGURE 16. rDS(ON) vs COMMON-MODE VOLTAGE (V+ = 3.6V)
FN8759.1
December 10, 2015
ISL71831SEH
V+ = 5V, VREF = 3.3V, VIN = 0V, RL = Open, TA = +25°C, unless otherwise specified.
80
80
70
70
+25°C
60
ADDRESS DELAY (ns)
ADDRESS DELAY (ns)
Typical Performance Curves
+125°C
50
40
30
-55°C
20
+125°C
60
50
40
30
-55°C
+25°C
20
10
10
0
3.0
3.5
4.0
4.5
5.0
0
3.0
5.5
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
FIGURE 18. ADDRESS PROPAGATION DELAY (LOW TO HIGH)
FIGURE 17. ADDRESS PROPAGATION DELAY (HIGH TO LOW)
40
35
+125°C
30
tADLH = 44.087ns
tBBM DELAY (ns)
2V/DIV
tADHL = 34.382ns
25
20
15
10
-55°C
+25°C
5
0
3.0
1V/DIV
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
200ns/DIV
FIGURE 19. ADDRESS PROPAGATION DELAY
FIGURE 20. BREAK-BEFORE-MAKE DELAY
60
50
1V/DIV
tBBM = 17.929ns
tENABLE DELAY (ns)
2V/DIV
+125°C
40
30
20
-55°C
10
0
3.0
200ns/DIV
FIGURE 21. BREAK-BEFORE-MAKE DELAY
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11
+25°C
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
FIGURE 22. ENABLE TO OUTPUT PROPAGATION DELAY
FN8759.1
December 10, 2015
ISL71831SEH
Typical Performance Curves
60
V+ = 5V, VREF = 3.3V, VIN = 0V, RL = Open, TA = +25°C, unless otherwise specified.
+125°C
tDISABLE DELAY (ns)
50
2V/DIV
40
1V/DIV
tDISABLE = 41.720ns
-55°C
30
+25°C
20
tENABLE = 22.670ns
10
0
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
5.0
5.5
200ns/DIV
FIGURE 23. DISABLE TO OUTPUT PROPAGATION DELAY
FIGURE 24. ENABLE/DISABLE PROPAGATION DELAY
90
120
80
OFF ISOLATION (dB)
OFF ISOLATION (dB)
100
80
60
40
20
70
60
50
40
30
20
10
0
100
1k
10k
100k
1M
10M
0
100
100M
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 25. OFF ISOLATION (V+ = 5V, +25°C, RL = 511Ω)
2.00
+125°C
1.80
CHARGE INJECTION (pC)
100
CROSSTALK (dB)
100M
FIGURE 26. OFF ISOLATION (V+ = 5V, +25°C, RL= OPEN)
120
80
60
40
20
0
100
10M
1.60
1.40
1.20
1.00
+25°C
0.80
0.60
-55°C
0.40
0.20
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 27. CROSSTALK (V+ = 5V, +25°C, RL = OPEN)
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12
10M
0
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
5.0
5.5
FIGURE 28. CHARGE INJECTION
FN8759.1
December 10, 2015
ISL71831SEH
Post Low Dose Rate Radiation Characteristics (V+ = 5V)
Unless otherwise
specified, V+ = 5V, VCM = 0, VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a low dose rate of <10mrad(Si)/s. This
data is intended to show typical parameter shifts due to low dose rate radiation. These are not limits nor are they guaranteed.
120
120
100
100
VIN = 0.5V
60
60
40
40
VIN = 2.25V
20
0
0
VIN = 0.5V
80
rDS(ON) (Ω)
rDS(ON) (Ω)
80
10
20
30
VIN = 2.25V
VIN = 4V
40
50
60
70
0
80
0
10
20
30
40
50
60
70
80
70
80
20
30
40
50
60
70
LOW DOSE RATE RADIATION (krad(Si))
80
LOW DOSE RATE RADIATION (krad(Si))
LOW DOSE RATE RADIATION (krad(Si))
FIGURE 29. rDS(ON) (V+ = 4.5V), BIASED
FIGURE 30. rDS(ON) (V+ = 4.5V), GROUNDED
120
120
100
100
80
80
GROUNDED
rDS(ON) (Ω)
rDS(ON) (Ω)
VIN = 4V
20
60
40
GROUNDED
60
40
BIASED
20
0
20
BIASED
0
10
20
30
40
50
60
70
0
80
0
10
FIGURE 31. rDS(ON) MINIMUM (V+ = 4.5V)
5.0
40
4.5
35
4.0
BIASED
rDS(ON) (Ω)
rDS(ON) (Ω)
40
50
60
3.5
GROUNDED
25
20
15
3.0
2.5
GROUNDED
2.0
BIASED
1.5
10
1.0
5
0.5
0
0
30
FIGURE 32. rDS(ON) MAXIMUM (V+ = 4.5V)
45
30
20
LOW DOSE RATE RADIATION (krad(Si))
LOW DOSE RATE RADIATION (krad(Si))
10
20
30
40
50
60
70
LOW DOSE RATE RADIATION (krad(Si))
FIGURE 33. rDS(ON) FLATNESS (V+ = 4.5V)
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13
80
0
0
10
FIGURE 34. rDS(ON) MATCH (V+ = 4.5V, VIN = 0.5V)
FN8759.1
December 10, 2015
ISL71831SEH
Post Low Dose Rate Radiation Characteristics (V+ = 5V)
5.0
1.0
4.5
0.8
4.0
0.6
3.5
0.4
LEAKAGE (nA)
rDS(ON) (Ω)
Unless otherwise
specified, V+ = 5V, VCM = 0, VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a low dose rate of <10mrad(Si)/s. This
data is intended to show typical parameter shifts due to low dose rate radiation. These are not limits nor are they guaranteed. (Continued)
3.0
2.5
GROUNDED
BIASED
2.0
1.5
0.0
-0.2
-0.4
1.0
-0.6
0.5
-0.8
0
0
10
20
30
40
50
60
70
-1.0
0
80
GROUNDED
0.2
BIASED
10
LOW DOSE RATE RADIATION (krad(Si))
5.5
0.8
5.0
0.6
4.5
GROUNDED
0.2
0.0
-0.2
-0.4
BIASED
3.5
GROUNDED
3.0
2.5
2.0
1.5
-0.6
1.0
-0.8
0.5
10
BIASED
4.0
LEAKAGE (nA)
LEAKAGE (nA)
1.0
-1.0
0
20
30
40
50
60
70
LOW DOSE RATE RADIATION (krad(Si))
0
80
0
FIGURE 37. IS(OFF) (V+ = 5.5V, VIN = 7V)
20
30
40
50
60
70
LOW DOSE RATE RADIATION (krad(Si))
80
1.0
0.8
0.8
GROUNDED
0.6
0.6
0.4
LEAKAGE (nA)
LEAKAGE (nA)
10
FIGURE 38. IS(ON) (V+ = 5.5V, VIN = 5V)
1.0
0.2
0.0
-0.2
BIASED
-0.4
0.2
0.0
-0.2
-0.6
-0.8
20
30
40
50
60
LOW DOSE RATE RADIATION (krad(Si))
FIGURE 39. ID(ON) (V+ = 5.5V, VIN = 5V)
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14
70
80
BIASED
-0.4
-0.8
10
GROUNDED
0.4
-0.6
-1.0
0
80
FIGURE 36. IS(OFF) (V+ = 5.5V, VIN = 5V)
FIGURE 35. rDS(ON) MATCH (V+ = 4.5V, VIN = 4V)
0.4
20
30
40
50
60
70
LOW DOSE RATE RADIATION (krad(Si))
-1.0
0
10
20
30
40
50
60
70
80
LOW DOSE RATE RADIATION (krad(Si))
FIGURE 40. ID(OFF) (V+ = 3.6V, VIN = 3.1V)
FN8759.1
December 10, 2015
ISL71831SEH
Post Low Dose Rate Radiation Characteristics (V+ = 3.3V)
120
120
100
100
80
80
60
VIN = 2.5V
40
VIN = 1.5V
rDS(ON) (Ω)
rDS(ON) (Ω)
Unless otherwise
specified, V+ = 3.3V, VCM = 0,VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a low dose rate of <10mrad(Si)/s. This
data is intended to show typical parameter shifts due to low dose rate radiation. These are not limits nor are they guaranteed.
VIN = 0.5V
60
40
20
20
0
0
10
20
30
40
50
60
70
0
80
0
10
40
50
60
70
80
120
120
100
GROUNDED
BIASED
100
80
rDS(ON) (Ω)
80
rDS(ON) (Ω)
30
FIGURE 42. rDS(ON) (V+ = 3V) - GROUNDED
FIGURE 41. rDS(ON) (V+ = 3V), BIASED
60
40
BIASED
GROUNDED
60
40
20
20
0
10
20
30
40
50
60
70
0
80
0
10
LOW DOSE RATE RADIATION (krad(Si))
30
40
50
60
70
80
70
80
FIGURE 44. rDS(ON) MAXIMUM (V+ = 3V)
45
5.0
40
4.5
35
20
LOW DOSE RATE RADIATION (krad(Si))
FIGURE 43. rDS(ON) MINIMUM (V+ = 3V)
4.0
GROUNDED
3.5
30
3.0
25
20
rDS(ON) (Ω)
rDS(ON) (Ω)
20
LOW DOSE RATE RADIATION (krad(Si))
LOW DOSE RATE RADIATION (krad(Si))
0
VIN = 0.5V
VIN = 1.5V
VIN = 2.5V
BIASED
15
2.5
1.5
10
1.0
5
0.5
0
0
0.0
10
20
30
40
50
60
LOW DOSE RATE RADIATION (krad(Si))
FIGURE 45. rDS(ON) FLATNESS (V+ = 3V)
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15
70
80
GROUNDED
2.0
BIASED
0
10
20
30
40
50
60
LOW DOSE RATE RADIATION (krad(Si))
FIGURE 46. rDS(ON) MATCH (V+ = 3V, VIN = 0.5V)
FN8759.1
December 10, 2015
ISL71831SEH
Post Low Dose Rate Radiation Characteristics (V+ = 3.3V)
5.0
1.0
4.5
0.8
4.0
0.6
3.5
0.4
LEAKAGE (nA)
rDS(ON)(Ω)
Unless otherwise
specified, V+ = 3.3V, VCM = 0,VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a low dose rate of <10mrad(Si)/s. This
data is intended to show typical parameter shifts due to low dose rate radiation. These are not limits nor are they guaranteed. (Continued)
3.0
2.5
GROUNDED
BIASED
2.0
1.5
0.2
0.0
-0.2
-0.4
1.0
-0.6
0.5
-0.8
0
0
10
20
30
40
50
60
70
LOW DOSE RATE RADIATION (krad(Si))
-1.0
80
GROUNDED
BIASED
0
FIGURE 47. rDS(ON) MATCH (V+ = 3V, VIN = 2.5V)
5.5
0.8
5.0
4.0
LEAKAGE (nA)
LEAKAGE (nA)
GROUNDED
0.4
0.2
0.0
-0.2
BIASED
3.0
2.5
2.0
1.5
1.0
-0.8
0.5
10
20
30
40
50
60
70
0
0
80
10
LOW DOSE RATE RADIATION (krad(Si))
FIGURE 49. IS(OFF) (V+ = 3.6V, VIN = 7V)
1.0
0.8
0.8
0.6
0.6
BIASED
GROUNDED
LEAKAGE (nA)
LEAKAGE (nA)
20
30
40
50
60
70
LOW DOSE RATE RADIATION (krad(Si))
0.2
0.0
-0.2
-0.4
0.0
-0.2
-0.4
-0.6
-0.8
20
30
40
50
60
LOW DOSE RATE RADIATION (krad(Si))
FIGURE 51. ID(ON) (V+ = 3.6V, VIN = 3.1V)
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16
70
80
BIASED
0.2
-0.8
10
GROUNDED
0.4
-0.6
0
80
FIGURE 50. IS(ON) (V+ = 3.6V, VIN = 7V)
1.0
-1.0
GROUNDED
BIASED
3.5
-0.6
0.4
80
4.5
0.6
-1.0
0
20
30
40
50
60
70
LOW DOSE RATE RADIATION (krad(Si))
FIGURE 48. IS(OFF) (V+ = 3.6V, VIN = 3.1V)
1.0
-0.4
10
-1.0
0
10
20
30
40
50
60
70
80
LOW DOSE RATE RADIATION (krad(Si))
FIGURE 52. ID(OFF) (V+ = 3.6V, VIN = 3.1V)
FN8759.1
December 10, 2015
ISL71831SEH
Applications Information
ISL71830SEH vs ISL71831SEH
Power-Up Considerations
There is a 16-channel version of the ISL71831SEH available in a
28 Ld CDFP. In terms of performance specs, the parts are very
similar in behavior. Apart from the apparent increase in channel
density, the ISL71831SEH does have slightly higher output
leakage compared to the ISL71830SEH due to having more
channels connected to the output. The supply current for the
ISL71831SEH is also a bit higher compared to the ISL71830SEH.
The circuit is designed to be insensitive to any given power-up
sequence between V+ and VREF, however, it is recommended
that all supplies power-up relatively close to each other.
Overvoltage Protection
The ISL71831SEH has overvoltage protection on both the input
as well as the output. On the output, the voltage is limited to a
diode past the rails. Each of the inputs has independent
overvoltage protection that works regardless of the switch being
selected. If a switch experiences an overvoltage condition, the
switch is turned off. As soon as the voltage returns within the
rails, the switch returns to normal operation.
VREF and Logic Functionality
The VREF pin sets the logic threshold for the ISL71831SEH. The
range for VREF is between 3V and 5.5V. The switching point is set
to around 50% of the voltage presented to VREF. This switching
point allows for both 5V and 3.3V logic control.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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17
FN8759.1
December 10, 2015
ISL71831SEH
Die Characteristics
Assembly Related Information
Die Dimensions
SUBSTRATE POTENTIAL
Floating
3102µm x 2800µm (122.1260mils x 110.2362mils)
Thickness: 483µm ± 25µm (19mils ± 1mil)
Additional Information
Interface Materials
WORST CASE CURRENT DENSITY
GLASSIVATION
1.6 x 105 A/cm2
Type: 12kÅ Silicon Nitride on 3kÅ Oxide
TRANSISTOR COUNT
TOP METALLIZATION
7734
Type: 300Å TiN on 2.8µm AlCu
In Bondpads, TiN has been removed.
Weight of Packaged Device
1.522 grams
BACKSIDE FINISH
Lid Characteristics
Silicon
Finish: Gold
Potential: Grounded, tied to package pin 29
PROCESS
P6SOI
Metalization Mask Layout
IN12
IN13
IN14
IN15
IN16
IN32
OUT
IN31
IN30
IN29
IN28
IN11
IN27
IN10
IN26
IN09
IN25
IN08
IN24
IN07
IN23
IN06
IN22
IN05
IN21
IN04
IN20
IN03
IN19
IN02
IN18
IN01
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V+
VREF
18
A0
A1
A2
A3
A4
EN
GND
IN17
FN8759.1
December 10, 2015
ISL71831SEH
TABLE 3. ISL71831SEH DIE LAYOUT X-Y COORDINATES
PAD
NUMBER
PAD
NAME
PACKAGING
PIN
ΔX
(µm)
ΔY
(µm)
X
(µm)
Y
(µm)
1
IN28
P42
110
110
2769.8
2467.8
2
IN29
P43
110
110
2526.8
2467.8
3
IN30
P44
110
110
2320.8
2467.8
4
IN31
P45
110
110
2114.8
2467.8
5
IN32
P46
110
110
1908.8
2467.8
9
OUT
P1
110
110
1268.8
2467.8
10
IN16
P3
110
110
1062.8
2467.8
11
IN15
P4
110
110
856.8
2467.8
12
IN14
P5
110
110
650.8
2467.8
13
IN13
P6
110
110
444.8
2467.8
14
IN12
P7
110
110
201.8
2467.8
15
IN11
P8
110
110
201.8
2261.8
16
IN10
P9
110
110
201.8
2055.8
17
IN9
P10
110
110
201.8
1849.8
18
IN8
P11
110
110
201.8
1643.8
19
IN7
P12
110
110
201.8
1437.8
20
IN6
P13
110
110
201.8
1231.8
21
IN5
P14
110
110
201.8
1025.8
22
IN4
P15
110
110
201.8
819.8
23
IN3
P16
110
110
201.8
613.8
24
IN2
P17
110
110
201.8
407.8
25
IN1
P18
110
110
201.8
201.8
26
V+
P19
110
110
427.8
201.8
27
VREF
P20
110
110
638.8
201.8
28
A0
P21
110
110
849.8
201.8
29
A1
P22
110
110
1055.8
201.8
30
A2
P23
110
110
1261.8
201.8
31
A3
P24
110
110
1467.8
201.8
32
A4
P25
110
110
1673.8
201.8
36
EN
P28
110
110
2313.8
201.8
37
GND
P29
110
110
2543.8
201.8
38
IN17
P31
110
110
2769.8
201.8
39
IN18
P32
110
110
2769.8
407.8
40
IN19
P33
110
110
2769.8
613.8
41
IN20
P34
110
110
2769.8
819.8
42
IN21
P35
110
110
2769.8
1025.8
43
IN22
P36
110
110
2769.8
1231.8
44
IN23
P37
110
110
2769.8
1437.8
45
IN24
P38
110
110
2769.8
1643.8
46
IN25
P39
110
110
2769.8
1849.8
47
IN26
P40
110
110
2769.8
2055.8
48
IN27
P41
110
110
2769.8
2261.8
NOTE: Origin of coordinates is the center of the die.
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19
FN8759.1
December 10, 2015
ISL71831SEH
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to the web to make sure that you have the latest revision.
DATE
REVISION
CHANGE
December 10, 2015
FN8759.1
On page 1
Changed in Description, 2nd paragraph “rON“to “rDS(ON)“
Changed in Description and Features supply voltage from “3.3V to 5V” to “3V to 5.5V”.
Updated Features “SEL/SEB LETTH” by changing V+ from 5V to 6.3V and value from 86.4 to 60MeV•cm2/mg.
Removed High Dose rate feature.
Updated Low Dose value from 100 to 75krad(Si) on Feature bullet and Note.
Made correction to package in last paragraph of description from “CQFP” to “CDFP”
Made correction to SMD from “5962-1548” to “5962-15248”
On page 4
-In the Abs Max Section, changed from “Maximum Supply Voltage (V+ to V-) (Note 5)……… 7V” to “Maximum
Supply Voltage (V+ to GND) (Note 5)……… 6.3V”
Updated Note 5 by changing value from 86.3 to 60MeV•cm2/mg
Electrical Spec changes
-Updated heading on “Electrical Specifications” table.
-Changed Parameter names from rON to rDS(ON).
-Changed rDS(ON) typical from 60 to 40.
-Removed MIN “15” from rDS(ON)
-Added Leakage to description of IIN(OFF-0V)
On page 5
-Changed tBBM typical from “15” to “18”
-Changed VCTE typical from “2” to “1.4”
-For VISO,
-Updated Test Conditions from “VEN = 0V” to “VEN = VREF”
-Moved typical values to MIN column.
-For VCT,
-Updated Test Conditions from “VEN = VREF” to “VEN = 0V”
-Moved typical values to MIN column.
On page 6
-Changed Parameter names from rON to rDS(ON).
-Changed rDS(ON) typical from 60 to 70.
-Added Leakage to description of IIN(OFF-0V)
On page 7
-Changed tBBM typical from “15” to “25”
On page 8
-Added Table 2
On page 9
-Updated Figure 7 by changing 1kΩ to 100Ω.
On page 11 through page 16
-Updated y-axis label on Figures 20, 22 and 23
-Updated y-axis label and title on Figures 29 through 35 and Figures 41 through 47
On page 18
-Replaced Metalization Mask Layout image.
On page 19
-Updated the Pad Name for Pad 26 from “VDD” to “V+”
September 24, 2015
FN8759.0
Initial Release
About Intersil
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address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
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Reliability reports are also available from our website at www.intersil.com/support.
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20
FN8759.1
December 10, 2015
ISL71831SEH
Package Outline Drawing
R48.A
48 CERAMIC QUAD FLATPACK PACKAGE (CQFP)
Rev 3, 10/12
1.118 (28.40)
1.080 (27.43)
0.572 (14.53)
0.555 (14.10)
#1 #48
0.287 (7.29)
0.253 (6.43)
0.040 (1.02) BSC
PIN 1
INDEX AREA
0.572 (14.53)
0.555 (14.10)
1.118 (28.40)
1.080 (27.43)
0.007 (0.18) MIN
0.015 (0.38)
0.008 (0.20)
0.015 (0.38) MIN
TOP VIEW
0.099 (2.51)
0.076 (1.93)
0.016 (0.41)
0.009 (0.23)
SIDE VIEW
NOTE:
1. All dimensions are in inches (millimeters).
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21
FN8759.1
December 10, 2015