User Guide 040 ISL71831SEHEV1Z Evaluation Board User Guide Description Key Features The ISL71831SEH is a radiation tolerant, 32-channel high ESD protected multiplexer that is fabricated using Intersil’s proprietary P6SOI (Silicon On Insulator) process technology to provide excellent reliability. It operates with a single supply voltage ranging from 3.0V to 5.5V. This evaluation board is designed to provide easy access to the capabilities of the part. • Jumper selectable input source for each input The evaluation board has a DIP switch, which provides a convenient way to address all 32 channels without the need for extra supplies. There’s also a BNC input available that will allow you to drive the address pins with a signal generator. • On-board enable switch • DIP switch to conveniently select 1 of 32 channels • BNC input for dynamic addressing • Multiple loading options with jumpers on VOUT • Convenient power connection References ISL71831SEH Datasheet Specifications This board has been configured and optimized for the following operating conditions: Ordering Information PART NUMBER • V+ = 3.0V to 5.5V ISL71831SEHEV1Z DESCRIPTION Evaluation board for the ISL71831SEH • VREF = 3.0V to 5.5V EVALUATION BOARD ISL71831SEH IN01 IN02 IN03 OUT ADC .. . IN32 SIGNAL GENERATOR INPUT 5 ADDRESS VREF EN BUS WIRE A0 A1 A2 A3 A4 FIGURE 1. ISL71831SEHEV1Z BLOCK DIAGRAM March 7, 2016 UG040.1 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2015, 2016. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. User Guide 040 ISL71831SEHEV1Z Evaluation Board FIGURE 2. TOP SIDE FIGURE 3. BOTTOM SIDE Power Supplies PCB Layout Guidelines This board has power supply inputs for V+ and VREF. There are no requirements for sequencing on these supplies, but it is recommended that the supplies come up relatively at the same time. In-line resistors are provided to V+ with decoupling capacitors close to the part for V+ and VREF. The in-line resistors are 100Ω but can be changed by the user for additional power supply filtering or to limit the rise time of the supply voltages. The ISL71831SEHEV1Z PCB layout has been optimized for ease of testing. When incorporating the ISL71831SEH into a system there are a few guidelines that can ensure optimal electrical and noise performance. The voltage ranges for V+ and VREF are +3V to +5.5V. The ISL71831SEH is a rail-to-rail mux and should be able to accommodate any input signal with a voltage level between or equal to the supply voltages. VREF is used to set the decoder logic levels. Submit Document Feedback 2 • Analog circuits can conduct noise through paths that connect it to the “outside world”. These paths include the V+, VREF, the input to any switch and the output. It is important to make sure these paths are kept away from known noise sources. • It is recommended to decouple the power supply pins (V+ and VREF) for power supply filtering. If the traces to the supply lines are long, it is recommended to use a larger 1µF capacitor at the point of entry for the supply and a smaller capacitor, like a 0.1µF, close to the part to reduce high frequency perturbations. UG040.1 March 7, 2016 SP2 SP3 OUT D OUT V1 D V2 TP17 TP9 J21 J18 VOUT R3 TP10 DNP C6 C5 100PF SP1 1UF J1 C1 J20 TP1 1UF Submit Document Feedback ISL71831SEHEV1Z Circuit Schematic V1 V2 D IN D D D D IN D J2 1 J29 2 3 1 2 3 1 2 3 1 2 3 1 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 TP2 J3 1 J30 3 D J4 1 J31 J5 1 J32 J6 1 J33 2 3 1 2 3 1 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 44 43 IN29 46 45 IN31 48 1 2 3 47 NC IN32 NC IN30 IN20 IN18 IN1 IN17 42 J37 41 1 40 J38 39 1 38 J39 37 1 36 J40 35 1 34 J41 33 1 32 J42 31 1 J43 1 30 NC GND 29 28 NC 27 26 25 V+ EN_B IN2 NC IN19 A4 IN3 19 J17 1 NC ISL71831SEHVF IN4 J16 1 OUT IN21 A3 18 IN22 IN5 A2 17 J15 1 IN23 IN6 24 16 IN24 IN7 A1 15 J14 1 U1 IN25 IN8 23 14 IN26 IN9 22 13 IN10 A0 12 J13 1 IN16 6 IN13 11 J12 IN27 VREF 10 IN28 IN11 User Guide 040 9 J11 1 J36 IN12 21 8 20 7 1 J35 1 1 J10 1 IN15 J9 1 IN14 J8 1 4 J34 5 J7 1 J44 1 V+ IN D IN R4 EN 10K TP11 R5 A4 10K R1 TP12 V+ TP3 OUT R6 A3 10 1UF C2 10K TP13 VREF IN R7 A2 10K TP14 TP4 R8 A1 10K D TP15 R9 A0 J19 49.9K R10 J27 D D D D 1 SW6 EN D 3 A4 SW5 3 3 UG040.1 March 7, 2016 D 1 8 A3 8 7 1 GND J26 6 SW4 7 3 6 A0 J28 J25 SW3 A1 J24 5 A2 5 1 4 A2 4 3 A3 J23 3 A1 3 1 A4 J22 2 SW2 2 1 D 1 EN TP16 3 TP8 VREF 10K 1 A0 C4 1UF OUT SW1 VREF TP7 D D FIGURE 4. ISL71831SEHEV1Z SCHEMATIC DRAWN BY: TIM KLEMANN DATE: 12/02/2013 DRAWING TITLE ISL71831SEH 32CH ANALOG MULT User Guide 040 Bill of Materials REFERENCE ITEM QTY DESIGNATOR VALUE TOL (%) RATING TYPE PCB FOOTPRINT MANUFACTURER MANUFACTURER PART NUMBER 1 1 C6 100pF 5 50V X7R 0805 PANASONIC 2 4 C1, C2, C4, C5 1µF 10 25V X7R 0805 AVX 3 1 R3 DNP 1 DNP 0805 GENERIC 4 1 R1 10Ω 1 1/10W 0805 VENKEL CR0805-8W-10R0FT 5 6 R4, R5, R6, R7, R8, R9 10kΩ 1 1/10W 0805 VENKEL CR0805-8W-1002FT (Pb-free) 6 1 R10 49.9Ω 1 1/10W 0805 ROHM 7 3 SP1-SP3 CONN TEKTRONIX 131-4353-00 8 18 P1-P4, P7-P18 THOLE KEYSTONE 1514-2 9 1 BNC1 CONN AMPHENOL 31-5329-51RFX 10 1 SW1-SW6 DIP GRAYHILL 78B06S 11 1 U1 28CDFP INTERSIL ISL71831SEH/PROTO 12 32 J2-J17, J29-44 THOLE BERG/FCI 68000-236HLF 13 10 J1, J18, J20-J27 BERG/FCI 69190-202HLF 14 4 Bottom four corners 3M Submit Document Feedback 4 ECU-V1H101JCG 08053C105KAT2A MCR10EZHF49R9 SJ-5003SPBL UG040.1 March 7, 2016 User Guide 040 Board Layout - 4 Layers FIGURE 5. SILKSCREEN TOP FIGURE 6. TOP LAYER Submit Document Feedback 5 UG040.1 March 7, 2016 User Guide 040 Board Layout - 4 Layers (Continued) FIGURE 7. PCB – INNER LAYER 1 (TOP VIEW) FIGURE 8. PCB – INNER LAYER 2 (TOP VIEW) Submit Document Feedback 6 UG040.1 March 7, 2016 User Guide 040 Board Layout - 4 Layers (Continued) FIGURE 9. PCB – BOTTOM LAYER (TOP VIEW) FIGURE 10. SILKSCREEN BOTTOM Submit Document Feedback 7 UG040.1 March 7, 2016 User Guide 040 Typical Performance Curves Unless otherwise noted: V+ = +15V, V- = -15V, VREF = 5.0V, TA = +25°C 90 120 +125°C +125°C 80 100 60 +25°C rDS(ON) (Ω) rDS(ON) (Ω) 70 50 40 -55°C 30 +25°C 60 -55°C 40 20 20 10 0 80 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 COMMON MODE VOLTAGE (V) 4.5 0 5.0 FIGURE 11. rDS(ON) vs COMMON MODE VOLTAGE (VS = 5V) 0 0.5 1.0 1.5 2.0 2.5 COMMON MODE VOLTAGE (V) 3.0 FIGURE 12. rDS(ON) vs COMMON MODE VOLTAGE (VS = +3.3V) 2V/DIV 2V/DIV tADLH = 44.087ns 1V/DIV tADHL = 34.382ns tBBM = 17.929ns 1V/DIV 200ns/DIV 200ns/DIV FIGURE 13. ADDRESS PROPAGATION DELAY FIGURE 14. BREAK-BEFORE-MAKE DELAY 2.0 +125°C 2V/DIV 1V/DIV tDISABLE = 41.720ns tENABLE = 22.670ns CHARGE INJECTION (pC) 1.8 1.6 1.4 +25°C 1.2 1.0 0.8 0.6 0.4 -55°C 0.2 0 3.0 200ns/DIV FIGURE 15. ENABLE/DISABLE PROPAGATION DELAY 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) FIGURE 16. CHARGE INJECTION Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the document is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 8 UG040.1 March 7, 2016