INTERSIL ISL57403IN

ISL5740
TM
Data Sheet
P RE L I M I NA R Y
June 2000
File Number
4821.2
3V Dual 10-Bit, 20/40/60MSPS A/D
Converter with Internal Voltage Reference
Features
The ISL5740 is a monolithic, dual 10-bit analog-to-digital
converter fabricated in an advanced CMOS process. It is
designed for high speed applications where integration,
bandwidth and accuracy are essential. The ISL5740
features a 9-stage pipeline architecture. The fully pipelined
architecture and an innovative input stage enable the
ISL5740 to accept a variety of input configurations, singleended or fully differential. Only one external clock is
necessary to drive both converters and an internal band-gap
voltage reference is provided. This allows the system
designer to realize an increased level of system integration
resulting in decreased cost and power dissipation.
• 9.1 Bits at fIN = 10MHz
The ISL5740 has excellent dynamic performance while
consuming less than 280mW power at 60MSPS. The A/D
only requires a single +3.0V power supply. Data output
latches are provided which present valid data to the output
bus with a latency of 5 clock cycles.
• TTL/CMOS(3V) Digital Inputs CMOS Digital Outputs
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . .20/40/60MSPS
• Low Power at 60MSPS. . . . . . . . . . . . . . . . . . . . . .280mW
• Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 6mW
• Wide Full Power Input Bandwidth. . . . . . . . . . . . . 400MHz
• SFDR at fIN = 10MHz . . . . . . . . . . . . . . . . . . . . . . . . .70dB
• Excellent Channel-to-Channel Isolation . . . . . . . . . . .75dB
• On-Chip Sample and Hold Amplifiers
• Internal Bandgap Voltage Reference . . . . . . . . . . . . 1.25V
• Single Supply Voltage Operation . . . . . . . . . .+2.7V - 3.6V
• Offset Binary or Two’s Complement Digital Data Output
Format
• Dual 10-Bit A/D Converters on a Monolithic Chip
• Pin Compatible Upgrade to AD9288
The ISL5740 is offered in 20MSPS, 40MSPS and 60MSPS
sampling rates.
Pinout
• Wireless Local Loop
Ordering Information
• PSK and QAM I&Q Demodulators
• Medical Imaging and Instrumentation
• Battery Powered Instruments
30
ISL5740/4IN
-40 to 85 48 Ld LQFP
Q48.7x7
40
ISL5740/6IN
-40 to 85 48 Ld LQFP
Q48.7x7
60
Evaluation Platform
GND
1
48 47 46 45 44 43 42 41 40 39 38 37
36
IIN+
2
3
35
34
ID0
4
33
IVRIN
5
VROUT
QVRIN
6
7
32
31
DVCC
GND
AVCC
S1
8
9
3-1
AVCC
27
GND
26
11
25
12
13 14 15 16 17 18 19 20 21 22 23 24
QD0
QD1
QD2
QD3
10
QD5
QD4
GND
GND
GND
DVCC
QD7
QD6
QIN+
ID1
28
QD8
S2
QIN-
30
29
QD9
IINDFS
DVCC
GND
25
AVCC
ISL5740 EVAL
Pinout
ID2
Q48.7x7
ID5
-40 to 85 48 Ld LQFP
ID4
ID3
ISL5740/3IN
• Wireless Communications Systems
ID7
ID6
20
ID8
Q48.7x7
DVCC
-40 to 85 48 Ld LQFP
GND
ID9
ISL5740/2IN
AVCC
I CLK
PACKAGE
SAMPLIN
G RATE
PKG. NO. (MSPS)
Q CLK
PART
NUMBER
TEMP.
RANGE
(oC)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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ISL5740
Functional Block Diagram
I/QINI/QCLK
CLOCK
I/QIN+
S/H
STAGE 1
2-BIT
FLASH
2-BIT
DAC
+
∑ -
X2
I/QD9 (MSB)
I/QD8
I/QD7
I/QD6
DIGITAL DELAY
AND
DIGITAL ERROR
CORRECTION
STAGE 8
I/QD5
I/QD4
I/QD3
2-BIT
FLASH
2-BIT
DAC
I/QD2
I/QD1
+
I/QD0 (LSB)
∑ -
X2
STAGE 9
2-BIT
FLASH
I OR Q CHANNEL
VROUT
MODE
DATA FORMAT
REFERENCE
I/QVRIN
AVCC
3-2
AGND
DVCC
DGND
S1/S2
DFS
ISL5740
Typical Application Schematic
ISL5740
IIN +
(2) IIN +
IIN -
(3) IIN -
QIN +
(11) QIN +
QIN -
(10) QIN -
(5) IVRIN
0.1µF
(LSB) ID0 (35)
ID0
ID1 (36)
ID1
ID2 (37)
ID3 (38)
ID2
ID3
ID4 (39)
ID4
ID5 (40)
ID5
ID6 (41)
ID6
ID7 (42)
ID7
ID8 (43)
ID8
(MSB) ID9 (44)
ID9
(LSB) QD0 (26)
QD0
QD1 (25)
QD1
QD2 (24)
QD3 (23)
QD2
QD3
QD4 (22)
QD4
QD5 (21)
QD5
QD6 (20)
QD6
QD7 (19)
QD7
QD8 (18)
QD8
(MSB) QD9 (17)
QD9
(6) QVRIN
(7) VROUT
CLOCK
ICLK (47)
QCLK (14)
S1 (8)
S1
S2 (9)
S2
DFS (4)
+3V
(13,30,31,48) AVCC DV
CC (15, 28, 33, 46)
+
10µF
DFS
0.1µF
(12,29,32) AGND
BNC AGND DGND
3-3
3V
+
0.1µF
DGND (16, 27, 34, 45)
10µF AND 0.1µF CAPS
ARE PLACED AS CLOSE
TO PART AS POSSIBLE
10µF
ISL5740
Pin Descriptions
Pin Descriptions
(Continued)
PIN NO.
NAME
Analog Ground
24
QD2
Q-Channel, Data Bit 2 Output
IIN+
I-Channel Positive Analog Input
25
QD1
Q-Channel, Data Bit 1 Output
3
IIN-
I-Channel Negative Analog Input
26
QD0
Q-Channel, Data Bit 0 Output (LSB)
4
DFS
Data Format Select (Low for Offset
Binary and High for Twos Complement
Output Format)
27
DGND
Digital Ground
28
DVCC
Digital Supply
29
AGND
Analog Ground
30
AVCC
Analog Supply
31
AVCC
Analog Supply
Q-Channel Voltage Reference Input
32
AGND
Analog Ground
PIN NO.
NAME
1
AGND
2
DESCRIPTION
5
IVRIN
I-Channel Voltage Reference Input
6
VROUT
+1.25V Reference Voltage Output
(Decouple with 0.1µF Capacitor)
DESCRIPTION
7
QVRIN
8
S1
Mode Select Pin 1 (See Table)
33
DVCC
Digital Supply
9
S2
Mode Select Pin 2 (See Table)
34
DGND
Digital Ground
10
QIN-
Q-Channel Negative Analog Input
35
ID0
I-Channel, Data Bit 0 Output (LSB)
11
QIN+
Q-Channel Positive Analog Input
36
ID1
I-Channel, Data Bit 1 Output
12
AGND
Analog Ground
37
ID2
I-Channel, Data Bit 2 Output
13
AVCC
Analog Supply
38
ID3
I-Channel, Data Bit 3 Output
14
QCLK
Q-Channel Clock Input
39
ID4
I-Channel, Data Bit 4 Output
15
DVCC
Digital Supply
40
ID5
I-Channel, Data Bit 5 Output
16
DGND
Digital Ground
41
ID6
I-Channel, Data Bit 6 Output
17
QD9
Q-Channel, Data Bit 9 Output (MSB)
42
ID7
I-Channel, Data Bit 7 Output
18
QD8
Q-Channel, Data Bit 8 Output
43
ID8
I-Channel, Data Bit 8 Output
19
QD7
Q-Channel, Data Bit 7 Output
44
ID9
I-Channel, Data Bit 9 Output (MSB)
20
QD6
Q-Channel, Data Bit 6 Output
45
DGND
Digital Ground
21
QD5
Q-Channel, Data Bit 5 Output
46
DVCC
Digital Supply
22
QD4
Q-Channel, Data Bit 4 Output
47
ICLK
I-Channel Clock Input
23
QD3
Q-Channel, Data Bit 3 Output
48
AVCC
Analog Supply
3-4
ISL5740
Absolute Maximum Ratings
TA = 25oC
Thermal Information
Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . . .4V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DVCC
Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVCC
Operating Conditions
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
ISL5740IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(Lead Tips Only)
Temperature Range
ISL5740IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AV CC = DV CC = +3.0V; I/QVRIN = 1.25V; fS = 60MSPS at 50% Duty Cycle;
CL = 10pF; TA = 25oC; Differential Analog Input, Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
10
-
-
Bits
ACCURACY
Resolution
Integral Linearity Error, INL
fIN = 10MHz
-
2
1
LSB
Differential Linearity Error, DNL
(Guaranteed No Missing Codes)
fIN = 10MHz
-
±0.4
±1.0
LSB
Offset Error, VOS
fIN = DC
-36
12
+36
LSB
Full Scale Error, FSE
fIN = DC
-3
1
3
%fS
Gain Matching
Full Scale (Peak-to-Peak)
-
±1.5
6
%fS
Minimum Conversion Rate
No Missing Codes
-
1
-
MSPS
Maximum Conversion Rate
No Missing Codes
60
-
-
MSPS
Effective Number of Bits, ENOB
fIN = 10MHz
9.1
-
-
Bits
Signal to Noise and Distortion Ratio, SINAD
RMS Signal
= -------------------------------------------------------------RMS Noise + Distortion
fIN = 10MHz
56.8
-
-
dB
Signal to Noise Ratio, SNR
RMS Signal
= ------------------------------RMS Noise
fIN = 10MHz
57
-
-
dB
Total Harmonic Distortion, THD
fIN = 10MHz
-70
-
-
dBc
2nd Harmonic Distortion
fIN = 10MHz
-
-
-
dBc
3rd Harmonic Distortion
fIN = 10MHz
-
-
-
dBc
Spurious Free Dynamic Range, SFDR
fIN = 10MHz
70
-
-
dBc
Intermodulation Distortion, IMD
f1 = 1MHz, f2 = 1.02MHz
-
-
-
dBc
I/Q Channel Crosstalk
-
-75
-
dBc
I/Q Channel Offset Match
-
10
-
LSB
I/Q Channel Full Scale Error Match
-
10
-
LSB
DYNAMIC CHARACTERISTICS
Transient Response
(Note 2)
-
1
-
Cycle
Over-Voltage Recovery
0.2V Overdrive (Note 2)
-
1
-
Cycle
3-5
ISL5740
Electrical Specifications
AV CC = DV CC = +3.0V; I/QVRIN = 1.25V; fS = 60MSPS at 50% Duty Cycle;
CL = 10pF; TA = 25oC; Differential Analog Input, Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Maximum Peak-to-Peak Differential Analog Input
Range (I/QIN+ - I/QIN-)
-
±0.5
-
V
Maximum Peak-to-Peak Single-Ended
Analog Input Range
-
1.0
-
V
ANALOG INPUT
Analog Input Resistance, RIN+ or RIN-
VIN+, VIN- = VREF, DC
-
1
-
MΩ
Analog Input Capacitance, CIN+ or CIN-
VIN+, VIN- = VREF, DC
-
10
-
pF
Analog Input Bias Current, IB+ or IB-
VIN+, VIN- = VREF, DC
(Notes 2, 3)
-10
-
10
µA
Differential Analog Input Bias Current
IBDIFF = (IB+ - IB-)
(Notes 2, 3)
-0.5
-
0.5
µA
Full Power Input Bandwidth, FPBW
(Note 2)
-
400
-
MHz
Analog Input Common Mode Voltage Range
(VIN+ + VIN-) / 2
Differential Mode (Note 2)
0.25
-
AVCC-0.25
V
Reference Output Voltage, VROUT (Loaded)
-
1.25
-
V
Reference Output Current, IROUT
-
1
-
mA
Reference Temperature Coefficient
-
200
-
ppm/oC
-
1.25
-
V
INTERNAL VOLTAGE REFERENCE
REFERENCE VOLTAGE INPUT
Reference Voltage Input, VRIN
Total Reference Resistance, RRIN
With VRIN = 1.25V
-
-
-
MΩ
Reference Current, IRIN
With VRIN = 1.25V
-
-
-
mA
SAMPLING CLOCK INPUT
Input Logic High Voltage, VIH
CLK
2.0
-
-
V
Input Logic Low Voltage, VIL
CLK
-
-
0.8
V
Input Logic High Current, IIH
CLK, VIH = 5V
-1
-
1
µA
Input Logic Low Current, IIL
CLK, VIL = 0V
-1
-
1
µA
Input Capacitance, CIN
CLK
-
-
-
pF
DIGITAL OUTPUTS
Output Logic High Voltage, VOH
IOH = 100µA
2.45
2.98
-
V
Output Logic Low Voltage, VOL
IOL = 100µA
-
0.001
0.5
V
-
7
-
pF
Aperture Delay, tAP
-
-
-
ns
Aperture Delay Match
-
100
-
ps
Aperture Jitter, tAJ
-
5
-
psRMS
Data Output Hold, tH
-
3
-
ns
Data Output Delay, tOD
-
4.5
-
ns
Output Capacitance, COUT
TIMING CHARACTERISTICS
Data Latency, tLAT
For a Valid Sample (Note 2)
-
7
-
Cycles
Power-Up Initialization
Data Invalid Time (Note 2)
-
-
-
Cycles
Sample Clock Pulse Width (Low)
(Note 2)
7.5
8.3
-
ns
3-6
ISL5740
Electrical Specifications
AV CC = DV CC = +3.0V; I/QVRIN = 1.25V; fS = 60MSPS at 50% Duty Cycle;
CL = 10pF; TA = 25oC; Differential Analog Input, Unless Otherwise Specified (Continued)
PARAMETER
Sample Clock Pulse Width (High)
TEST CONDITIONS
(Note 2)
Sample Clock Duty Cycle Variation
MIN
TYP
MAX
UNITS
7.5
8.3
-
ns
-
±5
-
%
POWER SUPPLY CHARACTERISTICS
Analog Supply Voltage, AVCC
(Note 2)
2.7
3.0
3.6
V
Digital Supply Voltage, DVCC1 and DVCC2
(Note 2)
2.7
3.0
3.6
V
Supply Current Total, ICCT
-
-
93.3
mA
Analog Supply Current IACC
-
-
68.3
mA
Digital Supply Current IDCC
-
-
25
mA
Power Dissipation Total PT
-
-
280
mW
Offset Error Sensitivity, ∆VOS
AVCC or DVCC = 3V ±5%
-
±0.5
-
LSB
Gain Error Sensitivity, ∆FSE
AVCC or DVCC = 3V ±5%
-
±0.5
-
LSB
NOTES:
2. Parameter guaranteed by design or characterization and not production tested.
3. With the clock low and DC input.
3-7
ISL5740
Timing Waveforms
ANALOG
INPUT
CLOCK
INPUT
SN - 1
HN - 1
SN
HN
SN + 1
HN + 1 SN + 2
SN + 5 HN + 5
SN + 6 HN + 6 SN + 7
HN + 7 SN + 8
HN + 8
INPUT
S/H
1ST
STAGE
2ND
STAGE
B1 , N - 1
B2 , N - 2
9TH
STAGE
B1 , N
B2 , N - 1
B9 , N - 5
DATA
OUTPUT
B1 , N + 1
B1 , N + 4
B2 , N + 4
B2 , N
B9 , N - 4
DN - 6
B1 , N + 5
B9 , N
DN - 5
DN - 1
4. SN : N-th sampling period.
5. HN : N-th holding period.
6. BM , N : M-th stage digital output corresponding to N-th sampled input.
7. DN : Final data output corresponding to N-th sampled input.
FIGURE 1. ISL5740 INTERNAL CIRCUIT TIMING
ANALOG
INPUT
tAP
tAJ
1.5V
tOD
tH
DATA
OUTPUT
2.4V
DATA N-1
DATA N
0.5V
FIGURE 2. ISL5740 INPUT TO OUTPUT TIMING
3-8
B1 , N + 7
B2 , N + 6
B9 , N + 2
DN
NOTES:
1.5V
B2 , N + 5
B9 , N + 1
tLAT
CLOCK
INPUT
B1 , N + 6
B9 , N + 3
DN + 1
DN + 2
ISL5740
TABLE 1. A/D CODE TABLE
OFFSET BINARY OUTPUT CODE
DIFFERENTIAL INPUT
VOLTAGE
(I/QIN+ - I/QIN-)
CODE CENTER
DESCRIPTION
MSB
LSB
I/QD9 I/QD8 I/QD7 I/QD6 I/QD5 I/QD4 I/QD3 I/QD2 I/QD1 I/QD0
+Full Scale (+fS) -1/4 LSB
0.499756V
1
1
1
1
1
1
1
1
1
1
+fS - 11/4 LSB
0.498779V
1
1
1
1
1
1
1
1
1
0
+3/4 LSB
732.422µV
1
0
0
0
0
0
0
0
0
0
-1/4 LSB
-244.141µV
0
1
1
1
1
1
1
1
1
1
-fS + 13/4 LSB
-0.498291V
0
0
0
0
0
0
0
0
0
1
-Full Scale (-fS) + 3/4 LSB
-0.499268V
0
0
0
0
0
0
0
0
0
0
NOTE:
8. The voltages listed above represent the ideal center of each output code shown with VREFIN = +1.25V.
Detailed Description
Φ1
Theory of Operation
The ISL5740 is a dual 10-bit fully differential sampling pipeline
A/D converter with digital error correction logic. Figure 15
depicts the circuit for the front end differential-in-differentialout sample-and-hold (S/H) amplifiers. The switches are
controlled by an internal sampling clock which is a nonoverlapping two phase signal, Φ1 and Φ2 , derived from the
master sampling clock. During the sampling phase, Φ1 , the
input signal is applied to the sampling capacitors, CS . At the
same time the holding capacitors, CH , are discharged to
analog ground. At the falling edge of Φ1 the input signal is
sampled on the bottom plates of the sampling capacitors. In
the next clock phase, Φ2 , the two bottom plates of the
sampling capacitors are connected together and the holding
capacitors are switched to the op amp output nodes. The
charge then redistributes between CS and CH completing one
sample-and-hold cycle. The front end sample-and-hold output
is a fully-differential, sampled-data representation of the
analog input. The circuit not only performs the sample-andhold function but will also convert a single-ended input to a
fully-differential output for the converter core. During the
sampling phase, the I/QIN pins see only the on-resistance of a
switch and CS . The relatively small values of these
components result in a typical full power input bandwidth of
400MHz for the converter.
I/QIN+
Φ1
Φ1
Φ1
CS
Φ2
I/QIN-
CH
-+
VOUT+
+-
VOUT-
CS
Φ1
CH
Φ1
FIGURE 3. ANALOG INPUT SAMPLE-AND-HOLD
As illustrated in the Functional Block Diagram and the timing
diagram in Figure 1, eight identical pipeline subconverter
stages, each containing a two-bit flash converter and a twobit multiplying digital-to-analog converter, follow the S/H
circuit with the ninth stage being a two bit flash converter.
Each converter stage in the pipeline will be sampling in one
phase and amplifying in the other clock phase. Each
individual subconverter clock signal is offset by 180 degrees
from the previous stage clock signal resulting in alternate
stages in the pipeline performing the same operation.
The output of each of the eight identical two-bit subconverter
stages is a two-bit digital word containing a supplementary bit
to be used by the digital error correction logic. The output of
each subconverter stage is input to a digital delay line which is
controlled by the internal sampling clock. The function of the
digital delay line is to time align the digital outputs of the eight
identical two-bit subconverter stages with the corresponding
output of the ninth stage flash converter before applying the
eighteen bit result to the digital error correction logic. The
digital error correction logic uses the supplementary bits to
correct any error that may exist before generating the final ten
bit digital data output of the converter.
Because of the pipeline nature of this converter, the digital
data representing an analog input sample is output to the
digital data bus following the 6th cycle of the clock after the
3-9
ISL5740
analog sample is taken (see the timing diagram in Figure 1).
This time delay is specified as the data latency. After the
data latency time, the digital data representing each
succeeding analog sample is output during the following
clock cycle. The digital output data is provided in offset
binary format (see Table 1, A/D Code Table).
Internal Reference Voltage Output, VROUT
The ISL5740 is equipped with an internal 1.25V bandgap
reference voltage generator, therefore, no external reference
voltage is required. VROUT should be connected to VRIN
when using the internal reference voltage. An external, usersupplied, 0.1µF capacitor may be connected from the VROUT
output pin to filter any stray board noise.
Reference Voltage Inputs, I/Q VREFIN
The ISL5740 is designed to accept a 1.25V reference
voltage source at the VRIN input pins for the I and Q
channels. Typical operation of the converter requires VRIN to
be set at 1.25V. The ISL5740 is tested with VRIN connected
to VROUT yielding a fully differential analog input voltage
range of ±0.5V.
The user does have the option of supplying an external 1.25V
reference voltage. As a result of the high input impedance
presented at the VRIN input pin, MΩ typically, the external
reference voltage being used is only required to source small
amount of reference input current.
significantly with the value of the analog input common
mode voltage.
For the AC coupled differential input (Figure 16) and with VRIN
connected to VROUT, full scale is achieved when the VIN and
-VIN input signals are 0.5VP-P, with -VIN being 180 degrees
out of phase with VIN . The converter will be at positive full
scale when the I/QIN+ input is at I/QVRIN + 0.25V and the
I/QIN- input is at I/QVRIN - 0.25V (I/QIN+ - I/QIN- = +0.5V).
Conversely, the converter will be at negative full scale when
the I/QIN+ input is equal to I/QVRIN - 0.25V and I/QIN- is at
I/QVRIN + 0.25V (I/QIN+ - I/QIN- = -0.5V).
The analog input can be DC coupled (Figure 17) as long as
the inputs are within the analog input common mode voltage
range (0.25V ≤ VDC ≤ 2.75V).
The resistors, R, in Figure 17 are not absolutely necessary
but may be used as load setting resistors. A capacitor, C,
connected from I/QIN+ to I/QIN- will help filter any high
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
VIN
I/QIN+
VDC
In order to minimize overall converter noise it is
recommended that adequate high frequency decoupling be
provided at the reference voltage input pin, VRIN .
Analog Input, Differential Connection
The analog input of the ISL5740 is a differential input that
can be configured in various ways depending on the signal
source and the required level of performance. A fully
differential connection (Figure 16 and Figure 17) will deliver
the best performance from the converter.
R
C
ISL5740
I/QVRIN
-VIN
R
VDC
I/QIN-
FIGURE 5. DC COUPLED DIFFERENTIAL INPUT
Analog Input, Single-Ended Connection
I/QIN+
VIN
R
The configuration shown in Figure 18 may be used with a
single ended AC coupled input.
ISL5740
I/QVRIN
-VIN
R
I/QIN-
FIGURE 4. AC COUPLED DIFFERENTIAL INPUT
Since the ISL5740 is powered by a single +3V analog
supply, the analog input is limited to be between ground and
+3V. For the differential input connection this implies the
analog input common mode voltage can range from 0.25V to
2.75V. The performance of the ADC does not change
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I/QIN+
VIN
R
VDC
ISL5740
I/QIN-
FIGURE 6. AC COUPLED SINGLE ENDED INPUT
Again, with VRIN connected to VROUT, if VIN is a 1VP-P
sinewave, then I/QIN+ is a 1.0VP-P sinewave riding on a
positive voltage equal to VDC . The converter will be at
positive full scale when I/QIN+ is at VDC + 0.5V (I/QIN+ -
ISL5740
I/QIN- = +0.5V) and will be at negative full scale when I/QIN+
is equal to VDC - 0.5V (I/QIN+ - I/QIN- = -0.5V). Sufficient
headroom must be provided such that the input voltage
never goes above +3V or below AGND. In this case, VDC
could range between 0.5V and 2.5V without a significant
change in ADC performance. The simplest way to produce
VDC is to use the I/QVRIN bias source, I/QVDC , output of
the ISL5740.
The single ended analog input can be DC coupled
(Figure 19) as long as the input is within the analog input
common mode voltage range.
VIN
I/QIN+
VDC
R
C
VDC
ISL5740
I/QIN-
FIGURE 7. DC COUPLED SINGLE ENDED INPUT
The resistor, R, in Figure 19 is not absolutely necessary but
may be used as a load setting resistor. A capacitor, C,
connected from I/QIN+ to I/QIN- will help filter any high
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
A single ended source may give better overall system
performance if it is first converted to differential before
driving the ISL5740.
Operational Mode
The ISL5740 contains several operational modes including a
normal two channel operation, placing one or both channels
in standby and delaying the Q channel data 1/2 clock cycle.
The operational mode is selected via the S1 and S2 pins and
is asynchronous to either clock. When either channel is
placed in standby, the output data is stalled and not high
impedance. When recovering from standby, valid data is
available after 20 clock cycles.
The delay mode can be used to set the Q channel 180
degrees out phase of the I channel if the same clock is
driving both channels. If separate, inverted clocks are used
for the I and Q channels, this feature can be used to align the
data.
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OPERATIONAL MODES
S1
S2
MODE
0
0
Standby I and Q Channels.
0
1
I channel operates normally with Q Channel in
standby mode.
1
0
I and Q Channels operating with I/Q output data in
phase.
1
1
I and Q Channels operating with Q data 180 degrees
out of phase.
Sampling Clock Requirements
The ISL5740 sampling clock input provides a standard highspeed interface to external TTL/CMOS logic families.
In order to ensure rated performance of the ISL5740, the
duty cycle of the clock should be held at 50% ±5%. It must
also have low jitter and operate at standard TTL/CMOS
levels.
Performance of the ISL5740 will only be guaranteed at
conversion rates above 1MSPS (Typ). This ensures proper
performance of the internal dynamic circuits. Similarly, when
power is first applied to the converter, a maximum of 20
cycles at a sample rate above 1MSPS must be performed
before valid data is available.
Supply and Ground Considerations
The ISL5740 has separate analog and digital supply and
ground pins to keep digital noise out of the analog signal
path. The part should be mounted on a board that provides
separate low impedance connections for the analog and
digital supplies and grounds. For best performance, the
supplies to the ISL5740 should be driven by clean, linear
regulated supplies. The board should also have good high
frequency decoupling capacitors mounted as close as
possible to the converter. If the part is powered off a single
supply then the analog supply can be isolated by a ferrite
bead from the digital supply.
Refer to the application note “Using Intersil High Speed A/D
Converters” (AN9214) for additional considerations when
using high speed converters.
ISL5740
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