Data Sheet

74ALVC125-Q100
Quad buffer/line driver; 3-state
Rev. 2 — 20 January 2014
Product data sheet
1. General description
The 74ALVC125-Q100 is a quad non-inverting buffer/line driver with 3-state outputs. The
output enable input (nOE) controls the 3 state outputs (nY). A HIGH on the nOE pin
causes the outputs to assume a high-impedance OFF-state.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 3) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 3)
 Specified from 40 C to +85 C
 Wide supply voltage range from 1.65 V to 3.6 V
 3.6 V tolerant inputs/outputs
 CMOS low power consumption
 Direct interface with TTL levels (2.7 V to 3.6 V)
 Power-down mode
 Latch-up performance exceeds 250 mA
 Complies with JEDEC standards:
 JESD8-7 (1.65 V to 1.95 V)
 JESD8-5 (2.3 V to 2.7 V)
 JESD8B/JESD36 (2.7 V to 3.6 V)
 ESD protection:
 MIL-STD-883, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
74ALVC125-Q100
NXP Semiconductors
Quad buffer/line driver; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74ALVC125D-Q100
40 C to +85 C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74ALVC125PW-Q100
40 C to +85 C
TSSOP14
plastic thin shrink small outline package; 14
leads; body width 4.4 mm
SOT402-1
74ALVC125BQ-Q100
40 C to +85 C
DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1
very thin quad flat package; no leads;14
terminals; body 2.5 x 3 x 0.85 mm
4. Functional diagram
2
1A
1
1OE
5
2A
4
2OE
1Y
3
2
2Y
1
6
1
3
EN1
5
6
4
9
3A
3Y
8
9
10
3OE
12
4A
13
4OE
8
10
4Y
11
12
11
13
mna229
mna228
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
nY
nA
nOE
mna227
Fig 3.
Logic diagram (one buffer)
74ALVC125_Q100
Product data sheet
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Rev. 2 — 20 January 2014
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2 of 15
74ALVC125-Q100
NXP Semiconductors
Quad buffer/line driver; 3-state
5. Pinning information
5.1 Pinning
1OE
1
terminal 1
index area
74ALVC125-Q100
1Y
3
12 4A
2OE
4
11 4Y
2A
5
10 3OE
2Y
6
9
3A
GND
7
8
3Y
1Y
3
12 4A
2OE
4
2A
5
2Y
6
11 4Y
GND(1)
10 3OE
9
8
14 VCC
13 4OE
13 4OE
7
2
2
3Y
1
1A
1A
GND
1OE
14 VCC
74ALVC125-Q100
3A
aaa-008234
Transparent top view
aaa-008233
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as a
supply pin or input.
Fig 4.
Pin configuration SO14 and TSSOP14
Fig 5.
Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
nA
2, 5, 9, 12
data input
nY
3, 6, 8, 11
bus output
nOE
1, 4, 10, 13
output enable (active LOW)
VCC
14
supply voltage
GND
7
ground (0 V)
6. Functional description
Table 3.
Function table[1]
Input
Output
nOE
nA
nY
L
L
L
L
H
H
H
X
Z
[1]
H = HIGH voltage level
L = LOW voltage level
X= don’t care
Z = high-impedance OFF-state
74ALVC125_Q100
Product data sheet
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Rev. 2 — 20 January 2014
© NXP B.V. 2014. All rights reserved.
3 of 15
74ALVC125-Q100
NXP Semiconductors
Quad buffer/line driver; 3-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
output voltage
VO
Conditions
VI < 0 V
[1]
VO > VCC or VO < 0 V
output HIGH or LOW state
[1] [2]
output 3-state
Power-down mode, VCC = 0 V
[2]
Max
Unit
0.5
+4.6
V
50
-
mA
0.5
+4.6
V
-
50
mA
0.5
VCC + 0.5
V
0.5
+4.6
V
0.5
+4.6
V
-
50
mA
100
mA
IO
output current
ICC
supply current
-
IGND
ground current
100
-
mA
Tstg
storage temperature
65
+150
C
-
500
mW
total power dissipation
Ptot
[1]
VO = 0 V to VCC
Min
Tamb = 40 C to +85 C
[3]
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2]
When VCC = 0 V (power-down mode), the output voltage can be 3.6 V in normal operation.
[3]
For SO14 packages: above 70 C derate linearly with 8 mW/K.
For TSSOP14 packages: above 60 C derate linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 C derate linearly with 4.5 mW/K.
74ALVC125_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 20 January 2014
© NXP B.V. 2014. All rights reserved.
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74ALVC125-Q100
NXP Semiconductors
Quad buffer/line driver; 3-state
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
VCC
Conditions
Min
Max
Unit
supply voltage
1.65
3.6
V
VI
input voltage
0
3.6
V
VO
output voltage
output HIGH or LOW state
0
VCC
V
output 3-state
0
3.6
V
power-down mode; VCC = 0 V
0
3.6
V
Tamb
ambient temperature
in free air
40
+85
C
t/V
input transition rise and fall rate
VCC = 1.65 V to 2.7 V
0
20
ns/V
VCC = 2.7 V to 3.6 V
0
10
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
40 C to +85 C
Conditions
Typ[1]
Min
VIH
VIL
VOH
VOL
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
input leakage current
74ALVC125_Q100
Product data sheet
Max
VCC = 1.65 V to 1.95 V
0.65  VCC -
-
V
VCC = 2.3 V to 2.7 V
1.7
-
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
V
VCC = 1.65 V to 1.95 V
-
-
0.35  VCC V
VCC = 2.3 V to 2.7 V
-
-
0.7
V
VCC = 2.7 V to 3.6 V
-
-
0.8
V
IO = 100 A; VCC = 1.65 V to 3.6 V
VCC  0.2
-
-
V
VI = VIH or VIL
IO = 6 mA; VCC = 1.65 V
1.25
1.51
-
V
IO = 12 mA; VCC = 2.3 V
1.8
2.10
-
V
IO = 8 mA; VCC = 2.3 V
1.7
2.01
-
V
IO = 12 mA; VCC = 2.7 V
2.2
2.53
-
V
IO = 18 mA; VCC = 3.0 V
2.4
2.76
-
V
IO = 24 mA; VCC = 3.0 V
2.2
2.68
-
V
-
-
0.2
V
VI = VIH or VIL
IO = 100 A; VCC = 1.65 V to 3.6 V
II
Unit
IO = 6 mA; VCC = 1.65 V
-
0.11
0.3
V
IO = 12 mA; VCC = 2.3 V
-
0.17
0.4
V
IO = 18 mA; VCC = 2.3 V
-
0.25
0.6
V
IO = 12 mA; VCC = 2.7 V
-
0.16
0.4
V
IO = 18 mA; VCC = 3.0 V
-
0.23
0.4
V
IO = 24 mA; VCC = 3.0 V
-
0.30
0.55
V
-
0.1
5
A
VCC = 3.6 V; VI = 3.6 V or GND
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Rev. 2 — 20 January 2014
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74ALVC125-Q100
NXP Semiconductors
Quad buffer/line driver; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
40 C to +85 C
Conditions
Typ[1]
Min
Unit
Max
IOZ
OFF-state output current
VI = VIH or VIL; VCC = 1.65 V to 3.6 V;
VO = 3.6 V or GND;
-
0.1
10
A
IOFF
power-off leakage current
VCC = 0 V; VI or VO = 0 V to 3.6 V
-
0.1
10
A
ICC
supply current
VCC = 3.6 V; VI = VCC or GND;
IO = 0 A
-
0.2
10
A
ICC
additional supply current
per input pin; VCC = 3.0 V to 3.6 V;
VI = VCC  0.6 V; IO = 0 A
-
5
750
A
CI
input capacitance
-
3.5
-
pF
[1]
All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit, see Figure 8.
Symbol
tpd
Parameter
propagation delay
40 C to +85 C
Conditions
Min
Max
VCC = 1.65 V to 1.95 V
1.3
2.4
5.3
ns
VCC = 2.3 V to 2.7 V
1.0
1.7
3.2
ns
nA to nY; see Figure 6
[2]
VCC = 2.7 V
-
2.0
3.1
ns
1.1
1.8
2.8
ns
VCC = 1.65 V to 1.95 V
1.4
3.9
6.4
ns
VCC = 2.3 V to 2.7 V
1.0
2.2
4.1
ns
-
2.7
4.3
ns
1.0
1.9
3.5
ns
VCC = 1.65 V to 1.95 V
1.8
3.9
5.9
ns
VCC = 2.3 V to 2.7 V
1.0
2.1
3.4
ns
-
2.9
4.0
ns
1.4
2.7
4.0
ns
VCC = 3.0 V to 3.6 V
ten
enable time
nOE to nY; see Figure 7
[2]
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
tdis
disable time
nOE to nY; see Figure 7
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
74ALVC125_Q100
Product data sheet
Unit
Typ[1]
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 20 January 2014
[2]
© NXP B.V. 2014. All rights reserved.
6 of 15
74ALVC125-Q100
NXP Semiconductors
Quad buffer/line driver; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit, see Figure 8.
Symbol
CPD
[1]
[2]
Parameter
40 C to +85 C
Conditions
power dissipation
capacitance
Unit
Min
Typ[1]
outputs HIGH or LOW state
-
27
-
pF
outputs 3-state
-
5
-
pF
Max
[3]
per buffer; VI = GND to VCC; VCC = 3.3 V
Typical values are measured at Tamb = 25 C
tpd is the same as tPHL and tPLH.
ten is the same as tPZH and tPZL.
tdis is the same as tPHZ and tPLZ.
[3]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
(CL  VCC2  fo) = sum of the outputs
11. Waveforms
VI
VM
nA input
GND
tPHL
tPLH
VOH
VM
nY output
VOL
mna230
Measurement points are given in Table 8.
VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 6.
Table 8.
Input nA to output nY propagation delay times
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
Vx
Vy
1.65 V to 1.95 V
0.5VCC
0.5VCC
VOL + 0.15 V
VOH  0.15 V
2.3 V to 2.7 V
0.5VCC
0.5VCC
VOL + 0.15 V
VOH  0.15 V
2.7 V
1.5 V
1.5 V
VOL + 0.3 V
VOH  0.3 V
3.0 V to 3.6 V
1.5 V
1.5 V
VOL + 0.3 V
VOH  0.3 V
74ALVC125_Q100
Product data sheet
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Rev. 2 — 20 January 2014
© NXP B.V. 2014. All rights reserved.
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74ALVC125-Q100
NXP Semiconductors
Quad buffer/line driver; 3-state
VI
nOE input
VM
GND
tPLZ
tPZL
VCC
output
LOW-to-OFF
OFF-to-LOW
VM
VX
VOL
tPHZ
tPZH
VOH
VY
output
HIGH-to-OFF
OFF-to-HIGH
GND
VM
outputs
enabled
outputs
enabled
outputs
disabled
mna362
Measurement points are given in Table 8.
VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 7.
Enable and disable times
VEXT
VCC
VI
RL
VO
G
DUT
RT
CL
RL
mna616
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 8.
Table 9.
Test circuitry for switching times
Test data
Supply voltage
Input
Load
VEXT
VI
tr, tf
CL
RL
tPLH, tPHL
tPLZ, tPZL
tPHZ, tPZH
1.65 V to 1.95 V
VCC
 2.0 ns
30 pF
1 k
open
2  VCC
GND
2.3 V to 2.7 V
VCC
 2.0 ns
30 pF
500 
open
2  VCC
GND
2.7 V
2.7 V
 2.5 ns
50 pF
500 
open
6V
GND
3.0 V to 3.6 V
2.7 V
 2.5 ns
50 pF
500 
open
6V
GND
74ALVC125_Q100
Product data sheet
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Rev. 2 — 20 January 2014
© NXP B.V. 2014. All rights reserved.
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74ALVC125-Q100
NXP Semiconductors
Quad buffer/line driver; 3-state
12. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
HE
v M A
Z
8
14
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
7
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.010 0.057
inches 0.069
0.004 0.049
0.05
0.244
0.039
0.041
0.228
0.016
0.028
0.024
0.01
0.01
0.028
0.004
0.012
θ
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
Fig 9.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT108-1
076E06
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Package outline SOT108-1 (SO14)
74ALVC125_Q100
Product data sheet
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Rev. 2 — 20 January 2014
© NXP B.V. 2014. All rights reserved.
9 of 15
74ALVC125-Q100
NXP Semiconductors
Quad buffer/line driver; 3-state
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
E
D
A
X
c
y
HE
v M A
Z
8
14
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
7
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.72
0.38
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT402-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Fig 10. Package outline SOT402-1 (TSSOP14)
74ALVC125_Q100
Product data sheet
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Rev. 2 — 20 January 2014
© NXP B.V. 2014. All rights reserved.
10 of 15
74ALVC125-Q100
NXP Semiconductors
Quad buffer/line driver; 3-state
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
SOT762-1
14 terminals; body 2.5 x 3 x 0.85 mm
A
B
D
A
A1
E
c
detail X
terminal 1
index area
terminal 1
index area
C
e1
e
2
6
y
y1 C
v M C A B
w M C
b
L
1
7
Eh
e
14
8
13
9
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
0.5
2
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT762-1
---
MO-241
---
EUROPEAN
PROJECTION
ISSUE DATE
02-10-17
03-01-27
Fig 11. Package outline SOT762-1 (DHVQFN14)
74ALVC125_Q100
Product data sheet
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Rev. 2 — 20 January 2014
© NXP B.V. 2014. All rights reserved.
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Quad buffer/line driver; 3-state
13. Abbreviations
Table 10.
Abbreviations
Acronym
Description
CDM
Charged Device Model
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MIL
Military
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74ALVC125_Q100 v.2
20140120
Product data sheet
-
74ALVC125_Q100 v.1
-
-
Modifications:
74ALVC125_Q100 v.1
74ALVC125_Q100
Product data sheet
•
Feature list corrected (errata).
20130628
Product data sheet
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Rev. 2 — 20 January 2014
© NXP B.V. 2014. All rights reserved.
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74ALVC125-Q100
NXP Semiconductors
Quad buffer/line driver; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74ALVC125_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 20 January 2014
© NXP B.V. 2014. All rights reserved.
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74ALVC125-Q100
NXP Semiconductors
Quad buffer/line driver; 3-state
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74ALVC125_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 20 January 2014
© NXP B.V. 2014. All rights reserved.
14 of 15
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NXP Semiconductors
Quad buffer/line driver; 3-state
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 20 January 2014
Document identifier: 74ALVC125_Q100