DA6180C

DA6180C.001
17 September, 2014
MAS6180C
AM Receiver IC
*
*
*
*
*
*
*
*
Single Band Receiver IC
High Sensitivity
Very Low Power Consumption
Wide Supply Voltage Range
Power Down Control
Control for AGC On
High Selectivity by Crystal Filter
Fast Startup Feature
DESCRIPTION
The MAS6180 AM-Receiver chip is a highly sensitive,
simple to use AM receiver specially intended to receive
time signals in the frequency range from 40 kHz to 100
kHz. Only a few external components are required for
time signal receiver. The circuit has preamplifier, wide
range automatic gain control, demodulator and output
FEATURES
•
•
•
•
•
•
•
•
•
•
•
comparator built in. The output signal can be
processed directly by an additional digital circuitry to
extract the data from the received signal. The control
for AGC (automatic gain control) can be used to switch
AGC on or off if necessary.
APPLICATIONS
Single Band Receiver IC
Highly Sensitive AM Receiver, 0.4 µVRMS typ.
Wide Supply Voltage Range from 1.5 V to 5.5 V
Very Low Power Consumption
Power Down Control
Fast Startup
Only a Few External Components Necessary
Control for AGC On
Wide Frequency Range from 40 kHz to 100 kHz
High Selectivity by Quartz Crystal Filter
Differential Input
•
Single Band Time Signal Receiver WWVB (USA),
JJY (Japan), DCF77 (Germany), MSF (UK), HGB
(Switzerland) and BPC (China)
BLOCK DIAGRAM
VDD
QOP
VDD
AGC Amplifier
QI
AON
QOM
RFIP
RFIM
Demodulator
&
Comparator
OUT
Power Supply/Biasing
VDD
VSS
PDN
AGC
DEC
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DA6180C.001
17 September, 2014
MAS6180 PAD LAYOUT
1160 µm
VDD
VSS
MAS6180Cx
RFIP
QI
PDN
AGC
AON
OUT
DEC
1320 µm
RFIM
QOP
QOM
VSS pad
bonded first!
DIE size = 1160 µm x 1320 µm; PAD size = 80 µm x 80 µm
Note: Because the substrate of the die is internally connected to VSS, the die has to be connected to VSS or left
floating. Please make sure that VSS is the first pad to be bonded. Pick-and-place and all component assembly
are recommended to be performed in ESD protected area.
Note: Coordinates are pad center points where origin has been located in bottom-left corner of the silicon die.
Pad Identification
Name
X-coordinate
Y-coordinate
Power Supply Voltage
Positive Quartz Filter Output
Negative Quartz Filter Output
Quartz Filter Input for Crystal
AGC Capacitor
Receiver Output
Demodulator Capacitor
AGC On Control
Power Down
Positive Receiver Input
Negative Receiver Input
Power Supply Ground
VDD
QOP
QOM
QI
AGC
OUT
DEC
AON
PDN
RFIP
RFIM
VSS
126 µm
126 µm
126 µm
126 µm
126 µm
126 µm
1034 µm
1034 µm
1034 µm
1034 µm
1034 µm
1034 µm
1122 µm
955 µm
787 µm
604 µm
435 µm
258 µm
261 µm
445 µm
613 µm
802 µm
980 µm
1111 µm
Note
1
2
3
4
5
5
Notes:
1) QOM bonding pad is electrically unconnected in MAS6180C1 version
2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated)
- the output is a current source/sink with |IOUT| > 5 µA
- at power down the output is pulled to VSS (pull down switch)
3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)
- Internal pull-up with current < 1 µA which is switched off at power down
4) PDN = VSS means receiver on; PDN = VDD means receiver off
Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up
(PDN=VSS) i.e. at the falling edge of PDN signal.
5) Receiver inputs RFIP and RFIM have both 1.4 MΩ biasing resistors towards VDD
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DA6180C.001
17 September, 2014
6)
ABSOLUTE MAXIMUM RATINGS
All Voltages with Respect to Ground
Parameter
Supply Voltage
Input Voltage
ESD Rating
Symbol
VDD-VSS
VIN
VESD
Latchup Current Limit
Operating Temperature
Storage Temperature
ILUT
TOP
TST
Conditions
For all pins,
Human Body Model (HBM)
For all pins
Min
Max
Unit
- 0.3
VSS-0.3
±2
+5.5
VDD+0.3
V
V
kV
±100
-40
- 55
+85
+150
mA
°C
°C
Stresses beyond those listed may cause permanent damage to the device. The device may not operate under these conditions, but it will
not be destroyed.
Note: In latchup testing the supply voltages are connected normally to the tested device. Then pulsed test current is fed to each input
separately and device current consumption is observed. If the device current consumption increases suddenly due to test current pulses
and the abnormally high current consumption continues after test current pulses are cut off then the device has gone to latch up. Current
pulse is turned on for 10 ms and off for 20 ms.
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 5.0V, Temperature = 25°C, unless otherwise specified.
Parameter
Operating Voltage
Current Consumption
Stand-By Current
Input Frequency Range
Minimum Input Voltage
Maximum Input Voltage
Receiver Input Resistance
Receiver Input Capacitance
Input Levels |lIN|<0.5 µA
Output Current
VOL<0.2 VDD;VOH >0.8 VDD
DCF77 Output Pulses
Symbol
Conditions
Min
Typ
Max
Unit
VDD
IDD
TA = -40°C..+85°C
1.5
5.0
66
68
43
45
5.5
80
V
µA
65
µA
0.1
100
1
µA
kHz
IDDoff
fIN
VIN min
VIN max
RRFI
CRFI
VIL
VIH
|IOUT|
Startup Time
T 100ms
T 200ms
T 100ms
T 200ms
T 500ms
T 200ms
T 500ms
T 800ms
T 200ms
T 500ms
T 800ms
T 200ms
T 500ms
T 800ms
TStart
Output Delay Time
TDelay
MSF Output Pulses
WWVB Output Pulses
JJY60 Output Pulses
JJY40 Output Pulses
VDD=1.5 V, Vin=0.4 µVrms
VDD=5 V, Vin=0.4 µVrms
VDD=1.5 V, Vin=20 mVrms
VDD=5 V, Vin=20 mVrms
See note below.
40
0.4
20
Differential Input,
f=77.5 kHz
600
1.1
0.35
VDD-0.35
5
1 µVrms ≤ VIN ≤
20 mVrms, see note below!
1 µVrms ≤ VIN ≤
20 mVrms, see note below!
1 µVrms ≤ VIN ≤
20 mVrms, see note below!
1 µVrms ≤ VIN ≤
20 mVrms, see note below!
1 µVrms ≤ VIN ≤
20 mVrms, see note below!
Fast Start-up, Vin=0.4 µVrms
Fast Start-up, Vin=20 mVrms
µVrms
mVrms
kΩ
pF
V
15
µA
95
195
120
220
520
200
500
800
210
505
800
200
495
790
1.3
3.5
50
ms
ms
ms
ms
ms
4
s
100
ms
Note: Stand-by current consumption may increase if V IH and V IL differ from VDD and 0 respectively.
Note: See Note 6: Time Signal Software’s Pulse Width Recognition Limits and Table 5 on page 7!
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DA6180C.001
17 September, 2014
TYPICAL APPLICATION
Note 1
Note 4
Optional
Control
for AGC on/hold
MAS6180C1
VDD
QOP
Note 5
QI
RFIP
VDD
Ferrite
Antenna
AON
QOM
AGC Amplifier
RFIM
Demodulator
&
Comparator
OUT
Receiver
Output
Power Supply/Biasing
VDD
VSS
PDN
Note 3
Power Down /
Fast Startup
Control
RVDD
10 Ω
AGC
CAGC
10 µF
DEC
CDEC
47 nF
Note 2
+5V
CVDD
10 µF
Figure 1. Application circuit of internal compensation capacitance option version MAS6180C1.
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17 September, 2014
TYPICAL APPLICATION (Continued)
Note 1: Crystals
The crystal as well as ferrite antenna frequencies are chosen according to the time-signal system (Table 1). More
detailed crystal nominal frequency is normally specified for certain load capacitance but in MAS6180 filter circuit
the load capacitance is not used. Effectively this means that most accurate filter frequency is achieved by using
about 3 Hz higher frequency crystal than the received time signal frequency. For example in DCF77 application a
77.503 kHz crystal resonates at the desired DCF77 77.500 kHz frequency when the load capacitor is missing.
Table 1. Time-Signal System Frequencies
Time-Signal System
Location
Antenna Frequency
Recommended Crystal Frequency
DCF77
HGB
MSF
WWVB
JJY
BPC
77.5 kHz
75 kHz
60 kHz
60 kHz
40 kHz and 60 kHz
68.5 kHz
77.503 kHz
75.003 kHz
60.003 kHz
60.003 kHz
40.003 kHz and 60.003 kHz
68.505 kHz
Germany
Switzerland
United Kingdom
USA
Japan
China
The crystal shunt capacitance C0 should be matched as well as possible with the internal shunt capacitance
compensation capacitor CC of MAS6180. See Compensation Capacitance Options on table 2.
Table 2 . Compensation Capacitance Options
Device
CC
Crystal Description
MAS6180C1
0.75 pF
For low C0 crystals
It should be noted that grounded crystal package has reduced shunt capacitance. This value is about 85% of
floating crystal shunt capacitance. For example crystal with 1 pF floating package shunt capacitance can have
0.85 pF grounded package shunt capacitance. PCB traces of crystal should be kept at minimum to minimize
additional parasitic capacitance which can cause capacitance mismatching.
Table 3 below presents some crystal manufacturers having suitable crystals for time signal receiver application.
Table 3. Crystal Manufacturers and Crystal Types in Alphabetical Order for Time Signal Receiver Application
Manufacturer
Crystal Type
Dimensions
Web Link
Citizen
Epson Toyocom
KDS Daishinku
Microcrystal
Seiko
Instruments
CFV-206
C-2-Type
C-4-Type
DT-261
MS3V-T1R
VTC-120
ø 2.0 x 6.0
ø 1.5 x 5.0
ø 2.0 x 6.0
ø 2.0 x 6.0
1.45 x 1.45 x 6.7
ø 1.2 x 4.7
http://www.citizen.co.jp/tokuhan/quartz/
http://www.epsontoyocom.co.jp/english/
http://www.kds.info/index_en.htm
http://www.microcrystal.com/
http://www.sii-crystal.com
5 (12)
DA6180C.001
17 September, 2014
TYPICAL APPLICATION (Continued)
Note 2: AGC Capacitor
The AGC and DEC capacitors must have low leakage currents due to very small signal currents through the
capacitors. The insulation resistance of these capacitors should be at minimum 100 MΩ. Also probes with at
least few 100 MΩ impedance should be used for voltage probing of the AGC and DEC pins. Electrolytic AGC
capacitor should have voltage rating at least 25 V for low enough leakage. DEC capacitor can be low leakage
chip capacitor.
It is recommended to connect both AGC and DEC capacitors to VDD (see application figure 1) although VSS
connection is also possible. The VDD connection provides better supply noise immunity because signals are
referenced to VDD. Additionally leakage currents are minimized in this connection because in power down the
AGC pin voltage is pulled to VDD (to minimum AGC gain) then corresponding to zero voltage over the AGC
capacitor.
Note 3: Power Down / Fast Startup Control
Both power down and fast startup are controlled using the PDN pin. The device is in power down (turned off) if
PDN = VDD and in power up (turned on) if PDN = VSS. Fast startup is triggered automatically by the falling edge
of PDN signal, i.e., controlling device from power down to power up. The VDD must be high before falling edge of
PDN to guarantee proper operation of fast startup circuitry. Before power up the device should have been kept in
power down state at least 50ms. This guarantees that the AGC capacitor voltage has been completely pulled to
VDD during power down. The startup time without proper fast startup control can be over minute but with fast
startup it is shortened typically to few seconds.
Note 4: Optional Control for AGC On/Hold
AON control pin has internal pull up which turns AGC circuit on all the time if AON pin is left unconnected.
Optionally AON control can be used to hold and release AGC circuit. Stepper motor drive of analog clock or
watch can produce disturbing amount of noise which can shift the input amplifier gain to unoptimal level. This can
be avoided by controlling AGC hold (AON=VSS) during stepper motor drive periods and releasing AGC
(AON=VDD) when motors are not driven. The AGC should be in hold only during disturbances and kept on other
time released since due to leakage the AGC voltage can change slowly even when in hold.
Note 5: Ferrite Antenna
The ferrite antenna converts the transmitted radio wave into a voltage signal. It has an important role in
determining receiver performance. Recommended antenna impedance at resonance is around 100 kΩ.
Low antenna impedance corresponds to low noise but often also to small signal amplitude. On the other hand
high antenna impedance corresponds to high noise but also large signal. The optimum performance where
signal-to-noise ratio is at maximum is achieved in between.
The antenna should have also some selectivity for rejecting near signal band disturbances. This is determined by
the antenna quality factor which should be approximately 100. Much higher quality factor antennas suffer from
extensive tuning accuracy requirements and possible tuning drifts by the temperature.
Antenna impedance Rant can be calculated using equation 1 where fres, L, Qant and C are resonance frequency,
coil inductance, antenna quality factor and antenna tuning capacitor respectively. Antenna quality factor Qant is
defined by ratio of resonance frequency fres and antenna bandwidth B (equation 2).
Rant = 2π ⋅ f res ⋅ L ⋅ Qant =
Qant =
f res
B
Qant
1
=
2π ⋅ f res ⋅ C 2π ⋅ B ⋅ C
Equation 1.
Equation 2.
Table 4 on next page presents some antenna manufacturers for time signal application.
6 (12)
DA6180C.001
17 September, 2014
TYPICAL APPLICATION (Continued)
Table 4. Antenna Manufacturers and Antenna Types in Alphabetical Order for Time Signal Application
Manufacturer Antenna Type
Dimensions
Web Link
C.E.C Coils
AP/AR Antenna Bars
HR Electronic
GmbH
Hitachi Metals
60716 (60 kHz)
60708 (77.5 kHz)
AN-T702Sxx
AN-T702Mxx
AN-T702Lxx
RCA-SMD-77A (77.5 kHz)
RCA-SMD-60A (60 kHz)
ACL80A (40 kHz)
Premo
Sumida
http://www.ceccoils.com/CECWEB/index
.aspx?lang=en
ø 10 x 60 mm
http://www.hrelectronic.com/
19 x 5.5 x 6.3 mm
28 x 5 x 5 mm
50 x 5 x 5 mm
75 x 15 x 6.3 mm
http://www.hitachimetals.co.jp/e/prod/prod06/p06_12.html
ø 10 x 80 mm
www.sumida.co.jp/jeita/XJA021.pdf
http://www.grupopremo.com/
Note 6: Time Signal Software’s Pulse Width Recognition Limits
The typical output pulse width specifications are presented in the electrical characteristics section on page 3. Due
to process variations the typical output pulse width can differ from these. Additionally the output pulse widths can
vary even more depending on the receiving antenna signal strength versus noise and disturbance conditions.
That is why it is important that the time signal decoding software has appropriate tolerance limits for managing
the output pulse width variations successfully. The table 5 presents recommended software pulse width tolerance
limits for recognizing pulses of different time signals.
Table 5. Recommended Software Pulse Width Recognition Limits for Different Time Signals
Parameter
Symbol
Min
Max
Unit
DCF77 Output Pulses
MSF Output Pulses
WWVB Output Pulses
JJY60 Output Pulses
JJY40 Output Pulses
T 100ms
T 200ms
T 100ms
T 200ms
T 500ms
T 200ms
T 500ms
T 800ms
T 200ms
T 500ms
T 800ms
T 200ms
T 500ms
T 800ms
40
140
50
170
400
100
400
700
100
400
700
100
400
700
130
250
160
300
600
300
600
900
300
600
900
300
600
900
ms
ms
ms
ms
ms
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DA6180C.001
17 September, 2014
PIN CONFIGURATION & TOP MARKING FOR PLASTIC TSSOP-16 PACKAGE
VSS
RFIM
VDD
QOP
QOM
OUT
6180zz
YYWW
QI
AGC
RFIP
PDN
AON
DEC
Top Marking Definitions:
zz = Version
YYWW = Year Week
PIN DESCRIPTION
Pin Name
Pin
Type
VDD
QOP
QOM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P
AO
AO
NC
AI
AO
NC
DO
AO
DI
DI
NC
AI
NC
AI
G
QI
AGC
OUT
DEC
AON
PDN
RFIP
RFIM
VSS
Function
Positive Power Supply
Positive Quartz Filter Output
Negative Quartz Filter Output
Note
1
2
Quartz Filter Input for Crystal
AGC Capacitor
Receiver Output
Demodulator Capacitor
AGC On Control
Power Down Input
Positive Receiver Input
Negative Receiver Input
Power Supply Ground
2
3
4
5
2
6
2
6
A = Analog, D = Digital, P = Power, G = Ground, I = Input, O = Output, NC = Not Connected
Notes:
1) QOM pin is electrically unconnected in MAS6180C1 version
2) Pin 4 between QOM and QI must be connected to IC’s filtered VDD (pin 1) to eliminate TSSOP package lead
frame parasitic capacitances disturbing the crystal filter performance and minimizing noise coupling. All other
NC (Not Connected) type pins are recommended to be connected to VSS.
3) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated)
- the output is a current source/sink with |IOUT| > 5 µA
- at power down the output is pulled to VSS (pull down switch)
4) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)
- Internal pull-up with current < 1 µA which is switched off at power down
5) PDN = VSS means receiver on; PDN = VDD means receiver off
- Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up
(PDN=VSS) i.e. at the falling edge of PDN signal.
6) Receiver inputs RFIP and RFIM have both 1.4 MΩ biasing resistors towards VDD
8 (12)
DA6180C.001
17 September, 2014
PACKAGE (TSSOP-16) OUTLINES
C
E
D
Seating Plane
B
F
G
H
A
O
Pin 1
B
Detail A
B
L
I
I1
K
P
Section B-B
J1
M
J
Dimension
N
Min
A
B
C
D
E
F
G
H
I
I1
J
J1
K
L
M
(The length of a terminal for
soldering to a substrate)
N
O
P
Detail A
Max
6.40 BSC
4.30
4.50
5.00 BSC
0.05
0.15
1.10
0.30
0.19
0.65 BSC
0.18
0.09
0.09
0.19
0.19
0°
0.24
0.50
0.28
0.20
0.16
0.30
0.25
8°
0.26
0.75
1.00 REF
12°
12°
Unit
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
Dimensions do not include mold flash, protrusions, or gate burrs.
All dimensions are in accordance with JEDEC standard MO-153.
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DA6180C.001
17 September, 2014
SOLDERING INFORMATION
◆ For Pb-Free, RoHS Compliant TSSOP-16
Resistance to Soldering Heat
Maximum Temperature
Maximum Number of Reflow Cycles
Reflow profile
According to RSH test IEC 68-2-58/20
260°C
3
Thermal profile parameters stated in IPC/JEDEC J-STD-020
should not be exceeded. http://www.jedec.org
max 0.08 mm
Solder plate 7.62 - 25.4 µm, material Matte Tin
Seating Plane Co-planarity
Lead Finish
EMBOSSED TAPE SPECIFICATIONS
Tape Feed Direction
P0
D0
P2
A
E1
F1
W
D1
A
A0
P
Tape Feed Direction
T
Section A - A
B0
S1
K0
Pin 1 Designator
Dimension
Min
Max
Unit
A0
B0
D0
D1
E1
F1
K0
P
P0
P2
S1
T
W
6.50
5.20
6.70
5.40
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
1.50 +0.10 / -0.00
1.50
1.65
7.20
1.20
11.90
1.85
7.30
1.40
12.10
4.0
1.95
0.6
0.25
11.70
2.05
0.35
12.30
10 (12)
DA6180C.001
17 September, 2014
REEL SPECIFICATIONS
W2
A
D
C
Tape Slot for Tape Start
N
B
W1
2000 Components on Each Reel
Reel Material: Conductive, Plastic Antistatic or Static Dissipative
Carrier Tape Material: Conductive
Cover Tape Material: Static Dissipative
Carrier Tape
Cover Tape
End
Start
Trailer
Dimension
A
B
C
D
N
W1
(measured at hub)
W2
(measured at hub)
Trailer
Leader
Weight
Leader
Components
Min
1.5
12.80
20.2
50
12.4
Max
Unit
330
14.4
mm
mm
mm
mm
mm
mm
18.4
mm
13.50
160
390,
of which minimum 160
mm of empty carrier tape
sealed with cover tape
mm
mm
1500
g
11 (12)
DA6180C.001
17 September, 2014
ORDERING INFORMATION
Product Code
Product
Description
Capacitance Option
MAS6180C1TC00
Single Band AM-Receiver IC
with Differential Input
CC = 0.75 pF
MAS6180C1UC06
Single Band AM-Receiver IC
with Differential Input
EWS-tested wafer,
diameter 8”,
thickness 395 µm ± 5%.
TSSOP-16, Pb-free, RoHS
compliant, Tape & Reel
CC = 0.75 pF
Contact Micro Analog Systems Oy for other wafer thickness options.
◆ The formation of product code
An example for MAS6180C1TC00:
MAS6180 C
1
Product
Design
Capacitance option:
name
version
CC = 0.75 pF
TC
Package type:
TC = 400 µm thick EWS tested wafer
00
Delivery format:
00 = undiced wafer
05 = dies on tray
06 = tape & reel
08 = in tube
LOCAL DISTRIBUTOR
MICRO ANALOG SYSTEMS OY CONTACTS
Micro Analog Systems Oy
Kutomotie 16
FI-00380 Helsinki, FINLAND
Tel. +358 10 835 1100
Fax +358 10 835 1109
http://www.mas-oy.com
NOTICE
Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or
performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits
shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no
claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and
Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or
modification.
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