Data Sheet

74AHC3GU04-Q100
Triple unbuffered inverter
Rev. 1 — 18 November 2013
Product data sheet
1. General description
The 74AHC3GU04-Q100 is a high-speed Si-gate CMOS device. This device provides
three inverter gates with unbuffered outputs.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +85 C and from 40 C to +125 C
 Symmetrical output impedance
 High noise immunity
 Low power dissipation
 Balanced propagation delays
 Multiple package options
 ESD protection:
 MIL-STD-883, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 )
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74AHC3GU04DP-Q100 40 C to +125 C
TSSOP8
plastic thin shrink small outline package; 8 leads; SOT505-2
body width 3 mm; lead length 0.5 mm
74AHC3GU04DC-Q100 40 C to +125 C
VSSOP8
plastic very thin shrink small outline package; 8
leads; body width 2.3 mm
SOT765-1
74AHC3GU04-Q100
NXP Semiconductors
Triple unbuffered inverter
4. Marking
Table 2.
Marking codes
Type number
Marking code[1]
74AHC3GU04DP-Q100
AU4
74AHC3GU04DC-Q100
AU4
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1
1A
1Y
1
1
7
3
1
5
6
1
2
7
3
2A
2Y
5
6
3A
3Y
2
A
mna721
mna720
Fig 1.
Logic symbol
Fig 2.
Y
mna045
IEC logic symbol
Fig 3.
Logic diagram (one gate)
6. Pinning information
6.1 Pinning
$+&*84
$
9&&
<
<
$
$
*1'
<
DDD
Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8)
74AHC3GU04_Q100
Product data sheet
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6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
1A, 2A, 3A
1, 3, 6
data input
GND
4
ground (0 V)
1Y, 2Y, 3Y
7, 5, 2
data output
VCC
8
supply voltage
7. Functional description
Table 4.
Function table
H = HIGH voltage level; L = LOW voltage level
Input
Output
A
Y
L
H
H
L
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
VI
Conditions
Min
Max
Unit
supply voltage
0.5
+7.0
V
input voltage
0.5
+7.0
V
20
-
mA
-
20
mA
input clamping current
VI < 0.5 V
[1]
IOK
output clamping current
VO < 0.5 V or VO > VCC + 0.5 V
[1]
0.5 V < VO < VCC + 0.5 V
IIK
IO
output current
-
25
mA
ICC
supply current
-
75
mA
IGND
ground current
75
-
mA
Tstg
storage temperature
65
+150
C
-
250
mW
total power dissipation
Ptot
[1]
[2]
Tamb = 40 C to +125 C
[2]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K.
74AHC3GU04_Q100
Product data sheet
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9. Recommended operating conditions
Table 6.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VCC
supply voltage
2.0
5.0
5.5
V
VI
input voltage
0
-
5.5
V
VO
output voltage
0
-
VCC
V
Tamb
ambient temperature
40
+25
+125
C
t/V
input transition rise and fall rate
VCC = 3.3 V  0.3 V
-
-
100
ns/V
VCC = 5.0 V  0.5 V
-
-
20
ns/V
10. Static characteristics
Table 7.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
25 C
Conditions
Min
VIH
VIL
VOH
VOL
HIGH-level
input voltage
Typ
40 C to +85 C
Max
Min
40 C to +125 C Unit
Max
Min
Max
VCC = 2.0 V
1.7
-
-
1.7
-
1.7
-
V
VCC = 3.0 V
2.4
-
-
2.4
-
2.4
-
V
VCC = 5.5 V
4.4
-
-
4.4
-
4.4
-
V
VCC = 2.0 V
-
-
0.3
-
0.3
-
0.3
V
VCC = 3.0 V
-
-
0.6
-
0.6
-
0.6
V
VCC = 5.5 V
-
-
1.1
-
1.1
-
1.1
V
HIGH-level
VI = VIH or VIL
output voltage
IO = 50 A; VCC = 2.0 V
1.9
2.0
-
1.9
-
1.9
-
V
IO = 50 A; VCC = 3.0 V
2.9
3.0
-
2.9
-
2.9
-
V
IO = 50 A; VCC = 4.5 V
4.4
4.5
-
4.4
-
4.4
-
V
IO = 4.0 mA; VCC = 3.0 V 2.58
-
-
2.48
-
2.40
-
V
IO = 8.0 mA; VCC = 4.5 V 3.94
-
-
3.8
-
3.70
-
V
LOW-level
input voltage
LOW-level
VI = VIH or VIL
output voltage
IO = 50 A; VCC = 2.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 50 A; VCC = 3.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 50 A; VCC = 4.5 V
-
0
0.1
-
0.1
-
0.1
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.36
-
0.44
-
0.55
V
IO = 8.0 mA; VCC = 4.5 V
-
-
0.36
-
0.44
-
0.55
V
- -
0.1
-
1.0
-
2.0
A
II
input leakage
current
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
- -
1.0
-
10
-
40
A
CI
input
capacitance
- 3.0
10
-
10
-
10
pF
74AHC3GU04_Q100
Product data sheet
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
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NXP Semiconductors
Triple unbuffered inverter
11. Dynamic characteristics
Table 8.
Dynamic characteristics
GND = 0 V; For test circuit, see Figure 6.
25 C
Symbol
Parameter
Conditions
tpd
propagation
delay
nA to nY; see Figure 5
[1]
VCC = 3.0 V to 3.6 V
[2]
Min
CL = 15 pF
CL = 50 pF
VCC = 4.5 V to 5.5 V
CL = 50 pF
power
dissipation
capacitance
[4]
per buffer;
VI = GND to VCC
[1]
tpd is the same as tPLH and tPHL.
[2]
Typical values are measured at VCC = 3.3 V.
Max
Min
Max
Min
Max
-
3.0
7.1
1.0
8.5
1.0
10.0
ns
-
4.3
10.6
1.0
12.0
1.0
13.5
ns
-
2.5
5.5
1.0
6.0
1.0
7.0
ns
-
3.5
7.0
1.0
8.0
1.0
9.0
ns
-
4
-
[3]
CL = 15 pF
CPD
Typ
40 C to +85 C 40 C to +125 C Unit
[3]
Typical values are measured at VCC = 5.0 V.
[4]
CPD is used to determine the dynamic power dissipation (PD in W).
-
-
-
-
pF
PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL  VCC2  fo) = sum of the outputs.
12. Waveforms
VI
VM
nA input
VM
GND
t PHL
t PLH
VOH
VM
nY output
VM
VOL
Fig 5.
mna344
The input (nA) to output (nY) propagation delays.
Table 9.
Measurement points
Type
74AHC3GU04-Q100
74AHC3GU04_Q100
Product data sheet
Input
Output
VM
VM
0.5VCC
0.5VCC
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Triple unbuffered inverter
VI
tW
90 %
negative
pulse
VM
0V
tf
tr
tr
tf
VI
90 %
positive
pulse
0V
VM
10 %
VM
VM
10 %
tW
VCC
VCC
G
VI
VO
RL
S1
open
DUT
CL
RT
001aad983
Test data is given in Table 10.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 6.
Test circuit for measuring switching times
Table 10.
Test data
Type
74AHC3GU04-Q100
74AHC3GU04_Q100
Product data sheet
Input
Load
S1 position
VI
tr, tf
CL
RL
tPHL, tPLH
tPZH, tPHZ
tPZL, tPLZ
VCC
 3 ns
15 pF, 50 pF
1 k
open
GND
VCC
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Triple unbuffered inverter
13. Typical transfer characteristics
mna397
2.0
VO
(V)
1.6
VO
mna398
1.0
3.0
ICC
(mA)
0.8
VO
(V)
1.2
0.6
0.8
0.4
10
VO
ICC
(mA)
8
6
1.5
4
ID (drain current)
0.4
0.2
ID (drain current)
0
2
0
0
0
0.4
0.8
1.2
1.6
0
0
2.0
1
2
VI (V)
Fig 7.
VCC = 2.0 V; IO = 0 A
Fig 8.
3
VI (V)
VCC = 3.0 V; IO = 0 A
mna399
6
50
VO
(V)
ICC
(mA)
40
VO
30
Rbias = 560 kΩ
3
20
VCC
ID (drain current)
10
0
0
0
Fig 9.
2
VCC = 5.5 V; IO = 0 A
74AHC3GU04_Q100
Product data sheet
4
VI (V)
0.47 μF
VI
(f = 1 kHz)
6
input
output
100 μF
A IO
GND
mna050
Fig 10. Test set-up for measuring forward
transconductance gfs = IO/VI at VO is
constant
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74AHC3GU04-Q100
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Triple unbuffered inverter
mna400
40
gfs
(mA/V)
30
20
10
0
0
2
4
VCC (V)
6
Fig 11. Typical forward transconductance gfs as a function of the supply voltage at Tamb = 25 C
14. Application information
Some applications are:
• Linear amplifier (see Figure 12)
• Crystal oscillator design (see Figure 13)
Remark: All values given are typical unless otherwise specified.
R2
R1
VCC
1 μF
R2
R1
U04
U04
C1
ZL
C2
out
mna053
mna052
Maximum Vo(p-p) = VCC  1.5 V centered at 0.5  VCC.
C1 = 47 pF (typ.)
G ol
G v = – --------------------------------------R1
1 + -------  1 + G ol 
R2
C2 = 22 pF (typ.)
R1 = 1 M to 10 M (typ.)
R2 optimum value depends on the frequency and
required stability against changes in VCC or average
minimum ICC (ICC is typically 2 mA at VCC = 3 V and
f = 1 MHz).
Gol = open loop gain
Gv = voltage gain
R1  3 k, R2  1 M
ZL > 10 k; Gol = 20 (typ.)
Typical unity gain bandwidth product is 5 MHz.
Fig 12. Used as a linear amplifier
74AHC3GU04_Q100
Product data sheet
Fig 13. Crystal oscillator configuration
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Triple unbuffered inverter
Table 11. External components for resonator (f < 1 MHz)
All values given are typical and must be used as an initial set-up.
Frequency
R1
R2
C1
C2
10 kHz to 15.9 kHz
22 M
220 k
56 pF
20 pF
16 kHz to 24.9 kHz
22 M
220 k
56 pF
10 pF
25 kHz to 54.9 kHz
22 M
100 k
56 pF
10 pF
55 kHz to 129.9 kHz
22 M
100 k
47 pF
5 pF
130 kHz to 199.9 kHz
22 M
47 k
47 pF
5 pF
200 kHz to 349.9 kHz
22 M
47 k
47 pF
5 pF
350 kHz to 600 kHz
22 M
47 k
47 pF
5 pF
Table 12.
Optimum value for R2
Frequency
R2
Optimum for
3 kHz
2.0 k
minimum required ICC
8.0 k
minimum influence due to change in VCC
1.0 k
minimum required ICC
4.7 k
minimum influence by VCC
0.5 k
minimum required ICC
2.0 k
minimum influence by VCC
6 kHz
10 kHz
14 kHz
>14 kHz
74AHC3GU04_Q100
Product data sheet
0.5 k
minimum required ICC
1.0 k
minimum influence by VCC
-
replace R2 by C3 with a typical value of 35 pF
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Triple unbuffered inverter
15. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
D
E
A
SOT505-2
X
c
HE
y
v M A
Z
5
8
A
A2
(A3)
A1
pin 1 index
θ
Lp
L
1
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(1)
e
HE
L
Lp
v
w
y
Z(1)
θ
mm
1.1
0.15
0.00
0.95
0.75
0.25
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
0.65
4.1
3.9
0.5
0.47
0.33
0.2
0.13
0.1
0.70
0.35
8°
0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT505-2
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
02-01-16
---
Fig 14. Package outline SOT505-2 (TSSOP8)
74AHC3GU04_Q100
Product data sheet
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Triple unbuffered inverter
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
D
E
SOT765-1
A
X
c
y
HE
v M A
Z
5
8
Q
A
A2
A1
pin 1 index
(A3)
θ
Lp
1
4
e
L
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(2)
e
HE
L
Lp
Q
v
w
y
Z(1)
θ
mm
1
0.15
0.00
0.85
0.60
0.12
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
0.5
3.2
3.0
0.4
0.40
0.15
0.21
0.19
0.2
0.13
0.1
0.4
0.1
8°
0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT765-1
REFERENCES
IEC
JEDEC
JEITA
MO-187
EUROPEAN
PROJECTION
ISSUE DATE
02-06-07
Fig 15. Package outline SOT765-1 (VSSOP8)
74AHC3GU04_Q100
Product data sheet
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16. Abbreviations
Table 13.
Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MIL
Military
MM
Machine Model
17. Revision history
Table 14.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74AHC3GU04_Q100 v.1
20131118
Product data sheet
-
-
74AHC3GU04_Q100
Product data sheet
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18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
Definition
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74AHC3GU04_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 18 November 2013
© NXP B.V. 2013. All rights reserved.
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NXP Semiconductors
Triple unbuffered inverter
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74AHC3GU04_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 18 November 2013
© NXP B.V. 2013. All rights reserved.
14 of 15
74AHC3GU04-Q100
NXP Semiconductors
Triple unbuffered inverter
20. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
17
18
18.1
18.2
18.3
18.4
19
20
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typical transfer characteristics . . . . . . . . . . . . 7
Application information. . . . . . . . . . . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 18 November 2013
Document identifier: 74AHC3GU04_Q100