Data Sheet

74CBTLVD3245-Q100
8-bit level-shifting bus switch with output enable
Rev. 2 — 22 January 2016
Product data sheet
1. General description
The 74CBTLVD3245-Q100 is an 8-pole, single-throw bus switch. The device features a
single output enable input (OE) that controls eight switch channels. The switches are
disabled when OE is HIGH. Schmitt trigger action at control inputs makes the circuit
tolerant of slower input rise and fall times. This device is fully specified for partial
power-down applications using IOFF. The IOFF circuitry disables the output, preventing the
damaging backflow current through the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +85 C and from 40 C to +125 C
 Supply voltage range from 3.0 V to 3.6 V
 High noise immunity
 Complies with JEDEC standard:
 JESD8-B/JESD36 (3.0 V to 3.6 V)
 ESD protection:
 MIL-STD-883, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 CDM AEC-Q100-011 revision B exceeds 1000 V
 5  switch connection between two ports
 Rail to rail switching on data I/O ports
 CMOS low power consumption
 Latch-up performance exceeds 250 mA per JESD78B Class I level A
 IOFF circuitry provides partial Power-down mode operation
 Multiple package options
74CBTLVD3245-Q100
NXP Semiconductors
8-bit level-shifting bus switch with output enable
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature
range
Name
74CBTLVD3245PW-Q100 40 C to +125 C TSSOP20
Description
Version
plastic thin shrink small outline package; 20
leads; body width 4.4 mm
SOT360-1
74CBTLVD3245BQ-Q100 40 C to +125 C DHVQFN20 plastic dual-in-line compatible thermal enhanced
very thin quad flat package; no leads; 20
terminals; body 2.5  4.5  0.85 mm
[1]
SOT764-1
Also known as QSOP20 package
4. Functional diagram
OE
19
A1
A2
A3
A4
A5
A6
A7
A8
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
B1
B2
B3
B4
B5
B6
B7
B8
001aao116
Fig 1.
Logic symbol
A1
2
18
9
11
A8
OE
Fig 2.
B1
B8
19
001aao117
Logic diagram
74CBTLVD3245_Q100
Product data sheet
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Rev. 2 — 22 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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74CBTLVD3245-Q100
NXP Semiconductors
8-bit level-shifting bus switch with output enable
5. Pinning information
5.1 Pinning
QF
WHUPLQDO
LQGH[DUHD
&%7/9'4
QF
$
9&&
&%7/9'4
$
2(
$
%
9&&
2(
$
%
%
$
%
$
$
%
$
%
$
%
$
%
$
%
$
$
%
$
%
$
$
%
*1' %
*1'
%
% *1' %
DDD
7UDQVSDUHQWWRSYLHZ
DDD
(1) This is not a supply pin, the substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad
however if it is soldered the solder land should remain
floating or be connected to GND.
Fig 3.
Pin configuration for TSSOP20 (SOT360-1)
Fig 4.
Pin configuration for DHVQFN20 (SOT764-1)
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
n.c.
1
not connected
A1 to A8
2, 3, 4, 5, 6, 7, 8, 9
data input/output (A port)
GND
10
ground (0 V)
B1 to B8
18, 17, 16, 15, 14, 13, 12, 11
data input/output (B port)
OE
19
output enable input (active LOW)
VCC
20
positive supply voltage
6. Functional description
Table 3.
Function selection[1]
Input
Input/output
OE
An, Bn
L
An = Bn
H
Z
[1]
H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
74CBTLVD3245_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 22 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
3 of 18
74CBTLVD3245-Q100
NXP Semiconductors
8-bit level-shifting bus switch with output enable
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
VCC
supply voltage
VI
input voltage
VSW
switch voltage
enable and disable mode
IIK
input clamping current
ISK
ISW
ICC
Min
Max
Unit
0.5
+4.6
V
[1]
0.5
+4.6
V
[1]
0.5
VCC + 0.5
V
VI/O < 0.5 V
50
-
switch clamping current
VI < 0.5 V
50
-
mA
switch current
VSW = 0 V to VCC
-
128
mA
supply current
-
+100
mA
IGND
ground current
100
-
mA
Tstg
storage temperature
65
+150
C
Ptot
total power dissipation
-
500
mW
[1]
[2]
Tamb = 40 C to +125 C
[2]
mA
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For TSSOP20 packages: above 60 C the value of Ptot derates linearly at 5.5 mW/K.
For DHVQFN20 packages: above 60 C the value of Ptot derates linearly at 4.5 mW/K.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
VCC
supply voltage
VI
input voltage
VSW
switch voltage
Tamb
ambient temperature
t/V
[1]
Conditions
Min
enable and disable mode
input transition rise and fall rate
VCC = 3.0 V to 3.6 V
[1]
Max
Unit
3.0
3.6
V
0
3.6
V
0
VCC
V
40
+125
C
0
200
ns/V
Applies to control signal levels.
74CBTLVD3245_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 22 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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74CBTLVD3245-Q100
NXP Semiconductors
8-bit level-shifting bus switch with output enable
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit
Conditions
Min
Typ[1]
Max
Min
Max
VIH
HIGH-level
input voltage
VCC = 3.0 V to 3.6 V
2.0
-
-
2.0
-
V
VIL
LOW-level
input voltage
VCC = 3.0 V to 3.6 V
-
-
0.9
-
0.9
V
II
input leakage
current
pin OE; VI = GND to VCC;
VCC = 3.6 V
-
-
1
-
20
A
Vpass
pass voltage
VI = VCC; see Figure 7 to
Figure 11
-
-
-
-
-
V
IS(OFF)
OFF-state
VCC = 3.6 V; see Figure 5
leakage current
-
-
1
-
20
A
IS(ON)
ON-state
VCC = 3.6 V; see Figure 6
leakage current
-
-
1
-
20
A
IOFF
power-off
VI or VO = 0 V to 3.6 V;
leakage current VCC = 0 V
-
-
10
-
50
A
ICC
supply current
VI = VCC; IO = 0 A; VCC = 3.6 V;
VSW = GND or VCC
-
-
20
-
50
A
VI = GND; IO = 0 A;
VCC = 3.6 V;
VSW = GND or VCC
-
-
100
-
150
A
-
-
300
-
2000
A
ICC
additional
supply current
pin OE; VI = VCC  0.6 V;
VSW = GND or VCC;
VCC = 3.6 V
CI
input
capacitance
pin OE; VCC = 3.3 V;
VI = 0 V to 3.3 V
-
0.9
-
-
-
pF
CS(OFF)
OFF-state
capacitance
VCC = 3.3 V; VI = 0 V to 3.3 V
-
2.5
-
-
-
pF
CS(ON)
ON-state
capacitance
VCC = 3.3 V; VI = 0 V to 3.3 V
-
9.0
-
-
-
pF
[1]
All typical values are measured at Tamb = 25 C.
[2]
One input at 3 V, other inputs at VCC or GND.
74CBTLVD3245_Q100
Product data sheet
[2]
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 22 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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74CBTLVD3245-Q100
NXP Semiconductors
8-bit level-shifting bus switch with output enable
9.1 Test circuits
VCC
VCC
OE
VIH
A
Bn
An
Is
Is
A
A
GND
VI
OE
VIL
Is
VO
An
Bn
GND
VI
001aan147
001aan148
VI = VCC or GND and VO = GND or VCC.
Fig 5.
VO
VI = VCC or GND and VO = open circuit.
Test circuit for measuring OFF-state leakage
current (one switch)
Fig 6.
Test circuit for measuring ON-state leakage
current (one switch)
9.2 Typical pass voltage graphs
001aam102
1.90
Vpass
(V)
1.85
20 μA
1.90
Vpass
(V)
1.85
1.80
100 μA
1.80
001aam103
20 μA
100 μA
1.75
1.75
1.70
1.70
2 mA
1.65
4 mA
2 mA
1.65
4 mA
1.60
1.55
3.0
3.2
1.60
3.4
3.6
1.55
3.0
VCC (V)
Fig 7.
Pass voltage versus supply voltage;
Tamb = 125 C (typical)
74CBTLVD3245_Q100
Product data sheet
3.2
3.4
3.6
VCC (V)
Fig 8.
Pass voltage versus supply voltage;
Tamb = 85 C (typical)
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74CBTLVD3245-Q100
NXP Semiconductors
8-bit level-shifting bus switch with output enable
001aam104
1.90
Vpass
(V)
1.85
20 μA
1.90
Vpass
(V)
1.85
1.80
100 μA
1.80
001aam105
20 μA
100 μA
1.75
1.75
1.70
1.70
2 mA
2 mA
4 mA
1.65
1.65
1.60
4 mA
1.60
1.55
3.0
3.2
3.4
1.55
3.0
3.6
3.2
VCC (V)
Fig 9.
3.4
3.6
VCC (V)
Fig 10. Pass voltage versus supply voltage;
Tamb = 0 C (typical)
Pass voltage versus supply voltage;
Tamb = 25 C (typical)
001aam106
1.90
Vpass
(V)
1.85
1.80
20 μA
1.75
100 μA
1.70
1.65
2 mA
4 mA
1.60
1.55
3.0
3.2
3.4
3.6
VCC (V)
Fig 11. Pass voltage versus supply voltage; Tamb = 40 C (typical)
74CBTLVD3245_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 22 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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74CBTLVD3245-Q100
NXP Semiconductors
8-bit level-shifting bus switch with output enable
9.3 ON resistance
Table 7.
Resistance RON
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12.
Symbol Parameter
RON
Tamb = 40 C to +85 C
Conditions
Tamb = 40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
ISW = 64 mA; VI = 0 V
-
3.7
7.0
-
10.0

ISW = 24 mA; VI = 0 V
-
3.7
7.0
-
10.0

ISW = 15 mA; VI = 1.2 V
-
4.7
10.0
-
12.0

ON resistance VCC = 3.0 V to 3.6 V[2]
[1]
Typical values are measured at Tamb = 25 C and nominal VCC.
[2]
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is
determined by the lower of the voltages of the two (A or B) terminals.
9.4 ON resistance test circuit
VSW
V
VCC
OE
VIL
An
VI
Bn
GND
ISW
001aan149
RON = VSW / ISW.
Fig 12. Test circuit for measuring ON resistance (one switch)
74CBTLVD3245_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 22 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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74CBTLVD3245-Q100
NXP Semiconductors
8-bit level-shifting bus switch with output enable
10. Dynamic characteristics
Table 8.
Dynamic characteristics
GND = 0 V; for test circuit see Figure 15
Symbol Parameter
Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit
Conditions
VCC = 3.0 V to 3.6 V
enable time
ten
disable time
Max
Min
Max
-
-
0.11
-
0.22
ns
1.5
2.9
5.0
1.5
6.0
ns
0.8
3.4
7.0
0.8
8.0
ns
[4]
OE to An or Bn;
see Figure 14
VCC = 3.0 V to 3.6 V
tdis
Typ[1]
[2][3]
propagation delay An to Bn or Bn to An;
see Figure 13
tpd
Min
[5]
OE to An or Bn;
see Figure 14
VCC = 3.0 V to 3.6 V
[1]
All typical values are measured at Tamb = 25 C and at nominal VCC.
[2]
The propagation delay is the calculated RC time constant of the on-state resistance of the switch and the load capacitance, when driven
by an ideal voltage source (zero output impedance).
[3]
tpd is the same as tPLH and tPHL.
[4]
ten is the same as tPZH and tPZL.
[5]
tdis is the same as tPHZ and tPLZ.
11. Waveforms
9,
LQSXW
90
90
9
W3+/
W3/+
92+
RXWSXW
90
90
92/
DDL
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 13. The data input (An, Bn) to output (Bn, An) propagation delay times
Table 9.
Measurement points
Supply voltage
Input
VCC
VM
VI
tr = tf
VM
VX
VY
3.0 V to 3.6 V
0.5VCC
VCC
 2.0 ns
0.9 V
VOL + 0.15 V
VOH  0.15 V
74CBTLVD3245_Q100
Product data sheet
Output
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 22 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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74CBTLVD3245-Q100
NXP Semiconductors
8-bit level-shifting bus switch with output enable
9,
2(LQSXW
90
90
*1'
W3/=
W3=/
9
RXWSXW
/2:WR2))
2))WR/2:
90
9;
92/
W3=+
W3+=
92+
9<
RXWSXW
+,*+WR2))
2))WR+,*+
90
*1'
VZLWFK
HQDEOHG
VZLWFK
GLVDEOHG
VZLWFK
HQDEOHG
DDD
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 14. Enable and disable times
74CBTLVD3245_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 22 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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74CBTLVD3245-Q100
NXP Semiconductors
8-bit level-shifting bus switch with output enable
9,
W:
QHJDWLYH
SXOVH
90
9
WI
WU
WU
WI
9,
SRVLWLYH
SXOVH
9
90
90
90
W:
9(;7
9&&
9,
*
5/
92
'87
57
5/
&/
DDH
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 15. Test circuit for measuring switching times
Table 10.
Test data
Supply voltage
Load
VCC
CL
RL
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
3.0 V to 3.6 V
30 pF
1 k
open
GND
3.6 V
74CBTLVD3245_Q100
Product data sheet
VEXT
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 22 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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74CBTLVD3245-Q100
NXP Semiconductors
8-bit level-shifting bus switch with output enable
11.1 Additional dynamic characteristics
Table 11. Additional dynamic characteristics
GND = 0 V.
Symbol Parameter
f(3dB)
[1]
3 dB frequency response
Tamb = 25 C
Conditions
VCC = 3.3 V; RL = 50 ; see Figure 16
Unit
Min
Typ
Max
-
575
-
[1]
MHz
fi is biased at 0.5VCC.
11.2 Test circuit
VCC
0.5VCC
OE
VIL
RL
Bn
fi
An
GND
dB
001aan156
Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads 3 dB.
Fig 16. Test circuit for measuring the frequency response when channel is in ON-state
74CBTLVD3245_Q100
Product data sheet
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Rev. 2 — 22 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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74CBTLVD3245-Q100
NXP Semiconductors
8-bit level-shifting bus switch with output enable
12. Package outline
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Fig 17. Package outline SOT360-1 (TSSOP20)
74CBTLVD3245_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 22 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
13 of 18
74CBTLVD3245-Q100
NXP Semiconductors
8-bit level-shifting bus switch with output enable
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Fig 18. Package outline SOT764-1 (DHVQFN20)
74CBTLVD3245_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 22 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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NXP Semiconductors
8-bit level-shifting bus switch with output enable
13. Abbreviations
Table 12.
Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MIL
Military
14. Revision history
Table 13.
Revision history
Document ID
Release date
74CBTLVD3245_Q100 v.2 20160122
Modifications:
•
Product data sheet
Change notice
Supersedes
-
74CBTLVD3245_Q100 v.1
-
-
Figure 14 updated.
74CBTLVD3245_Q100 v.1 20151016
74CBTLVD3245_Q100
Data sheet status
Product data sheet
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 22 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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74CBTLVD3245-Q100
NXP Semiconductors
8-bit level-shifting bus switch with output enable
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74CBTLVD3245_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 22 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
16 of 18
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No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74CBTLVD3245_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 22 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
17 of 18
NXP Semiconductors
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17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
9.1
9.2
9.3
9.4
10
11
11.1
11.2
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical pass voltage graphs . . . . . . . . . . . . . . . 6
ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ON resistance test circuit . . . . . . . . . . . . . . . . . 8
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Additional dynamic characteristics . . . . . . . . . 12
Test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Contact information. . . . . . . . . . . . . . . . . . . . . 17
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2016.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 22 January 2016
Document identifier: 74CBTLVD3245_Q100