Application Note: SLA7070M Series Motor Driver ICs

Application Note
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PRODUCT
DESCRIPTION
Series SLA7070M
Motor Driver ICs
INTRODUCTION
This document describes the function and features of
SLA7070M series, which are unipolar 2-phase stepping motor
driver ICs. This document contains preliminary information on
the products under development. Should you have any questions, including information on options, contact your nearest
sales or representative office.
 Synchronous PWM chopping function prevents motor noise
in Hold mode
 Sleep mode for reducing the IC input current in stand-by state
 Built-in protection circuitry against motor coil opens/shorts
option available (NEW, patent pending)
Features
 Power supply voltages, VBB : 46 V(max.), 10 to 44 V normal
operating range
 Logic supply voltages, VDD: 3.0 to 5.5 V
 Maximum output currents: 1 A, 1.5 A, 2 A, 3 A
 Built-in sequencer
 Simplified clock-in stepping control
 Both full/half-stepping, and microstepping versions;
microstepping versions (SLA7075M, -76M, -77M, -78M)
are capable of full-, half-, quarter-, eighth-, and sixteenthstepping
 Built-in sense resistor, RSInt (NEW)
 All variants are pin-compatible for enhanced design flexibility
 ZIP type 23-pin molded package (SLA package)
 Self-excitation PWM current control with fixed off-time
For microstepping parts, off-time adjusted automatically by
step reference current ratio (3 levels)
 Built-in synchronous rectifying circuit reduces losses at PWM
off (NEW)
Contents
Introduction
Part Numbers and Options
Specifications
Reference Voltage Setting
Allowable Power Dissipation
Package Outline Drawing, SLA-23 Pin
Functional Block Diagram and Pin Assignments
Application Example for Microstepping Products
Truth Tables
Logic Input Pins
Step Sequencing
Individual Circuit Description
Functional Description
Application Information
Thermal Design Information
Characteristic Data
All performance characteristics given are typical values for
circuit or system baseline design only and are at the nominal
operating voltage and an ambient temperature of +25°C, unless
otherwise stated.
Sanken Power Devices
from Allegro MicroSystems
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Series SLA7070M
Motor Driver ICs
or s
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PART NUMBERS AND OPTIONS
The following are the product variants and optional features
available in the SLA7070M series.
NOTE
The following abbreviations are used throughout this
document to refer to product variants:
PR – Product with both Protection Circuitry and
built-in RSInt options
R – Product with the built-in RSInt option
Not all combinations of standard models and product options are
available in high-volume production quantities. For information
on product availability, and assistance with determining the IC
features that are the best fit for your application, please contact
our sales office or representative.
Part Number
2
Protection
SLA7070MR
RSInt
SLA7070MPR
Protection Circuitry and RSInt
SLA7071MR
RSInt
SLA7071MPR
Protection Circuitry and RSInt
SLA7072MR
RSInt
SLA7072MPR
Protection Circuitry and RSInt
SLA7073MR
RSInt
SLA7073MPR
Protection Circuitry and RSInt
SLA7075MR
RSInt
SLA7075MPR
Protection Circuitry and RSInt
SLA7076MR
RSInt
SLA7076MPR
Protection Circuitry and RSInt
SLA7077MR
RSInt
SLA7077MPR
Protection Circuitry and RSInt
SLA7078MR
RSInt
SLA7078MPR
Protection Circuitry and RSInt
Output Current, IOUT
(A)
Sequencer
Blanking Time
(µs)
Full/half Step
3.2
Clock Edge
1
1.5
2
3
Positive
1
1.5
Microstep
2
3
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Series SLA7070M
Motor Driver ICs
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS, valid at TA = 25°C, applicable to both PR and R products, unless otherwise specified
Characteristics
Symbol
Remarks
Ratings
Units
Load (Motor) Supply Voltage
VM
46
V
Main Power Supply Voltage
VBB
46
V
Logic Supply Voltage
VDD
7
V
SLA7070M and SLA7075M
1.0
A
SLA7071M and SLA7076M
1.5
A
SLA7072M and SLA7077M
2.0
A
Output Current
IOUT
3.0
A
Logic Input Voltage
VIN
–0.3 to VDD+0.3
V
REF Input Voltage
VREF
–0.3 to VDD+0.3
V
Sense Voltage
VSInt
SLA7073M and SLA7078M
Power Dissipation
PD
tw < 1 µs is not considered
±2
V
Without heat sink
4.7
W
Junction Temperature
TJ
150
°C
Ambient Temperature
TA
–20 to 85
°C
Storage Temperature
Tstg
–30 to 150
°C
RECOMMENDED OPERATING RANGES, applicable to both PR and R products, unless otherwise specified
Min
Max
Units
Load (Motor) Supply Voltage
Characteristics
VM
–
44
V
Main Power Supply Voltage
VBB
10
44
V
Logic Supply Voltage
VDD
Surge voltage at VDD pin should be less
than ±0.5 V to avoid malfunctioning in
operation
3.0
5.5
V
Case Temperature
TC
Measured at pin 12, without heat sink
–
90
°C
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Symbol
Remarks
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Series SLA7070M
Motor Driver ICs
ELECTRICAL CHARACTERISTICS, valid at TA = 25°C, VBB = 24 V, VDD = 5 V, applicable to both PR and R products, unless
otherwise specified
Characteristics
Main Power Supply Current
Logic Power Current
MOSFET Breakdown Voltage
Maximum Response Frequency
Logic Supply Voltage
Logic Supply Current
REF Input Voltage
REF Input Current
SENSE Voltage
Sleep-Enable Recovery Time
Switching Time
4
Symbol
Test Conditions
Min.
Typ.
Max.
Units
mA
IBB
Normal mode
–
–
15
IBBS
Sleep1 and Sleep2 modes
–
–
100
µA
–
–
5
mA
IDD
VDSS
fclk
VBB = 44 V, IDS = 1 mA
Clock Duty Cycle = 50%
–
–
–
V
250
–
–
kHz
VIL
–
–
0.25 × VDD
V
VIH
0.75 × VDD
–
–
V
IIL
–
±1
–
µA
IIH
–
±1
–
µA
–
–
–
V
2.0
–
VDD
V
–
±10
–
µA
VREF – 0.03
VREF
VREF + 0.03
V
VREF
See pages 6 and 7
VREFS
Output OFF, Sleep1 mode, IBBS in specification,
sequencer = enable
IREF
VSInt
VREF = 0.1 V to 0.5 V, Step reference current
ratio: 100%
tSE
VREF = 2.0 V → 1.5 V
100
–
–
µs
tcon
Clock → Output ON
–
2.0
–
µs
tcoff
Clock → Output OFF
–
1.5
–
µs
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STEPPING CHARACTERISTICS, applicable to both PR and R products; representative values from SLA7070M series shown
Valid at TA = 25°C, VBB = 24 V, VDD = 5 V, unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Units
–
100
–
%
Full/half step products, SLA7070M, SLA7071M, SLA7072M, and SLA7073M
Step Reference Current Ratio
PWM Minimum On-Time
PWM Off-Time
Mode F
Mode 8
VREF ≈ VSInt = 100 %, VREF = 0.1 to 0.5 V
–
70
–
%
ton(min)
–
3.2
–
µs
toff
–
12
–
µs
Microstepping products, SLA7075M to SLA7078M
Step Reference Current Ratio
Mode F
–
100
–
%
Mode E
–
98.1
–
%
Mode D
–
95.7
–
%
Mode C
–
92.4
–
%
Mode B
–
88.2
–
%
Mode A
–
83.1
–
%
Mode 9
–
77.3
–
%
Mode 8
–
70.7
–
%
Mode 7
VREF ≈ VSInt = 100 %, VREF = 0.1 to 0.5 V
–
63.4
–
%
Mode 6
–
55.5
–
%
Mode 5
–
47.1
–
%
Mode 4
–
38.2
–
%
Mode 3
–
29
–
%
Mode 2
–
19.5
–
%
–
9.8
–
%
–
–
1.25
V
Mode 1
Mo (Load) Output Voltage
Mo (Load) Output Current
PWM Minimum On-Time
PWM Off-Time
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VMOL
IMOL = 1.25 mA
VMOH
IMOH = –1.25 mA
VDD – 1.25
–
–
V
IMOL
–
–
1.25
mA
IMOH
–1.25
–
–
mA
ton(min)
–
1.7
–
µs
toff1
Mode 8 to Mode F
–
12
–
µs
toff2
Mode 4 to Mode 7
–
9
–
µs
toff3
Mode 1 to Mode 3
–
7
–
µs
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Motor Driver ICs
OUTPUT CHARACTERISTICS for both PR and R products
Valid at TA = 25°C, VBB = 24 V, VDD = 5 V, unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Units
IDS = 1 A
–
0.7
0.85
Ω
If = 1 A
–
0.85
1.1
V
IDS = 1.5 A
–
0.45
0.6
Ω
If = 1.5 A
–
1.0
1.25
V
IDS = 2 A
–
0.25
0.4
Ω
If = 2 A
–
0.95
1.2
V
IDS = 3 A
–
0.18
0.24
Ω
If = 3 A
–
0.95
2.1
V
Min.
Typ.
Max.
Units
0.296
0.305
0.314
Ω
0.1
–
0.3
V
0.296
0.305
0.314
Ω
0.1
–
0.45
V
0.199
0.205
0.211
Ω
0.1
–
0.4
V
0.150
0.155
0.160
Ω
0.1
–
0.45
V
IOUT = 1.0 A (SLA7070M and SLA7075M)
Output On Resistance
Body Diode Forward Voltage
RDS(ON)
Vf
IOUT = 1.5 A (SLA7071M and SLA7076M)
Output On Resistance
Body Diode Forward Voltage
RDS(ON)
Vf
IOUT = 2.0 A (SLA7072M and SLA7077M)
Output On Resistance
Body Diode Forward Voltage
RDS(ON)
Vf
IOUT = 3.0 A (SLA7073M and SLA7078M)
Output On Resistance
Body Diode Forward Voltage
RDS(ON)
Vf
BUILT-IN SENSE RESISTOR CHARACTERISTICS for PR and R products
Valid at TA = 25°C, VBB = 24 V, VDD = 5 V, unless otherwise specified
Characteristics
Symbol
Test Conditions
IOUT = 1.0 A (SLA7070MPR, SLA7070MR, SLA7075MPR, and SLA7075MR)
Sense Resistor Rating*
RSInt
Tolerance: ±3 %
REF Input Voltage
VREF
Within specified current limit
IOUT = 1.5 A (SLA7071MPR, SLA7071MR, SLA7076MPR, and SLA7076MR)
Sense Resistor Rating*
RSInt
Tolerance: ±3 %
REF Input Voltage
VREF
Within specified current limit
IOUT = 2.0 A (SLA7072MPR, SLA7072MR, SLA7077MPR, and SLA7077MR)
Sense Resistor Rating*
RSInt
Tolerance: ±3 %
REF Input Voltage
VREF
Within specified current limit
IOUT = 3.0 A (SLA7073MPR, SLA7073MR, SLA7078MPR, and SLA7078MR)
Sense Resistor Rating*
RSInt
Tolerance: ±3 %
REF Input Voltage
VREF
Within specified current limit
*RSInt includes approximately 5 mΩ circuit resistance in addition to the resistance of the resistor itself.
6
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Motor Driver ICs
PROTECTION CIRCUIT CHARACTERISTICS*
Valid at TA = 25°C, VBB = 24 V, VDD = 5 V, unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Units
0.65
0.7
0.75
V
PR products
Overcurrent Sense Voltage
FLAG Output Voltage
FLAG Output Current
VOCP
Motor coils shorted
VFlagL
IFLAGL = 1.25 mA
VFlagH
IFLAGH = –1.25 mA
–
–
1.25
V
VDD – 1.25
–
–
V
IFlagL
–
–
1.25
mA
IFlagH
–1.25
–
–
mA
*Protection circuits work on the condition of VSInt ≥ VOCP.
REFERENCE VOLTAGE SETTING
VREF (REF/SLEEP1 Pin)
PR and R Products
VDD
VREF
Sleep1 Set Range
2.0 V
Prohibition Zone
VOCP
0.7 V
0.45 V
0.4 V
0.3 V
PR products only
Motor Current Set Range
0V
1.0 A
Devices
2.0 A
Devices
1.5, 3.0 A
Devices
Motor Current Set Range is determined by the built-in resistor value, RSInt. For PR products, pay extra
attention to the change-over between the motor current specification range, IMO, and the Sleep1 Set Range.
VOCP falls on the "prohibition zone" threshold. If the change-over time is too slow, OCP operation would
start when VSInt > VOCP .
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Allowable Power Dissipation, PD (W)
Series SLA7070M
Motor Driver ICs
θj-a= 33.8℃/W
3
2
1
0
0
10
20
30
40
50
60
70
ALLOWABLE POWER DISSIPATION
80
90
Ambient Temperature, TA (°C)
PR and R Products
Allowable Power Dissipation, PD (W)
5
4
θj-a= 26.6℃/W
3
2
1
0
0
10
20
30
40
50
60
70
Ambient Temperature, TA (°C)
8
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PACKAGE OUTLINE DRAWING, SLA-23 PIN
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Series SLA7070M
Motor Driver ICs
FUNCTIONAL BLOCK DIAGRAM AND PIN ASSIGNMENTS
Full/half step products: SLA7070MPR, SLA7071MPR, SLA7072MPR, and SLA7073MPR
PreDriver
PreDriver
Sequencer
&
Sleep Circuit
Protect
Protect
DAC
SenseA
20 21 22 23
Reg.
MIC
+
Comp
-
5
OutB
11
OutB
9 16 10 15
OutB
8
OutB
7
VBB
Clock
Reset
M3
6
F/R
18
M2
13
M1
14
N.C.
OutA
4
Flag
OutA
3
Ref/Sleep1
OutA
2
VDD
OutA
1
OSC
RSInt
DAC
Synchro
Control
PWM
Control
17
Sync
+
Comp
-
PWM
Control
OSC
19
SenseB
RSInt
12
Gnd
For R products, protection circuits not built-in. FLAG pin is not connected internally.
Pin No.
1
2
3
4
Symbol
OutA
OutA
Functions
Output of phase A
Output of phase Ā
Pin No.
Symbol
Functions
13
Ref / Sleep1
Input for control current and Sleep 1 setting
14
VDD
Power supply to logic
15
Reset
Reset for internal logic
16
F/R
Forward / reverse switch input
Phase A current sensing
17
Sync
Synchronous PWM control switch input
No internal connection
18
Flag*
Output from protection circuits monitor
19
SenseB
5
SenseA
6
NC
7
M1
8
M2
9
M3
10
Clock
Step clock input
11
VBB
Main power supply (for motor)
12
GND
Ground
Commutation and Sleep2 setting
20
21
OutB
Output of phase B̄
OutB
Output of phase B
22
23
*Flag pin active on PR products only; not internally connected for R products.
10
Phase B current sensing
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Microstepping products: SLA7075MPR, SLA7076MPR, SLA7077MPR, and SLA7078MPR
11
PreDriver
PreDriver
Sequencer
&
Sleep Circuit
Protect
Protect
DAC
+
Comp
-
5
20 21 22 23
Reg.
MIC
SenseA
OutB
9 16 10 15
OutB
8
OutB
7
OutB
6
VBB
Clock
Reset
M3
F/R
18
M2
13
M1
14
Mo
OutA
4
Flag
OutA
3
Ref/Sleep1
OutA
2
VDD
OutA
1
OSC
RSInt
DAC
Synchro
Control
PWM
Control
17
Sync
+
Comp
-
PWM
Control
OSC
19
SenseB
RSInt
12
Gnd
For R products, protection circuits not built-in. FLAG pin is not connected internally.
Pin No.
1
2
3
4
Symbol
OutA
OutA
Functions
Output of phase A
Output of phase Ā
Pin No.
Symbol
Functions
13
Ref / Sleep1
Input for control current and Sleep1 setting
14
VDD
Power supply to logic
15
Reset
Reset for internal logic
16
F/R
Forward / reverse switch input
Phase A current sensing
17
Sync
Synchronous PWM control switch input
Output from monitor of 2-phase excitation
status
18
Flag*
Output from protection circuits monitor
19
SenseB
5
SenseA
6
Mo
7
M1
8
M2
9
M3
10
Clock
Step clock input
11
VBB
Main power supply (for motor)
12
GND
Ground
Commutation and Sleep2 setting
20
21
Phase B current sensing
OutB
Output of phase B̄
OutB
Output of phase B
22
23
*Flag pin active on PR products only; not internally connected for R products.
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APPLICATION EXAMPLE FOR MICROSTEPPING PRODUCTS
Microstepping products: SLA7075MPR, SLA7076MPR, SLA7077MPR, and SLA7078MPR
VBB = 10~44 V
VDD = 3.0~5.5 V
VI+
Sleep
Q1
r1
OutA
OutA
Microcomputer
VBB
SLA 707xM
GND
SenseB
Single-Point
Ground
Logic Ground
Power Ground
• Take precautions to avoid noise on the VDD line; noise levels
greater than 0.5 V on the VDD line may cause device malfunction. Noise can be reduced by separating the Logic Ground
and the Power Ground on a PCB from the GND pin (pin 12).
• Constants, for reference use only:
12
OutB
r3
C2
r1 = 10 kΩ
r2 = 1 kΩ (VR)
r3 = 10 kΩ
OutB
+
CA
C1
Reset
Clock
F/R
M1
M2
M3
Sync
Mo or NC
Flag
Ref/Sleep1
SenseA
+
CB
r2
VDD
VS+
• Unused logic input pins (F / R, M1, M2, M3, RESET, and
SYNC) must be pulled up / down to VDD or ground. If those
unused pins are left open, the device malfunctions.
• Unused logic output pins (Mo, FLAG) must be kept open.
CA = 100 µF / 50 V
CB = 10 µF / 10 V
C1 = 0.1 µF
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TRUTH TABLES
Common Input Pins
The following truth table is valid for the common input pins of
both models of the SLA7070M series
Truth Table for Common Input Pins
Applicable both series models; PR and R products
Pin Name
Low Level
High Level
Reset
Normal
operation
Logic reset
F/R
Forward
Reverse
M1
M2
M3
Clock
POS Edge
–
Commutation / Sleep2 Function Setting The following truth
table is valid for the common Mx pins of both models of the
SLA7070M series.
Truth Table for Commutation / Sleep2 Function
Applicable both series models; PR and R products
Pin Name
Commutation /
Sleep2 function
Ref / Sleep1
Normal
operation
Sleep1 function
–
Sync
Non-sync PWM
control
Sync PWM
control
–
• The Reset function is asynchronous. If the input on the Reset
pin is High, the internal logic circuit is reset. At this point, if the
Ref pin stays Low, then the DMOS outputs turn on at the starting
point of excitation. Note that the Disable control is not available
with the Reset pin signal.
• The Sync function is active only at “2-phase excitation timing." If this function is used at other than 2-phase excitation
timing, an overall balance might collapse because PWM off-time
and set current are different in each phase A and phase B control
scenario. (2-phase excitation timing is a point where the step
reference current ratio of both phase A and phase B is Mode 8.)
Sleep Functions
The Hold mode stops motor rotation when applying current
into a motor, and the device remains in Active status. Sleep1 is
a sleep operation when logic circuits operate according to input
signals. Sleep2 is a sleep operation in which the status of the
logic circuits do not vary, but instead, they keep the same state as
before the sleep function is initiated.
Sleep1 Function Setting Voltage at the REF / SLEEP1 pin
controls the PWM current and the Sleep1 function. For normal
operation, VREF should be below 1.5 V (Low level). Applying a
voltage greater than 2.0 V (High level) to the REF / SLEEP1 pin
disables the outputs and puts the motor in a free state (coast).
This function is used to minimize power consumption when the
device is not in use. Although it disables much of the internal
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circuitry, including the output MOSFETs and regulator, the
sequencer / translator circuit is active. Therefore, a microcontroller can set the step starting point for the next operation during
the Sleep1 function.
Full / Half Step
Microstepping
L
Full step (Mode 8 fixed)
Full step (Mode 8 fixed)
L
L
Full step (Mode F fixed)
Full step (Mode F fixed)
H
L
Half step
Half step
H
L
Half step (Mode F fixed)
Half step (Mode F fixed)
L
H
H
L
H
L
H
H
H
H
H
M1
M2
M3
L
L
H
L
H
L
Quarter step
Sleep2 function
Eighth step
Sixteenth step
Sleep2 function
In the Sleep2 function, the outputs are disabled and the driver
supply current (IBB) is reduced. However, unlike the Sleep1
function, the logic circuitry is put into a "standby" state and
therefore the sequencer / translator is not activated, even if a step
command signal occurs on the CLOCK input pin.
Monitor Output Pin
The pin used to monitor the device output is different between
these configurations:
• Microstepping products: Mo (2-phase excitation timing)
• PR products: Flag (Protection circuit operation timing)
Note that PR products with microstepping have both of the
monitor output pins.
Truth Table for Monitor Outputs
Pin Name
Low Level
High Level
Mo
Other than 2-phase
excitation timing
2-phase excitation timing
FLAG
Normal operation
Protection circuit operation
The outputs turn off at the point where the protection circuit
starts operating. To release the protection state, reinput the logic
supply voltage.
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LOGIC INPUT PINS
The low pass filter incorporated with the logic input pins (RESET, CLOCK, F / R, M1, M2, M3, and SYNC) improves noise
rejection. The logic inputs are CMOS input compatible, and
therefore they are in high impedance state. Use the IC at a fixed
input level, either Low or High.
RESET input
Input Logic Timing
CLOCK signal. This device includes clock-in type of control that
simplifies the interface.
• Reset release and CLOCK input timing
• RESET input pulse width
The Reset pulse width is equivalent to the high pulse level hold
time. It should be greater than the 2 µs CLOCK input pulse
width.
• Pulse characteristics
A low-to-high and high-to-low transition on the CLOCK input
sequences the translator / sequencer. Clock pulse width should
be set at 2 µs in both positive and negative polarities. Therefore,
clock response frequency becomes 250 kHz.
F / R, M1, M2, and M3 logic change
Logic level inputs on F / R, M1, M2, and M3 set the translator
step direction (F / R) and step mode (M1, M2, and M3; refer to
the Commutation Truth Table). Changes to these inputs do not
take effect until the rising edge of the CLOCK input. However,
depending on the type and state of a motor, there may be errors
in motor operation. A thorough evaluation on the changes of
sequence should be carried out.
• Set-up and hold times before and after Clock pulse
With regard to the input logic of the F / R, M1, M2, and M3 pins,
a 1 µs delay should occur both before and after the pulse edges,
as set-up and hold times. The sequencer logic circuitry might
malfunction if the logic polarity is changed during these set-up
and hold times. Refer to the figure below.
Reset
The RESET input sets the translator / sequencer to a predefined
Home state and turns off all of the DMOS outputs. A low pass
filter is incorporated into the Reset circuit; therefore, a greater
than 5 µs delay is required between the falling edge of the RESET input and the rising edge of the CLOCK input.
2μs(min)
5μs(min)
POS Edge
4μs(min)
Clock
2μs(min)
2μs(min)
F/R
M1
M2
M3
Reset
2μs(min)
1μs(min) 1μs(min)
1μs(min) 1μs(min)
2μs(min)
Logic Input Timing
2μs(min)
5μs(min)
8μs(min)
Clock
4μs(min)
4μs(min)
14
F/R
M1
M2
M3
1μs(min)
1μs(min)
115 Northeast Cutoff,
Box 15036
Massachusetts 01615-0036
1μs(min)Worcester,
1μs(min)
1μs(min)
1μs(min)
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STEP SEQUENCING
All illustrations in this section are based on step sequencing at the POS (Positive) edge.
Full step; for both microstepping and full / half step products
M1: L, M2: L, M3: L (Mode 8)
R ESET
…
C LO C K
0
2
1
B
FWD
CW
A
A
0
70.7
0
70.7
CREW
CW
B
M1: H, M2: L, M3: L (Mode F)
R ESET
…
C LO C K
0
1
2
B
FWD
CW
A
A
0
0
CREW
CW
0
10
B
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Half step; for both microstepping and full / half step products
M1: L, M2: H, M3: L (Mode 8, F)
R ES ET
…
C LO C K
0
1
2
3
4
B
FWD
CW
A
A
0
70.7
CREW
CW
0
70.7
0
10
B
M1: H, M2: H, M3: L (Mode F)
R ES ET
…
C LO C K
0
1
2
3
B
FWD
CW
A
A
0
0
CREW
CW
0
10
B
16
115 Northeast Cutoff, Box 15036
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0
2
B
B
3
4
CREW
CW
A
5
6
7
８
…
Quarter step; for microstepping products
M1: L, M2: L, M3: H
1
38.2
CFWD
W
0
10
92.4
70.7
38.2
A
C LO C K
R ES ET
0
92.4
0
70.7
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4
0
3
19.5
2
38.2
70.7
CFWD
W
83.1
92.4
0
1
55.5
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036
92.4
98.1
0
10
83.1
70.7
55.5
38.2
19.5
A
C LO C K
R ES ET
0
98.1
18
B
B
5
6
7
8
CREW
CW
9
A
10
11
12
13
14
15
16
…
Eighth step; for microstepping products
M1: H, M2: L, M3: H
98.1
92.4
A
0
10
95.7
83.1
88.2
77.3
70.7
63.4
55.5
47.1
38.2
29.0
19.5
9.8
0
CFWDW
0
1
2
70.7
88.2
83.1
C LO C K
4
47.1
3
55.5
R ES ET
95.7
98.1
5
6
7
8
B
B
0
www.allegromicro.com
92.4
9
10
11
12
13
14
16
CREW
CW
15
17
18
A
19
20
21
22
23
24
25
26
27
28
29
30
31
32
…
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Sixteenth step; for microstepping products
M1: L, M2: H, M3: H
19
9.8
19.5
29.0
38.2
63.4
77.3
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Excitation Change Sequence
The change behavior is determined by the settings of the excitation pin (M1, M2, and M3) before and after the step signal.
Excitation Mode State Table
Internal Sequence State
Direction
Phase A
Phase B
PWM
Mode
PWM
Mode
Full Step
Mode 8
Mode F
Step Sequencing
Half Step
1/ Step
4
Mode 8, F
Mode F
1/
8
A
8
B
8
X
X*
X
X*
X
A
7
B
9
A
6
B
A
A
5
B
B
A
4
B
C
X
A
3
B
D
Rev.
A
2
B
E
A
1
B
F
–
–
B
F
X
X
X
1
B
F
Ā
2
B
E
Ā
3
B
D
Ā
4
B
C
X
Ā
5
B
B
Ā
6
B
A
Ā
7
B
9
Ā
8
B
8
X
X*
X
X*
X
Ā
9
B
7
Ā
A
B
6
Ā
B
B
5
Ā
C
B
4
X
Ā
D
B
3
Ā
E
B
2
Ā
F
B
1
Ā
F
–
–
X
X
X
Ā
F
1
Ā
B̄
E
2
Ā
B̄
D
3
Ā
B̄
C
4
X
Ā
B̄
B
5
Ā
B̄
A
6
Ā
B̄
9
7
Ā
B̄
8
8
X
X*
X
X*
X
Ā
B̄
7
9
Ā
B̄
6
A
Ā
B̄
5
B
Ā
B̄
4
C
X
Ā
B̄
3
D
Ā
B̄
2
E
Ā
B̄
1
F
Ā
B̄
–
–
F
X
X
X
B̄
A
1
F
B̄
A
2
E
B̄
A
3
D
B̄
A
4
C
X
B̄
A
5
B
B̄
A
6
A
B̄
A
7
9
B̄
A
8
8
X
X*
X
X*
X
B̄
A
9
7
B̄
A
A
6
B̄
A
B
5
B̄
A
C
4
X
B̄
A
D
3
B̄
A
E
2
B̄
A
F
1
B̄
A
F
–
–
X
X
X
A
F
B
1
Fwd.
A
E
B
2
A
D
B
3
A
C
B
4
X
A
B
B
5
A
A
B
6
A
9
B
7
∗ Sequence state is Mode 8, but step reference current ratio is Mode F. Mode F has step reference current ratio of 100%, and PWM off-time of 12 μs.
20
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036
Step
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1/
16
Step
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
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INDIVIDUAL CIRCUIT DESCRIPTION
Monolithic IC (MIC)
The descriptions of the monolithic IC (MIC) elements in this
section are applicable to both models of products: PR and R.
However, the blanking time differs among some options, and
current value in low current mode will vary according to the
minimum on-time difference.
• Sequencer Logic
The single CLOCK input is used for step timing. Direction is
controlled by the F / R input.
Commutation mode is controlled by the combination of the M1,
M2, and M3 logic levels. For details, refer to the Commutation
Truth Table on page 13.
• PWM Current Control
Each pair of outputs is controlled by a fixed off-time PWM
current-control circuit. The internal oscillator (OSC) sets the
off-time. Its operation mechanism is identical to that of the
SLA7060M family. Refer to the Functional Description section
for further details.
• Synchronous Operation Mode
This function prevents occasional motor noise during Hold
mode, which normally results from asynchronous PWM operation of both motor phases. A logic high at the SYNC input sets
synchronous operation. A logic low sets asynchronous operation.
The use of synchronous operation during normal stepping is not
recommended because it produces less motor torque and can
cause motor vibration due to staircase current.
The use of synchronous operation when the motor is not in
operation is allowed only in full/half step sequence timing, due
to the difference in the current controlled and PWM off-time at
other step sequence timings.
• DAC (D-to-A Converter)
In microstep sequencing, the current at each step is set by the
value of a sense resistor (RSInt), a reference voltage (VREF), and
the output voltage of the DACs, controlled by the output of the
sequencer (translator). Refer to the Stepping Characteristics table
on page 5.
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• Regulator Circuit
The integrated regulator circuit is used in driving the output
MOSFET gates and powering other internal linear circuits.
• Protection Circuit
A built-in protection circuit against motor coil opens or shorts is
available in the PR products. Protection is activated by sensing
voltage on the internal RSInt resistors; therefore, an overcurrent
condition cannot be detected which results from the the OUT
pins or SENSEx pins, or both, shorting to GND.
Protection against motor coil opens is available only during
PWM operation; therefore, it does not work at constant voltage
driving, when the motor is rotating at high speed.
Operation of the protection circuit disables all of the DMOS
outputs. To come out of protection mode, cycle the logic supply,
VDD.
Output MOSFET Chip
The value of the built-in output DMOS chip varies according
to which of the four different output current ratings has been
selected.
Sense Resistor
Sense resistors are incorporated in the PR and R products to
detect motor current. The resistance varies according to which
of the four different output current ratings has been selected, as
follows:
Output Current
(A)
RSInt Resistance
(Ω Typ.)
1
0.305
1.5
0.305
2
0.205
3
0.155
Each resistance shown above includes the inherent resistance
(approximately 5 mΩ) in the resistor itself.
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FUNCTIONAL DESCRIPTION
PWM Current Control
The description in this section is applicable to the PR and R
products.
• Blanking time
The actual operating waveforms on the SENSEx pins when driving a motor are shown in figure 1. Immediately after PWM turns
OFF, ringing (or spike) noise on the SENSEx pins is observed
for a few μs. Ringing noise can be generated by various causes,
such as capacitance between motor coils and inappropriate motor
wiring.
Each pair of outputs is controlled by a fixed off-time (7 to 12 μs,
depending on stepping mode) PWM current-control circuit that
limits the load current to a desired value, ITRIP. Initially, an outt
put is enabled and current flows through the motor winding and
the current-sense resistors. When the voltage across the currentsense resistor equals the DAC output voltage, VTRIP , the currentsense comparator resets the PWM latch. This turns off the driver
for the fixed off-time, during which the load inductance causes
the current to recirculate for the off-time period. Therefore, if the
ringing noise on the sense resistor equals and surpasses VTRIP ,
PWM turns off.
To prevent this phenomenon, the blanking time is set to override
signals from the current-sense comparator for a certain period
right after PWM turns on (figure 2).
t
Expanded Time Scale
Out
ITRIP
0
Out
500 ns/Div.
5 µs/Div.
Figure 1. Operating waveforms on the SENSEx pins during PWM chopping
A
PWM Pulse Width
tON
tOFF
(Fixed)
ITRIP
0
A
Blanking Time
Figure 2. SENSEx pins pattern during PWM control
22
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PWM Off Period
The PWM off-time for the SLA7070M series is controlled as a
fixed time by an internal oscillator. It also is switched in 3 levels
by current proportion (see the Electrical Characteristics table).
In addition, the SLA7070M series provide a function that
decreases losses occurring when the PWM turns off. This function dissolves back EMF stored in the motor coil at MOSFET
turn-on, as well as at PWM turn-on (synchronous rectification
operation).
Figure 3 shows the difference in back EMF generative system
between the SLA7060M series and SLA7070M series. The
SLA7060M series performs on–off operations using only the
MOSFET on the PWM-on side, but the SLA7070M series also
performs on–off operations using only the MOSFET on the
PWM-off side. To prevent simultaneous switching of the MOSFETs at synchronous rectification operation, the IC has a dead
time of approximately 0.5 µs. During dead time, the back EMF
flows through the body diode on the MOSFET.
SLA7060M Series
SLA7070M Series
VBB
Ion
VBB
Ioff
Ion
Ioff
Stepper Motor
Vg
Stepper Motor
Vg
Vg
Vg
Back EMF at Dead Time
VS
+V
PWM On
RSExt
PWM Off
VS
+V
PWM On
Vg
Vg
FET Gate 0
Signal
RSInt
t
PWM On
PWM Off
Dead
Time
FET Gate 0
Signal
Vg
PWM On
Dead
Time
t
Vg
VREF
VREF
VS
VS
0
0
t
t
Figure 3. Synchronous rectification operation. During Dead Time,
the Back EMF flows through the body diode of the MOSFET
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Protection Functions: PR Types
The PR types of the SLA7070M series include a motor coil
short-circuit protection circuit and a motor coil open protection
circuit. They are described in this section.
• Motor Coil Short-Circuit Protection (Load Short) Circuit
This protection circuit, embedded in the SLA7070M series, begins to operate when the device detects an increase in the voltage
level on the sense resistor, VSInt .
The voltage at which motor coil short-circuit protection starts
its operation, VOCP, is set at approximately 0.7 V. The output is
disabled at the time the protection circuit starts.
In order for the motor coil short-circuit protection circuit to operate, VSInt must be greater than VOCP .
Overcurrent that flows without passing the sense resistor is undetectable. To resume the circuit after protection operates, VDD
must be cycled.
• Motor Coil Open Protection
Details of this functions is not disclosed yet due to our patent
policy.
VM
Coil Short Circuit
+V
Coil Short Circuit
Stepper Motor
VS
RSInt
Output Disable
VOCP
VREF
Vg
Normal Operation
VS
0
t
Figure 4. Motor coil short circuit protect circuit operation. Overcurrent that flows without passing the sense resistor is undetectable. To recover the circuit after protection operates, VDD must be cycled and started up again.
24
115 Northeast Cutoff, Box 15036
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APPLICATION INFORMATION
Motor Current Ratio Setting (R1, R2, RSInt)
The setting calculation of motor current IOUT on SLA7070M
series is determined by the ratios of external components R1, R2,
and RSInt (refer to the application example circuit on page 12).
The following is a formula for calculating IOUT:
R2
(1)
IOUT =
VDD RSInt
R1 + R2
when VREF is within specification. If VREF is set less than 0.1 V,
variation or impedance of the wiring pattern may influence the
IC and the possibility of less accurate current sensing becomes
high.
The standard voltage of current ITRIP that SLA7070M series
controls is partially divided by the internal DAC:
VREF
(2)
ITRIP =
Mode Proportion
RSInt
For RSInt value, see Sense Resistor section, page 21.
Lower Limit of Control Current
The SLA7070M series uses a self-oscillating PWM current
control topology in which the off- time is fixed. As energy stored
in motor coil is eliminated within fixed the PWM off-time, coil
current flows intermittently, as shown in figure 5.
Thus, average current decrease and motor torque also decrease.
The point intermissive current starts flowing to the coil is considered as the lower limit of the control current. The lower limit
of control current differs by conditions of motor or other factors,
but it is calculated from the following formula.
(3)
·
¨
IOUT(min) =
VM + RDS(on)× IOUT
RM
1
–1¸
× ©
©
¸
t


off
© exp –
 ¸
ª
 Tc  ¹
where:
Tc = LM / RM , and
(4)
VM is the motor supply voltage,
RDS(on) is the MOSFET on resistance,
IOUT is the target current level,
RM is the motor winding resistance,
LM is the motor winding reactance, and
tOFF is the PWM off-time.
Even if the control current value is set at less than the lower limit
of the control current, there is no setting at which the IC fails to
operate. However, control current will worsen against setting
current.
Avalanche Energy
In the unipolar topology of the SLA7070M series, a surge
voltage (ringing noise) that exceeds the MOSFET capacity to
withstand might be applied to the IC. To prevent damage, the
SLA7070M series is designed a MOSFET having sufficient avalanche resistance to withstand this surge voltage. Therefore, even
if surge voltages occur, users will be able to use the IC without
any problems. However, in cases in which the motor harness is
long or the IC is used above its rated current or voltage, there
is a possibility that an avalanche energy could be applied that
exceeds Sanken design expectations. Thus, users must test the
avalanche energy applied to the IC under actual application
conditions.
Figure 5. Control current lower limit model waveform. The circled area indicates interval
when the coil current generated is 0 A.
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The following procedure can be used to check the avalanche
energy in an application. The schematic in figure 6 illustrates
the location for the voltage test points and circuit characteristics.
The timing diagram illustrates the waveform characteristics
resultant.
The avalanche energy, EAV, can be calculated using the following
formula:
��� � �������
� �����
VM
���
���
��
(5)
�
��� �����
� ��������
By comparing the EAV calculated with the graph shown in
figure 9, the application can be evaluated if it is safe for the IC
by being within the avalanche energy-tolerated dose range of the
MOSFET.
V D S(A V )
ID
Stepper Motor
VD S(A V )
ID
RSInt
t
Figure 6. Test points and characteristics (left panel) and
breakdown waveform (right).
Given:
VDS(AV) = 1 A,
ID = 1 A, and
t = 0.5 µs.
On-Off Sequence of Power Supply (VBB and VDD)
There is no restriction of the on-off sequence of the main power
supply, VBB, and the logic supply, VDD.
Motor Supply Voltage (VM) and Main Power Supply
Voltage (VBB)
Because the SLA7070M series has a structure that separates the
control IC (MIC) and the power MOSFETs as shown in the schematics on pages 10 and 11, motor supply and main power supply
are separated. Therefore, it is possible to drive the IC with using
different power supplies and different voltages for motor supply
and main power supply. However, extra caution is needed because the supply voltage ranges differ among power supplies.
20
SLA7073M and
SLA7078M
EAV [mJ ]
16
12
SLA7072M
and SLA7077M
8
SLA7071M and
SLA7076M
4
SLA7070M and
SLA7075M
0
0
25
50
75
100
125
Product Temperature, Tc [°C]
Figure 7. SLA7070M series iterated avalanche energy tolerated dose, EAV(max).
26
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036
150
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Internal Logic Circuits
• Reset
The sequencer circuit of this product is initialized after logic
supply (VDD) is applied, and the power on reset function operates. To initialize the sequencer, the output immediately after
power-on indicates that the status that the power circuits are in
the home state. In a case where the sequencer must be reset after
motor has been operating, a reset signal must be inputted on the
RESET pin. In a case in which external reset control is not necessary, the RESET pin is not used, and must be fixed at a logic
low level on the application circuit board.
• CLOCK Input
When the CLOCK input signal stops, excitation changes to
the motor Hold state. At this time, there is no difference if the
CLOCK input signal is at the low level or the high level. The
SLA7070M series is designed to move 1 step at a time, when a
Clock pulse edge is detected.
• Chopping Synchronous Circuit
The SLA7070M series has a chopping synchronous function to
protect from abnormal noises that may occasionally occur during
the motor-Hold state. This function can be operated by setting
the SYNC terminal at high level. However, if this function is
used during motor rotation, control current does not stabilize,
and therefore this may cause reduction of motor torque or
increased vibration. So, Sanken does not recommend using this
function while the motor is rotating. In addition, the synchronous
circuit should be disabled in order to control motor current properly in case it is used other than in dual excitation state (Modes 8
and F) or single excitation Hold state.
In normal operation, generally the input signal for switching can
be sent from an external microcomputer. However, in applications where the input signal cannot be transmitted adequately
due to limitations of the port, the following method can be taken
to use the functions.
The schematic diagram in figure 8 shows how the IC is designed
so that the Sync signal can be determined by the CLOCK input
signal. When a logic high signal is received on the CLOCK pin,
the internal capacitor, C, is charged, and the Sync signal is set to
logic low level. However, if the Clock signal cannot rise above
logic low level (such as when the circuit between the microcomputer and the IC is not adequate), the capacitor is discharged by
the internal resistor, R, and the Sync signal is set to logic high,
causing the IC to shift to synchronous mode.
The RC time constant in the circuit should be determined by the
minimum clock frequency used. In the case of a sequence that
keeps the CLOCK input signal at logic high, an inverter circuit
must be added. In a case where the Clock signal is set at an
undetermined level, an edge detection circuit (figure 9) can be
used to prepare the signal for the CLOCK input, allowing correct
processing by the circuit shown in figure 8.
• Output Disable (Sleep1 and Sleep2) Circuits
There are two methods to set this IC at motor free-state (coast,
with outputs disabled). One is to set the REF/SLEEP1 pin to
more than 2 V (Sleep1), and the other (Sleep2) is to set the
excitation signals (pins M1, M2, and M3). In either way, the IC
will change to Sleep mode, stopping the main power supply at
the same time, and decreasing circuit current. The difference
between the two methods is that, in the first way, the internal
sequencer remains in an enabled state, and in the latter method,
the IC enters the Hold state. Moreover, in the method using
VCC
Clock
74HC14
74HC14
R
Sync
Clock
C
Figure 8. Clock signal shutoff detection circuit, using
74HC14s.
www.allegromicro.com
Step
Clock
Figure 9. Clock signal edge detection circuit, inputs
to example circuit shown in figure 8.
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the excitation signals (Sleep2), excitation timing remains in a
"standby" state, even if a signal is inputted on the CLOCK pin
during Sleep mode.
• REF/SLEEP1 Pin
When awaking to normal operating mode (motor rotation) from
disabled (Sleep1 or Sleep2) mode, set an appropriate delay time
from cancellation of the disable mode to the initial CLOCK
input edge. In doing so, consider not only of rise time for the
IC, but also of the rise time for the motor excitation current, is
important (see figure 10).
• Standard voltage setting for output current level setting
• Output enable-disable control input
These functions are further described in the Truth Tables section
(page 13), and in the discussion of output disabling, above.
The REF/SLEEP1 pin provides access to the following functions:
The figure in the Reference Voltage Setting section (page 7),
shows the general relationship between the reference voltage,
VREF , (REF/SLEEP1 pin) setting voltage and performance.
There are, however, situations in which extra caution should be
exercised. These are shown in figure 11:
REF/SLEEP1 or
M1, M2, and M3
Range A. In this range, control current value also varies in accordance with VREF. Therefore, losses in the IC and the sense
resistors must be given extra consideration.
100 µs
(minimum)
CLOCK
Range B. In this range, the voltage that switches output enable
and disable (Sleep mode) exists. At enable, the same cautions
apply as in range A. In addition, for some cases, there are possibilities that the output status will become unstable as a result of
iteration between enable and disable.
t
Internal Control Current Setting Voltage
(Mode F)
[V]
Figure 10. Timing delay between disable cancellation
and the next Clock input
2.5
Output disable (Sleep mode)
setting voltage range
Range B
2.0
1.5
Range A
1.0
Control current input voltage range
0.5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
REF/SLEEP1 Pin Voltage VREF [V]
Figure 11. Relationship between external and internal reference voltages and performance. Ensure that
the absolute maximum current level is not reached.
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• Logic Input Pins
when they are left open.
If a logic input pin (CLOCK, RESET, F/R, M1, M2, M3, or
SYNC) is not used (fixed logic level), the pin must be tied to
VDD or GND. Please do not leave them floating, because there
is possibility of undefined effects on IC performance
• Output Pins
The Mo and FLAG output pins are designed as monitor outputs,
and inside of the IC is an output inverter (see figure 12). Therefore, let these pins float if they are not used.
VDD
Static electricity
protection circuit
Mo or FLAG
Figure 12. Mo pin (SLA 7075M through SLA 7078M models
only) and FLAG pin general internal circuit layout
www.allegromicro.com
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THERMAL DESIGN INFORMATION
It is not practical to calculate the power dissipation of SLA7070M
series accurately, because that would require factors that are variable during operation, such as time periods and excitation modes
during motor rotation, input frequencies and sequences, and so
forth. Given this situation, it is preferable to perform an approximate calculation at worst conditions. The following is a simplified formula for calculation of power dissipation:
where:
�� � � ����
����������������
Based on the PD calculated using the above formulas, the expected increase in operating junction temperature, ∆TJ , of the
IC can be estimated using figure 13. This result must be added
to the worst case ambient temperature when operating, TA(max).
Based on the calculation, there is no problem unless TA(max) +
∆TJ > 150°C.
(6)
�
However, final confirmation must be made by measuring the IC
temperature during operation and then verifying power dissipa-
PD is the power dissipation in the IC,
IOUT is the operating output current,
tion and junction temperature in the corresponding graph.
RDS(on) is the on resistance of the output MOSFET, and
When the IC is used with a heat sink attached, device package
RSInt is current sense resistance.
thermal resistance, RθJA, is a variable used in calculating ∆Tj-a.
Increase in Junction Temperature
�TJ (°C)
150
125
100
�TJ-A = 26.6 x PD
75
�TC-A = 21.3 x PD
50
25
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Maximum Allowable Power Dissipation, PD(max) (W)
Figure 13. Temperature increase
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The value of RθJA is calculated from the following formula:
�θ��≈�θ����θ�����θ����θ����θ���
(7)
where RθFin is the thermal resistance of the heat sink.
∆TJA can be calculated with using the value of RθJA:
�������������
����
(8)
The following procedure should be used to measure product
temperature in actual operation and then estimate junction temperature:
1. Measure the ambient temperature, TA.
2. With the device mounted but not operating, measure the temperature of the device case at the center (pin 12).
3. Power-on the device, and after it reaches operating temperature, take the measurement again.
4. Subtract the value found in step 2 from the value found in
step 3. This will provide a value for ∆TCA.
CAUTION
The SLA7070M series is designed as a multichip, with separate power elements (MOSFET), control IC (MIC), and sense
resistance. Consequently, because the control IC cannot accurately detect the temperature of the power elements (which are
the primary sources of heat), the ICs do not provide a protection
function against overheating. For thermal protection, users must
conduct sufficient thermal evaluations to be able to ensure that
the junction temperature does not exceed the warranty level
(150°C).
This thermal design information is provided for preliminary
design estimations only. The thermal performance of the IC will
be significantly determined by the conditions of the application,
in particular the state of the mounting PCB, heat sink, and the
ambient air. Before operating the IC in an application, the user
must experimentally determine the actual thermal performance.
5. Refer to figure 13 and locate the value found in step 4 on the
∆TCA trace.
The maximum recommended case temperatures (at the center,
pin 12) for the IC are:
6. Determine the corresponding power dissipation, PD.
• With no external heat sink connection: 90°C
7. Substitute the values into equation 8.
• With external heat sink connection: 80°C
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CHARACTERISTIC DATA
Output MOSFET On-Voltage, VDS(on)
SLA7071M/SLA7076M
SLA7070M/SLA7075M
1.4
1.4
Iout=1.5A
Iout=1A
1.2
1.2
1.0
0.8
Iout=0.5A
0.6
VDS(on) [V]
VDS(on) [V]
1.0
0.8
Iout=1A
0.6
0.4
0.4
0.2
0.2
0.0
0.0
-25
0
25
50
75
-25
100 125
Product Temp Tc[C]
0
75
100 125
SLA7073M/SLA7078M
1.2
1.4
Iout=3A
Iout=2A
1.2
1.0
1.0
0.6
Iout=1A
VDS(on) [V]
0.8
VDS(on) [V]
50
� ������ �� �� �����
SLA7072M/SLA7077M
Iout=2A
0.8
0.6
0.4
Iout=1A
0.4
0.2
0.2
0.0
0.0
-25
32
25
0
25 50 75 100 125
Product Temp Tc[C]
-25
0
25 50 75 100 125
Product Temp Tc[C]
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Output MOSFET Body Diodes Forward Voltage, VF
SLA7071M/SLA7076M
SLA7070M/SLA7075M
1.1
1.0
1.0
0.9
0.9
VF [V]
VF [V]
1.1
0.8
Iout=1A
0.8
0.7
Iout=0.5A
0.7
Iout=1.5A
Iout=1A
0.6
-25
0
25 50 75 100 125
Product Temp Tc[C]
0.6
-25
SLA7072M/SLA7077M
0 25 50 75 100 125
Product Temp Tc[C]
SLA7073M/SLA7078M
1.1
1.1
1.0
1.0
0.9
0.9
Iout=2A
0.8
VF [V]
VF [V]
Iout=3A
Iout=2A
0.8
Iout=1A
0.7
Iout=1A
0.7
0.6
0.6
-25
0
25 50 75 100 125
Product Temp Tc[C]
www.allegromicro.com
-25
0
25 50 75 100 125
Product Temp Tc[C]
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WARNING — These devices are designed to be operated at lethal voltages and energy levels. Circuit designs
that embody these components must conform with applicable safety requirements. Precautions must be
taken to prevent accidental contact with power-line potentials. Do not connect grounded test equipment.
The use of an isolation transformer is recommended during circuit development and breadboarding.
The products described herein are manufactured in Japan by Sanken
Electric Co., Ltd. for sale by Allegro MicroSystems, Inc.
Sanken and Allegro reserve the right to make, from time to time, such
departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its
products. Therefore, the user is cautioned to verify that the information
in this publication is current before placing any order.
When using the products described herein, the applicability and suitability of such products for the intended purpose shall be reviewed at
the users responsibility.
Although Sanken undertakes to enhance the quality and reliability
of its products, the occurrence of failure and defect of semiconductor
products at a certain rate is inevitable.
Users of Sanken products are requested to take, at their own risk, preventative measures including safety design of the equipment or systems
against any possible injury, death, fires or damages to society due to
device failure or malfunction.
Sanken products listed in this publication are designed and intended
for use as components in general-purpose electronic equipment or
apparatus (home appliances, office equipment, telecommunication
equipment, measuring equipment, etc.). Their use in any application
requiring radiation hardness assurance (e.g., aerospace equipment) is
not supported.
When considering the use of Sanken products in applications where
higher reliability is required (transportation equipment and its control
systems or equipment, fire- or burglar-alarm systems, various safety
devices, etc.), contact a company sales representative to discuss and
obtain written confirmation of your specifications.
The use of Sanken products without the written consent of Sanken
in applications where extremely high reliability is required (aerospace
equipment, nuclear power-control stations, life-support systems, etc.) is
strictly prohibited.
The information included herein is believed to be accurate and reliable. Application and operation examples described in this publication
are given for reference only and Sanken and Allegro assume no responsibility for any infringement of industrial property rights, intellectual
property rights, or any other rights of Sanken or Allegro or any third
party that may result from its use.
G2,IC-FAE
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34